JPH0236572A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0236572A JPH0236572A JP63185614A JP18561488A JPH0236572A JP H0236572 A JPH0236572 A JP H0236572A JP 63185614 A JP63185614 A JP 63185614A JP 18561488 A JP18561488 A JP 18561488A JP H0236572 A JPH0236572 A JP H0236572A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- contact hole
- resistance
- channel
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に係り、特に横形ＤＳＡ（二重拡散
自己整合方式）パワーＭＯＳＦＥＴ（絶縁ゲート電界効
果トランジスタ）のユニットセル構造に関するー
〔従来の技術〕
一横形ＤＳＡパワーＭＯ８ＦＥＴは半導体基体の表面に
絶縁ゲートをマスクとして不純物の２重拡散により自己
整合的にチャネル長を規定するものであり、そのゲート
電極は、第３図乃至第４図に示すように、従来からある
直線ストライプを極１を配置したものと、米国モトロー
ラ社により１９８４年頃に発表されたハチの巣（ｃｅｌ
ｌｕｌａｒ）構造配置とがある。このハチの巣装置のＭ
ＯＳＦＥＴは第５図乃至第６図に示すように縦横方向に
所定間隔に配置されたソース・コンタクト部（７，９）
を枠状のボ１７ Ｓ ｉゲート電極１が完全に取り囲み
、それらをポリＳ ｉ電極の接続片１２を介して一方向
に連続するように接続したレイアウトを有する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a unit cell structure of a lateral DSA (double diffused self-aligned type) power MOSFET (insulated gate field effect transistor). Technology] The horizontal DSA power MO8FET defines the channel length in a self-aligned manner by double diffusion of impurities using an insulated gate as a mask on the surface of the semiconductor substrate, and its gate electrode is as shown in Figs. 3 to 4. As shown in Figure 1, there is a conventional linear stripe with pole 1 arrangement, and a beehive (cel
lular) structural arrangement. M of this honeycomb device
As shown in FIGS. 5 and 6, the OSFET has source contact portions (7, 9) arranged at predetermined intervals in the vertical and horizontal directions.
It has a layout in which the frame-shaped holes 17 are completely surrounded by the Si gate electrode 1, and they are connected continuously in one direction via the connecting piece 12 of the poly Si electrode.
このようなハチの巣状配置の絶縁ゲートを有するＭＯＳ
ＦＥＴは、従来の直線ストライプ状配置のそれに比べて
、単位面積当りのゲート幅を畏〈形成することができ、
それだけオン抵抗が小さく、したがって損失も小さくＭ
ＯＳＦＥＴとしての効率がよい、
〔発明が解決しようとする課題〕
ハチの巣状ゲート電極構造では枠状部の内側にそってゲ
ート電極にチャネルか形成されるが、枠状部を接続する
部分１２ではチャネルの形成さねない無効ｇｔｉ分が存
在するため、単位面積に占めるゲート幅の割合が充分に
大きいとは言えない。このことにより、上記構造で低オ
ン抵抗化を図る場合に、ユニットセル数を多くする必要
かあり、チップ面積の増加ＶＣつながることになる。MOS with insulated gates arranged in a honeycomb arrangement like this
FETs can be formed with a much wider gate width per unit area than conventional linear stripe arrangements.
The on-resistance is that much smaller, and therefore the loss is also smaller.
[Problem to be solved by the invention] In the honeycomb gate electrode structure, a channel is formed in the gate electrode along the inside of the frame-shaped part, but the part 12 connecting the frame-shaped part has good efficiency as an OSFET. In this case, since there is an invalid gti portion in which a channel cannot be formed, it cannot be said that the ratio of the gate width to the unit area is sufficiently large. As a result, when lowering the on-resistance with the above structure, it is necessary to increase the number of unit cells, which leads to an increase in the chip area VC.
本発明は上記した問題を解決するためのもので。The present invention is intended to solve the above-mentioned problems.
その目的とするところは横形パ’７−Ｍ０８ＦＥＴの基
板における実装密度を向上し、低イオン抵抗化を図るこ
とにある。The purpose of this is to improve the mounting density of the horizontal PA'7-M08FET on the substrate and to lower the ionic resistance.
上記目的を達成するために１本発明の横形ＤＳＡバ’７
−Ｍ０８ＦＥＴにおいては、半導体基体表面に所定間隔
で縦横に配置されたソース及びドレインの各コンタクト
部を交互に囲むように変形さｒたストライブ状ゲートを
形成するものである。In order to achieve the above object, the horizontal DSA bar '7 of the present invention is
In the -M08FET, deformed stripe-shaped gates are formed so as to alternately surround source and drain contact portions arranged vertically and horizontally at predetermined intervals on the surface of the semiconductor substrate.
上記変形されたストライプ状ゲートは矩形波状て形成さ
ｊ、その矩形部分でソース及びドレイン’、＝）＞各°
′リド部を片方がら交互′囲む一！−冗形成されるもの
である。The above deformed striped gate is formed in a rectangular wave shape, and the rectangular portion has a source and a drain ', =) > each degree.
One that surrounds the lid part alternately from one side to the other! -It is redundant.
上記のように構成された横形１） Ｓ ＡパワーＭＯＳ
ＦＥＴにおいては、ゲートをｒ（形ストライプ状に形成
することにより、ゲートＰ！縁膜直下の半導体基体表面
のチャネルはゲートにそって断絶されることなく形成さ
れ、無効な部分が全くなく、シたがって単位面積当りの
チャネル幅も増し、ドレイン電流を大きくすることがで
きる。その結果チャネル部の抵抗が低下し、オン抵抗を
小さくてることか町ｎｇとなる。Horizontal type 1) S A power MOS configured as above
In an FET, by forming the gate in an r (shaped stripe shape), the channel on the surface of the semiconductor substrate directly under the gate P! edge film is formed without being disconnected along the gate, and there is no ineffective part, and the Therefore, the channel width per unit area is increased, and the drain current can be increased.As a result, the resistance of the channel portion is reduced, and the on-resistance is reduced.
本発明な一実施例について図面を参照し説明する。 An embodiment of the present invention will be described with reference to the drawings.
第１図は横形パワーＡ１０８ Ｆ Ｅ Ｔの平面図であ
り、ｌはポリＳｉゲート電極、２はソース・コンタクト
ホール、５はドレイン・コンタクトホールである。ゲー
ト″ｌｒＬ極１は矩形波状に曲折した変形ストライブ状
としてならべて形成さね、隣り合うλゲートの間でソー
ス・コンタクトホール２を囲み１、１
他方側でドレイン・コンタクトホール５を囲むようにな
っている。FIG. 1 is a plan view of the horizontal power A108 FET, where l is a poly-Si gate electrode, 2 is a source contact hole, and 5 is a drain contact hole. The gates ``lrL'' poles 1 are arranged in a deformed strip shape bent in a rectangular wave shape, and surround the source contact hole 2 between adjacent λ gates 1, 1, and surround the drain contact hole 5 on the other side. It has become.
ｉ折面図である、
６はｎ−型Ｓｉ基板（又はエピタキシャルｎ型層）、７
はチャネル部となるｐ層、８は深く形成したｐウェル層
、９はソースｎ 拡散層、１０はドレインｎ 拡散層で
ある。ｌはポＩＪ Ｓ ｉゲート電極、１１はゲートＳ
ｉｎ、膜、３はソースＡτ’ｆ１１ｈ、４はドレイン電
流電極であろうソースｎ）＃９とチャネル部ｐ層はゲー
トをマスクに２重拡散するＤＳＡ構造であって、自己整
合的にチャネル長、しきい値電圧の制御がなされる。6 is an n-type Si substrate (or epitaxial n-type layer), 7 is an i-fold view.
8 is a p-layer forming a channel portion, 8 is a deeply formed p-well layer, 9 is a source n-diffusion layer, and 10 is a drain n-diffusion layer. 1 is the gate electrode, 11 is the gate S
in, film, 3 is the source Aτ'f11h, 4 is the drain current electrode, and the source n) #9 and the channel part p layer have a DSA structure in which double diffusion is performed using the gate as a mask, and the channel length is adjusted in a self-aligned manner. , the threshold voltage is controlled.
チャネル９層の一部に深いｐ ウェル層８を形成するこ
とにより１等電位線の集中を緩和させ、ドレイン−ソー
ス耐圧σ）低下を防止している。By forming a deep p-well layer 8 in a part of the channel 9 layer, the concentration of one equipotential line is relaxed and a decrease in the drain-source breakdown voltage σ) is prevented.
不発明は以上説明したように構成されているσ）で以下
に記載のような効果を奏する。The non-invention has the following effects with σ) configured as described above.
ポリＳｉゲートを矩形波状変形ストライブ状としたこと
により、従来の直線ストライプ状の構造と比較してゲー
ト幅が２倍程度に長くなった結果オン抵抗を約５０％低
減が可能となる。By making the poly-Si gate into a rectangular wave-shaped deformed stripe shape, the gate width becomes about twice as long as compared to the conventional straight stripe structure, making it possible to reduce the on-resistance by about 50%.
本発明によるＤＳＡパワーＭＯ８構造を採用すルコトで
、コンタクトサイズ、ポリＳｉゲート長を一定とし、パ
ワーＭＯ８部の面積を同一とした場合のゲート幅はハチ
の巣構造のゲート幅の約１４倍に長くすることが可能で
ある。この結果、オン抵抗をＬ（ゲート長）／Ｗ（ゲー
ト幅）と考え、Ｗを１．４倍した場合、約２．８％低減
することができた。ハチの巣状構造ではチャネルの形成
しない無効部分が存在（接続部）したが、本発明ではゲ
ート電極が連続しており、ソース側のゲート電極下に無
効部分が存在せず、したがってオン抵抗の低減を可能と
する。In the case where the DSA power MO8 structure according to the present invention is adopted, the gate width is approximately 14 times the gate width of the honeycomb structure when the contact size and poly-Si gate length are constant and the area of the power MO8 part is the same. It is possible to make it longer. As a result, when considering the on-resistance as L (gate length)/W (gate width) and multiplying W by 1.4, it was possible to reduce the on-resistance by about 2.8%. In the honeycomb structure, there is an ineffective part (connection part) where no channel is formed, but in the present invention, the gate electrode is continuous, and there is no ineffective part under the gate electrode on the source side, so the on-resistance is reduced. This makes it possible to reduce
本発明のゲート電極構造を採用すれば、オン抵抗を一定
とした場合、直線ストライプ状、ハチの巣状構造に比し
て、チップサイズで１８％、３０％の縮小が可能となっ
た。By employing the gate electrode structure of the present invention, when the on-resistance is kept constant, the chip size can be reduced by 18% and 30% compared to linear stripe-like and honeycomb-like structures.
第１図は本発明の一実施例を示すパワーＭＯ８ＦＥＴの
一部平面図である。
第２図は第１図の断面図である。
第３図は従来の直線ストライプ状ゲート電極をもつパワ
ーＭＯ８ＦＥＴの一部平面図、第４図は第３図の縦断面
図である。
第５図はハチの巣状ゲート電極をもつパワーＭＯ８ＦＥ
Ｔの一部平面図、
第６図は第５図の縦断面図である。
ｌ・・・ポリＳｉゲート電極、２・・・ソース・コンタ
クトホール、３・・・ソースＡ、ｅ電極、４・・・ドレ
イ４す′ＩＩＬ他、５・・・ドレインコンタクトホール
、６・・・Ｓｉ基板。
第
図
曇！
図FIG. 1 is a partial plan view of a power MO8FET showing an embodiment of the present invention. FIG. 2 is a sectional view of FIG. 1. FIG. 3 is a partial plan view of a power MO8FET having a conventional linear striped gate electrode, and FIG. 4 is a longitudinal sectional view of FIG. 3. Figure 5 shows a power MO8FE with a honeycomb gate electrode.
A partial plan view of T. FIG. 6 is a vertical sectional view of FIG. 5. 1... Poly-Si gate electrode, 2... Source contact hole, 3... Source A, e electrode, 4... Drain 4'IIL, etc., 5... Drain contact hole, 6...・Si substrate. Figure cloudy! figure
Claims (1)
体表面に所定間隔で縦横に配置されたソース及びドレイ
ンの各コンタクト部を交互に囲むように変形されたスト
ライプ状ゲートを有することを特徴とする半導体装置。 ２、上記変形されたストライプ状ゲートは矩形波状に形
成されている請求項１に記載の半導体装置。[Claims] 1. A lateral DSA power MOSFET, characterized by having stripe-shaped gates deformed so as to alternately surround source and drain contact portions arranged vertically and horizontally at predetermined intervals on the surface of a semiconductor substrate. semiconductor device. 2. The semiconductor device according to claim 1, wherein the deformed striped gate is formed in a rectangular wave shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63185614A JPH0236572A (en) | 1988-07-27 | 1988-07-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63185614A JPH0236572A (en) | 1988-07-27 | 1988-07-27 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0236572A true JPH0236572A (en) | 1990-02-06 |
Family
ID=16173884
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63185614A Pending JPH0236572A (en) | 1988-07-27 | 1988-07-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0236572A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2752337A1 (en) * | 1996-08-06 | 1998-02-13 | Motorola Semiconducteurs | Horizontal double diffusion MOSFET for switching application |
| KR100223917B1 (en) * | 1996-06-29 | 1999-10-15 | 구본준 | The structure of a mos transistor |
| US6107650A (en) * | 1994-02-21 | 2000-08-22 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and manufacturing method thereof |
-
1988
- 1988-07-27 JP JP63185614A patent/JPH0236572A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6107650A (en) * | 1994-02-21 | 2000-08-22 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and manufacturing method thereof |
| US6323508B1 (en) | 1994-02-21 | 2001-11-27 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and manufacturing method thereof |
| US6331466B1 (en) | 1994-02-21 | 2001-12-18 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and manufacturing method thereof |
| KR100223917B1 (en) * | 1996-06-29 | 1999-10-15 | 구본준 | The structure of a mos transistor |
| FR2752337A1 (en) * | 1996-08-06 | 1998-02-13 | Motorola Semiconducteurs | Horizontal double diffusion MOSFET for switching application |
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