JPH0236385A - Digital pulse compressing device - Google Patents
Digital pulse compressing deviceInfo
- Publication number
- JPH0236385A JPH0236385A JP63186396A JP18639688A JPH0236385A JP H0236385 A JPH0236385 A JP H0236385A JP 63186396 A JP63186396 A JP 63186396A JP 18639688 A JP18639688 A JP 18639688A JP H0236385 A JPH0236385 A JP H0236385A
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- JP
- Japan
- Prior art keywords
- output
- circuit
- digital
- switch
- signal
- Prior art date
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Links
- 230000006835 compression Effects 0.000 claims abstract description 24
- 238000007906 compression Methods 0.000 claims abstract description 24
- 230000015654 memory Effects 0.000 claims abstract description 16
- 238000006243 chemical reaction Methods 0.000 abstract description 15
- 238000001228 spectrum Methods 0.000 abstract description 7
- 230000021615 conjugation Effects 0.000 abstract description 2
- 230000009466 transformation Effects 0.000 abstract description 2
- 230000005540 biological transmission Effects 0.000 description 9
- 230000001360 synchronised effect Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 4
- 238000005311 autocorrelation function Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Radar Systems Or Details Thereof (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕゛
この発明は、パルス圧縮レーダ用に用いられるディジタ
ル・パルス圧縮装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] This invention relates to a digital pulse compression device used for pulse compression radar.
一般に、パルス圧縮レーダは、リニアＦＭ波形やバーカ
ー・コードによる位相変調波形のように自己相関関数が
インパルスに近い波形をもつパルスを送受信し、受信処
理において受信信号と送信信号波形の相互相関をとるこ
とにより受信パルスを時間軸上で圧縮するとともに振幅
方向へ積み上げ、信号対雑音比の改善及び距離分解能の
向上を図るものである。この構成は、Ｍ、１．スコルニ
クレーダーハンドブック”マグロ−ヒル インターナシ
ョナルブックカンパニー２０−１〜２０−４頁（Ｍ、
Ｉ。In general, pulse compression radar transmits and receives pulses whose autocorrelation function is close to an impulse, such as a linear FM waveform or a phase modulation waveform using a Barker code, and cross-correlates the received signal and transmitted signal waveforms during reception processing. This compresses the received pulses on the time axis and stacks them up in the amplitude direction, thereby improving the signal-to-noise ratio and distance resolution. This configuration consists of M,1. Skolnikrader Handbook” McGraw-Hill International Book Company pp. 20-1 to 20-4 (M,
I.
５ｋｏｌｎｉｋ Ｒａｄａｒ Ｈａｎｄｂｏｏｋ’
ＭｃＧｒａｗ−Ｈｉｌｌ Ｉｎｔｅｒｎａｔｉｏｎａｌ
Ｂｏｏｋ Ｃｏｍｐａｎｙ ｐｐ、２０−１〜２０−
４ ）で示されているようにマツチド・フィルタ回路で
構成され、従来パルス圧縮処理をディジタル回路で実現
する方法としては第３図に示すものがあった。5kolnik Radar Handbook'
McGraw-Hill International
Book Company pp, 20-1~20-
As shown in 4), there is a method shown in FIG. 3 as a conventional method of realizing pulse compression processing using a digital circuit.
第３図において、１は同期位相検波器、２はＡ／Ｄ変換
器、３は高速フーリエ変換回路（以下、ｒＦＦＴ回路」
という）、４は複素乗算器、５はフィルタ係数メモリ、
６は逆フーリエ変換回路（以下、ｒｌＦＦＴＪという）
である。In Fig. 3, 1 is a synchronous phase detector, 2 is an A/D converter, and 3 is a fast Fourier transform circuit (hereinafter referred to as rFFT circuit).
), 4 is a complex multiplier, 5 is a filter coefficient memory,
6 is an inverse Fourier transform circuit (hereinafter referred to as rlFFTJ)
It is.
以下、この従来技術の動作について説明する。The operation of this prior art will be explained below.
同期位相検波器１及びＡ／Ｄ変換器２を経た時系列の受
信信号ｘ （ｔ）はＦＦＴ回路３によりフーリエ変換さ
れ、周波数スペクトラムＸ（ω）に変換される。一方、
フィルタ係数メモリ５は、予め送信信号の周波数スペク
トルの複素共役値Ｘ” （ω）を計算して記憶させて
あり、複素乗算器４により受信信号スペクトラムＸ（ω
）との積がとられる。The time-series received signal x (t) that has passed through the synchronous phase detector 1 and the A/D converter 2 is Fourier transformed by the FFT circuit 3 and converted into a frequency spectrum X(ω). on the other hand,
The filter coefficient memory 5 calculates and stores in advance the complex conjugate value X'' (ω) of the frequency spectrum of the transmitted signal, and the complex multiplier 4 calculates and stores the complex conjugate value X'' (ω) of the frequency spectrum of the transmitted signal.
) is taken.
この乗算結果は、ＩＦＦＴ回路６により逆フーリエ変換
されて再び時系列に戻され、出力ｙ （ｔ）となる。This multiplication result is subjected to inverse Fourier transform by the IFFT circuit 6 and returned to the time series again, resulting in an output y (t).
上記の処理によりｙ（ｔｌは式（１）のように表すこと
ができる。Through the above processing, y(tl) can be expressed as in equation (1).
式（１）をウィナ−ヒンチン（Ｗｉｅｎｅｒ−Ｋｈｉｎ
ｔｃｈｉｎｅ）の定理により書き直すと、式（２）とな
る。Expression (1) can be expressed as Wiener-Khin.
When rewritten using the theorem of tchine), equation (2) is obtained.
式（２）は受信信号の自己相関関数であるため、ｙ（１
）はインパルス状の波形として出力され、パルス圧縮動
作がなされることになる。Since equation (2) is the autocorrelation function of the received signal, y(1
) is output as an impulse waveform, and a pulse compression operation is performed.
なお、ＩＦ信号入力を同期位相検波器１でＣ０ＨＯとの
位相検波を行って直交ベクトルＩ／Ｑビデオに変換し、
Ａ／Ｄ変換器２で変換クロック毎にディジタル信号に変
換する動作については周知のことであり、説明を省略す
る。In addition, the IF signal input is subjected to phase detection with C0HO by the synchronous phase detector 1, and converted into orthogonal vector I/Q video.
The operation of converting each conversion clock into a digital signal by the A/D converter 2 is well known, and the explanation thereof will be omitted.
さらに、Ａ／Ｄ変換器２においては、変換クロックの周
期が実際上は有限の値であることから、変換時の周波数
特性歪みが存在し、別途得られたフィルタ係数との間に
不整合が生しることも周知のことである。Furthermore, in the A/D converter 2, since the period of the conversion clock is actually a finite value, there is frequency characteristic distortion at the time of conversion, and there is a mismatch between the frequency characteristic and the separately obtained filter coefficient. It is also well known that this happens.
従来のディジタル・パルス圧縮装置は、以上のように構
成されているので、送受信波形毎に、それに対応したフ
ィルタ係数をＲＯＭ等のフィルタ係数メモリ上に用意し
ておく必要があり、汎用性に欠けるとともに送受信波形
を多種使い分けるようなレーダにおいては、フィルタ係
数メモリを多数設けて切換え使用せねばならず、ハード
・ウェア規模の増大を招くという欠点があった。Conventional digital pulse compression devices are configured as described above, so it is necessary to prepare filter coefficients corresponding to each transmitted and received waveform in a filter coefficient memory such as ROM, which lacks versatility. In addition, in a radar that uses a variety of transmitting and receiving waveforms, a large number of filter coefficient memories must be provided and used selectively, resulting in an increase in the hardware scale.
また、一般にディジタル・パルス圧縮装置では上述のよ
うにＩＦ倍信号同期位相検波器及びＡ／Ｄ変換器により
ベクトルＩ／Ｑビデオを経てディジタル信号に変換する
ことが不可欠であるが、上記従来装置ではこれらの変換
誤差を考慮したフィルタ係数の設定が困難であった。In general, in a digital pulse compression device, as mentioned above, it is essential to convert the vector I/Q video into a digital signal using an IF multiplied signal synchronous phase detector and an A/D converter, but in the conventional device described above, It has been difficult to set filter coefficients that take these conversion errors into consideration.
この発明は、上記のような問題点を解消するためになさ
れたものであり、任意の送受信波形に対し、Ａ／Ｄ変換
系の変換誤差を含めた形で適応できて汎用性のある、し
かも若干のハード・ウェア規模の増加で実現することの
できるディジタル・パルス圧縮装置を得ることを目的と
する。This invention was made in order to solve the above-mentioned problems, and is a versatile device that can be applied to arbitrary transmitted and received waveforms, including the conversion error of the A/D conversion system. The object of the present invention is to obtain a digital pulse compression device that can be realized with a slight increase in hardware scale.
この発明に係るディジタル・パルス圧縮装置は、先ず初
期設定として送信信号発生回路からの送信信号をパルス
圧縮回路の入力へ供給し、受信処理と同様にＡ／Ｄ変換
及びＦＦＴ回路でのフーリエ変換を行い、その周波数ス
ペクトラム出力をフィルタ係数メモリの方へ切換えて複
素共役をとった後、フィルタ係数メモリへ記憶させ、受
信処理時には、受信信号をパルス圧縮入力へ供給すると
ともに、ＦＦＴ回路出力を複素乗算器側へ切換えて上記
フィルタ係数メモリから読み出したフィルタ係数と乗算
し、さらにこれをＩＦＦＴ回路に通してパルス圧縮を行
うものである。The digital pulse compression device according to the present invention first supplies the transmission signal from the transmission signal generation circuit to the input of the pulse compression circuit as an initial setting, and performs A/D conversion and Fourier transformation in the FFT circuit in the same way as reception processing. After switching the frequency spectrum output to the filter coefficient memory and taking the complex conjugate, it is stored in the filter coefficient memory, and during reception processing, the received signal is supplied to the pulse compression input, and the FFT circuit output is complex multiplied. The multiplication is performed by the filter coefficient read from the filter coefficient memory, and then passed through the IFFT circuit to perform pulse compression.
この発明においては、フィルタ係数用メモリの内容は、
上記のように既存のＡ／Ｄ変換系及びＦＦＴ回路を用い
て送信信号から生成されるので、Ａ／Ｄ変換系の変換誤
差を考慮した形で、送信信号波形の変化に適応すること
ができ、しかもかかる汎用性のあるディジタル・パルス
圧縮装置を若干のハード・ウェア規模の増加で得ること
ができる。In this invention, the contents of the filter coefficient memory are:
As mentioned above, since it is generated from the transmission signal using the existing A/D conversion system and FFT circuit, it is possible to adapt to changes in the transmission signal waveform while taking conversion errors of the A/D conversion system into account. Moreover, such a versatile digital pulse compression device can be obtained with a slight increase in hardware scale.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例によるディジタル・パルス圧
縮装置を示し、図において、１は同期位相検波器、２は
Ａ／Ｄ変換器、３はＦＦＴ回路、４は複素乗算器、５は
フィルタ係数メモリ、６はＩＦＦＴ回路、７は送信信号
生成回路、８は送信信号と受信信号を切換えるアナログ
切換器、９はディジタル切換器、１０は複素共役回路で
ある。FIG. 1 shows a digital pulse compression device according to an embodiment of the present invention, in which 1 is a synchronous phase detector, 2 is an A/D converter, 3 is an FFT circuit, 4 is a complex multiplier, and 5 is a complex multiplier. A filter coefficient memory, 6 an IFFT circuit, 7 a transmission signal generation circuit, 8 an analog switch for switching between a transmission signal and a reception signal, 9 a digital switch, and 10 a complex conjugate circuit.
本実施例においては第３図の従来回路に比し、ＩＦ切換
器８、ディジタル切換器９、及び複素共役回路１０が付
加されている。In this embodiment, compared to the conventional circuit shown in FIG. 3, an IF switch 8, a digital switch 9, and a complex conjugate circuit 10 are added.
以下、第１図を用いて、本実施例の作用、動作について
説明する。Hereinafter, the function and operation of this embodiment will be explained using FIG. 1.
初期設定時、アナログ切換器８は、送信信号生成回路７
の出力を通し、ＩＦ受信信号入力を遮断するように切換
えられている。又、ディジタル切換器９は複素共役回路
１ｏへ出力が得られるように切換えられており、送信信
号は同期位相検波器１及びＡ／Ｄ変換器２を経て、ディ
ジタル信号に変換されてＦＦＴ回路３でフーリエ変換さ
れて、周波数スペクトラムＸ（ω）に変換される。この
Ｘ（ω）はディジタル切換器９を経て、複素共役回路１
０へ導かれ、複素共役値Ｘ＊ （ω）に変換されてフィ
ルタ係数メモリ５に書き込まれる。At the time of initial setting, the analog switch 8 is connected to the transmission signal generation circuit 7.
The output is switched to cut off the IF reception signal input. Further, the digital switch 9 is switched so that an output is obtained to the complex conjugate circuit 1o, and the transmitted signal passes through the synchronous phase detector 1 and the A/D converter 2, is converted into a digital signal, and is sent to the FFT circuit 3. The signal is Fourier transformed into a frequency spectrum X(ω). This X(ω) passes through the digital switch 9 and is transferred to the complex conjugate circuit 1
0, converted into a complex conjugate value X* (ω), and written into the filter coefficient memory 5.
次に、パルス圧縮動作時には、アナログ切換器８はＩＦ
受信信号入力を通し、送信信号を遮断するように切換え
られ、ディジタル切換器９は複素乗算器４へ出力が得ら
れるように切換えられており、ＩＦ信号入力は、ＦＦＴ
回路３までは上記と同様の処理がなされ、ディジタル切
換器９にて、複素乗算器４へＸ（ω）を出力する。一方
、フィルタ係数メモリ５は、初期設定により設定された
Ｘ” （ω）を読み出し、複素乗算器４でＸ（ω）・
Ｘ″（ω）の乗算を行って、ＩＦＦＴＦＦＴ回路６逆フ
ーリエ変換されて、時系列上のパルス圧縮出力を得る。Next, during pulse compression operation, the analog switch 8
The digital switch 9 is switched to pass the received signal input and cut off the transmitted signal, and the digital switch 9 is switched to provide an output to the complex multiplier 4, and the IF signal input is connected to the FFT.
Up to the circuit 3, the same processing as above is performed, and the digital switch 9 outputs X(ω) to the complex multiplier 4. On the other hand, the filter coefficient memory 5 reads out X" (ω) set by the initial setting, and uses the complex multiplier 4 to
The signal is multiplied by X'' (ω) and subjected to inverse Fourier transform in the IFFTFFT circuit 6 to obtain a time-series pulse compression output.
次に、第２図は本発明の第２の実施例として、直交ベク
トルＩ／Ｑビデオでの送受信信号の切換えを行った例を
示す。Next, FIG. 2 shows, as a second embodiment of the present invention, an example in which transmission and reception signals are switched in orthogonal vector I/Q video.
この第２の実施例は第１図の第１の実施例に対し、送信
信号波形を直交ベクトルＩ／Ｑビデオの段階で描出し、
Ａ／Ｄ変換器２人力で送受信号を切換えるようにした点
が相違する。This second embodiment differs from the first embodiment shown in FIG. 1 in that the transmitted signal waveform is depicted at the orthogonal vector I/Q video stage,
The difference is that the transmitting and receiving signals are switched by two A/D converters manually.
水筒２の実施例においても、Ａ／Ｄ変換器２の変換誤差
を含むフィルタ係数が得られることから、上記第１の実
施例と同様の効果が得られる。In the embodiment of the water bottle 2 as well, since filter coefficients including conversion errors of the A/D converter 2 are obtained, the same effects as in the first embodiment can be obtained.
なお、上記実施例では複素共役回路１０をディジタル切
換器９とフィルタ係数メモリ５０間に設けているが、フ
ィルタ係数メモリ５と複素乗算器４との間、又はディジ
タル切換器９と複素乗算器４との間に設けてもよく、上
記と同様の効果が得られることはいうまでもない。In the above embodiment, the complex conjugate circuit 10 is provided between the digital switch 9 and the filter coefficient memory 50; Needless to say, the same effect as above can be obtained.
また、複素共役回路１０で単に複素共役を行うのみでな
く、上述した レーダーハンドブック”に示されている
ようなレンジ・サイドローブ抑圧用ウェイティング係数
を乗じてもよく、本質的に上記と同様の効果が得られる
。Furthermore, in addition to simply performing complex conjugation in the complex conjugate circuit 10, it may also be multiplied by a weighting coefficient for range sidelobe suppression as shown in the above-mentioned "Radar Handbook", which essentially produces the same effect as above. is obtained.
以上のように、この発明によれば、ディジタルパルス圧
縮装置の一部をなすＡ／Ｄ変換変換度ＦＦＴ回路を用い
てフィルタ係数を得るように構成したので、Ａ／Ｄ変換
変換度換誤差を含めた形で任意の送受信波形に適応でき
、汎用性のあるディジタル・パルス圧縮装置を若干のハ
ード・ウェア規模の増加で実現することができる効果が
ある。As described above, according to the present invention, since the filter coefficient is obtained using the A/D conversion degree FFT circuit which is a part of the digital pulse compression device, the A/D conversion degree conversion error can be reduced. This has the effect of being able to adapt to any transmitting/receiving waveforms and realizing a versatile digital pulse compression device with a slight increase in hardware scale.
第１図はこの発明の第１の実施例によるディジタル・パ
ルス圧縮装置を示す系統図、第２図はこの発明の第２の
実施例を示す系統図、第３図は従来のディジタル・パル
ス圧縮装置を示す系統図である。
図において、１は同期位相検波器、２はＡ／Ｄ変換器、
３はＦＦＴ回路、４は複素乗算器、５はフィルタ係数メ
モリ、６はＩＦＦＴ回路、７は送信信号生成回路、８は
アナログ切換器、９はディジタル切換器、
０は複素共役回路である。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a system diagram showing a digital pulse compression device according to a first embodiment of the present invention, FIG. 2 is a system diagram showing a second embodiment of this invention, and FIG. 3 is a system diagram showing a conventional digital pulse compression device. It is a system diagram showing an apparatus. In the figure, 1 is a synchronous phase detector, 2 is an A/D converter,
3 is an FFT circuit, 4 is a complex multiplier, 5 is a filter coefficient memory, 6 is an IFFT circuit, 7 is a transmission signal generation circuit, 8 is an analog switch, 9 is a digital switch, and 0 is a complex conjugate circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
装置において、 中間周波数帯の送信信号と受信信号とを切り換えるアナ
ログ切換器と、 該アナログ切換器からのＩＦ帯の送信信号または受信信
号入力を直交ベクトルＩ／Ｑビデオに変換する同期位相
検波器と、 該直交ベクトルＩ／Ｑビデオをディジタル信号に変換す
るＡ／Ｄ変換器と、 その出力をフーリエ変換するＦＦＴ回路と、その出力を
複素共役回路側と複素乗算器側とに切り換えるディジタ
ル切換器と、 その出力の複素共役をとる複素共役回路と、その出力を
記憶するフィルタ係数メモリと、上記ディジタル切換器
からの出力に上記フィルタ係数メモリの出力を複素乗算
する複素乗算器と、その出力を逆フーリエ変換するＩＦ
ＦＴ回路とを備え、パルス圧縮波形を得ることを特徴と
するディジタル・パルス圧縮装置。(1) In a digital pulse compression device in a pulse radar, there is an analog switch that switches between a transmit signal and a receive signal in the intermediate frequency band, and an orthogonal vector I that inputs the transmit signal or receive signal in the IF band from the analog switch. A/D converter that converts the orthogonal vector I/Q video into a digital signal, an FFT circuit that Fourier transforms its output, and a complex conjugate circuit side that converts the output. a complex conjugate circuit that takes the complex conjugate of its output, a filter coefficient memory that stores the output, and a digital switch that switches the output from the digital switch to the complex multiplier side; A complex multiplier that multiplies and an IF that performs inverse Fourier transform on its output
1. A digital pulse compression device comprising an FT circuit and obtaining a pulse compression waveform.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63186396A JPH0690277B2 (en) | 1988-07-26 | 1988-07-26 | Digital pulse compressor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63186396A JPH0690277B2 (en) | 1988-07-26 | 1988-07-26 | Digital pulse compressor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0236385A true JPH0236385A (en) | 1990-02-06 |
| JPH0690277B2 JPH0690277B2 (en) | 1994-11-14 |
Family
ID=16187669
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63186396A Expired - Fee Related JPH0690277B2 (en) | 1988-07-26 | 1988-07-26 | Digital pulse compressor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0690277B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0566268A (en) * | 1991-09-06 | 1993-03-19 | Mitsubishi Electric Corp | Digital pulse compression device |
| JP2008175552A (en) * | 2007-01-16 | 2008-07-31 | Japan Radio Co Ltd | Compression coefficient generating apparatus |
| JP2008292343A (en) * | 2007-05-25 | 2008-12-04 | Nec Engineering Ltd | Fm-cw radar |
| JP2011191133A (en) * | 2010-03-12 | 2011-09-29 | Toshiba Denpa Products Kk | Pulse compression device of radar reception signal |
| US9571066B2 (en) | 2012-02-20 | 2017-02-14 | Nec Corporation | Digital filter circuit, digital filter processing method and digital filter processing program storage medium |
-
1988
- 1988-07-26 JP JP63186396A patent/JPH0690277B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0566268A (en) * | 1991-09-06 | 1993-03-19 | Mitsubishi Electric Corp | Digital pulse compression device |
| JP2008175552A (en) * | 2007-01-16 | 2008-07-31 | Japan Radio Co Ltd | Compression coefficient generating apparatus |
| JP2008292343A (en) * | 2007-05-25 | 2008-12-04 | Nec Engineering Ltd | Fm-cw radar |
| JP2011191133A (en) * | 2010-03-12 | 2011-09-29 | Toshiba Denpa Products Kk | Pulse compression device of radar reception signal |
| US9571066B2 (en) | 2012-02-20 | 2017-02-14 | Nec Corporation | Digital filter circuit, digital filter processing method and digital filter processing program storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0690277B2 (en) | 1994-11-14 |
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