JPH0229988A - Memory device - Google Patents

Abstract

PURPOSE:To attain high speed random access by dividing the dynamic RAM group of a respective page unit into plural groups, obtaining a memory system which can access independently and accessing by page accessing. CONSTITUTION:A page address latch 8 of a memory accessing device 2a stores an old page address designated before one access, receives a page address 6 with the accessing of a processor 1 and transfers an old page address 9 to a page address comparing circuit 10 on latching a new page address. The page address comparing circuit 10 compares the new page address 6 with the old page address 9, executes the decision whether the addresses of the both are coincident or not, and by a page accessing means constituted with a multiplexer 12 and a RAS/CAS generating circuit 13, when the addresses of the both are coincident, page access according to the old page address 9 is outputted to a dynamic memory system 3a, and when they are not coincident, the page access by the new page address 6 is outputted to the system 3a.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory device, and particularly to a memory device suitable for accessing a memory system having a dynamic RAM group at high speed.

[Conventional technology]

Conventionally, large-scale memory systems for high-speed processors have consisted of a cache memory system composed of static memory in order to shorten access time, and a large-scale memory system composed of dynamic RAM as an access device for the cache memory system. A method is adopted in which a high-speed buffer is provided between the large-scale memory system and the processor. As a technique related to accessing the cache memory, the technique described in Japanese Patent Application Laid-open No. 197842/1983 is known.

[Problem to be solved by the invention]

However, conventional technology basically uses a buffer system to speed up access, and this technology is not effective for programs that are executed over long periods of time or for data that is used over long periods of time. Operate. However, in systems that include many dynamic processing systems where dynamic factors such as interrupts occur frequently, and the programs being executed and the data being processed also frequently change, the problem is that the real-time processing capacity decreases. was there. Furthermore, using a high-speed cache memory in a system increases costs, and the access mechanism for controlling the cache memory also becomes complex and expensive.

An object of the present invention is to provide a memory device that enables high-speed access even in a system that includes many dynamic processing systems in which programs and data to be processed change frequently.

[Means to solve the problem]

In order to achieve the above object, the present invention collects a plurality of dynamic RAMs in which a plurality of memory cells are arranged in a matrix in page units, and dynamic RAMs in each page unit.
The AM group is divided into multiple groups, with a set of pages storing data that is unlikely to cause access interference between pages, and the dynamic RA of each group is
M is configured with memory systems that respond to page access (fast page mode, static column mode, or nibble mode), and access for specifying the page address of each group's memory system independently for each group's memory system. In response to the access, storage means stores an old page address specified at least one access before this access; and in response to the access to the page address, a new page address specified by this access is stored in the storage means. a determining means for determining whether the content of the old page address matches, and when the determining result of the determining means is a match, a page access is performed according to the old page address, and when the determination result is a mismatch, a page access is performed using a new page address. This memory device is provided with paging access means for issuing commands to the memory systems of each group.

In addition, each page-based dynamic RAM group is used as a memory system for storing instruction data, which is an instruction code that defines the processing operation of a processor connected to the dynamic memory device, and for storing the contents of data to be processed according to the instruction code. The memory system is divided into at least two independent groups, and each group's memory system is provided with the storage means, determination means, and paging access means.

[Operation] When the access command means outputs an access for specifying the page address of the memory system of each group, in response to this access, it is determined whether the contents of the old page address and the new page address match, When the determination result is a match, a page access is performed according to the old page address, and when the determination result is a mismatch, the page to be accessed is updated to a new page, and then a page access is performed using the new page address. That is, when there is no change in the page address, high-speed continuous page access is performed according to the old page address, and only when the page address changes, normal DRA is performed according to the new page address.
M accesses are performed. Therefore, even when performing page access, memory access takes time due to the overhead of switching pages for one access that changes the page address, and when there is no change in the page address, a page without overhead with a constant page address is used. Access is performed. In the present invention, the page switching overhead that occurs when a page address changes can be reduced by grouping together pieces of data that are likely to cause inter-page access interference, and configuring a plurality of groups.
By allocating each group to an independent dynamic memory system controlled by an independent memory access device, the probability of page address change is greatly reduced, and page switching overhead is minimized to achieve high-speed access. It becomes possible.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, the memory system in this embodiment includes an instruction dynamic memory system 3a, a memory access device [2
Dynamic memory system 3b for system and data including a
, a system including a memory access unit W2b, and each part receives data from the processor 1 via a data bus 4, addresses via an address bus 5, and clock signals via a clock line 27. , control line 20. Control signals are supplied via the decoder circuit 18, respectively.

The dynamic memory systems 3a and 3b are composed of a plurality of dynamic RAM groups in which a plurality of memory cells are arranged in a matrix, grouped in page units, and each system is designed such that access interference is unlikely to occur between pages. It consists of a memory system that collects information and responds to page accesses. That is, in this embodiment, the dynamic RAM group for each page is divided into two groups, with programs and data sets that are unlikely to cause access interference between pages as one group, and the dynamic RAM in each group is configured to respond to page accesses. It consists of memory systems 3a and 3b. Conversely, inter-page access interference may frequently occur between each memory system (3a, 3b in this example). In other words, groups of programs or data that are likely to cause inter-page interference are separated and Assign it to the system.

In this embodiment, as an example, the memory system 3a stores instruction data, which is an instruction code to be executed by the processor 1, and the memory system 3b stores operand data, which is the content of data to be processed according to the instruction code. It is supposed to be done. As the data address of each memory system, an upper address is assigned as a page address (ROv address), and a lower address is assigned as a data address (COLUMN address).

Here, page access refers to DRAM access modes such as high-speed page mode, static column mode,
and nibble mode access. In other words, page access is defined here as fixing the page address assigned to the ROW address and accessing data in the same page at high speed by changing the data address assigned to the COLUMN address. What is effective in the present invention is random access. However, for continuous access to consecutive addresses such as fetching instruction data (for example, access to the instruction dynamic memory system 3a in this example), the nibble mode is used. It is also possible to use From now on, we will proceed with the explanation assuming that page access is performed using high-speed page mode as a typical page access.

The memory access devices 2a, 2b include a page address latch 81 as a storage means and a page address comparison circuit 10 as a determination means. It is composed of a multiplexer 12 and a RAS/■ generation circuit 13. In addition, it is a memory access device! Since Z2b has the same function as the memory access device 2a, only the specific configuration of the memory access device 2a is shown.

The page address latch 8 receives the page address 6 output to the address bus 5 upon access by the processor 1 as an access command means, and transfers the currently specified page address (new page address) at the rising edge of the address strobe signal ADS19. It is designed to latch with. That is, the address strobe signal ADS19a
Until it starts up, the previously accessed page address (old page address) 6 is latched. When the new page address is latched, the old page address 9 is transferred to the page address comparison circuit 1.
It is configured to transfer to 0. The page address comparison circuit 10 compares the new page address 6 and the old page address 9, determines whether the contents of the two addresses match or not, and when the determination result is a match, sends a high-level comparison signal 11. If the determination result is a non-coincidence, a low level comparison signal 11 is output to the RAS/2 generation circuit 13. The RAS/■ generating circuit 13 receives the comparison signal 11 from the processor 1 and the page address comparison circuit 10 so as to satisfy the input timing of the RAS signal 15a and the ■ signal 16a of the dynamic memory system 3a.
Based on this, a RAS signal 15a and a signal 16a are output to the dynamic memory system 3a.

Note that in this example, the rising and falling timings and logic states of the RAS signal and the (2) signal are A specified for standard dynamic memory ICs.
It follows C timing.

Further, the multiplexer 12 receives the data address 7 and the new page address 6, selects the new page address 6 using the period when the RAS signal 15a is rising or the period when the signal 16a is falling, and selects the new page address 6 when the RAS signal 15a is rising. It is output as a memory address signal 14a at a timing that can be latched into the dynamic memory system 3a at the falling edge. Also, R
Data address 7 is selected using the period when the AS signal 15a is falling or the period when the signal 16a is rising, and the data address 7 is selected as the memory address signal 14a at the timing when the signal 16a falls and can be latched into the dynamic memory system 3a. Output. That is, the multiplexer 12 is configured to switch the memory address signal 14a to the dynamic memory system 3a upon receiving the RAS signal 15a, and the multiplexer 12 and the RAS/■ generation circuit 13 constitute paging access means. . In this example, the page address 6 sent from the processor 1 as a new page address is directly input to the multiplexer 12, but the RAS signal 15a
As long as the condition that the page address output to 14a can be latched to the dynamic memory system 3a at the rising timing of After that, the output signal 9 (2a
The signal indicated by the dotted line in the box) may be sent to the multiplexer 12 as new page address data.Also, if the memory access cycle is composed of a pipeline bus cycle (described later), the address previously output from the processor may be sent to the multiplexer 12 as new page address data. It is necessary to provide means for once latching the information 6 and 7, and to transfer the page address and data address latched by the latching means to the multiplexer 12. In this case, regarding the page address 6, it is also possible to use the page address latch 9 as a latch means.

Furthermore, the access is terminated using the signal 16a, which is also transferred to the READY signal generation circuit 22 as the bus termination request signal 24a, and based on this, the READY signal 23 is output to the processor 1 at an appropriate timing. Processor 1 is notified of the end of the bus cycle.

Further, the decoder circuit 18 receives a control signal 20 from the processor 1, and also receives an address 21 from the address bus signal 5 and decodes it, and if the processor requests access to the dynamic memory systems 3a and 3b, it responds accordingly. Memory access devices 2a and 2b
Address strobe signals ADS19a and 1 corresponding to
Outputs 9b. In this example, it also plays the role of outputting a write signal 25 indicating a write command from the processor to the dynamic memory systems 3a and 3b. Further, a signal 26 indicating whether a bus cycle is being executed is sent from the decoder circuit 18 to the READY signal generating circuit 22.
is being output.

The memory access device 12b and the dynamic memory system 3b also have the same functions as 2a and 3a,
Each can be accessed independently.

Next, a case where the new page address 6 and the old page address 9 do not match and a case where they match will be explained based on FIG.

In FIG. 2, states SQL to SO4 show a case where the old page address 9 indicated in the previous access and the currently accessed new page address 6 are different.

That is, 0 indicates the operation timing when the page address comparison circuit 10 determines that the new page address 6 and the old page address 9 do not match.The valid period during which both page addresses are compared is the new page address. 6 is output from the processor 1 until the time when the address strobe signal A D S 19 rises, which is the timing at which this address is latched into the page address latch 8. That is, from the beginning of state S1 to the falling edge of state SO3.

When the processor 1 outputs the address strobe signal ADS19a from the falling edge of state S01 to the falling edge of state 803 according to the program, within the active period when this signal is at LO level, and when the page address comparison circuit 10 compares The comparison result is latched at the rising edge of state S01, which presents a correct comparison result.

A comparison signal 11 is output. That is, in accordance with the access from the processor 1, the page address comparison circuit 10 compares the new page address 6 and the old page address 9, and when the comparison result is a mismatch, the comparison signal 11 is at the LO level, and when the comparison result is a match, the comparison signal 11 is at the LO level. A comparison signal 11 at HI level is output. When the comparison result is non-coincidence, the comparison signal 11 at LO level is output at the falling edge of state S01. If the comparison signal 11 is at the LO level at the time of the rise of state SQL, the RAS/2 generation circuit 13 inverts the RAS signal 15 to the HI level. Note that if the RAS signal 15 is at HI level at the falling timing of state S02,
The RAS/■ generating circuit 13 maintains the ■ signal 16 at HI level. On the other hand, the RAS signal 15 is lowered to the LO level after a sufficient RAS precharge time. In this case, the RAS signal 15 is inverted to the LO level for three clocks, that is, at the rising edge of 5OWI. Thereafter, one clock later, the (2) signal 16 is also inverted to the LO level. When the {circle around (2)} signal 16 is output, the READY signal 23 is output from the READY signal generating circuit 22 to the processor 1 and the memory access device [2a] at the falling edge of state 5OW4. As a result, the bus state ends with the rise of state SO4, and at this point the comparison signal 11 is inverted to E (I level).

(2) Signal 16 also returns to HI level (inactive state). Note that the RAS signal 15 is maintained at the LO level.

In this way, if the page addresses do not match, the RAS
Precharge time (5OW1 from the beginning of state SO2
In order to satisfy the access time of the dynamic memory system 3a, in this example, four clock wait states SOWI to SOWI5OW4 are required. That is, when the page addresses match, the data address (■ address) 7 is transferred to the dynamic memory system 3 as a page mode access according to the old page address 9.
However, when the page addresses do not match, the transfer time of data address 7 is delayed by the RAS precharge time.

Next, a case where the page addresses match, that is, a case where the new page address 6 and the old page address 9 match will be explained using states Sll to S14. In this case, the valid period during which both page addresses are compared is from the output of the new page address to the address strobe signal A.
This is until the DS19 starts up.

When both page addresses match as determined by the page address comparison circuit 1o, they are already at the HI level at the time of rise of state Sll. That is, the level of the comparison signal 11 becomes H at the rising edge of state SO4.
Since it is inverted to I level, it is maintained at HI level at the time of rising of state Sll. Further R.A.
The S signal 15a is also kept at the LO level. and.

When the next state S12 rises, the ■ signal 16a is inverted to the LO level. When this signal is output to the READY signal generation circuit 22, the READY signal 23 is inverted to the LO level at the rising edge of state S13, and this bus cycle ends at the rising edge of state S14.

In this way, when the page addresses match, there is no wait state processing and page mode access is executed according to the old page address 9. That is, the page address is fixed and access according to the data address (■ address) 7 is executed.

Note that as the memory address signal 14a, RAS
When jfl No. 15a is at HI level, new page address 6 is output, and when RAS signal 15a is at LO level, data address (■) 7 is output. As a result, the RAS signal 15a.

(2) A necessary memory address can be latched into the dynamic memory system 3a at the falling edge of the signal 16a.

The page access method in this embodiment has been described above, taking the dynamic memory system 3a and the memory access device 112a as examples. It is assumed that the dynamic memory system 3b and the memory access device 2b have the same functions as 3a and 2b.

Next, according to this embodiment, a plurality of independent dynamic memory systems (3a, 3b) and memory access devices (2
The effects of providing a, 2 and b) will be explained based on FIG.

If the dynamic RAM group is used as a single group and handled by one memory access device, for example, memory data where address 5,100 is specified as the page address and addresses O~7.56~61 are specified as the data address. When a fetch sequence is executed, access interference between pages occurs every time the page address changes.

A large number of wait states are inserted, and the processing speed of the processor 1 is significantly reduced. On the other hand, in this embodiment, a set of pages that are unlikely to cause access interference between pages is treated as one group, and, for example, the dynamic memory system 3a stores instruction data, which is instruction code data for specifying processing operations of the processor 1. The dynamic memory system 3b stores operand data to be processed according to the instruction code. That is, memory data includes instruction data and operand data, and instruction fetches and data fetches coexist in a fetch sequence, but are often far from the address where the instruction exists. Therefore, there is a high probability that instruction data and operand data are located at different page addresses, and if they are stored together in one dynamic memory system and page access is performed, page mismatches will occur frequently. , there is a high possibility that page switching overhead will increase and system performance will deteriorate. Therefore, a set of instruction data is selected as the first group of items that are unlikely to cause access interference between pages and allocated to the dynamic memory system 3a for instructions, and a set of operand data is selected as the second group for data use. Dynamic memory system 3
By allocating it to b, it is possible to adopt a configuration in which data that is likely to interfere with page addresses is placed in a separate group. Therefore, when the memory data fetch sequence shown in FIG. 3 is executed, access to the dynamic memory 3a is executed when 5 is specified as the page address, and access to the dynamic memory 3a is executed when the page address 100 is specified as the page address. Access to the system 3a is executed, the page address is fixed, and access is executed according to the contents of the data address. As a result, memory access device 2
A one-car memory system in which the page address comparison circuit 10 of the memory access device 12b has the page address 5 latched for a long period of time, and the page address comparison circuit 10 of the memory access device 12b has the page address 100 latched for a long period of time. data can be accessed in a non-wait state.

In this way, dynamic memory systems are grouped into groups that are unlikely to cause access interference between pages, so if each memory system is accessed using page mode access, speeds of random access can be achieved in the same way as with cache memory. . this is,
For example, as in this example, there is a very high possibility that instruction data exists in the same address area as the instruction data, and operand data exists in the same address area as the operand data, and the probability that the processor handles them continuously in the processing sequence is very high. is high, so there is almost no access interference between pages within each group. Therefore, if the page address space per page is large enough, the probability of page address mismatch is extremely small. Grouping by method is very effective for speeding up the system.

Also, applications where the program to be processed changes frequently due to dynamic factors such as one interrupt, for example.

Conventional high-speed buffer technology using cache memory is not suitable for control systems and automatic machine controllers because it involves a large overhead such as reloading instructions and data. On the other hand, according to the method of this embodiment, an overhead of 4 machine states (100 ns) is generated with 25 ns as one state only when the page address changes, but since the possibility of the page address changing is extremely small, , almost non-wait operation is possible and sufficient real-time access performance can be provided.

Furthermore, according to the embodiment described above, a high-speed buffer memory is not required, so that a very inexpensive memory system can be constructed.

In addition, when controlling access to a dynamic memory system, refresh control and dynamic RAM
RAS due to page access mode restrictions due to side
Precharge control is required, but these functions are performed by the memory access device l! Although it may be provided outside of 2a and 2b, it is also possible to incorporate it inside. When provided externally, it is necessary to provide the memory access devices 2a, 2b with a function of raising the RAS signal 15 by applying a refresh request from the outside. It is effective to give a refresh address instead of the page address 6 during this time, and to latch the refresh address into the dynamic memory systems 3a and 3b by lowering the RAS signal after a sufficient RAS precharge time. It is true. Similarly, when returning from a refresh cycle to a normal bus cycle, after a sufficient RAS precharge time has elapsed, the page address to be executed is latched in the dynamic memory systems 3a and 3b at the falling edge of the RAS signal 15, and page access is performed. If provided internally, all necessary functions, including refresh address generation circuits, can be integrated into one or multiple IC chips to access the dynamic memory system. It is also possible to do so. In this case, it is possible to configure the entire system integrated into an IC similar to that of FIG. 1.

The above has described an example of the configuration of the present invention when the high-speed page mode of DRAM is used for page access. As mentioned above, DRAM page access modes currently include a high-speed page mode, a static column mode, and a nibble mode.

In static column mode, the control of the RAS signal is the same as in high-speed page mode, but there is no need to latch the data address into the dynamic memory system using the signal.Instead, when reading, the data to be read is determined using the data address signal. The memory access device that controls the dynamic memory system must be provided with a circuit that applies a write pulse to the target memory cell when the target dynamic memory system is accessed during writing. It is necessary to provide Furthermore, while accessing in the static column mode, it is necessary to keep the ■signal at the LO level, and as in this embodiment, the ■signal directly applied to the memory system is used to signal the completion of a bus cycle. Therefore, within the memory access device, a signal having a function similar to the signal (2) in this embodiment, that is, a signal indicating that access to the memory system has started in that bus cycle. It is necessary to generate and provide it to the READY signal generation circuit 22.

Page access using nibble mode is basically the same as page access using high-speed page mode, except that there is no need to externally supply a data address to the dynamic memory system other than the access immediately after the page address is switched. . Therefore, basically the system and timing shown in this embodiment can be used as is. However, in nibble mode, data addresses are automatically generated using an up counter in a dynamic memory (DRAM) IC, so data addresses can only be selected consecutively. If it is continuous, it can be used for burst transfer and is effective, but it is not suitable for random access. Also, even if it doesn't cause a page mismatch.

If the memory addresses to be accessed are discontinuous, it must be considered the same as a page mismatch. Therefore, if the data address of the corresponding dynamic memory system that processor 1 is currently trying to access is It is necessary for each memory access device to have a means for determining whether the data address at the time of access is equal to the one incremented by one, and if it is not equal, it is necessary to start an access cycle that is considered to be equivalent to a page mismatch. A memory access device must be configured.

Next, an exemplary configuration of a system using the dynamic memory device 112 of the present invention will be described in detail.

FIG. 4 shows a case where the processor 1 of the embodiment shown in FIG. 1 is simply configured with only the CPU 100. The address bus 5 is directly input from the CPLIloo to the memory access devices 2a, 2b of the present invention, and the data bus 4 is directly connected from the CPU 100 to the dynamic memory systems 3a, 3b of the present invention. Similar to the embodiment shown in FIG. 1, a set of instruction data and an operand data set that are likely to cause inter-page access interference are stored separately in separate dynamic memory systems 3a and 3b, respectively. As a result, inter-page access interference can be extremely reduced, and overhead due to page address mismatch can be minimized, so high-speed access to the dynamic memory system in page access mode can be constantly performed. A signal line 108 for exchanging an access request signal (ADS) to the dynamic memory system and an access start signal from the memory access mechanism 2at2b.
is connected to a system control logic 101 including various decoding circuits and READY generation circuits.

The system control logic 101 has a signal line 103
The necessary address information and status information are sent to the CPU10.
I am communicating with 0.

The system control logic also plays the role of generating necessary control signals for other subsystems, obtaining necessary information from other subsystems, and transmitting it to the CPU. FIG. 4 shows the simplest configuration as an implementation example of the present invention, and the cost performance is also very high.

FIG. 5 shows an example in which the processor 1 of FIG. 1 is configured to include an instruction cache memory 109a and an instruction cache memory controller 110a for controlling it. The instruction cache memory controller 110a sends necessary address and status information to cputoo via a signal 104a.
interact with In addition, the instruction cache memory system 1
Necessary information is exchanged between the instruction cache memory controller 110a and the instruction cache memory controller 110a using the signal 11A 105a.

Access to the instruction dynamic memory system 38 of the present invention and the memory access device 2a that controls it is as follows:
The target physical address 106a of the main memory, which is generated by the instruction cache memory 109a and the instruction cache memory controller 110a when the cache memory misses, and the input/output signal 1 of data to and from the cache memory.
Access to the data dynamic memory system 3b and its memory access device 2b is performed using the control signal line 102a containing the access request stone to the memory access device 07a and the memory access device 2a, as shown in FIG. Similarly, the basic effect is the same as the example shown in FIG. Although it matches well with the present invention, which aims to speed up the data transfer of Inferior.

However, if a static memory having a considerably faster access time than the page access mode of the dynamic memory system can be used in the instruction cache memory system 109a, the CPU with a higher frequency can be used.
becomes possible to drive.

FIG. 6 shows that the processor 1 is equipped with a single cache memory system 109 that contains not only instruction data but also operand data and a cache memory controller 110 that controls it, and that the CPU 100 always accesses the cache memory system 109. It is configured to do so. This structure within the processor is a common cache memory system that has traditionally been used. Here, the dynamic memory device 112 of the present invention is used as a main memory system, and is used to exchange target data with a signal line 106 that provides a physical address on the main memory where the target data exists when a cache memory miss occurs. A signal line 107 and a signal line 102 for exchanging necessary status and control signals connect the CPU via a cache memory system 109 and cache memory controller
Adopt a configuration that connects with If a static memory (SRAM) with the same manufacturing process as a DRAM used in a dynamic memory system is used as a cache memory, as long as the present invention is used, the access speed will be lower than that of the configuration shown in FIG. 4 without a cache. As mentioned above, there is no superiority, and the configuration shown in FIG. 4 is far more advantageous in terms of real-time processing performance. The cache memory system 109 and the cache memory controller 110 are connected to a CP.
It is a 1-chip IC together with U100, but a special high-speed S
If RAM is used in the cache memory system 109, the transfer of instruction data and operand data between the main memory system 112 and the cache memory system 109 according to the present invention can be speeded up for the same reason as the configuration shown in FIG. Therefore, the CPU 100 can be operated at a higher frequency. In terms of real-time processing performance, since operand data is also exchanged via the cache memory 109, the real-time processing performance is further degraded compared to the configuration shown in FIG.

The example in FIG. 7 shows a case where the processor 1 is configured by separately providing an instruction cache memory system 109a and a data cache memory system 109t+. The basic characteristics of system performance are the same as in the example shown in FIG. The dynamic memory device 112 of the present invention can improve the hit rate to the instruction cache memory system 10 and thereby improve the system performance.
9a and controller 110a may be connected to the instruction dynamic memory system 3a and its memory access device 2a, and the data cache memory system 109b and controller 110b may be connected to the data dynamic memory system 3b and its memory access device 2b. Therefore, it can be said that this configuration has excellent connectivity with the present invention.

In the configuration shown in FIG. 8, the processor 1 is configured with a single CPU,
The basic structure and basic characteristics of system performance are the same as the configuration shown in FIG. The difference is that the structure has an independent set of address signal line 5b for operand data communication and data signal line 4b for operand data communication.Therefore, by adopting a CPU with this structure, the dynamic When connecting to a memory device, the signal lines 5a and 4a are directly connected to the dynamic memory system 3a for commands and its memory access device 2a, and the signal lines 5b and 4b are connected directly to the dynamic memory system 3b for data and its memory access device 2a. Since it is only necessary to connect to 2b, the connectivity with the present invention is very good.The advantages of this type of CPU are as follows.

a) Exchanging operand data with the outside and fetching instructions can be executed in parallel, so the external system and CPU
It is possible to improve the data communication throughput between

b) Since instruction fetch cycles and operand data read and write cycles can be processed in parallel, CPU
The flow of instructions and data within the CPU can be made smooth, and therefore disturbances in pipeline processing within the CPU can be minimized.

The advantage of a) is that the throughput of data communication with the outside of the CPU is improved, the amount of data that can be processed per unit time is increased, and the performance of the CPU is improved. The advantage of b) is the effect of improving the processing efficiency inside the CPU, thereby improving the performance of the CPU. In any case, it is advantageous as a method of enhancing the performance of the CPU itself, and it is thought that the number of CPUs with this architecture will increase in the future. The advantage of this is that there is less interference between pages when a page is accessed, the overhead due to page address mismatch is minimized, and the CPU has separate signal lines for instructions and operand data. The benefits are essentially different. However, the combination of the dynamic memory device of the present invention and the CPU 100a as shown in FIG. 8 can effectively combine the advantageous characteristics of both, and can achieve the highest performance as a whole system. The configuration shown in FIG. 8 is most advantageous in terms of real-time processing performance because no cache memory is involved, and is suitable for dynamic problem processing.

The example in FIG. 9 uses CPIJlooa, which has independent signal lines for instructions and operand data.
This realizes the configuration shown in FIG.

The basic system characteristics are similar to the 5th Wi example, but the 9th Wi
In the case of the example shown in the figure, the performance of the CPU itself can be expected to improve, and therefore, as in the case of FIG. 8, the system performance can also be expected to improve accordingly.

In the example of FIG. 10, as in the case of FIG. 9, the CPU 100a
The configuration shown in FIG. 7 was realized using the following. The basic system characteristics are the same as the example shown in FIG. 7, but the system performance can be expected to improve by the amount of improvement in CPU performance. It has the lowest real-time processing performance, like a mainframe, and is suitable for applications where you want to shorten the average machine cycle and improve average processing performance as much as possible rather than real-time processing performance.

Next, a comparison will be made between a general system and a system using the present invention.

FIG. 11 shows an example of a general high-speed processing processor system using the cache system 114. 12
0 is a general main storage device, which is controlled by a DRAM controller 116. In order to speed up communication between the cache system (consisting of a cache memory 111 and a cache memory controller 112) and the main storage device, the number of bits of the data communication path 117 is increased to make the channel thicker, or the channel is made thicker by using multiple banks. Some systems use memory interleaving in combination with burst transfer to compensate for the slowness of DRAM access. The processor 1 and the cache system are connected by a data communication signal line 4, an address signal line 5, and a control signal line 104. - On the other hand, between the cache system 114 and the main memory 120, there is a data communication path 117, a physical address signal [118] of the main memory, and a control signal line 119.
combined by If the processor 1 does not have a built-in cache memory, communication between the processor 1 and the cache system 114 is based on random access;
Data transfer in blocks is used between cache system 114 and main memory 120. If the processor 1 includes another cache memory system, there is a high possibility that communication between the external cache memory system 114 and the processor 1 will also be data transfer in blocks. The reason why a cache memory system is vulnerable to dynamic problems is as follows.

a) A cache memory system is a memory system with a limited and very small capacity, and when the problem or data to be processed changes dynamically and frequently (for example, interrupt processing), programs and processes that need to be executed in the cache memory are stored in the cache memory. The probability that the required data does not exist increases. therefore,
Access to the main memory system is required, and the overhead for this becomes very large.

b) Communication between the cache memory system and main memory is based on block data transfer, and the processor is idle until the data transfer for a predetermined block is completed.Therefore, this not only causes a direct performance decline, but also reduces performance. Consistency in execution of processing required for time processing is low.

C) Communication itself between the cache memory system and the main memory system is slow.

By using the present invention, the above problems a) to C) can be improved as follows.

1) Regarding problem a), according to the present invention, the main memory system can obtain a random access speed comparable to that of the cache memory, so that the cache memory closest to the main memory system can be removed.

That is, using the example of FIG. 11, the cache system 114 can be removed and the main memory system can be directly connected to the processor. therefore.

This allows the processor to randomly access a huge physical memory space.

2) Regarding problem b), according to the present invention, it becomes possible for a processor to constantly execute high-speed random access to the main memory system, and processing can be executed continuously without interruption. .

3) Regarding problem c), according to the present invention, the main memory system can obtain access performance comparable to high-speed static memory, so there is no need for block data transfer or expansion of the number of transfer bits. High-speed transfer between the main memory system and the main memory system can be realized. If data is transferred between cache memory in the processor, the transfer block can be made very small (ideally, 1 block = 1 word), and real-time processing performance can be improved. .

Next, a method of operating the dynamic memory device of the present invention at a higher frequency to further shorten the machine cycle of the processor will be described.

FIG. 12 shows one of the dynamic memory devices of the present invention.
Two groups (a set of one dynamic memory system 3 and one memory access device 2) are shown. The basic configuration is the same as that shown in FIG. 1, except that the inside of the dynamic memory system 3 is separated into two banks (bank E300 and bank 0301). Along with this, bank E300 and bank o301
In this embodiment, a bank ■ generating means 13a for generating separate ■signals (■E and ■O) and a bank selection means 13b for determining in which bank the ■signal is generated are added. , When data address 7 is an even number, bank E300 is selected and accessed (giving the ■E signal), and when data address 7 is an odd number, bank 0301 is selected and accessed (giving the ■O signal).

do)

The operation and effects of this embodiment will be explained using FIGS. 13 and 14. FIG. 14 shows normal page access (in high speed page mode) using the present invention. BS indicates the bus state of the processor, and in this example, one bus cycle is equivalent to one processor cycle.

Further, in this example, a processor that performs bus access using pipeline bus access is targeted.

Pipeline bus access means one bus cycle (or one processor cycle) in advance.

This access method outputs the address to be used in the next bus cycle, latches that address, and uses it in the actual bus cycle. By adopting this method,
Access that makes full use of the bus cycle time becomes possible. In the future, as the machine cycle of processors becomes shorter, it will become difficult to output an address within a bus cycle and ensure sufficient address access time. It is expected that more and more processors will adopt it. Now, in the present invention, items that are unlikely to cause inter-page access interference are grouped into one group, so within each group, for example, a group of instruction data, a group of array variable data, etc. In other words, when a processor accesses a dynamic memory system allocated to a certain group, data address 7 has a high probability that data is arranged consecutively in the address space. According to the normal page access shown in FIG. 14, in which there is a high probability that ``signal precharge time'' (■precharge time) p t 2 and ■ are activated within one bus cycle time, Access time kept at a
It is necessary to satisfy t2, and in order to secure pt2, at
There is a problem that 2 cannot be made large enough.

This problem can be solved by using the two panther system of the present invention shown in FIG. The time chart shown in FIG. 13 is displayed when a page is accessed according to this embodiment. That is, an even number data address (m in the figure).

When the bus state (BS) has n is an integer), ■
E160 is activated, and when the bus state has an odd number of data addresses, O161 is activated. ■E160 activates bank E300 of dynamic memory system 3.

■O activates bank o301.

From BSxn− to BSxn+x, even data addresses and odd data addresses appear alternately, so
■E160 and ■O161 are activated alternately.

Therefore, by using the period when each bank is not accessed, the precharge time pt of ■E and ■O is
t can be secured. However, BSan+z and B
When changing the data address of Szm, since the even numbered addresses are consecutive (2n+2 and 2m), the same bank, that is, bank E300, is accessed continuously, so there is a possibility that the precharge time cannot be secured. Therefore, when accesses to the same bank occur consecutively, the bank selection means 13b determines this and the W
AIT signal 7c is generated and sent to RAS/■ generating means 13. RAS/■Generation means 1
3 uses the signal line 24a to tell the processor to insert the wAIT state into the bus cycle from the WAIT signal 7c and the generation signal 16 (in the example of FIG. 1, it is sent to the READY signal generation circuit 22). , this inserts a WAIT state called BSWx-.

After securing precharge time for ■E160 with BSzm, ■F with BSWz-! 160 is activated, and accesses to E300 are executed continuously and without contradiction.

Note that even if accesses occur consecutively to the same bank, one or more idle states (cycles in which the processor does not request access to the dynamic memory system 3) are inserted between the two bus cycles. In this case, it is more effective not to generate the WAIT signal 7c.

The bank ■ generating means 13a receives the ■ switching information 7b, and when the ■ generating signal from the RAS/■ generating means 13 is active and the signal 7b indicates access to bank E300, it makes ■ E160 active LO. If signal 7b instructs access to bank 0301, ① O160 is made active LO and applied to bank 0301.

In this embodiment, banks are provided corresponding to even and odd data addresses, but the number n of banks is arbitrary (n≧
22). In that case, the data address is m,
If the bank number is fl (0≦Q≦n-1), use integer operation to divide by m @ n (m÷n), so that the remainder matches the bank number Ω, that is, m = n-. +Q
(fi, m, n.

The bank switching means determines that (all k is an integer) holds, and the switching signal 7b is sent to the bank generating means 13a to generate signals corresponding to each bank. The problem is the same as in the case of the two-vanta system.

It's like that.

With this method, the access time atl of (2) can be shortened and it becomes possible to support processors with faster machine cycles.

Finally, an embodiment in which a refresh cycle generation function is incorporated into the memory access device 2 of the present invention will be described.
This will be explained using FIG. 12. The refresh request generating means 12a sends a request to the RAS/■ generating means 13 for a certain period of time (
refresh request 12c every refresh cycle)
generate.

When the current memory access cycle to the dynamic memory system 3 is completed, the RAS/■ generating means 13
Alternatively, if the RAS signal 15 has been completed, the RAS signal 15 is immediately raised and made inactive, and information indicating that a refresh cycle has started is sent back to the refresh request generation means 12a via the signal 12b, and upon receiving it, the multiplexer 12 is refreshed. Information requesting generation of an address is sent by signal 12d. Multiplexer 12 is provided with a counter for generating a refresh address, and generates a refresh address on signal 14 in accordance with signal 12d. RAS/■ Generating means is sufficient RAS
After securing the precharge time, the RAS signal is lowered and the refresh address is latched into the dynamic memory system 3. Also, after the refresh is completed, raise the RAS signal again to ensure sufficient RAS.
After securing the precharge time, it is effective to lower the RAS signal in order to latch the most recently selected page address in the dynamic memory system 3. Namely.

Thereby, there is a high possibility that the next page access can be started immediately.

〔Effect of the invention〕

As explained above, according to the present invention, a dynamic RAM group for each page is divided into a plurality of groups, with a set of pages storing data that is unlikely to cause access interference between pages as one group, and each By configuring the group's dynamic RAM with memory that responds to page accesses, multiple independently accessible memory systems are prepared, and each memory system is accessed through page accesses, making it possible to use high-speed static memory. It is possible to achieve high-speed access similar to that of a cache memory system and minimize overhead when a page mismatch (page fault) occurs, making it possible to perform high-speed random access similar to that of a cache memory, and also to support many dynamic processing systems that are weak in cache memory systems. This can contribute to increasing the processing speed of a system that includes

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
A time chart for explaining the operation of the device shown in the figure,
FIG. 3 is a diagram for explaining the effect of the device shown in FIG.
Figures 4, 5, and 6. 7, 8, 9, 10, and 11. FIG. 12 is a block diagram showing another embodiment of the present invention, and FIGS. 13 and 14 are time charts illustrating the state of access to a normal page of the present invention. DESCRIPTION OF SYMBOLS 1... Processor, 2a, 2b... Memory access device, 3a... Dynamic memory system for instructions,
3b...Dynamic memory system for data, 4.
...Data bus, 5...Address bus, 6...New page address, 8...Page address latch, 9...
- Old page address, 10... Page address comparison circuit, 11... Comparison signal, 12... Multiplexer,
13...RAS/■ generation circuit, 18...decoder. $4- Figure 5. Amendment to the procedure for closing the Kayabokujikohobroom (method) 1. Indication of the case Patent Application No. 71723 of 1999 2. Name of the invention Memory device 3゜ Person making the amendment Relationship to the case Patent Applicant's name (510) Hitachi Co., Ltd. 4, Tsuyoshi Osamu Address: 5-1 Marunouchi-chome, Chiyoda-ku, Tokyo 100 Name (6850) Patent attorney Grade 5 Figures 13 and 14 of the drawings subject to amendment figure. 6. Contents of the correction Figures 13 and 14 will be corrected as shown in the attached sheet (no other content changes other than the figure number). Graduation 130 Engraving of φTE drawing (no changes in content) Fig. 13

Claims (1)

[Claims] 1. A plurality of dynamic RAMs in which a plurality of memory cells are arranged in a matrix are grouped in page units, and the dynamic RAM group in each page unit stores data that is unlikely to cause access interference between pages. Divide the set of pages in each group into multiple groups, configure the dynamic RAM of each group with a memory system that responds to page access (access by fast page mode, static column mode, or nibble mode), and in response to an access for specifying a page address for each group of memory systems independently, at least one
a storage means for storing an old page address specified before access; and in response to the access to the page address,
determining means for determining whether the new page access specified by this access matches the content of the old page address stored in the storage means; and when the determination result of the determining means is a match, the page access according to the old page address is performed; 1. A memory device comprising a memory access device having paging access means for instructing each group's memory system to access a page using a new page address when the determination results do not match. 2. The memory device according to item 1 above is connected to a processor, and the connection means includes a communication means for obtaining instruction data, which is an instruction code that defines the processing operation of the processor, from the dynamic memory device. a communication means for exchanging operand data to be processed according to an instruction code with the dynamic memory device, the dynamic memory system storing the instruction data; and the dynamic memory system storing the operand data. The memory device according to claim 1, wherein the memory device is divided into two independent groups. 3. In the memory device described in item 2 above, the connected processor has communication means for obtaining instruction data, which is an instruction code that defines the processing operation of the processor, and operands to be processed according to the instruction code. A communication means for exchanging data is provided independently, and the communication of the instruction data and the communication of the operant data are executed in parallel. A dynamic memory system for storing operand data and a memory access device corresponding thereto are allocated, and a dynamic memory system for storing operand data and a memory access device corresponding thereto are allocated to the operand data communication means. Device. 4. In the memory device described in item 1 above, the dynamic memory system constituting at least one group is further divided into n sets of banks (bank number m=0 to n-1).
), and the mth bank (0≦m≦n-1) matches the remainder when the given data address A is divided by n by integer operation (A÷n), that is, A=
A memory device characterized in that a bank access determination means is provided in the memory access device so as to respond only when expressed as a×n+m (A, a, n, and m are all integers). 5. In the memory device according to item 4 above, means for switching the ■signal to the dynamic memory system is provided, and the bank access determining means switches the ■signal applied to the dynamic memory system by the switching means to select the target bank. 1. A memory device characterized in that a switching signal for outputting a signal (1) only is generated and applied to the switching means. 6. In the memory device described in item 4 above, the number of divided banks is n = 2, and the even numbered data addresses are assigned to the first bank, and the odd numbered data addresses are assigned to the second bank. A dynamic memory device featuring: 7. The dynamic memory device according to item 5 above, characterized in that the precharge time of the (1) signal applied to each bank is allocated to a time when that bank is not being accessed. 8. Dynamic RAM is organized in page units, and the dynamic RAM group for each page is divided into multiple groups, each group is a set of pages that are unlikely to cause access interference between pages, and the dynamic RAM in each group is divided into pages. comprising a memory system that responds to accesses, and a memory system for each group that responds to accesses for page addressing of each group, respectively;
A page address storage means for storing an old page address at least one access before this access, and a determining means for determining whether the new page address specified in this access matches the old page address are provided, and the determination result is A memory device that executes page access according to the old page address when there is a match, and executes page access according to the new page address after updating the page to be accessed to a new page when there is a mismatch.