JPH02246350A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To conduct a test accurately in a short time by providing a transistor for testing, which has the same characteristics as those of a tested transistor and to which terminals, test voltage is input from the outside and from which outputs are extracted, are connected. CONSTITUTION:The title device is constituted (IV, IVX, OUT) so that a transistor 4A for testing, the same as a transistor displaying narrow channel characteristics, is included and test voltage is input to the transistor 4A for testing while an output displaying the result of the input is extracted. Consequently, the presence of the generation of narrow channel characteristics in the semiconductor integrated circuit device can be inspected directly. Accordingly, the presence of the generation of the narrow channel characteristics can be inspected accurately in a short time.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device including a transistor having narrow channel characteristics. The purpose is to provide a semiconductor integrated circuit device that can be tested accurately in a short period of time. It is configured to include a test transistor connected to a terminal through which a test voltage can be input and an output can be taken out.

As a result, the product is classified as defective.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device including a transistor having narrow channel characteristics.

As the amount of information to be processed increases, semiconductor integrated circuit devices are required to be faster and more dense.

Such requirements inevitably require miniaturization of device structures. As a miniaturization technique for CMOS transistors, there are cases where the channel width (W) is made smaller and the channel length (L) is made longer. Making the channel width very small and making the channel length long will lead to an increase in the ON resistance of the transistor, and the threshold voltage (V th' will show a very high value as the channel length becomes long due to gate length dependence). Become.

Such characteristics are called narrow channel characteristics.

When such narrow channel characteristics occur, in severe cases, the transistor may not operate properly unless a considerably high gate voltage is applied. [Prior Art] Semiconductor integrated circuit devices affected by narrow channel characteristics Examples of semiconductor integrated circuit devices including inverter latches are shown in FIGS. 4 and 5. FIG. 4 shows a schematic diagram of the IC chip, and FIG. 5 shows a detailed circuit diagram of an inverter latch.

As shown in FIG. 4, a plurality of circuits including inverter latches 2 are formed on the IC chip 1.

This inverter latch 2 has M as shown in FIG.
It includes an OS inverter 3, a feedback inverter 4 made of a CMOS transistor connected in antiparallel to the CMOS inverter 3, and a dry parameter made of a CMOS transistor for driving the CMOS inverter 3.

Under normal conditions, when the logic level of terminal C is “H”, terminal C
In the case of the logic ``L'' level of X, when an ``H'' level is given as the data D, the input side node 7 of the CMOS inverter 3 becomes the logic ``H'' level due to the positive side power supply voltage V 2 C . At this time, the output logic of CMOS inverter 3 is "L'" level, and feedback inverter 4
The input logic becomes "L° level" and the output logic becomes "H" level. This signal state is maintained as long as there is no change in data D and the node 7 is latched to "H". The output signal is "L". Output at level.

In the above inverter latch 2, the feedback inverter 4
is composed of a CMOS transistor (3) whose channel width is much narrower than that of the CMOS inverter (3). Therefore, this feedback inverter 4 may be affected by narrow channel effects.

When a narrow channel effect occurs, the threshold voltage vLh of each transistor of the feedback inverter 4 becomes high, and the transistor cannot be turned on at a normal operating voltage. As a result, if the positive power supply voltage V 1 drops due to some reason, data cannot be held, and the latch is a defective product.

The occurrence of such narrow channel characteristics does not occur incidentally in each IC chip individually, but rather tends to occur in a lot of IC chips or in the same wafer due to manufacturing process-related causes.

I including a transistor exhibiting such narrow channel characteristics
Since the C chip is a defective product and has a defect that prevents it from operating normally, it must be eliminated through testing in advance.

Conventionally, IC chips are placed in high-temperature environments and CMOS
The test time is equal to the time constant of the capacitors of the 30 inverters, and it is confirmed whether or not the data latched in the CMOS inverter 3 changes over time. If there is a change, the data is fed back by the feedback inverter 4. Therefore, the feedback inverter 4 was deemed not to be operating and the product was judged to be defective.

[Problem to be solved by the invention]

However, traditional testing methods require longer testing times;
Furthermore, in a high-temperature environment, the threshold voltage of a transistor decreases, making it impossible to accurately determine whether a narrow channel effect is occurring, making complete inspection difficult.

An object of the present invention is to provide a semiconductor integrated circuit device that includes a transistor that may exhibit narrow channel characteristics and can be tested accurately in a short time.

[Means to solve the problem]

In order to solve the above problems, the present invention provides a semiconductor integrated circuit device including a transistor (4) that has the possibility of exhibiting narrow channel characteristics, which has the same characteristics as the transistor (4), and which is provided with a test voltage applied externally. and
It is equipped with a test transistor (4A) connected to a terminal from which an output can be taken out.

[Effect]

According to the present invention, a semiconductor integrated circuit device includes a test transistor (4A) that is the same as a transistor (4) exhibiting narrow channel characteristics, and a test voltage is applied to the transistor (4A) for testing. The configuration (1, I
, 0UT), it is possible to directly test whether or not narrow channel characteristics occur in the semiconductor integrated circuit device. As a result, it becomes possible to perform inspections more accurately and in a shorter time than in the past.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

First Embodiment FIG. 1 shows a first embodiment of the present invention. In FIG. 1, the same parts as in FIG. 4 are given the same reference numerals, and the explanation thereof will be omitted.

The difference between FIG. 1 and FIG. 4 is that a test circuit 6 is formed within the IC chip 1.

As shown in FIG. 2, the test circuit 6 is a test feedback inverter 4A that is formed in the same manufacturing process as the feedback inverter 4 included in each inverter latch 2 and has the same characteristics as the feedback inverter 4. and the test voltage V, VX (VX is the inverted signal of V).
It has an ND gate 8. The input terminal IvX of the test feedback inverter 4A and one input terminal Iv of the NAND gate 8 are led out to the terminal section of the IC chip 1, and the output terminal of the test feedback inverter 4A is connected to the other input terminal of the NAND gate 8. and the output terminal OU of the NAND gate 8
T is led out to the terminal portion of the IC chip 1 (see FIG. 1).

In the above circuit, when testing the operation, input terminal 1
'H' level on V, positive power supply voltage V on input terminal Ivx
When inputting the 'H2 level C which is lower than the level of , the expected value of the input logic of the NAND gate 8 in normal case is "H" level, and at this time the output terminal O
UT is output at "L" level.

However, if the above logic condition is not satisfied, it can be assumed that the IC chip 1 is defective and that a narrow channel effect is occurring in the feedback inverter 4 included in the IC chip 1. Because the test feedback inverter 4A
are produced in the same lot or in the same manufacturing process as each feedback inverter 4, and can be considered to have the same characteristics.

Conversely, if the test result is normal, the IC
This means that the entire chip 1 can be presumed to be a good product, and its quality can be guaranteed.

In this way, by forming the test feedback inverter 4A as a so-called dummy transistor in advance in the IC chip 1, it is possible to directly judge pass/fail at room temperature, allowing accurate testing in a short time. becomes.

Second Embodiment Next, a second embodiment of the present invention is shown in FIG. In FIG. 3, parts that overlap with those in FIG. 1 are denoted by the same reference numerals, and explanations thereof will be omitted.

The feature of this embodiment is that instead of forming the test circuit 6 separately as shown in FIG. 1, the feedback inverter 4 itself, which is originally formed in the 1c chip 1, can be directly tested. .

That is, a NAND gate 8 is formed near the feedback inverter 4 included in any one of the plurality of inverter latches 2, and a circuit configuration similar to that shown in FIG. , output terminal O
UT is led out to the terminal section of one IC chip. Then, a switching circuit (not shown) is provided so that each of the test circuits 6B, 6C, and 6D is separated from the original circuit in the test mode, and returns to the original circuit configuration in the normal operation mode of the IC chip 1. .

With this configuration, the feedback inverter 4 itself that operates as the feedback inverter 4 during normal operation can be inspected more directly, and the degree of quality assurance when the inspection result is normal can be improved. becomes.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to test the same or itself as a transistor formed in the semiconductor integrated circuit device that may exhibit narrow channel characteristics, which enables more direct and accurate testing. can be done in a short time.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram of a test circuit, FIG. 3 is an explanatory diagram of a second embodiment of the present invention, and FIG. 4 is a conventional semiconductor integrated circuit device. FIG. 5 is an explanatory diagram showing an example of an inverter clutch. 1...IC chip 2...Inverter latch 3...CMOS inverter 4...Feedback inverter 4A...Feedback inverter for test 5...Driver 6...Test circuits 6B to 6D...Test Circuit 7... Node 8... NAND gate V... Positive side power supply voltage C ■... Negative side power supply voltage S rv... Input terminal Ivx... Input terminal ■... Test voltage VX・...Test voltage OUT...Output end leather! ! August 1st implementation column A circuit diagram of test circuit Figure 2 Explanation diagram of the second embodiment of the present invention Figure 3 Explanation showing an example of IC chip conventional semiconductor assembly Y4 circuit Figure 4. Illustration of August showing an example of Impatala Tara. Figure 5.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device including a transistor (4) having the possibility of exhibiting narrow channel characteristics, having the same characteristics as the transistor (4), inputting a test voltage from the outside, And a terminal (I_
1. A semiconductor integrated circuit device comprising a test transistor (4A) to which V, I_V_X, OUT) are connected. 2. The semiconductor integrated circuit device according to claim 1, wherein the test transistor (4A) is a transistor formed exclusively for testing separately from transistors constituting the semiconductor integrated circuit device itself. Integrated circuit device. 3. The semiconductor integrated circuit device according to claim 2, wherein the test transistor (4A) is a transistor arbitrarily selected from transistors constituting the semiconductor integrated circuit device itself. .