JPH02161751A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain element isolating regions reliably by forming isolating grooves on the surface layer of a semiconductor substrate, forming a doped region of the same conductivity type as that of the substrate and having a density higher than that of the substrate on the bottoms of the grooves, depositing a film of BSG or the like on the whole surface to a thickness corresponding to a half or more of the width of the grooves while filling the grooves therewith and etching off the BSG film other than their parts within the grooves. CONSTITUTION:Resist pattern 110 having windows in groove forming regions is formed on the surface of a P-type Si substrate 101 and the exposed surface sections of the substrate 101 are subjected to reactive ion etching so that 1mum wide and 2mum deep grooves 103 having approximately vertical side faces or widened towards the lower end are formed into lattices. Then, a P<+> type region 104 with a density of 1X10<14>/cm<3> or over is formed on the bottom of each groove 103 by ion implantation or the like. An insulating film 105 of SiO2, PSG, BSG or the like is deposited on the whole surface, while the grooves 103 are filled therewith. Unrequired parts of the film 105, namely those outside the grooves 103 are removed by etching. In this manner, the element isolating grooves 103 having the film 105 on the regions 104 can be obtained. Thus, the manufacture of a highly integrated MOSLSI with high performance can be facilitated substantially.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
LSI (Metal Oxide Semic
onductorLarge 5calc Integ
The present invention relates to a method for manufacturing a semiconductor device that improves the isolation technology of C1rcuit.

Conventionally, a selective oxidation method has been generally used as a method for isolating elements in the manufacturing process of semiconductor devices, particularly MO3LSIs. This method will be explained below using an n-channel MO8LSI as an example.

First, a 5i02 film 2 is grown by thermal oxidation on a p-type Si substrate 1 having a < (100) crystal plane as shown in FIG.
Deposit. Next, a resist film 4 is formed on the element forming area by photolithography, and using this as a mask, the Si3N4 film other than the element forming area is etched away to form a Si3N4 pattern 3''.After that, for example, boron ion implantation is performed. Then, a p+ region 5 as a channel stopper region is formed in the field portion (as shown in FIG. 1(b)).

After removing the resist film 4, wet oxidation is performed using the Si3N4 pattern 3' as a mask to selectively grow a thick field oxide film 6 (as shown in FIG. 1(c)). Subsequently, the Si3N4 pattern 3'' and the 5i02 film 2'' are removed by etching to form an element forming region 7 separated by a field oxide film 6 (as shown in FIG. 1(d)). Then the first
As shown in Figure (c), after forming a gate electrode made of polycrystalline silicon in the element formation region 7 via a gate oxide film 8, for example, arsenic is diffused to form n
° form regions to, ii. Finally, a CVD-'S i 02 film 12 as an interlayer insulating film is deposited, and the n' region 1
0. CVD-3i corresponding to I l and gate electrode 9
After opening a bad number of contact holes 13 in the 02 film 12 portion, A and Q wirings 14 are formed to form an n-channel MO3L.
SI is manufactured (as shown in FIG. 1(r)).

However, using the conventional selective oxidation method mentioned above, MO
The method for manufacturing 3LSI has various drawbacks as shown below.

FIG. 2 shows in detail the cross-sectional structure when the field oxide film 6 is formed using the Si3N 1 pattern 3' shown in FIG. 1 ((d)) as a mask.

It is generally known that in the selective oxidation method, the field oxide film 6 grows by digging into the region below the Si3N4 pattern 3- (region F in FIG. 2). This is due to the fact that during field oxidation, the oxidant is
The field oxide film 6 consists of a portion D1 where an oxide film is formed due to diffusion through the two films 2, a so-called bird's beak, and a portion E where a thick portion of the field oxide film 6 wraps around in the lateral direction. F
For example, the length of the Si3N4 pattern 3' is 10
00 people, and the 5i02 membrane 2 below it is 1 under the condition of 1000 people.
When the field oxide film 6 is grown to a thickness of 1 μm, the thickness reaches approximately 1 μm. Therefore, the width C of the field area is S
If the distance MA between the i3N4 patterns 3' is 2μIn,
Since F is 1 μm, it cannot be made smaller than 4 μm, so LSI
This is a major hindrance to the integration of For these reasons, we have recently developed a method of increasing the thickness of the Si3N 1 pattern 3- and thinning the underlying 5i02 film 2 to suppress bird's beak (part 0 in the figure), as well as methods of increasing the growth thickness of the field oxide film 6. Attempts have been made to reduce the thickness of the field oxide film and to suppress the penetration (F) of the field oxide film. However, in the former case, the stress at the edge of the field becomes large and defects are likely to occur, and in the latter case, there are problems such as a low field inversion voltage, and there are limits to island integration using the selective oxidation method.

In addition, when a channel stopper is provided, boron ion-implanted for the channel stopper is re-diffused laterally during field oxidation, and a part of the element forming region 7 becomes the p1 region 5 as shown in FIG. 3(a). Therefore, the effective device area becomes narrow from the width of G to the width of H. As a result, narrow channel effects such as a decrease in transistor current and an increase in threshold voltage occur, which becomes a problem as devices become smaller. Furthermore, by expanding the p+ region in the lateral direction, the junction between the n+ region 11 (10) and the p+ region 5 in the element forming region 7 becomes wider, as shown in FIG. The floating capacitor between 1 and 1 becomes large. This floating capacitor cannot be ignored as the device becomes smaller.

As described above, when the selective oxidation method is used, various problems arise in the integration of LIS, and the following problems arise. This will be explained with reference to FIG.

Substrate 1 to package the completed LSI pellet
Mount it on bed 15 of the package.

In the operating state of the LIS, the potential of each element region 1 (i1 to 103) such as the source and drain varies arbitrarily depending on the circuit operation.
A displacement current will flow in accordance with the variation in the potential of q.

For example, element region 18. The displacement current for bed 15
is conductive and the substrate 1 and the bed 15 are electrically connected, for example, element region 161 = resistor R1 - bed 15, element region 161 - resistor R2 - bed 151, element region 161 - resistor R.

The voltage flows through buses such as the bed 15, etc., and the potential of the element region 1G and the nearby substrate 1 fluctuates by this voltage drop. Such variations in substrate potential are unfavorable in terms of circuit operation. In particular, the voltage in the element region 1B+ fluctuates,
If the element region 162 does not change, the element regions 161 and 1
The potential of the substrate 1 in the vicinity of 132 also differs, resulting in an inconvenience in that the device characteristics differ depending on the location on the pellet. To improve this, it would be better to reduce the resistance in the board, but resistors R5 to R8r R9
~ R11 etc. are determined by the relationship between the concentration of the substrate set from the element characteristics and the film thickness of the substrate when connecting the substrate to the bed, and the value for boat fishing is about 1009 to several 100 Ω. It is difficult to reduce this to an extreme level.

Since the resistors R and -R5 are in the field region 6, they should originally be lowered regardless of the device characteristics. however,
With the method described above, the concentration of pl cannot be increased and the resistance is extremely high. For example, field ion implantation El I
At approximately X 1013/cd, the sheet resistance of the p+ layer is approximately 10:97 or more.

(Problems to be Solved by the Invention) The present invention has been made to solve the above-mentioned conventional problems, and is a method for manufacturing a semiconductor device that achieves high integration and high performance by establishing a new element isolation method. This is what we are trying to provide.

[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention will be described in detail above.

The first invention of the present application will be explained in detail.

First, a mask material, such as a resist pattern, from which a portion where a groove is to be formed is removed is formed on a semiconductor substrate, and then a portion of the substrate exposed from the mask material is selectively etched to a desired depth to form a groove. In this case, if reactive ion etching or reactive ion etching is used as the etching means, it is possible to provide a groove portion with vertical side surfaces. However, the groove portion having reversely tapered side surfaces may be provided by other etching means. One or more grooves may be provided in the substrate, and the depth of the grooves may be changed.

Next, using a mask material such as a resist pattern as a mask, impurities of the same conductivity type as the substrate are added to the groove (for example, boron if the substrate is p-type, phosphorus if it is n-type).

Arsenic, etc.) is implanted or diffused by ion implantation or a diffusion method at a dose of I x 1014/c- or more to form an impurity region. Doping with impurities is not limited to the case where all the grooves are doped; it may also be carried out only on some grooves or a part of the grooves by blocking a part of the groove or some other grooves by photolithography or the like. Further, this doping may be performed on the side surfaces of the trench by oblique ion implantation or lateral diffusion.

Subsequently, after removing the mask material, an insulating material is deposited over the entire surface of the semiconductor substrate including the grooves to a thickness equal to or more than half the short width of the opening of at least one groove to insulate the opening of at least one groove. Fill with materials. Examples of such an insulating material include 5i02. Si3N4 or L' is Ag2
03, and in some cases, phosphorus silicide glass.

A low temperature melting insulating material such as boron silicide glass may also be used. As a means for depositing this insulating material, a CVD method, a PVD method such as a sputtering method, etc. can be used. Furthermore, during this deposition, if the insulating material is deposited to a thickness less than half the short width of the opening of the groove, a concave hole communicating with the opening will be formed in the insulating material embedded in the groove, and during etching, The disadvantage is that the insulating material within the groove is etched through the recessed hole. Note that, prior to depositing the insulating material, the entire semiconductor substrate having a groove, or at least a portion of the groove, may be oxidized or nitrided to grow an oxide film or a nitride film to an extent that the groove is not blocked. At this time, impurity doping may be done before or after oxidation or nitridation. By using such a h method in combination, the obtained field region is composed of an insulating material formed by depositing a highly dense oxide film or nitride film in contact with the substrate in the trench, and only the insulating material is used. The element isolation performance can be significantly improved compared to the one consisting of the following. Furthermore, after depositing the insulating material, a low-temperature melting substance such as boron or phosphorus is applied to the entire or part of the surface layer of the insulating film.

Either arsenic or the like is doped and heat treated to melt the doped layer of the insulating film, or a low-temperature melting insulating material such as boron silicide glass (BSG), phosphorus silicide glass ( PSG) or arsenic silicide glass (A s S G), etc. may be deposited, and this low-temperature melting insulating film may be melted, or any one of the following treatments may be performed. By adopting such a method, if the part corresponding to the groove becomes concave due to the deposition conditions of the insulating material, the concave part can be filled and flattened, and as a result, the insulating material remaining in the groove can be removed when the entire surface is etched. This has the effect of preventing the inconvenience of being below the level of the opening.

Next, the insulating film deposited on the semiconductor substrate is removed by etching without using a mask material until the semiconductor substrate portions other than the groove are exposed to form a field region in which the insulating material remains in the groove. As the etching means in this step, for example, a whole surface etching method using an etching solution or a plasma etchant, an active ion etching method, a soching method, etc. can be adopted. Thereafter, active elements such as MOS and bipolar are formed in element formation regions separated by field regions to manufacture a semiconductor.

According to the first invention of the present application, a groove is provided in a semiconductor substrate, a part of the groove is doped with an impurity of the same conductivity type as the substrate at a predetermined dose, and an insulating material is applied to the entire surface of the substrate including the groove. After the insulating film is deposited to a thickness that is more than half the short width of the opening of at least one trench, the insulating film is etched until the parts of the substrate other than the trench are exposed. On the other hand, a buried diffusion layer can be provided with self-line, and an insulating material can be left on top of it, which can form a field region.
A semiconductor device having various effects as shown below can be provided.

(1) Since the area of the field region is determined by the area of the groove portion prepared in advance on the substrate, the desired fine field region can be easily formed by reducing the area of the groove portion.
^ It is possible to obtain a semiconductor device with a high degree of integration.

(2) The depth of the field region is determined by the depth of the groove provided in the substrate, regardless of the area, so the depth can be arbitrarily selected, and current leakage between elements can be prevented in the field region. This can be reliably prevented and a high-performance semiconductor device can be obtained.

(3) After forming the groove and selectively doping the groove with an impurity to prevent inversion, the impurity region is regenerated because it does not require a high-temperature, long-time thermal oxidation process like the conventional selective oxidation method. It is possible to diffuse and extend to the surface of the element forming region, thereby preventing reduction of the effective field area. Furthermore, it is also possible to prevent out-diffusion of impurities and doping of the substrate surface with impurities. In this case, if the impurity doping is performed by ion implantation, the impurity ion implantation layer can be formed at the bottom of the trench, and even if the ion implantation layer is re-diffused, it will still reach the surface layer of the element formation region (element formation area). Since it does not extend, reduction of the effective field area can be prevented.

(4) As a result of (3) above, the concentration of impurity doping can be increased, the resistance of the impurity region can be lowered, and the inconvenience of fluctuations in substrate potential and substrate potential differing depending on the location on the chip can be corrected. Can be done.

(5) When a field region is formed by leaving insulating material in all of the grooves, the substrate is flattened, which prevents breakage from occurring during subsequent electrode wiring formation.
can.

Next, the second invention of the present application will be explained in detail.

After doping the impurity into the groove at a predetermined dose through a process similar to that of the first invention described above, an insulating material is applied onto the semiconductor substrate at least in the short width of the opening of one groove provided in the substrate. Deposit to more than half the thickness. Next, at least one of the region of the insulating film including a part of the trench filled up to the opening with an insulating material or the region of the insulating film that is to become a field region other than the trench is covered with a mask material, for example, a resist pattern. cover. Subsequently, etching is performed until the mask material and parts of the substrate other than the grooves are exposed, and the insulating material is left in the grooves to form a field region and also on the substrate other than the grooves.

In this case, the field regions formed on the substrate other than the trench include those that are integrated with the field region of the trench. Thereafter, active elements such as MOS and bipolar are formed in element formation regions separated by field regions to manufacture a semiconductor device.

According to the second invention of the present application, in addition to achieving the various effects described above, the field region embedded in the semiconductor substrate and the field region on the conductive substrate other than the groove portion are integrally formed with the field region. Alternatively, it is possible to obtain a semiconductor device having separate field regions of different shapes.

Next, the third invention of the present application will be explained.

First, after forming a mask material, such as a resist pattern, from which at least two or more proximate groove formation areas are removed on a semiconductor substrate, the portion of the substrate exposed from the mask material is removed to a desired depth by the same means as described above. Selective etching provides at least adjacent first grooves. In this case, the first groove may have a configuration in which, in addition to two or more adjacent groove groups, one or more grooves are provided in a portion of the substrate that is distant from this groove group.

Subsequently, the first groove is doped with an impurity of the same conductivity type as the substrate at a predetermined dose using a mask material. Subsequently, after removing the mask material, an insulating material is deposited over the entire surface of the semiconductor substrate including the first trench to a thickness that is at least half the short width of the openings of two or more adjacent trenches, thereby forming a barrier between the trenches. Fill the opening with insulating material. Examples of such an insulating material include 5i02. Si3N, 1 or Ag
2O3, etc. In some cases, low-temperature melting insulating materials such as phosphorus silicide glass (PSG), arsenic silicide glass (AsSG), and boron silicide glass (BSG) may be used. Examples of the means for depositing such an insulating material include a CVD method, a PVD method such as a sputtering method, and the like. Note that a channel stopper region may be formed in the substrate by selectively doping a portion of the first groove with an impurity having the same conductivity type as the substrate prior to the deposition of the insulating material. Furthermore, prior to the deposition of the insulating material, the entire semiconductor substrate having the first groove portion, or at least a portion of the groove portion, is oxidized or nitrided to grow an oxide film or nitride film to an extent that the groove portion is not blocked. Good too. Additionally, a low-temperature melting insulating material may be formed after the insulating material is deposited as described above.

Next, the insulating film deposited on the semiconductor substrate is removed by etching without using a mask material until portions of the semiconductor substrate other than the first groove are exposed, leaving the insulating material in at least two adjacent grooves. As the etching means in this first step, for example, an entire surface etching method using an etching solution, a plasma etchant, or even active ion etching can be adopted.

Next, a portion of the semiconductor substrate between two or more adjacent trenches is selectively etched, leaving an insulating material behind, to provide a second trench between adjacent first trenches. In this case, the first grooves are filled with an insulating material, and the semiconductor substrate between the grooves to be etched has selective etching properties with respect to the insulating material, so that two or more adjacent first grooves are partly etched. Even if etching is performed in an exposed state, the second groove can be formed with self-line in relation to the first groove. Next, after doping the second groove with an impurity of the same conductivity type as the substrate as necessary, an insulating material is applied to the entire surface of the semiconductor substrate to a thickness that is more than half the short width of the opening of the second groove. accumulate.

The insulating material used here may be the same as described above. Subsequently, the insulating film is etched until the main surface of the semiconductor substrate is exposed, leaving the insulating material in the second groove, and is integrated with the insulating material left in the first groove on both sides of this groove to form a wide field. Form a region. After that, MOS is installed in the element formation region separated by the field region.
A semiconductor device is manufactured by forming active elements such as bipolar.

According to the present invention, the excellent effects <1) to (5) described above can be achieved, and an arbitrary wide field region without steps can be formed, resulting in higher integration and higher performance. In addition, a semiconductor device that achieves high reliability can be obtained.

Next, the fourth invention of the present application will be explained in detail.

First, after forming a mask material, such as a resist pattern, from which a groove portion is to be formed on a semiconductor substrate, the portion of the substrate exposed from the mask material is selectively etched to a desired depth using the same means as described above. 1 groove is provided.

Next, an impurity having the same conductivity type as the substrate is applied to at least a portion of the first groove using a microphone material.
Doping is carried out at a dose equal to or higher than the above. Subsequently, after removing the mask material, the entire surface of the semiconductor substrate including the first grooves is filled with an insulating material in the same manner as described above to fill the grooves.

Next, the insulating film on the semiconductor substrate is removed by etching without using a mask material, leaving the insulating material in the first groove. Subsequently, an oxidation-resistant film is selectively formed directly or via an insulating layer on the main surface of the semiconductor substrate where the insulating film remains.

Such an oxidation-resistant film is Si3N4 film, AJ7203.
Examples include membranes and the like. Subsequently, using the oxidation-resistant film as a mask, selective etching is performed between the first trenches to form second trenches. After that, field oxidation is performed using this oxidation-resistant film as a mask, and a wide field region is formed by filling the space between the first trenches with acid (1) and integrating it with the insulating film left in the first trench. do.

(Example) Next, an example in which the present invention is applied to manufacturing an n-channel MO3LSI will be described with reference to the drawings.

Example 1 First, a p-type silicon substrate 10 having a (100) crystal plane was prepared.
A resist pattern 102 in which the groove portions were to be formed was removed was formed on the resist pattern 102 by photoetching (FIG. 5(a), not shown).

Subsequently, the silicon substrate lot was etched by reactive ion etching using the resist pattern 102 as a mask. At this time, as shown in FIG. 5(b), a lattice-shaped groove 103 having nearly vertical side surfaces and having a width of 1 μm and a depth of 2 μm was formed.

Subsequently, using the same resist pattern 102 as a mask, boron, which is an impurity having the same conductivity type as the substrate 101, is applied at an acceleration voltage of 50 keV and a dose of m I x 1016/cl.
(7) After ion implantation under the conditions, heat treatment is performed to
A p-domain region 104 was formed at the bottom of 03 to prevent inversion (as shown in FIG. 5(e)).

Next, after removing the resist pattern 102, 5i0
2 was deposited by the CVD method so that the thickness (0.8 μm) was more than half (0.5 μm) of the width (S) of the opening of the groove portion 103. At this time, 5to2 is the substrate 101 and the groove 1.
CVD-8i02 was gradually deposited on the inner surface of 03 and was fully filled up to the opening of the groove 103 as shown in FIG. 5(d).
A film 105 was formed. It should be noted that during this deposition, rediffusion of the p1 region 104 hardly occurred because the high-temperature, long-time thermal oxidation treatment as in the selective oxidation method was eliminated.

Next, coat the CVD-5i02 film 105 with ammonium fluoride.
The entire surface of the silicon substrate 101 other than the groove 103 was etched until it was exposed. At this time, CVD on the substrate 101
-S i 02 film portion is removed by the film thickness, and CV D -S is removed only in the groove 103 as shown in FIG. 5(e).
iO2 was left behind, 1 thereby forming a field region 10B embedded within the substrate lot. after that,
They were separated in a field area 10G according to a conventional method. A gate electrode 108 made of polycrystalline silicon is formed in the Q-shaped element formation region via gate oxidation @107, and arsenic is diffused to form n+ regions 109 and 1 as sources and drains.
10 was formed. Furthermore, an interlayer insulating film 111 made of CVD-5i02 is deposited, and a contact hole 112 (the contact hole for the gate electrode is not shown) is opened in the interlayer insulating film txt portion corresponding to the gate electrode 108 and the n+ region 109, 110. After that, an /it film was deposited on the entire surface and electrode separation was performed to form a source extraction AI electrode 113, a drain extraction AJ electrode 4, and a gate extraction Afi electrode (not shown), thereby manufacturing an n-channel MO3LSI (
FIG. 5 (illustrated in ).

In the MO5LSI obtained in Example 1, since the field region 10B is determined by the width of the groove 103, it can be made into an extremely fine area with a width of 1 μm, which reduces the area occupied by the field region in the LSI and increases the height of the field region. We were able to achieve integration. Furthermore, when a field oxidation layer 6 with a narrow width is formed using the conventional selective oxidation method as shown in FIG. tended to flow more easily. On the other hand, although the field region 10B of this embodiment has a narrow width as shown in FIG. 7, its depth is sufficiently large, for example, 2 μm, so that the distance between the n' layers can be sufficiently long.
It was possible to prevent leakage current from flowing between the layers.

Furthermore, the silicon substrate 10 after the field region 10B is formed
1, as shown in FIG. 5(e) in the above process, there is no step difference between the field region and the element forming region, and the area is flat.
When the electrodes 113 and 114 were formed, it was possible to prevent a break from occurring between the field region and the element formation region.

Furthermore, since there is no field oxidation as in the selective oxidation method, it is possible to prevent defects in the silicon substrate due to the stress generated when the field oxide film digs into the Si3N layer. Furthermore, the p' region 104 can be highly concentrated and have a low resistance (sheet resistance of 10 to 2007), which improves the inconvenience of fluctuations in substrate potential and variations in substrate potential depending on location. can.

Note that in the first embodiment, after forming the resist pattern 102 directly on the silicon substrate 101, the groove portion 103 was provided in the substrate lot using this resist pattern as a mask.
As shown in FIG. 8(a), after depositing an insulating film 115 on a silicon substrate 101, a resist pattern 102 is placed on the insulating film 115.
is formed, and using this as a mask, the insulating film 115 is etched by reactive ion etching to form an opening l16.
This may be carried out by a step of providing a groove 103 in the substrate 01 below it (as shown in FIG. 8(b)). In this case, after patterning the insulating film 115 of the silicon substrate 101 as shown in FIG. 9(a), reactive ion etching may be performed using this insulating film as a mask to form the groove 103 (see FIG. 9(b). ).

Example 2 First, a p-type silicon substrate 1 shown in FIG.
3fI whose opening width is different from S, Si, and S3 by photolithography using reactive ion etching in 01.
I! Grooves 103, 103' and 103' were provided. Note that the relationship between the widths of the openings is Sl<32<S3.

Next, using the same method as in Example 1, the groove was doped with an impurity (boron) at a seed amount of, for example, lXl0''/e- to form a p region.At this time, the groove S3 was formed with a resist using photolithography or the like. No cover impurity doping was performed.Subsequently, 5i02 was formed into the groove portion 103' by CVD.
The film was deposited to be slightly thicker than 1/2 of the width (Si) of the opening. At this time, Fig. 10(b) 1. :Groove portion 103.103' I:CV D-3i02 film 10 as shown
5 is fully filled up to the opening, but the grooves 103 and 10
CVD-5 is used in the groove 103'' whose opening width is larger than 3'.
iO□@105 was deposited only on the inner peripheral surface, and a concave depression 117 was formed.

Next, when the thickness of the CVD-5i02 film 105 on the substrate 101 (approximately S2/2) was etched with ammonium fluoride, as shown in FIG.
,,52(7) Groove 103.103'l,: 4;i
CV D -8iO2 is left in the predetermined field area 10B.

10G' forms t'L t knee 1)<, groove 103
(7) All of the CVD-5i02 was removed to form a concave portion. These concave portions can be used as the VMO8 region in subsequent steps, and the photo-etching process for creating the four parts again after the field region is formed can be omitted. was completed.

Example 3 First, as shown in FIG. 11(a), a p-type silicon substrate 10 is prepared.
1, the widths of the openings are sl, Si, S, by photolithography using reactive ion etching.

A groove 103'' that changes intermittently from S3 is provided.
The width of the opening in the groove 103' is S, <82 <
The relationship is 83. Then, add boron to I x 10]6/
A CVD-3i02 film is doped with CD at a dose of 2 and deposited by CVD to be slightly thicker than 1/2 of the width of the opening (Si). CVD on the substrate 101 after being deposited on the inner circumferential surface of the part with an opening width of 83.
When etching was performed with ammonium fluoride by the thickness of the S i O2 film, the opening had a width of S, as shown in Fig. 11(b).
, Si 1. :cVD-3i 02 film 105 remained, and a portion of the same width S3 was removed to obtain an open field region LH''.

Example 4 First, as shown in FIG. 12(a), a p-type silicon substrate 1
A plurality of grooves 103, . 1
After forming the holes 32, 103j, and 103J, a p-type impurity such as boron is doped at 1 x 1016/ci to form a p+ region 104, and the grooves 5i02 are formed by CVD to form each trench I03. The CVD-3i02 film 105 is deposited to a thickness that is more than half the width of the opening of ~1034.
was formed (as shown in FIG. 12(b)).

Next, the C applied from the substrate 101 to a part of the groove 1032 is
VD-8i02 film 105 part, groove part 1033 CVD-8iO□ film 10 extending from the no part to part of the groove part 103.1
A resist film 118+ is formed on the film portion 05 and the CV D Si O2 film 105 portion on the substrate toi by photolithography.
, 1182, 1183 (Fig. 12 (
c) As shown). After that, resist film 118+ = 118
3 and the grooves 1031 to 1034 were etched with ammonium fluoride until the parts of the substrate 101 other than the grooves 1031 to 1034 were exposed.
As shown in Figure 2(d), CVD-03 is inside the groove ioa.
Field region 108 left by J Si02, field region 1061 formed by integrating CVD-5i02 left in the trench and CVD SiO2 left on the substrate 101, ? g parts 1033 and 103
,,1. : A field region 1062 formed by integrating the remaining CVD-5i02 and the CVD-3in2 left on the substrate 101, and a wide field region 10 consisting of the CVD-3i02 left on the substrate 101.
6"' was formed. When providing a plurality of MOS transistors on such a silicon substrate 101 according to a conventional method, the substrate 1
Metal wiring could be formed using the field region 10G+, 160□, to6'' in which the CVD SiO2 on 01 remained.

Immediately after providing the p+ region 104 in Example 4, boron doping is performed using the resist pattern 118' formed by photolithography as a mask to form the p" region 104 under the field region 10G11062 formed in the subsequent process. may be formed (Fig. 13<:a>, (b
). Further, if necessary, a part of the p+ region 104' may be made into an n+ region and used as a wiring layer.

Example 5 First, three grooves 103. each having the same opening width were formed on a lot of p-type silicon substrate by photolithography using reactive ion etching. , 1032. After providing 103, ions such as boron are implanted (1x 101b/
cd) The p+ region 104 is formed in the groove 1 by optical etching.
A resist pattern 119 was formed in which a portion of the substrate 101 between 032 and 1033 was removed (as shown in FIG. 14(a)). Subsequently, the surface of the substrate 101 between the grooves 1032 and 1033 was etched using the resist pattern 119 as a mask to form a removed portion 120, and then the resist pattern 119 was removed (as shown in FIG. 14(b)). Note that the p+ region 104 may be formed after this.

Next, 5i02 is formed into each groove part 1031 to 1 by CVD method.
It was deposited so that it was slightly thicker than half the width of 033. At this time, as shown in FIG. 14(e), the groove 103+ -10
33 is sufficiently filled with the CVD-5i02 film 105, and the CVD-5i0 film 105 corresponding to the removed portion 120 is
The 105'' portion of the second film was depressed more than the other areas.

Next, as shown in FIG. 14(d), the depressed portion of the CVD-3i02 film 105 due to photolithography is coated with resist 11+.
21, the resist film 121 and the grooves 103, -
When etching was performed with ammonium fluoride until the parts of the substrate 101 other than 1033 were exposed, grooves 1031 to 1033 were etched.
Field area 106 left by CVD-5iO□
．． ~1063 and groove portion 1032.

A wide CVD-5t02 that is integrated with the CVD S i 02 of 1033 and whose top surface is at the level of the substrate 101.
A field region 10 [i'''' was formed consisting of (
(Illustrated in FIG. 14(C)). Such a silicon group 11i 1
When a plurality of MOS transistors are provided on the substrate 101 according to a conventional method, metal wiring etc. can be formed by using the wide field region 106'' made of CVD-5i, O□ on the substrate 101, and the field region 10B Since "" is at the same level as the board lot, it was possible to prevent the wiring from breaking.

Note that as shown in FIG. 15, an n+ region 104a as a diffusion wiring layer may be formed in the substrate region below the field region 100''.

Example 6 First, a p-type silicon substrate 20 with a (100) crystal plane was prepared.
! A resist pattern 202 from which the groove portions were to be formed was removed by photoetching was formed thereon (as shown in FIG. 16(a)).

Subsequently, the silicon substrate 20+ was etched by reactive ion etching using the resist pattern 202 as a mask. At this time, as shown in Figure 16(b),
A plurality of first grooves 2031 to 20 with nearly vertical side surfaces
35 were formed. Note that the groove portion 2031 has a width of 1.5 p.
The grooves had dimensions of 2 μm and 7R, and were provided at a sufficient distance from other grooves. - The blade grooves 2032 to 2035 each have dimensions of 1 um in width and 2 um in R4, and are provided close to each other with an interval of 1 um. Subsequently, using the same resist pattern 202 as a mask, boron, which is an impurity of the same conductivity type as the substrate 201, is applied at an acceleration voltage of 50 KeV and a dose of ji.
After ion implantation under the conditions of ilX1016/C-, a heat treatment was performed to form a p+ region 204 as an inversion prevention layer at the bottoms of the grooves 2031 to 2035 (as shown in FIG. 16(e)).

Next, after removing the resist pattern 202, 5i0
2 to half the opening width (0) of the groove 2031 by CVD method.
, 75 pm) or more (1.0 μm). At this time, 5i02 is on the substrate 201 and in the groove 20.
Fig. 16(d)
As shown in FIG. 2, a CVD-3i02 film 205 was formed which was sufficiently filled up to the openings of the grooves 2031 to 2035. It should be noted that during this deposition, re-diffusion of the p'' region 204 hardly occurred because the high-temperature, long-term heat treatment such as in the selective oxidation method was eliminated.

In the next step, the entire surface of the CVD S f O2 film 205 was etched with ammonium fluoride until the main surface of the silicon substrate 201 was exposed. At this time, CVD-5102 on board 20+
Only the thick bone of the M portion is removed, and CVD-
5i 02205 left behind.

Next, the first groove portions 2032 to 2032 provided close to each other
Residual CVD in grooves 2032 to 2035 at both ends of 2035
-3i After covering a portion of 02205 except the area between the grooves with a resist film 206, reactive ion etching was performed. At this time, as shown in FIG.
The portions of the silicon substrate 201 in between were selectively removed to form three second grooves 207 to 2073 having nearly vertical side surfaces and each having a width of 1 μm and a height of 2 μm. Subsequently, the resist film 206 is masked and boron, which is an impurity of the same conductivity type as the substrate 201, is ion-implanted under the conditions of an acceleration voltage of 50 KcV and a dose of m 1 x 10'''/cd, and then heat treatment is performed to form the second impurity. Grooves 2071-2
A p+ region 204 as an anti-inversion layer was formed at the bottom of the resist film 20 (as shown in FIG. 16(g)).
After removing 6, 5LO2 is deposited in the CVD groove part 207.
1 to 2073 (7) The film was deposited to a thickness (0.8 μm) that was at least half the width of the opening (0.5 μm). At this time, 5i02 is located on the substrate 201 and the second groove portions 2071 to 2.
The CVD-3i02 film 208 was gradually deposited on the inner surface of the CVD-3i02 film 208, and was sufficiently filled up to the openings of the second trenches 2071 to 2073, as shown in FIG. 16 (11). Note that during this CVD process, the p+ region 204' at the bottom of the first grooves 2032 to 2035 and the second grooves 2071 to 2073 are removed.
The bottom p+ region 204' was integrated to form a wide p1 region 204.

Next, the VD-8i02 film 208 was etched with ammonium fluoride until the main surface of the silicon substrate 201 was exposed. Only part of the thick bone is removed, and CVD-S i
0220&'# remains, and these grooves 2071 to 2073
CVD left in the first grooves 2032 to 2035 on both sides
- Wide width (by integrating with 8i 02205')
A field region 209 of 7 μm) was formed. In addition,
CVD-9i02205 left in the first groove 2031
is used as a field region 209' having a width of 1.5 μm. Thereafter, a gate electrode 211 made of polycrystalline silicon is formed via a gate oxide film 210 in an island-shaped element formation region separated by a narrow field region 209' and a wide field region 209, and arsenic is diffused to form a source. , n' regions 212 and 213 were formed as drains. Furthermore, an interlayer insulating film 214 made of CVD-3i02
are deposited to form gate electrodes 2+1 and n′ regions 212, 2
A contact hole 2I5 is formed in the interlayer insulating film 214 portion corresponding to 13 (the contact hole for the gate electrode is not shown).
After opening the hole, an Ag film is vacuum-deposited on the entire surface, and electrode separation is performed to form a source extraction AJ electrode 21B1, a drain extraction AJ electrode 217, and a gate extraction Al electrode (not shown) to form an n-channel MO3-LSI. Manufactured (
(Illustrated in FIG. 16(j)).

The MO3LSI obtained in Example 6 has a narrow field region 209' and a wide field region 20g, and the silicon substrate 201 after forming the field regions 209 and 209' is shown in FIG. 16 (1) in the above step. jealous,
Since there is no step difference between the field region and the element formation region, and the structure is flat, the structure is advantageous against step breakage between the field region and the element formation region when the AN electrodes 218 and 217 are formed. . In addition, the p′ regions 204 and 204°, which serve as buried diffusion regions, are the groove portions 203,
, 2032 to 2035, and 2071 to 2073, the LS does not diffuse to the element formation region.
It greatly contributed to the integration of I.

Sate, this practical side 1. t CV D Si A p+ region was provided in both parts under the O2 film 205 and 208, but
It is sufficient that at least one of them is a p+ region (as shown in FIGS. 17(a) and 17(b)). Furthermore, CVD-5i0
Rather than the entire area under the two films 205' or 208', only a part of the area may be a p'' region.
Only one of the 102 films 205' and 208' may have a p+ region, and the CVD-8i02 film 2
Regardless of 05' and 208', the p1 region and the 11 region (wiring layer) may coexist by using photolithography or the like. In particular, as shown in FIG.
If it is set to 4a, there is a margin for preventing field inversion. Further, in the sixth embodiment, after providing the first groove portion or the second groove portion in the semiconductor substrate, an oxide film or a nitride film may be grown on the entire surface of the semiconductor substrate or at least a part of the groove portion. In this case, impurity doping may be performed before or after the formation of the oxide film or nitride film.

In Example 6, after depositing an insulating material on a semiconductor substrate provided with at least a first groove, or after depositing an insulating material on a semiconductor substrate provided with a second groove, the whole or part of the surface layer of the insulating film is heated at a low temperature. The doping material may be doped and the doped layer of the insulating film may then be melted.

Furthermore, in this Example 6, after depositing an insulating material on the semiconductor substrate provided with at least the first groove, or after depositing the insulating material on the same substrate provided with the second groove, the insulating material is deposited on the entire or part of the insulating film. A low-temperature melting insulating film may be deposited and then melted.

Example 7 First, a silicon substrate (p type, crystal orientation: (100)
) 301 using a photolithography method etc. to form a resist film 302.
Patterning is performed (as shown in FIG. 19(a)).

1. Using the resist pattern 302 as a mask. Machining and notching are performed to form a narrow groove portion 303 with vertical or nearly vertical side surfaces. The depth of this groove portion 303 is, for example, 2 μm. Further, the etching/soching method may be ion etching or active ion etching (as shown in FIG. 19(b)).

Next, using the resist pattern 302 as a mask, for example, boron is doped at an acceleration voltage of 50 keV s ff1I.
Ion implantation is performed under the condition of XIO''/c- to form a p° region inversion prevention IL layer (IL layer) 304 at the bottom of the trench 303 (first
Figure 9 (C) diagram). After peeling off the resist pattern 302, the thickness of the resist pattern 302 is at least half the width of the groove 303 (for example, the groove 303).
The width of 3 is 1. Ojtm, the film thickness is 0.5 μm or more, such as 0.6 μm) (for example, CVD5i0
2 film or Si3N4 film) 305 is deposited to fill the trench 303 (as shown in FIG. 19(d)). The insulating film layer 1 is etched until the silicon base 11Z301 is exposed. As a result, the field insulating film 30 is buried only in the groove portion 303.
5. , 3052. 3053 remains (Figure 19(e)
(Illustrated).

Next, a thin insulating film (for example, 5
00 thermal oxide film) 306 is formed, and this insulating film 306
Oxidation resistant film on top (e.g. 3000 Si3N, 1 film)
307 (as shown in FIG. 19(f)). Buried field insulating films 305, ~3053 using photolithography
The resist film 308 is placed so that all or part of the boundary is on top.
Buttering. Then, using this resist film 308 as a mask, the oxidation-resistant film 307 is etched, the thin insulating film 306 is etched, and the silicon substrate 301 is etched.
A groove 309 is formed by etching. When etching this silicon substrate 301, the buried field insulating films 3051 to 3053 are not etched at all or are hardly etched (No. 19).
Figure<g>Illustrated). Note that the resist film 308 may be peeled off before etching the thin insulating film 30B or the silicon substrate 301, and the subsequent etching may be performed using the oxidation-resistant film 307 as a mask. Also, the etching depth of the silicon substrate 301 will vary depending on the subsequent oxidation conditions, etc.
For example, here it is assumed that there are 5,000 people.

Next, using the resist pattern 308 (the oxidation-resistant film 307 if the resist pattern 308 is peeled off in the above step) as a mask, for example, arsenic or phosphorus is applied at an accelerating voltage of 50 eV.
, an n+ region 310 is formed at the bottom of the trench 309 by ion implantation at a dose m I
(Figure 9 (h) shown). Next, resist pattern 308
After stripping off the oxidation-resistant film 307, field oxidation is performed using the oxidation-resistant film 307 as a mask to form the buried field insulating film 3051.
．． A field oxide film 311 with a film thickness of 1 μm, for example, is formed between 3052 and a wide field insulating film. If the field oxide film 311 is formed to have a depth twice the etching depth of the silicon substrate 301, a wide field insulation region that is flat and wide with the element formation region can be formed (as shown in FIG. 19 (1)). . At this time, as the buried field insulating films 305, 305□, Si3N
If a 5i02 film is used as the buried field insulating films 3052 and 3053, in principle, no horizontal encroachment (bird's beak) of the field oxide film 311 occurs during field oxidation. Toku is hardly a problem.

Next, the oxidation-resistant film 307 and the thin insulating film 30 thereunder are formed.
6 is removed by etching (as shown in FIG. 19(j)).

Finally, a gate oxide film 312 and a gate electrode (for example, polycrystalline silicon) 313 are formed, and arsenic, for example, is diffused to form n+ regions 314 and 315 that will become sources and drains.
An interlayer insulating film (for example, a CVD-3in2 film) 31B is deposited, a contact hole 317 is opened, and, for example, All wires 318 and 319 are provided, thereby completing the main steps of LIS (as shown in FIG. 19(k)).

By using the above steps, it is possible to overcome various drawbacks when using the selective oxidation method described above, and also to form a field insulating region of any width with no step and having a buried diffusion layer underneath. It becomes possible to form. Therefore, it can greatly contribute to higher integration and higher performance of LSI.

Here, the relationship between the n+ layer and the p+ layer may be such that the p+ layer 304° is formed under the field oxide film 311 as shown in FIG. ', and any other combination may be used as long as a part of the field below the field is a p+ layer, such as the n+ layer 304a.

Note that when forming the groove portion 303 in the silicon substrate 301,
In the embodiment shown in FIGS. 19(a) to 19(k), the resist film 302 was used as a mask to open the silicon substrate 301 before photolithography.
The groove portion 303' may be formed by growing the insulating film 320 and the silicon substrate 301 using a photolithography method and using the resist film 321 as a mask.

Further, after patterning this insulating film 320 (as shown in FIG. 23(a)), etching may be performed using this insulating film 320 as a mask to form the groove portion 303 (see FIG. 23(a)).
Figure (b) shown).

Furthermore, an insulating film 322 may be grown inside the trench 303 before filling the trench 303 with the insulation M305 (as shown in FIG. 24). This insulating film 322 may be formed by, for example, oxidizing the silicon substrate 301, or may be formed by depositing a CVD film or the like. Note that the width of the opening of the groove 303 at this time is narrowed by twice the thickness of the insulating film 322.

When the insulating film 304 is etched to leave the buried field insulating films 3051 to 3o53 only in the trench 303, the field insulating films 3051 to 3063 are
The structure may be such that it falls down from the surface of k 301.

In the embodiment shown in FIGS. 19(a) to 19(k), the oxidation-resistant film 307 is deposited and then the oxidation-resistant film 307 is deposited using photolithography.
07 and the silicon substrate 301. First, the silicon substrate 301 was etched to form a groove 309, and later an oxidation-resistant Il! Field oxidation may be performed after depositing 307 and etching the oxidation-resistant film 307 in the groove 309 using photolithography.

In the embodiment shown in FIGS. 19(a) to (k), field oxidation was performed after etching the oxidation-resistant film 307 and etching the silicon substrate 301 to form a groove 309. After etching the film 307, field oxidation may be performed without etching the silicon substrate 303 (FIG. 25(a)).

(b) As shown). At this time, the insulating film 30B does not necessarily have to be deposited. Furthermore, even if the insulating film 30B is left on the substrate like the 5i02 film, if the underlying substrate (for example, the silicon substrate 301) is oxidized during field oxidation, it will not be as shown in FIG. 25(a). Thin insulating film 3
Field oxidation may be performed without etching 06.

Alternatively, after the oxidation-resistant film 307 shown in FIG. 25(b) is used as a mask, the field oxidation M 311 may be etched to form a flat structure (as shown in FIG. 26). In this case, the present invention is applicable not only to a case where the silicon substrate 301 is subjected to field oxidation without being etched, but also to a case where the silicon substrate 301 is etched and then subjected to field oxidation. This is effective when the field oxide film 311 has become thick and extends above the surface of the silicon substrate 301, impairing its flatness, even though the silicon substrate 301 has been etched.

In Examples 1 to 7 above, ion implantation was performed almost perpendicularly to the substrate 301 for doping with impurities of the same conductivity type as the substrate, but as shown in FIG. 27, ion implantation was performed diagonally. There is also a p+ region 3 on the side surface of the groove portion 303.
04'' may be formed, and this may be performed by a diffusion method instead of ion implantation.

Further, in the above embodiments, the grooves are vertical or nearly vertical, but the grooves 403 are not necessarily limited to this, and the grooves 403 whose side surfaces have an inclination angle θ may be formed (see FIG. 28(a),
(b) shown), the thickness of the insulating film 405 to be deposited at this time is [acoL (
θ/2)] /2 or more. In this case, a groove with a flat bottom and sloped sides may be used.

Furthermore, as shown in FIG. 29(a), when etching the insulating film 502 on the substrate 501, it is not necessary to etch until the substrate 501 is exposed; instead, as shown in FIG. 29(b), the insulating film 502' is left. It may also be used as an interlayer insulating film for a gate film or a part thereof.

In addition, when a groove 503 is provided in the substrate 501 using the mask material 504 on the substrate 501 as a mask as shown in FIG.
5G2 may be deposited and then the mask material 504 may remain when etching the insulating film 502 (see FIG. 30).
b) As shown).

[Effects of the Invention] As detailed above, the present invention provides a MOSLS that achieves high integration and high performance by establishing a new element isolation method.
A method for manufacturing semiconductor devices such as I can be provided.

[Brief explanation of the drawing]

Figures 1(a) to (r) show n using the conventional selective oxidation method.
Cross-sectional view showing the manufacturing process of channel MOSLSI, 2nd
The figure is an enlarged cross-sectional view showing the state of the semiconductor substrate after selective oxidation in the above process, Figures 3(a) and (b) are cross-sectional views for explaining the problems of the conventional selective oxidation method, and Figure 4 is the conventional method. 5(a) to 5(f) are cross-sectional views showing the manufacturing process of an n-channel MOSLSI in Example 1 of the present invention. 6 and 7 are cross-sectional views showing changes in length between elements separated by field regions formed by the conventional method and Example 1, and FIGS. 8(a), (b), and 9. (a)
. 10(b) is a cross-sectional view of the steps up to groove formation showing modified examples of the first embodiment of the present invention, and FIGS. 10(a) to (e) are field areas of MOSLSI in the second embodiment of the present invention. 12(a) to 12(d) are cross-sectional views showing the formation process, FIGS. 13(a) and 13(b) are cross-sectional views showing the field region forming step of MOSLSI in Example 4, and FIGS. 14(a) to 14(b) are cross-sectional views showing the field region forming step as a modification of Example 4. (e) is a cross-sectional view showing the MOSLSI field region forming step in Example 5 of the present invention, FIG. 15 is a cross-sectional view showing the state after forming the field region as a modification of Example 5, ) to (j) are cross-sectional views showing the manufacturing process of MOSLSI in Example 6 of the present invention, and FIGS. 17(a), (b), and 18 are modified examples of Example 6 after field region formation. 19(a) to (K) are sectional views showing the manufacturing process of MOSLSI in Example 7 of the present invention, and FIG. 20. FIG. 21 is a cross-sectional view showing the state after field region formation, which is a modified example of Example 7, FIG. 22, and FIG. 23(a).
, (b) are cross-sectional views showing a modification of the groove formation in the seventh embodiment, FIG. 24 is a cross-sectional view showing still another modification of the seventh embodiment, and FIGS. 25(a), (b), and 26 is a sectional view showing a modification of the field region formation in the seventh embodiment, FIGS. 27, 28(a), (b), and 29.
Figures (a), (b), Figure 30 (a), (b)
2A and 2B are cross-sectional views showing the second step of forming a field region, respectively, showing other embodiments of the present invention. 101.201, 301, 401.501...Semiconductor substrate, 103°103, , ~1034. 203+
~203s, 303,403.503...
Groove, 104.204.204', 204", 204
"'', 304.304'...p'' region inversion prevention layer)
, 104a, 204a, 304a-n'' fffi region (wiring layer) 105.205, 305 ■ region, 110.213, 115 type drain region, 113° 114.216, 217, 318.319...Ap wiring.

Claims (8)

[Claims] (1) providing a first groove portion having vertical or nearly vertical side surfaces in a desired portion of the semiconductor substrate;
Impurities of the substrate and conductivity type are added to each groove at 1×10^1^4/
forming an impurity region by doping with a dose of cm^2 or more; and forming an insulating film over the entire surface of the semiconductor substrate including the first trench to a thickness of at least half the minimum width of the opening of the first trench. a step of etching the insulating film until the main surface of the semiconductor substrate is exposed and leaving the insulating film in the first groove; and a step of depositing the insulating film on the remaining main surface of the semiconductor substrate. After depositing an oxidation-resistant film and selectively etching the oxidation-resistant film between the first trenches to form a second trench, field oxidation is performed using the oxidation-resistant film as a mask to form the first trench. Fill the space between the grooves with an oxide film,
A method of manufacturing a semiconductor device, comprising the step of forming a wide field region by integrating the insulating film left in the first trench. (2) The method of manufacturing a semiconductor device according to claim 1, wherein the step of doping with impurities is performed immediately after providing the second groove portion. (3) The method of manufacturing a semiconductor device according to claim 1, characterized in that the step of doping with impurities is carried out after providing the first trench and also after providing the second trench. (4) After depositing an oxidation-resistant film on the main surface of the semiconductor substrate where the insulating film remains, the oxidation-resistant film and the first
By selectively etching between the grooves, a second groove is provided that has the insulating film left in the first groove on at least part of the side surfaces, and then field oxidation is performed using the oxidation-resistant film as a mask. A method of manufacturing a semiconductor device according to any one of claims 1 to 3, characterized in that: (5) After providing the first groove in the semiconductor substrate or doping with impurities, the entire surface of the semiconductor substrate or at least a part of the groove is oxidized or nitrided to form an oxide film or an oxide film to an extent that the first groove is not blocked. A method of manufacturing a semiconductor device according to any one of claims 1 to 4, characterized in that a nitride film is grown. (6) After depositing an insulating film on the semiconductor substrate provided with the first groove, a low-temperature melting insulating film is deposited on the whole or part of this insulating film, and after melting the low-temperature melting insulating film, Claim 1 characterized in that the film is etched.
A method for manufacturing a semiconductor device according to any one of items 1 to 4. (7) After providing a second groove portion having the insulating film left in the first groove portion on at least a part of the side surface by selectively etching the space between the first groove portions of the semiconductor substrate where the insulating film remains. , a second oxidation-resistant film is deposited on the entire surface of the semiconductor substrate.
A method for manufacturing a semiconductor device according to any one of claims 1 to 4, characterized in that the oxidation-resistant film in the groove portion of the semiconductor device is etched, and then field oxidation is performed using the oxidation-resistant film as a mask. . (8) The semiconductor device according to any one of claims 1 to 7, characterized in that after field oxidation, a part of the field oxide film is etched using the oxidation-resistant film as a mask to obtain a flat structure. Production method.