JPH0214648A - Data transmission circuit - Google Patents

Abstract

PURPOSE:To recover synchronization quickly even in the occurrence of synchronization deviation by sending a data of the same level and having more bit number than the bit number of a sent, data serially just after the transmission of the data of the prescribed bit number. CONSTITUTION:A parallel data on a data line 10 in bit number (m) is latched by a latch circuit 1. An output data from the latch circuit 1 is given to an input terminal of a multiplexer 2. Other n-set of input terminals 3 of the multiplexer 2 are kept to a low level (n>m). The multiplexer 2 according to a command from a counter 4 outputs the input data by m-bit inputted to the input terminal to an output line 7 one by one bit each sequentially and a data (clear bit) of a low level by n-bit given to the input terminal 3 is outputted sequentially. Thus, even if synchronization deviation takes place on the way of data transmission, the reception side detects the clear bit and the synchronization is recovered in the succeeding cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data transmission circuit, and more particularly to a data transmission circuit that converts parallel data into serial data and transmits the converted data.

(Prior Art) In digital systems such as computers, parallel data is transmitted at various locations. For example, LED
When transmitting parallel data to a display device in order to display the parallel data on a display device in which a large number of
A data transmission circuit as shown in the figure was used. In this circuit, each output terminal of a latch circuit 42 that latches parallel data on a data bus 41 having a width of several lθ bits is connected to a corresponding Ll! in a display 43. Transmission line 4 to D44
5 is wired.

In a circuit that transmits parallel data as it is, problems such as out-of-synchronization do not occur. However, in this case, transmission lines 45 for the number of bits of parallel data are required, and There are problems such as that the wiring becomes complicated and that many transmission lines 45 must be routed. Particularly when the display device 43, which is an element that uses data, is located far away from the place where the data is generated, that is, the data bus 41.

The complicated printed circuit board and long transmission line 45 were cost prohibitive.

In order to solve the above-mentioned problems, a data transmission circuit is used that converts parallel data into serial data and transmits the converted data. An example is shown in FIG. data bus 51
The above parallel data is subjected to parallel-to-serial conversion by a parallel-to-serial converter 52 in synchronization with the clock on a clock line 53, and is output to a transmission line 54. On the receiving side, data on the transmission line 54 is serial-parallel converted by a serial-parallel converter 55 in synchronization with a clock. The parallel data thus obtained is used to drive the LED 57 of the display 56. Furthermore, a parallel-to-serial converter 52 and a serial to
A control signal is supplied to the parallel converter 55 from a control circuit 58 .

(Problem to be Solved by the Invention) In the data transmission circuit that performs the parallel-to-serial conversion described above, a synchronization shift occurs due to the influence of noise mixed in the 2 transmission line 54 and the clock line 53, and the 9 display 56 does not display correctly. There is a fear. Therefore, in such a data transmission circuit, as in the circuit shown in FIG. 5, a control circuit 58 is provided which supplies a control signal to the parallel-to-serial converter 52 and the serial-to-parallel converter 55.
This control signal prevented synchronization. still.

In some cases, the control signal may be realized by software instead of the control circuit 58.

As mentioned above, when parallel data is converted from parallel to serial and transmitted, there is a problem in that a complicated control circuit 58 or software is required to prevent synchronization and a line for sending control signals is required. Ta.

The present invention was made in view of the current situation, and
The purpose is to provide a data transmission circuit which has a simple configuration that does not require means such as a control circuit, and which can quickly recover synchronization even when synchronization has occurred.

(Means for Solving the Problems) The data transmission circuit of the present invention includes a means for converting parallel data from parallel to serial and transmitting it, and immediately after transmitting the parallel data, a number of bits greater than the number of bits of the parallel data is transmitted. and means for serially transmitting data of the same level.

Thereby, the above objective is achieved.

(Example) The present invention will be described below with reference to Examples.

A circuit diagram of an embodiment of the present invention is shown in FIG. Parallel data on data line IO is latched by latch circuit 1. Let the number of bits of the data line 10 be m.

The output data from the latch circuit is input to the input terminal of the multiplexer 2. The other n input terminals 3 of the multiplexer 2 are set to low level. However, n>m. The multiplexer 2 sequentially outputs the data input to the input terminal one bit at a time to the output line 7 in accordance with the command from the counter 4. The counter 4 operates according to a clock input via a clock line 5, and its period is m+n+1. A start bit is output from the counter 4 via a start focus line 6. The data on output line 7 and the start bit on start bit line 6 are combined by OR gate 8 and output to transmission line 9.

The circuit of FIG. 1 operates as described below.

Counter 4 outputs a high level start bit at the first count. 2nd count of counter 4 ~ (m+1)
At the count, m bits of input data of the multiplexer are sequentially output. Counter 4's (m+2)th count~
At the (m.+n+1) count. The multiplexer 2 sequentially outputs n bits of low level data input to the input terminal 3. This low level data is called a clear bit. Thereafter, the above-described operation is repeated.

FIG. 2 shows an example of a display circuit that receives and displays data transmitted according to this embodiment. A transmission line 9 is connected to the input end of the serial-parallel converter 21. The serial-parallel converter 21 converts data input via the transmission line 9 into parallel data in synchronization with the clock.
Using this parallel data, the LED 23 of the display 22
to drive. The transmission line 9 is also connected to a clear focus detection circuit 24 and a start bit detection circuit 25. The start bit detection circuit 25 is . When the clear bit detection circuit 24 detects a clear bit, it waits for the appearance of a start bit. When the start bit is detected, the data transmitted following the start bit is detected.

The serial-to-parallel converter 21 converts the data into parallel data.

The third timing chart is a timing chart when the data transmission circuit of the above-described embodiment and the above-described display circuit are operated in combination.
As shown in the figure. Here - as an example.

m=35. Let n=44. Therefore, the number of bits transmitted in one cycle is 80. As described above, on the transmission line 9, following the start bit 31, 35 bits of data 32 and 44 bits of clear bit 33 are transmitted. On the display circuit side, after detecting the start bit 31, serial-to-parallel conversion is performed while counting clocks, and the converted data is latched at the 36th count when the conversion of 35 bits of data 32 is completed.

At the next 37th count, Syria Frey parallel converter 21
Clear the conversion register in

As shown on the line indicated by [Display data update cycle], one display is updated once every 80 clocks.

As mentioned above, immediately after transmitting data of a predetermined number of bits, clear bits with a number of bits greater than the number of bits of that data are transmitted, so even if a synchronization error occurs during data transmission, the clear bits are not received. can regain synchronization in the secondary cycle by detecting a clear bit on the side.

2. The data display circuit of the present invention can be applied to various fields of transmitting parallel data, but a particularly suitable field of application is when it is used as a display circuit for data output from the I10 unit of a programmable controller. I can do it.

(Effects of the Invention) According to the present invention, although the present invention has a simple configuration that does not require complicated and costly means such as a control circuit for preventing synchronization, - A data transmission circuit is provided that can quickly recover synchronization even if this occurs.

Figure 1 is a circuit diagram of an embodiment of the present invention, Figure 2 is a circuit diagram of an example of a display circuit that displays data transmitted by the embodiment, and Figure 3 is a circuit diagram of an example of the embodiment. Timing charts showing the operation when combined with the above display circuit, and FIGS. 4 and 5 are circuit diagrams of examples of conventional data transmission circuits.

l...Latch circuit, 2...Multiplexer 23...
・Input terminal into which low level data is input, 4...Counter, 2...Clock line, 6...Start bit line.

7...Output line, 9...Transmission line, 31...Start bit 32...Data, 33...Clear bit.

that's all

Claims (1)

[Claims] 1. It is equipped with means for converting parallel data into serial data and transmitting the same, and means for serially transmitting data of the same level with a number of bits greater than the number of bits of the parallel data immediately after transmitting the parallel data. data transmission circuit.