JPH02125472A - Semiconductor device using quantum interference transistor - Google Patents
Semiconductor device using quantum interference transistorInfo
- Publication number
- JPH02125472A JPH02125472A JP27729988A JP27729988A JPH02125472A JP H02125472 A JPH02125472 A JP H02125472A JP 27729988 A JP27729988 A JP 27729988A JP 27729988 A JP27729988 A JP 27729988A JP H02125472 A JPH02125472 A JP H02125472A
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- Prior art keywords
- layer
- channel layer
- semiconductor
- energy gap
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Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 230000004888 barrier function Effects 0.000 claims abstract description 39
- 230000005641 tunneling Effects 0.000 claims abstract description 15
- 239000010409 thin film Substances 0.000 claims abstract description 12
- 230000000694 effects Effects 0.000 claims description 9
- 230000001902 propagating effect Effects 0.000 claims description 4
- 239000013598 vector Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 22
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 11
- 239000010408 film Substances 0.000 abstract description 9
- 238000000206 photolithography Methods 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66977—Quantum effect devices, e.g. using quantum reflection, diffraction or interference effects, i.e. Bragg- or Aharonov-Bohm effects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Junction Field-Effect Transistors (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、アハラノフ−ボーム効果を利用した量子干渉
トランジスタを有する半導体装置に係り、特に超高速ス
イッチング素子及び多値論理素子として用いられる半導
体装置に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device having a quantum interference transistor using the Ahranov-Bohm effect, and particularly to a semiconductor device used as an ultra-high-speed switching element and a multivalued logic element. It is related to.
従来の量子干渉トランジスタにおいては、プロシーディ
ンブオブザアイイーディーエム、４゜１．１９８６ （
ＰＲＯＣＥＥＤＩＮＧＳ ＯＦ ＴＨＥ ＩＥＤＭ、
４．１．１９８６）記載のように、ソース電極がチャネ
ル層に隣接して設けられており、フェルミ分布した電子
が直接チャネル内に注入されていた。この素子の部分断
面図を第２図に示す。この素子は、エネルギーギャップ
の狭い半導体から成るチャネル層１と、該チャネル層上
中及びその上下に設けられたエネルギーギャップの広い
半導体から成る障壁層２と、ソース電極と接続するソー
ス領域３と、ドレイン電極と接続するドレイン領域４と
、上記障壁層２を介してチャネル層１上に設けられ、ゲ
ート電極と連絡するゲート領域５を有し、チャネル層内
を伝播する電子波の干渉効果（ｅｌｅｃｒｔｒｏｓｔａ
ｔｉｃＡｈａｒａｎｏｖ Ｂｏｈｍ ｅｆｆｅｃｔ）を
利用して動作する。Regarding conventional quantum interference transistors, Proceedings of the IDM, 4°1.1986 (
PROCEEDINGS OF THE IEDM,
4.1.1986), a source electrode was provided adjacent to the channel layer, and Fermi distributed electrons were directly injected into the channel. A partial cross-sectional view of this element is shown in FIG. This device includes a channel layer 1 made of a semiconductor with a narrow energy gap, a barrier layer 2 made of a semiconductor with a wide energy gap provided above and below the channel layer, and a source region 3 connected to a source electrode. It has a drain region 4 connected to the drain electrode, and a gate region 5 provided on the channel layer 1 via the barrier layer 2 and communicating with the gate electrode.
ticAharanov Bohm effect).
上記従来技術は、ソース領域でフェルミ分布していた電
子が直接チャネル層に注入される構造となっている。こ
の時、流れるドレイン電流は、で与えられる。ここで、
ｋ−、ｋｙはＸ＋ ｙ方向の電子の波数ベクトル、Ｗは
チャネル厚み１ｍは電子の有効質量、ｆはフェルミ分布
関数、Ｖｏはドレイン電圧１毛はブランク定数の１／２
πの値、ｅは電子の電荷である。またＩ Ｔ（ｋ、）１
２は従来構造による電子波の透過確率で、
で与えられる。ここでＶａはゲート電圧、Ｌはゲート長
である。このＩ ”ｒ（ｋｘ）１２のゲート電圧依存性
により、ドレイン電流Ｉｏは第３図のような振動を生じ
、スイッチング動作、あるいは多値論理動作が可能とな
る。しかし、この構造では、前述のようにフェルミ分布
した様々な波数ベクトルに、を持つ電子がソース電極か
ら注入されるため、ドレイン電流振動のピーク／バレイ
比が小さいという問題があった６
本発明の目的は、ドレイン電流振動のピーク／バレイ比
が大きい量子干渉トランジスタを有する半導体装置を提
供することにある。The conventional technique described above has a structure in which electrons distributed in Fermi distribution in the source region are directly injected into the channel layer. At this time, the flowing drain current is given by: here,
k-, ky are the wave number vectors of electrons in the
The value of π, e is the charge of the electron. Also I T(k,)1
2 is the transmission probability of electronic waves through the conventional structure, which is given by: Here, Va is the gate voltage and L is the gate length. This gate voltage dependence of I''r(kx)12 causes the drain current Io to oscillate as shown in Figure 3, making switching operation or multi-value logic operation possible.However, with this structure, the above-mentioned Since electrons having various wave number vectors with Fermi distribution are injected from the source electrode, there is a problem that the peak/valley ratio of drain current oscillation is small6. An object of the present invention is to provide a semiconductor device having a quantum interference transistor with a large /valley ratio.
〔課題を解決するための手段〕□
上記目的は、（１）エネルギーギャップの狭い半導体か
ら成るチャネル層と、該チャネル層中及び該チャネル層
上下に設けられたエネルギーギャップの広い半導体から
成る障壁層と、ソース電極、ドレイン電極及び上記障壁
層を介して該チャネル層上に設けられたゲート電極を有
し、該チャネル層内を伝播する電子波の干渉効果を利用
して動作する量子干渉トランジスタを有する半導体装置
において、上記チャネル層と上記ソース電極の間に、少
なくともエネルギーギャップの狭い半導体薄膜と２層の
エネルギーギャップの広い半導体薄膜とから成る共鳴ト
ンネリングバリアを設けたことを特徴とする量子干渉ト
ランジスタを有する半導体装置、（２）エネルギーギャ
ップの狭い半導体から成るチャネル層と、該チャネル層
中及び該チャネル層上下に設けられたエネルギーギャッ
プの広い半導体から成る障壁層と、ソース電極、ドレイ
ン電極及び上記障壁層を介して該チャネル層上に設けら
れたゲート電極を有し、該チャネル層内を伝播する電子
波の干渉効果を利用して動作する量子干渉トランジスタ
を有する半導体装置において。[Means for Solving the Problems] □ The above objects are: (1) a channel layer made of a semiconductor with a narrow energy gap; and a barrier layer made of a semiconductor with a wide energy gap provided in the channel layer and above and below the channel layer; and a quantum interference transistor that has a source electrode, a drain electrode, and a gate electrode provided on the channel layer via the barrier layer, and operates using the interference effect of electron waves propagating within the channel layer. A quantum interference transistor, characterized in that a resonant tunneling barrier comprising at least a semiconductor thin film with a narrow energy gap and two semiconductor thin films with a wide energy gap is provided between the channel layer and the source electrode. (2) a channel layer made of a semiconductor with a narrow energy gap; a barrier layer made of a semiconductor with a wide energy gap provided in the channel layer and above and below the channel layer; a source electrode, a drain electrode, and the above. A semiconductor device including a quantum interference transistor having a gate electrode provided on the channel layer via a barrier layer and operating by utilizing the interference effect of electron waves propagating within the channel layer.
上記チャネル層と上記ソース電極の間に、特定の波数ベ
クトルを持つ量子のみを通過させる共鳴トンネリングバ
リアを設けたことを特徴とする量子干渉トランジスタを
有する半導体装置によって達成される。This is achieved by a semiconductor device having a quantum interference transistor, characterized in that a resonant tunneling barrier is provided between the channel layer and the source electrode, allowing only quanta having a specific wave number vector to pass through.
本発明における共鳴トンネリングバリアは、エネルギー
ギャップの狭い半導体薄膜をエネルギーギャップめ広い
半導体薄膜で挟んだ２重障壁構造を少なくとも有するも
のであればよく、さらに上記構造の外側にエネルギーギ
ャップの狭い半導体薄膜と広い半導体薄膜をそれぞれ設
けた５層構造としてもよく、なおさらにそれぞれの半導
体層を同様に加えた構造としてもよい。The resonant tunneling barrier in the present invention may have at least a double barrier structure in which a semiconductor thin film with a narrow energy gap is sandwiched between semiconductor thin films with a wide energy gap, and furthermore, a semiconductor thin film with a narrow energy gap and a semiconductor thin film with a narrow energy gap on the outside of the above structure. It may be a five-layer structure in which a wide semiconductor thin film is provided respectively, or it may be a structure in which each semiconductor layer is added in the same way.
エネルギーギャップの狭い半導体薄層の厚みは、５０〜
１００人の範囲が好ましく、エネルギーギャップの広い
半導体薄層の厚みは、１０〜１００人の範囲が好ましい
。The thickness of the semiconductor thin layer with a narrow energy gap is 50~
The thickness of the semiconductor thin layer with a wide energy gap is preferably in the range of 10 to 100 people.
本発明の半導体装置の一例の部分断面図を第１図に示す
。ソース電極と接続するソース領域３とチャネル層１と
の間に、エネルギーギャップの狭い半導体薄膜をエネル
ギーギャップの広い半導体薄膜で挟んだ２重障壁構造共
鳴トンネリングバリア６を設ける。FIG. 1 shows a partial cross-sectional view of an example of the semiconductor device of the present invention. A double barrier structure resonant tunneling barrier 6 in which a semiconductor thin film with a narrow energy gap is sandwiched between semiconductor thin films with a wide energy gap is provided between a source region 3 connected to a source electrode and a channel layer 1.
上記のように導入した共鳴トンネリングバリアは、第４
図のようにその透過確率１Ｔｎ（ｋｘ）ｌ”がδ−関数
的になり、特定の波数に、を持つ電子のみを通過させる
フィルターとして働く。すなわち、Ｔ Ｒ（ｋ Ｘ ）
ｌ ” Σδ（ｋ、−ｋｏ）となる。このため、本構
造トランジスタにおけるドレイン電流は、
となり、第５図のようにゲート電圧に対してＯとＩｏの
間を振動し、ビーク／バレイ比を無限大とすることがで
きる。The resonant tunneling barrier introduced as above is the fourth
As shown in the figure, the transmission probability 1Tn (k
l'' Σδ(k, -ko). Therefore, the drain current in the transistor with this structure is as shown in Fig. 5, and it oscillates between O and Io with respect to the gate voltage, and the peak/valley ratio increases. It can be infinite.
以下、本発明の一実施例の量子干渉トランジスタを有す
る半導体装置の製造方法を第６図（ａ）〜第６図（ｇ）
により説明する。A method for manufacturing a semiconductor device having a quantum interference transistor according to an embodiment of the present invention will be described below with reference to FIGS. 6(a) to 6(g).
This is explained by:
第６図（ａ）二半絶縁性Ｇ ａ Ａ ｓ基板７上にＭＢ
Ｅ法でｉ −Ａ Ｑｏ、、Ｇａ０．、Ａｓ層８（膜厚１
００人）、１−ＧａＡｓ層９（膜厚１５０人）、ｉ −
Ａ Ｑｏ、３Ｇａ０，７ＡｓｌｌＯ（膜厚１００人）を
成長させる。FIG. 6(a) MB on the semi-insulating G a As substrate 7
By the E method, i −A Qo, , Ga0. , As layer 8 (film thickness 1
00 people), 1-GaAs layer 9 (film thickness 150 people), i −
A Qo, 3Ga0,7AsllO (film thickness: 100 nm) is grown.
第６図（ｂ）：ＥＢ法によりチャネル内障壁１１（障壁
長さＬ ＜０．２μｍ）を形成した後、Ｍ Ｂ Ｅ法で
１−ＧａＡｓ層１２（膜厚１５０人）、１−ＡＱｏ。FIG. 6(b): After forming an intra-channel barrier 11 (barrier length L<0.2 μm) by the EB method, a 1-GaAs layer 12 (thickness: 150 μm) and 1-AQo are formed by the MBE method.
Ｇａ、、、Ａｓ層１３（膜厚１００人）を成長させる。A Ga,..., As layer 13 (thickness: 100 mm) is grown.
第６図（Ｃ）：通常のフォトリングラフィ技術により、
メサ領域１４を形成する。Figure 6 (C): By ordinary photolithography technique,
A mesa region 14 is formed.
第６図（ｄ）：ＭＢＥ法でｉ −Ａ Ｑ、、３Ｇａ、、
、Ａｓ層１５（膜厚５０人）、１−ＧａＡｓ層１６（膜
厚１００人）、ｉ −Ａ （１６，ｘＧａｏ、７重８層
１７ （膜厚５０人）を成長させる。Figure 6(d): i-A Q,,3Ga,, by MBE method
, As layer 15 (thickness: 50 layers), 1-GaAs layer 16 (thickness: 100 layers), i - A (16,xGao, 7-fold, 8-layer layer 17 (thickness: 50 layers)).
第６図（ｅ）：通常のフォトリソグラフィ技術により、
上記ｉ −Ａ Ｑｏ、、Ｇａ、、７Ａｓ層１５．１−Ｇ
ａＡｓ層１６、ｉ −ＡＱ６１Ｇａｏ、７Ａｓ層１７か
ら成る２重障壁構造共鳴トンネリングバリア１８を形成
する。Figure 6(e): By normal photolithography technology,
The above i-A Qo, , Ga, , 7As layer 15.1-G
A double barrier structure resonant tunneling barrier 18 consisting of an aAs layer 16, an i-AQ61Gao layer 17, and a 7As layer 17 is formed.
第６図（ｆ）：ＭＢＥ法ｎ’−ＧａＡｓ層（キャリア濃
度２ Ｘ １０” ａａ −” 、膜厚３０００λ）を
成長させた後、ＥＢ法によりソース領域１９、ゲート領
域２０、ドレイン領域２１を形成する。FIG. 6(f): After growing an n'-GaAs layer (carrier concentration 2 x 10" aa -", film thickness 3000λ) by MBE method, the source region 19, gate region 20, and drain region 21 are grown by the EB method. Form.
第６図（ｇ）：通常のりフトオフ法により、ソース電極
２２、ゲート電極２３、ドレイン電極２４を形成する。FIG. 6(g): A source electrode 22, a gate electrode 23, and a drain electrode 24 are formed by a normal lift-off method.
電極材料としては、ＡｕＧｅ／Ｎｉ／Ａｕを各々６００
／１００／６００人蒸着する。As electrode materials, AuGe/Ni/Au were used at 600% each.
/100/600 people are deposited.
実施例２：本発明の他の実施例の量子干渉トランジスタ
を有する半導体装置の製造方法を第７図（ａ）〜第７図
（ｅ）により説明する。実施例１と同様に第６図（ｂ）
の状態に製造する。Embodiment 2: A method of manufacturing a semiconductor device having a quantum interference transistor according to another embodiment of the present invention will be explained with reference to FIGS. 7(a) to 7(e). As in Example 1, FIG. 6(b)
Manufactured to the condition of
第７図（ａ）二通常のフォトリソグラフィ技術により、
ソース電極頭ｆｉ２５、ドレイン電極領域２６を形成す
る。FIG. 7(a) 2 By ordinary photolithography technique,
A source electrode head fi25 and a drain electrode region 26 are formed.
第７図（ｂ）：通常のフォトリングラフィ技術により、
メサ領域１４を形成する。Figure 7(b): By ordinary photolithography technique,
A mesa region 14 is formed.
第７図（ｃ）：ＭＢＥ法でｉ −Ａ Ｑｏ、Ｇａ、、、
Ａｓ層１５ （膜厚５０人）、ｉ −ＧａＡｓＪｉ）１
６ （膜厚１００人）。Figure 7(c): i −A Qo, Ga, , by MBE method
As layer 15 (film thickness 50 layers, i-GaAsJi) 1
6 (film thickness 100 people).
ｉ −Ａ Ｑ、、、Ｇａ０．、Ａｓ層１７（膜厚５０人
）を成長させた後、通常のフォトリングラフィ技術によ
り、ソース電極領域に上記３層から成る２重障壁構造共
鳴トンネリングバリア１８を形成する。i-A Q, , Ga0. After growing the As layer 17 (film thickness: 50 nm), a double barrier structure resonant tunneling barrier 18 consisting of the three layers described above is formed in the source electrode region by ordinary photolithography technology.
第７図（ｄ）ＣＭＢＥ法でｎ’−ＧａＡｓ層（キャリア
濃度２ Ｘ １０” ａｎ−’ 、膜厚３０００人）を
成長させた後、ＥＢ法によりソース領域１９、ゲート領
域２０、ドレイン領域２１を形成する。FIG. 7(d) After growing an n'-GaAs layer (carrier concentration 2 x 10"an-', film thickness 3000 layers) using the CMBE method, the source region 19, gate region 20, and drain region 21 are grown using the EB method. form.
第７図（ｅ）二通常のリフトオフ法により、ソースな極
２２．ゲート電極２３、ドレイン電極２４を形成する。FIG. 7(e) Two source poles 22. A gate electrode 23 and a drain electrode 24 are formed.
電極材料、厚みは、実施例１と同じである。The electrode material and thickness are the same as in Example 1.
実施例３：実施例１及び２において、２重障壁構造共鳴
トンネリングバリア１８を構成するｉ−Ａ Ｑ ６．３
Ｇａ６．−ＨＡｓ層１５、ｉ −Ａ Ｑ。、、Ｇａ、
、、Ａｓ層１７を１−ＡＱＡｓ（膜厚２０人）に置き換
えても同様の結果を得た。Example 3: In Examples 1 and 2, i-A Q 6.3 constituting the double barrier structure resonance tunneling barrier 18
Ga6. -HAs layer 15, i -A Q. ,,Ga,
Similar results were obtained even when the As layer 17 was replaced with 1-AQAs (thickness: 20).
実施例４：実施例１及び２において、２重障壁構造共鳴
トンネリングバリア１８を構成するｉ−Ａ Ｑ ６ 、
ｓ Ｇ ａ ６ 、７ Ａ ｓ層１５、ｉ−ＧａＡｓ
層１６．１−ＡＱ（１，３Ｇａ、、、Ａｓ層１７をｉ
−ＩｎＡＱＡｓ、ｉ −ＩｎＧａＡｓ、ｉ−ＩｎＡＱＡ
ｓに置き換えても同様の結果を得た。Example 4: In Examples 1 and 2, i-A Q 6 constituting the double barrier structure resonance tunneling barrier 18,
s Ga 6 , 7 As layer 15, i-GaAs
Layer 16.1-AQ (1,3 Ga,..., As layer 17 is i
-InAQAs, i-InGaAs, i-InAQAs
Similar results were obtained by replacing s with s.
本発明によれば、ピーク電流値が一定で、ピーク／バレ
イ比の大きな量子干渉トランジスタを有する半導体装置
を実現できた。例えば従来の量子干渉トランジスタはピ
ーク／バレイ比が４層１程度であったが、本発明におい
ては１０：１以上のものが得られた。そのため超高速ス
イッチング素子、及び多値論理素子として適用した時、
大きな効果が得られた。According to the present invention, it was possible to realize a semiconductor device having a quantum interference transistor with a constant peak current value and a large peak/valley ratio. For example, conventional quantum interference transistors had a peak/valley ratio of about 4 layers to 1, but in the present invention, a peak/valley ratio of 10:1 or more was obtained. Therefore, when applied as an ultra-high-speed switching element and a multi-value logic element,
A great effect was obtained.
第１図は本発明による量子干渉トランジスタを有する半
導体装置の部分の断面図、第２図は従来構造の量子干渉
トランジスタの断面図、第３図は従来構造で得られるド
レイン電流−ゲート電圧特性を示す図、第４図は２重障
壁構造共鳴トンネリングバリアのフィルタ特性を示す図
、第５図は本発明による量子干渉トランジスタのドレイ
ン電流−ゲート電圧特性を示す図、第６図及び第７図は
本発明の実施例の量子干渉トランジスタを有する半導体
装置の製作工程を示す部分断面図である。
１・・・チャネル層
２・・・障壁層
３．１９・・・ソース領域
４．２１・・・ドレイン領域
５．２０・・・ゲート領域
６．１８・・・２重障壁構造共鳴トンネリングバリア７
・・・半絶縁性基板
８ 、１０．１３．１５．１７− ｉ −Ａ Ｑ、、、
Ｇａ、、、Ａｓ層９ 、１２．１６− ｉ −ＧａＡｓ
層１１・・・チャネル内障壁
１４・・・メサ領域
２２・・・ソース電極
２３・・・ゲート電極
２４・・・ドレイン電極
２５・・・ソース電極領域
２６・・・ドレイン電極領域Fig. 1 is a cross-sectional view of a portion of a semiconductor device having a quantum interference transistor according to the present invention, Fig. 2 is a cross-sectional view of a quantum interference transistor with a conventional structure, and Fig. 3 shows drain current-gate voltage characteristics obtained with the conventional structure. 4 is a diagram showing the filter characteristics of the double barrier structure resonant tunneling barrier, FIG. 5 is a diagram showing the drain current-gate voltage characteristics of the quantum interference transistor according to the present invention, and FIGS. 6 and 7 are FIG. 3 is a partial cross-sectional view showing the manufacturing process of a semiconductor device having a quantum interference transistor according to an embodiment of the present invention. 1... Channel layer 2... Barrier layer 3.19... Source region 4.21... Drain region 5.20... Gate region 6.18... Double barrier structure resonant tunneling barrier 7
...Semi-insulating substrate 8, 10.13.15.17-i-A Q,,,
Ga,..., As layer 9, 12.16-i-GaAs
Layer 11... In-channel barrier 14... Mesa region 22... Source electrode 23... Gate electrode 24... Drain electrode 25... Source electrode region 26... Drain electrode region
Claims (1)
層と、該チャネル層中及び該チャネル層上下に設けられ
たエネルギーギャップの広い半導体から成る障壁層と、
ソース電極、ドレイン電極及び上記障壁層を介して該チ
ャネル層上に設けられたゲート電極を有し、該チャネル
層内を伝播する電子波の干渉効果を利用して動作する量
子干渉トランジスタを有する半導体装置において、上記
チャネル層と上記ソース電極の間に、少なくともエネル
ギーギャップの狭い半導体薄膜と２層のエネルギーギャ
ップの広い半導体薄膜とから成る共鳴トンネリングバリ
アを設けたことを特徴とする量子干渉トランジスタを有
する半導体装置。 ２、エネルギーギャップの狭い半導体から成るチャネル
層と、該チャネル層中及び該チャネル層上下に設けられ
たエネルギーギャップの広い半導体から成る障壁層と、
ソース電極、ドレイン電極及び上記障壁層を介して該チ
ャネル層上に設けられたゲート電極を有し、該チャネル
層内を伝播する電子波の干渉効果を利用して動作する量
子干渉トランジスタを有する半導体装置において、上記
チャネル層と上記ソース電極の間に、特定の波数ベクト
ルを持つ電子のみを通過させる共鳴トンネリングバリア
を設けたことを特徴とする量子干渉トランジスタを有す
る半導体装置。[Claims] 1. A channel layer made of a semiconductor with a narrow energy gap; a barrier layer made of a semiconductor with a wide energy gap provided in the channel layer and above and below the channel layer;
A semiconductor having a source electrode, a drain electrode, and a gate electrode provided on the channel layer via the barrier layer, and having a quantum interference transistor that operates using the interference effect of electron waves propagating within the channel layer. The device has a quantum interference transistor characterized in that a resonant tunneling barrier consisting of at least a semiconductor thin film with a narrow energy gap and two semiconductor thin films with a wide energy gap is provided between the channel layer and the source electrode. Semiconductor equipment. 2. A channel layer made of a semiconductor with a narrow energy gap; a barrier layer made of a semiconductor with a wide energy gap provided in the channel layer and above and below the channel layer;
A semiconductor having a source electrode, a drain electrode, and a gate electrode provided on the channel layer via the barrier layer, and having a quantum interference transistor that operates using the interference effect of electron waves propagating within the channel layer. A semiconductor device having a quantum interference transistor, characterized in that a resonant tunneling barrier is provided between the channel layer and the source electrode to allow only electrons having a specific wave number vector to pass through.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27729988A JP2675362B2 (en) | 1988-11-04 | 1988-11-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27729988A JP2675362B2 (en) | 1988-11-04 | 1988-11-04 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02125472A true JPH02125472A (en) | 1990-05-14 |
| JP2675362B2 JP2675362B2 (en) | 1997-11-12 |
Family
ID=17581603
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27729988A Expired - Lifetime JP2675362B2 (en) | 1988-11-04 | 1988-11-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2675362B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0537889A2 (en) * | 1991-10-14 | 1993-04-21 | Fujitsu Limited | Quantum interference effect semiconductor device and method of producing the same |
| US5416040A (en) * | 1993-11-15 | 1995-05-16 | Texas Instruments Incorporated | Method of making an integrated field effect transistor and resonant tunneling diode |
| WO2007040072A1 (en) * | 2005-10-03 | 2007-04-12 | Sharp Kabushiki Kaisha | Electromagnetic field detection element and device employing it |
| US12091710B2 (en) | 2006-05-11 | 2024-09-17 | Bio-Rad Laboratories, Inc. | Systems and methods for handling microfluidic droplets |
-
1988
- 1988-11-04 JP JP27729988A patent/JP2675362B2/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0537889A2 (en) * | 1991-10-14 | 1993-04-21 | Fujitsu Limited | Quantum interference effect semiconductor device and method of producing the same |
| EP0537889A3 (en) * | 1991-10-14 | 1995-03-15 | Fujitsu Ltd | |
| US5416040A (en) * | 1993-11-15 | 1995-05-16 | Texas Instruments Incorporated | Method of making an integrated field effect transistor and resonant tunneling diode |
| WO2007040072A1 (en) * | 2005-10-03 | 2007-04-12 | Sharp Kabushiki Kaisha | Electromagnetic field detection element and device employing it |
| US8331057B2 (en) | 2005-10-03 | 2012-12-11 | Sharp Kabushiki Kaisha | Electromagnetic field detecting element utilizing ballistic current paths |
| US12091710B2 (en) | 2006-05-11 | 2024-09-17 | Bio-Rad Laboratories, Inc. | Systems and methods for handling microfluidic droplets |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2675362B2 (en) | 1997-11-12 |
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