JPH0210436A - Save processing system - Google Patents

Abstract

PURPOSE:To hasten the start of interruption handling of a processor by providing two general register groups and a memory only for save processing. CONSTITUTION:Two general register groups 3 and 4 hold data to be processed by a processor 2, and two assignment flags 8 and 9 indicate assignment of general register groups 3 and 4 to the processor 2. When a request of interruption handling occurs in a data processor 1, contents of general register groups 3 and 4 assigned to the processor 2 in the present processing are saved in a memory 6. At this time, an address generating circuit 7 indicates register addresses of registers to be saved in the memory 6 and memory addresses of save destinations. A save control circuit 5 reports the start of save processing to the memory 6 and the address generating circuit 7 in accordance with the interrupt report from the processor 2 and information of assignment flags 8 and 9 and selects register addresses to be used by general register groups 3 and 4 and data to be saved in the memory 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device capable of performing interrupt processing, and particularly relates to a save processing method that is performed prior to interrupt processing when an interrupt occurs.

[Conventional technology]

As shown in FIG. 2, the conventional data processing device 31 includes:
Only one general-purpose register group 33 existed.

When a request for interrupt processing is generated in the data processing bag W31, the processor 32 performs save processing prior to interrupt processing. In this case, the processor 32 specifies one register in the general-purpose register group 33 via the register address viI35. The general-purpose register group 33 sends the data of the register specified by the register address line 35 to the processor 32 via the data line 36. After taking in the data sent out via the data line 36, the processor 32 notifies the main storage device 34 of a write request via the control line 39, and at the same time sends out a memory address via the address line 37 to write the data. Data is sent via line 38. When the main storage device 34 accepts the write request, it writes the data sent via the data line 38 to the address notified via the address line 37. The processor 32 performs the above processing until the data of all registers in the general-purpose register group 33 is transferred to the main storage device 34, and starts interrupt processing after the save processing is completed.

[Problem to be solved by the invention]

In the conventional save processing method described above, the processor fetches data from individual registers in the general-purpose register group and issues a write request to the main memory each time the data is written. The disadvantage is that the start of processing is delayed.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide a save processing method that enables save processing to be performed in parallel with interrupt processing, thereby making it possible to speed up the start of interrupt processing by a processor.

[Means to solve the problem]

The save processing method of the present invention provides a data processing device capable of performing interrupt processing according to an interrupt level, which includes two general-purpose register groups that hold data to be processed by a processor, and one general-purpose register group that holds data processed by a processor. The two allocations indicating that a group allocation is being performed are a flag and a method for saving the contents of the general-purpose register group allocated to the processor in the current process when an interrupt processing request occurs to the data processing device. an address generating circuit that instructs the register address of a register to be saved to this memory and a memory address of a saving destination; and an interrupt notification from the processor and the allocation is performed based on flag information. and a save control circuit that notifies the user of the start of save processing, selects a register address used in the general-purpose register group, selects data to be saved in the memory, and sets and resets a flag for the allocation.

[Effect]

In the save processing method of the present invention, two general-purpose register groups hold data to be processed by the processor, two allocation flags indicate that the general-purpose register group is allocated to the processor, and the memory is used by the data processing device. When an interrupt processing request occurs, the contents of the general-purpose register group allocated to the processor in the current processing are saved, and the address generation circuit instructs the register address of the register to be saved to memory and the memory address of the save destination. Then, the save control n circuit notifies the memory and address generation circuit of the start of save processing based on the interrupt notification from the processor and the allocation flag information, selects the register address used in the general-purpose register group, and saves it to the memory. Data selection and allocation involves setting and resetting flags.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a circuit block diagram showing the configuration of a data processing apparatus I in which a save processing method according to an embodiment of the present invention is applied. This data processing device 1 includes a processor 2, general-purpose register groups 3 and 4, a save control circuit 5, and a memory 6.
, address generation circuit 7, allocation is flags 8 and 9, selectors 10 to 13, and register address 49114.
~17, memory address line 18, and control lines 19~22
The main part is composed of data lines 23 to 27, and a monitoring line 2nd.

The processor 2 is a circuit that processes data sent via the data line 25.

The general-purpose register group 3 and the general-purpose register group 4 are circuits that hold data processed by the processor 2.

The save control circuit 5 switches the control line 2 according to the instruction from the control line I9.
0 to the memory 6 and the address generation circuit 7, and information from the monitor line 28 is sent to the selector 10.0 via the control line 21. Selector 11. A selection instruction is given to the selector 12 and the selector 13, and the assignment is flag 8 and the assignment is flag 90 via the control line 22.
This is a circuit that performs cent or reset.

The memory 6 is a memory dedicated to save processing that stores data sent via a data line 26 to an address designated by a memory address line 18 in response to an instruction from a control line 20.

The address generation circuit 7 is a circuit that generates a memory address and a register address according to instructions from the control line 20, and sends out the register address and the memory address via the register address line 15 and the memory address 118, respectively.

The allocation flag 8 and the allocation flag 9 are flags that display the allocation of the general-purpose register group 3 and the general-purpose register group 4 to the processor 2. It is set or set by 22.

Selector IO and selector 11 are selectors that output register addresses sent via register address line 15 or register address line 14 to register address line 17 and register address line 16, respectively, according to instructions from control line 21.

Selector 12 and selector 13 are selectors that output data sent via data line 23 or data line 24 to data line 26 and data line 25, respectively, according to instructions from control line 21.

Next, the operation of the save processing method of this embodiment configured as described above will be explained.

When a request for interrupt processing is generated in the data processing device 1, the processor 2 notifies the save control circuit 5 via the control line 19 that the request for interrupt processing has been generated.

The save control circuit 5 switches the control line 2 according to an instruction from the control line 19.
0 and notifies the start of the save process via the monitor line 28.
The assignment is sent via the control line 21 to the selector 10. in accordance with the information of the assignment flag 8 and the assignment flag 9. Selector 11. The selector 12 and the selector 13 are selected, and the control line 22 sets or assigns flag 8 for allocation and flag 9 for allocation.

For example, in the process immediately before interrupt processing, processor 2
Monitor that general-purpose register group 3 is allocated to
When the information of allocation flag 8 and allocation flag 9 sent via A28 indicates (when allocation flag 8 is cents and allocation flag 9 is reset)
, the save control circuit 5 selects the register address line 15 as the output of the selector 1O by the control iTI line 21, selects the register address line 14 as the output of the selector 11, selects the data line 23 as the output of the selector 12,
The data line 24 is selected as the output of the selector 13. At the same time, the control line 22 resets the allocation flag 8, and the control yA22 sets the allocation flag 9, thereby allocating the general-purpose register group 4 to the processor 2 that is about to start interrupt processing. As a result, processor 2 uses the register address &? 114, notifies the register address to the general-purpose register group 4 via the selector 11 and the register address line 16, and sets data in the general-purpose register group 4 via the data line 27, and
．． Data in the general-purpose register group 4 can be loaded via the selector 13 and the data line 25.

After the general-purpose register group 4 is allocated, the processor 2 uses the general-purpose register group 4 to start interrupt processing.

In parallel with the interrupt processing of the processor 2, the address generation circuit 7 performs control? 11 line 20, register addresses and memory addresses to be subjected to save processing are sequentially generated, and register address line 15. The register address is notified to the general-purpose register group 3 via the selector 10 and the register address line 17, and the memory address is notified to the memory 6 via the memory address line 1.

General-purpose register group 3 transfers the contents of the register designated by register address line 17 to data line 23 . Selector 12
and sequentially sent to the memory 6 via the data line 26.

Memory 6 fits! 20, the data sent via the data line 26 is sequentially stored in the memory specified by the memory address line 18.

Then, the above save process is performed in parallel with the interrupt process until all the contents of the general purpose register group 3 are stored in the memory 6.

〔Effect of the invention〕

As explained above, the present invention is equipped with two general-purpose register groups and a memory dedicated to save processing, so that save processing can be performed in parallel with interrupt processing, thereby allowing the processor to start interrupt processing earlier. effective.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing the configuration of a data processing apparatus to which a save processing method according to an embodiment of the present invention is applied, and FIG. 2 is a diagram for explaining a conventional save processing method. In the figure, l...data processing device, 2...3, 4...5...6...7...8, 9...10-13, 14-17, 18...19 ~22・23~27・28・・・ Processor, general-purpose register group, save control circuit, memory, address generation circuit, allocation is flag, selector, register address line, memory address line, control line, data line, monitoring line be.

Claims (1)

[Scope of Claims] A data processing device capable of performing interrupt processing according to an interrupt level, comprising: two general-purpose register groups that hold data to be processed by a processor; and an allocation of the general-purpose register group to the processor. a memory for saving the contents of the general-purpose register group allocated to the processor in the current process when an interrupt processing request occurs to the data processing device; an address generation circuit that instructs a register address of a register to be saved and a memory address of a save destination; and an address generation circuit that instructs the memory and the address generation circuit to start a save process based on an interrupt notification from the processor and information on the allocation flag. A save processing method comprising: a save control circuit that notifies and selects a register address to be used in the general-purpose register group, selects data to be saved to the memory, and sets and resets the allocation flag.