JPH01283839A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH01283839A
JPH01283839A JP11301988A JP11301988A JPH01283839A JP H01283839 A JPH01283839 A JP H01283839A JP 11301988 A JP11301988 A JP 11301988A JP 11301988 A JP11301988 A JP 11301988A JP H01283839 A JPH01283839 A JP H01283839A
Authority
JP
Japan
Prior art keywords
substrate
polyimide
moisture
semiconductor device
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11301988A
Other languages
Japanese (ja)
Inventor
Juri Kato
樹理 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP11301988A priority Critical patent/JPH01283839A/en
Publication of JPH01283839A publication Critical patent/JPH01283839A/en
Pending legal-status Critical Current

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  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To prevent invasion of moisture into inside of an IC from the periphery of the IC clip so as to improve humidity resistance and elevate reliability by contacting, in a scribe area, an Si substrate or thermal oxide film on the Si substrate directly with polyimide resin formed at the upper layer. CONSTITUTION:An ICAL pad 2 is formed on an Si substrate 1, which is covered with a passivation CVD SiO2 3 and CVD Si3N4 and further covered with a polyimide film 5 in a scribe area 6, and there the polyimide 5 contacts directly with the Si substrate 1. Accordingly, moisture invading from the interface 11 is absorbed in the polyimide 5 having high hygroscopicity and does not permeate into the inside. Hereby, moisture and contaminant do not invade inside the IC. which realizes the product with high reliability.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はSiを基板とする半導体装置に関し、特に高信
品1cを必要とする分野において有効である。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device using Si as a substrate, and is particularly effective in a field requiring a high-reliability product 1c.

〔発明の[要〕[Essentials of the invention]

本発明は、ICチップの周辺、スクライブ構造において
、Si基板またはSi基板上の熱酸化膜と上層に形成す
るポリイミド樹脂か直接、接して成ることを特徴とした
半導体装置に関する。
The present invention relates to a semiconductor device characterized in that in the periphery of an IC chip or in a scribe structure, a Si substrate or a thermal oxide film on the Si substrate is in direct contact with a polyimide resin formed as an upper layer.

〔従来の技術〕[Conventional technology]

従来、ICチップの周辺は、第3図に示すように、Si
基板1のスクライブ領域6には、CVD蓄積したS i
 O2が接し、その上にCVD蓄積した5llN4膜4
が形成されていた。
Conventionally, the periphery of an IC chip is made of Si, as shown in Figure 3.
In the scribe area 6 of the substrate 1, CVD accumulated S i
5llN4 film 4 that is in contact with O2 and has been accumulated by CVD
was formed.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、従来の半導体装置ではCVD SiO2
膜3とSi基板1の界面から、水分及び水分に含まれた
不純物が侵入し、例えば、ALパッド2を腐蝕しICの
不良原因となっている6本発明の目的は、ICチップ周
辺から、IC内部への水分の侵入を防ぎ、耐湿性を改善
、高信頼度の半導体装置を提供することにある。
However, in conventional semiconductor devices, CVD SiO2
Moisture and impurities contained in the moisture enter from the interface between the film 3 and the Si substrate 1, corroding the AL pad 2 and causing IC failure. The purpose of this invention is to prevent moisture from entering inside an IC, improve moisture resistance, and provide a highly reliable semiconductor device.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、CV D S iO2膜またはCVDSi、
N<とSi基板からの水分の侵入を防ぐため、CV D
 (’) S i O2またはS l s N 4 (
7)外側ノスクライブ領域には、ポリイミドが直接Si
基板または熱酸化5sto2上に接している構造を持つ
The present invention is a CV D SiO2 film or CVDSi,
To prevent moisture from entering from the N< and Si substrates, CVD
(') S i O2 or S l s N 4 (
7) Polyimide is directly attached to Si in the outer noscribed area.
It has a structure in contact with the substrate or thermal oxidation 5sto2.

〔作 用〕[For production]

この場合、ポリイミドとSi基板または熱酸化膜界面か
ら侵入した水分は1、吸湿性を持つポリイミドにて吸収
され、IC内部への水分の侵入を防ぐことができる。こ
のため、本発明に依れば、ICチップ周辺から、IC内
部への水分及び汚染物質の侵入がなく、言信頼度の半導
体装置を提供する。
In this case, moisture that has entered from the interface between the polyimide and the Si substrate or the thermal oxide film is absorbed by the hygroscopic polyimide, thereby preventing moisture from entering into the IC. Therefore, according to the present invention, there is provided a highly reliable semiconductor device in which moisture and contaminants do not enter into the IC from around the IC chip.

〔実 施 例〕〔Example〕

以下、実施例を用いて詳細に説明する。第1図及び第2
図は、本発明による半導体装置の実施例で、パッド及び
スクライブ領域造の断面図である。
Hereinafter, it will be explained in detail using examples. Figures 1 and 2
The figure is a cross-sectional view of a pad and scribe region structure in an embodiment of a semiconductor device according to the present invention.

第1図は、Si基板1上ICALバツド2が形成サレ、
パッシベーションCvDSiO23、C■DSisNa
4に覆れ、さらに、スクライブ領域6は、ポリイミド膜
5で覆われ、ポリイミド5は、直接Si基板1と接触し
ている。8はパッド開穴部であり、後工程で、外部との
接続をするなめ例えばハンダバンプ、ボンディングを行
なう領域である。第2図は、Si基板1に熱酸化膜7が
存在し、ALパッド2が形成され、パッシベーションS
 i s N 4膜4及びポリイミドg!5で覆れてい
る。
FIG. 1 shows the formation of the ICAL bump 2 on the Si substrate 1.
Passivation CvDSiO23, C■DSisNa
Furthermore, the scribe region 6 is covered with a polyimide film 5 , and the polyimide 5 is in direct contact with the Si substrate 1 . Reference numeral 8 denotes a pad opening, which is an area where connection with the outside, such as a solder bump or bonding, will be performed in a later process. In FIG. 2, a thermal oxide film 7 is present on a Si substrate 1, an AL pad 2 is formed, and a passivation S
is N 4 membrane 4 and polyimide g! It is covered with 5.

スクライブ領域6は、ポリイミド膜5と熱酸化膜7が直
接接触している9本発明の実施例では、IC周辺、スク
ライブ領域では、ポリイミド膜が直接Si基板または熱
酸化膜に接触し、かつ、CvD S i O2またはC
V D S 12N sまたはSi基板が接触する界面
、例えば第3図の界面9.10が、ポリイミドで覆われ
ている。従って、第1.2図の界面11から侵入する水
分は、吸湿性の高いポリイミド5に吸収され、内部に浸
透しない。
In the scribe region 6, the polyimide film 5 and the thermal oxide film 7 are in direct contact with each other.9 In the embodiment of the present invention, around the IC, in the scribe region, the polyimide film is in direct contact with the Si substrate or the thermal oxide film, and CvD Si O2 or C
The interface with which the V D S 12N s or Si substrate comes into contact, for example interface 9.10 in FIG. 3, is covered with polyimide. Therefore, moisture entering from the interface 11 in FIG. 1.2 is absorbed by the highly hygroscopic polyimide 5 and does not penetrate inside.

なお、第2図における界面12は、熱酸化膜とSi基板
の界面で、ここからの水分の拡散はほとんど無視できる
Note that the interface 12 in FIG. 2 is the interface between the thermal oxide film and the Si substrate, and the diffusion of moisture from this interface can be almost ignored.

〔発明の効果〕〔Effect of the invention〕

以上から、本発明による半導体装置は、耐湿性に優れた
高信頼度ICを提供する。
As described above, the semiconductor device according to the present invention provides a highly reliable IC with excellent moisture resistance.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は本発明による実施例を示す半導体装
置の断面図を示す、第3図は従来の半導体装置の断面図
を示す。 1・・・Si基板 2・・・ALパッド 3・・・CvDSiO2 4・・・CvDSi、N4 5・・・ポリイミド 6・・・スクライブ領域 7・・・熱酸化膜 8・・・パッド開穴部 9.10.11.12 ・・・各々の膜の界面 以上 出願人 セイコーエプソン株式会社 代理人 弁理士 上 柳 雅 誉(他1名)71図 Ji 2図 ?
1 and 2 show a cross-sectional view of a semiconductor device according to an embodiment of the present invention, and FIG. 3 shows a cross-sectional view of a conventional semiconductor device. 1... Si substrate 2... AL pad 3... CvDSiO2 4... CvDSi, N4 5... Polyimide 6... Scribe region 7... Thermal oxide film 8... Pad opening part 9.10.11.12 ...More than the interface of each film Applicant Seiko Epson Co., Ltd. Agent Patent attorney Masa Homare Kamiyanagi (and 1 other person) Figure 71 Ji Figure 2?

Claims (1)

【特許請求の範囲】[Claims]  ICチップの周辺、すなわちスクライブ領域が、Si
基板またはSi基板上の熱酸化膜と上層に形成するポリ
イミド樹脂が直接、接して成ることを特徴とする半導体
装置。
The periphery of the IC chip, that is, the scribe area, is
A semiconductor device characterized in that a thermal oxide film on a substrate or a Si substrate is in direct contact with a polyimide resin formed as an upper layer.
JP11301988A 1988-05-10 1988-05-10 Semiconductor device Pending JPH01283839A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11301988A JPH01283839A (en) 1988-05-10 1988-05-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11301988A JPH01283839A (en) 1988-05-10 1988-05-10 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH01283839A true JPH01283839A (en) 1989-11-15

Family

ID=14601402

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11301988A Pending JPH01283839A (en) 1988-05-10 1988-05-10 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH01283839A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5358883A (en) * 1992-02-03 1994-10-25 Motorola, Inc. Lateral bipolar transistor
US5923072A (en) * 1994-08-19 1999-07-13 Fujitsu Limited Semiconductor device with metallic protective film
US5990542A (en) * 1995-12-14 1999-11-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US5990491A (en) * 1994-04-29 1999-11-23 Semiconductor Energy Laboratory Co., Ltd. Active matrix device utilizing light shielding means for thin film transistors
US6225218B1 (en) 1995-12-20 2001-05-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and its manufacturing method
US6800875B1 (en) 1995-11-17 2004-10-05 Semiconductor Energy Laboratory Co., Ltd. Active matrix electro-luminescent display device with an organic leveling layer
US7163854B2 (en) 1996-11-07 2007-01-16 Semiconductor Energy Laboratory Co., Ltd. Fabrication method of a semiconductor device

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5358883A (en) * 1992-02-03 1994-10-25 Motorola, Inc. Lateral bipolar transistor
US5990491A (en) * 1994-04-29 1999-11-23 Semiconductor Energy Laboratory Co., Ltd. Active matrix device utilizing light shielding means for thin film transistors
US6501097B1 (en) 1994-04-29 2002-12-31 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device
US5923072A (en) * 1994-08-19 1999-07-13 Fujitsu Limited Semiconductor device with metallic protective film
US6867434B2 (en) 1995-11-17 2005-03-15 Semiconductor Energy Laboratory Co., Ltd. Active matrix electro-luminescent display with an organic leveling layer
US6800875B1 (en) 1995-11-17 2004-10-05 Semiconductor Energy Laboratory Co., Ltd. Active matrix electro-luminescent display device with an organic leveling layer
US6787887B2 (en) * 1995-12-14 2004-09-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US5990542A (en) * 1995-12-14 1999-11-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US7034381B2 (en) 1995-12-14 2006-04-25 Semiconductor Energey Laboratory Co., Ltd. Semiconductor device
US6225218B1 (en) 1995-12-20 2001-05-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and its manufacturing method
US7750476B2 (en) 1995-12-20 2010-07-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a reliable contact
US7163854B2 (en) 1996-11-07 2007-01-16 Semiconductor Energy Laboratory Co., Ltd. Fabrication method of a semiconductor device
US7470580B2 (en) 1996-11-07 2008-12-30 Semiconductor Energy Laboratory Co., Ltd. Fabrication method of a semiconductor device

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