JPH01232765A - Insulated-gate field-effect transistor - Google Patents
Insulated-gate field-effect transistorInfo
- Publication number
- JPH01232765A JPH01232765A JP5736388A JP5736388A JPH01232765A JP H01232765 A JPH01232765 A JP H01232765A JP 5736388 A JP5736388 A JP 5736388A JP 5736388 A JP5736388 A JP 5736388A JP H01232765 A JPH01232765 A JP H01232765A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- main body
- drain
- channel
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 18
- 239000000463 material Substances 0.000 claims abstract description 27
- 230000000694 effects Effects 0.000 abstract description 19
- 238000000034 method Methods 0.000 abstract description 16
- 239000012535 impurity Substances 0.000 abstract description 11
- 238000005468 ion implantation Methods 0.000 abstract description 9
- 239000000969 carrier Substances 0.000 abstract description 6
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 230000006866 deterioration Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 37
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 30
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 18
- 235000012239 silicon dioxide Nutrition 0.000 description 15
- 239000000377 silicon dioxide Substances 0.000 description 15
- 108091006146 Channels Proteins 0.000 description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 230000005684 electric field Effects 0.000 description 9
- 229910052697 platinum Inorganic materials 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000005360 phosphosilicate glass Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000000116 mitigating effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔ａ要］
絶縁ゲート電界効果トランジスタ（ＭＯＳＦＥＴ）の改
良に関し、特に、ゲートとドレインとの間に薄くドーピ
ングされた領域が付加されているドレイン（Ｌ Ｄ Ｄ
（Ｌｉｇｈｔｌｙ Ｄｏｐｅｄ Ｄｒａｉｎ） ）を
有するＭＯＳ Ｆ ＥＴのＬＤＤ内の電界強度を緩和す
る構造的改良に関し、
短チャンネル効果を生ずることなく、またホントキャリ
ヤによるａ能劣化を生ずることのないＭＯＳＦＥＴを提
供することを目的とし、絶縁ゲート電界効果トランジス
タのゲート電極を、チャンネルに対応する領域に形成さ
れる主体部と、ゲート電極に対応する領域とソース・ド
レイン領域に対応する領域との間に前記主体部の側壁に
連接して形成される縁端部とをもって構成し、該縁端部
を構成する材料の仕事関数を、前記主体部を構成する材
料の仕事関数と異なる値とすることにより構成される。DETAILED DESCRIPTION OF THE INVENTION [a] This invention relates to improvements in insulated gate field effect transistors (MOSFETs), and in particular to improvements in insulated gate field effect transistors (MOSFETs), in which a thinly doped region is added between the gate and the drain (LDD
(Lightly Doped Drain)) To provide a MOSFET that does not cause short channel effects or deterioration of a-power due to real carriers, with regard to structural improvement for mitigating the electric field strength in an LDD of a MOSFET having a light carrier. For the purpose of It is constructed by having an edge portion formed in connection with the side wall, and the material making up the edge portion has a work function different from the work function of the material making up the main body portion.
本発明は、絶縁ゲート電界効果トランジスタ（ＭＯＳＦ
ＥＴ）の改良に関する。特に、ゲートとドレインとの間
に薄くドーピングされた領域が付加されているドレイン
（Ｌ Ｄ Ｄ （Ｌｉｇｈｔｌｙ Ｄｏｐ−ｅｄ Ｄｒ
ａｉｎ） ）を有するＭＯＳ Ｆ ＥＴのＬＤＤ内の電
界強度を緩和する構造的改良に関する。The present invention is an insulated gate field effect transistor (MOSF)
ET). In particular, a lightly doped Dr.
This invention relates to a structural improvement for mitigating the electric field strength in an LDD of a MOS FET with ain) ).
ＭＯＳＦＥＴのソース・ドレイン間の電位曲線は、ドレ
イン近傍において電位変化率が最も大きい。すなわち、
ドレイン近傍において電界強度が最も高い。そこで、ド
レインのゲート電極に近い領域に、不純物濃度の低い領
域（ＬＤＤ層）を浅（形成すれば、ドレイン近傍の電位
変化率が緩くなり、したがって、ドレイン近傍の電界強
度が低下することが知られている。In the source-drain potential curve of a MOSFET, the potential change rate is greatest near the drain. That is,
The electric field strength is highest near the drain. Therefore, it is known that if a shallow region with low impurity concentration (LDD layer) is formed in the region close to the gate electrode of the drain, the rate of change in potential near the drain becomes slower, and therefore the electric field strength near the drain decreases. It is being
しかし、素子の微細化が進み、ゲート長すなわちソース
・ドレイン間の距離が短くなると、電界強度レヘルが全
体的に高くなり、電界強度の最も高いドレイン近傍にお
いて高いエネルギーを持ったホットキャリヤが発生し、
そのホットキャリヤがゲート絶縁膜と半導体層との界面
あるいはゲート絶縁膜中に入り、そのためＭＯＳＦＥＴ
のしきい値が変化する現象（ホットキャリヤ効果）が発
生するようになった。However, as devices become smaller and the gate length, that is, the distance between the source and drain becomes shorter, the electric field strength level increases overall, and hot carriers with high energy are generated near the drain where the electric field strength is highest. ,
The hot carriers enter the interface between the gate insulating film and the semiconductor layer or into the gate insulating film, and therefore the MOSFET
A phenomenon in which the threshold value changes (hot carrier effect) has started to occur.
この現象（ホットキャリヤ効果）は、種々解析された結
果、ゲート電極とドレインとのオーバーランプ量を大き
くすれば、ホットキャリヤによるＭＯＳＦＥＴのしきい
値の変化が少なくなることが判明した。これは、ゲート
電極とドレインとをオーバーランプさせると、このオー
バーラツプされた領域の薄い不純物濃度の領域（ＬＤＤ
）によってソース・ドレイン間の電位分布が平均化され
、トレイン近傍における電位の勾配が緩くなり、ドレイ
ン近傍での電界強度が緩和されるからである。As a result of various analyzes of this phenomenon (hot carrier effect), it has been found that if the amount of overlap between the gate electrode and the drain is increased, the change in the threshold value of the MOSFET due to hot carriers will be reduced. When the gate electrode and drain are overlamped, this overlapped region has a thin impurity concentration region (LDD).
), the potential distribution between the source and drain is averaged, the potential gradient near the train becomes gentler, and the electric field intensity near the drain is relaxed.
第９図参照
そこで、このゲート電極とトレインとをオーバーランプ
させＬＤＤを積極的に形成する方法として、第９図に示
すように、多結晶シリコン等よりなるゲート電極４０の
表面に対して斜め方向からイオンを注入して、ゲート電
極４０と接する半導体基板４１の表層に不純物を導入し
てドレイン４４を形成するとともに、ゲート電極４０と
オーバーラツプするＬＤＤ層２を形成する方法が使用さ
れるようになった。なお、図中、４３はゲート絶縁膜で
ある。Refer to FIG. 9 Therefore, as a method of positively forming an LDD by overlamping the gate electrode and the train, as shown in FIG. A method has come to be used in which ions are implanted to introduce impurities into the surface layer of the semiconductor substrate 41 in contact with the gate electrode 40 to form the drain 44 and to form the LDD layer 2 overlapping the gate electrode 40. Ta. Note that in the figure, 43 is a gate insulating film.
前記の斜めイオン注入法を使用して、ゲート電極とドレ
インとの間に十分なオーバーラツプ領域（ＬＤＤ碩域）
を形成しようとすると、必然的に、ドレイン４４の拡散
深さが深くなってしまい、ソース・ドレイン間隔が短い
短チヤンネルトランジスタにおいて問題となる短チャン
ネル効果が顕著に発生し、しきい値電圧の低下等の問題
が生ずるようになった。Using the above-mentioned oblique ion implantation method, a sufficient overlap region (LDD region) is created between the gate electrode and the drain.
If an attempt is made to form a transistor, the diffusion depth of the drain 44 will inevitably become deep, and the short channel effect, which is a problem in short channel transistors with a short source-drain distance, will occur, resulting in a decrease in the threshold voltage. Problems such as these have started to occur.
本発明の目的は、これらの欠点を解消することにあり、
短チャンネル効果を生ずることなく、またホントキャリ
ヤ効果による機能劣化を生ずることのないＭＯＳＦＥＴ
を提供することにある。The purpose of the present invention is to eliminate these drawbacks,
MOSFET that does not cause short channel effects or functional deterioration due to real carrier effects
Our goal is to provide the following.
（課題を解決するための手段〕
上記の目的は、絶縁ゲート電界効果トランジスタのゲー
ト電極（６・２７）を、チャンネルに対応する領域に形
成される主体部（６１・２３）と、ゲート電極（６・２
７）に対応する領域とソース・ドレイン領域（１０・２
９）に対応する領域との間に前記主体部（６１・２３）
の側壁に連接して形成される縁端部（６２・２６）とを
もって構成し、該縁端部（６２・２６）を構成する材料
の仕事関数を、前記主体部（６１・２３）を構成する材
料の仕事関数と異なる値とすることによって達成される
。(Means for Solving the Problems) The above object is to separate the gate electrodes (6, 27) of an insulated gate field effect transistor from the main body (61, 23) formed in the region corresponding to the channel and the gate electrode (6, 27) 6.2
7) and the source/drain region (10.2
9) between the main body part (61 and 23)
The main body part (61, 23) is composed of an edge part (62, 26) formed in connection with the side wall of the main body part (61, 23), and the work function of the material forming the edge part (62, 26) This is achieved by setting the work function of the material to a different value.
そして、ｎチャンネル型ＭＯ３ＦＥＴの場合は、前記縁
端部（６２）の材料の仕事関数を、前記主体部（６１）
の材料の仕事関数より小さくし、また、ｐチャンネル型
ＭＯＳ Ｆ ＥＴの場合は、前記縁端部（６２）の材料
の仕事関数を、前記主体部（６１）の材料の仕事関数よ
り大きくすればよい。In the case of an n-channel MO3FET, the work function of the material of the edge portion (62) is set to the material of the main portion (61).
and in the case of a p-channel MOS FET, the work function of the material of the edge portion (62) is made larger than the work function of the material of the main body portion (61). good.
なお、前記縁端部（６２）の材料の仕事関数は、縁端部
（６２）内のすべての領域で同一であっても、また同一
でなくてもよく、さらに縁端部（６２）の材料を主体部
（６１）の材料と異なる材料をもって構成することも、
また主体部（６１）の材料と同一であるが、主体部（６
１）の材料とは反対の導電型を有する材料をもって構成
することもできる。Note that the work function of the material of the edge (62) may or may not be the same in all regions within the edge (62); The material may be made of a material different from that of the main body portion (61).
Also, although the material is the same as that of the main body part (61), the material of the main body part (61) is
It can also be constructed using a material having a conductivity type opposite to that of the material 1).
［作用〕
本発明に係る絶縁ゲート電界効果トランジスタにおいて
は、ゲート電極６・２７の主体部６１・２３と縁端部６
２・２６とを異なる仕事関数を有する材料をもって形成
すること＼されているので、絶縁部下部のチャンネル領
域には主体部下部のチャンネル領域よりも前記仕事関数
差分だけ多く可動電荷が誘起され、あたかも、ＬＤＤが
縁端部６２・２６の下部領域まで延在していると同様に
、ホットキャリヤ効果は抑制される。換言すれば、ドレ
イン近傍における電位の勾配が緩やかになり、ドレイン
近傍での電界強度が低下する。その結果、ホントキャリ
ヤの発生にもとづく欠陥が解消する。しかも、従来技術
で実行された斜めイオン注入法等が不要となるので、ド
レインの拡散深さを浅く形成することができ、短チャン
ネル効果も防止できる。[Function] In the insulated gate field effect transistor according to the present invention, the main portions 61 and 23 and the edge portions 6 of the gate electrodes 6 and 27
2 and 26 are formed using materials having different work functions, more mobile charges are induced in the channel region under the insulating portion than in the channel region under the main body portion by the work function difference, as if , the LDD extends to the lower regions of the edges 62, 26 as well, hot carrier effects are suppressed. In other words, the potential gradient near the drain becomes gentler, and the electric field intensity near the drain decreases. As a result, defects caused by the generation of true carriers are eliminated. Moreover, since the oblique ion implantation method performed in the prior art is not necessary, the drain diffusion depth can be formed to be shallow, and the short channel effect can also be prevented.
以下、図面を参照しつ一１本発明の二つの実施例に係る
ＭＯＳ Ｆ ＥＴについて説明する。MOS FETs according to two embodiments of the present invention will be described below with reference to the drawings.
策１貫
第２図参照
ｐ型シリコン基板ｌに、ＬＯＣＯ３用窒化シリコンマス
ク（図示せず）を使用してｐ゛イオン注入なしてチャン
ネルカット層３を形成し、ＬＯＣＯ８法を使用してフィ
ールド絶縁１１！２を形成して素子分離をなす。酸化し
て全面に約２００人厚の二酸化シリコン膜４を形成し、
この二酸化シリコンｌ！Ｊ４を介してしきい値電圧制御
用のイオン注入をした後、気相成長法を使用して全面に
多結晶シリコン層を形成し、ｐ型不純物例えばボロンを
イオン注入してｐ”型多結晶シリコン層５を形成する。Plan 1: Refer to Figure 2. A channel cut layer 3 is formed on a p-type silicon substrate l using a silicon nitride mask for LOCO3 (not shown) without P ion implantation, and field insulation is performed using the LOCO8 method. 11!2 is formed to perform element isolation. Oxidize to form a silicon dioxide film 4 about 200 mm thick on the entire surface,
This silicon dioxide! After ion implantation for threshold voltage control through J4, a polycrystalline silicon layer is formed on the entire surface using a vapor phase growth method, and p type impurities such as boron are ion implanted to form a p'' type polycrystalline silicon layer. A silicon layer 5 is formed.
第３図参照
フォトリソグラフィー法を使用してｐ”型多結晶シリコ
ンＮ５渣パターニングしてｐ”型多結晶シリコン層より
なるゲート電極６を形成し、このゲート電極６をマスク
として、ｎ型不純物例えばヒ素を、打ち込みイオンエネ
ルギー６０Ｋｅ Ｖ、ドーズ量Ｉ Ｘ１０１３ｃｍ−”
をもってイオン注入し、５００〜６００人厚のｎ−型Ｌ
ＤＤ層７を形成する。Refer to FIG. 3. A p" type polycrystalline silicon N5 residue is patterned using a photolithography method to form a gate electrode 6 made of a p" type polycrystalline silicon layer, and using this gate electrode 6 as a mask, an n type impurity, e.g. Arsenic was implanted at an ion energy of 60 Ke V and a dose of I x 1013 cm.
500 to 600 thick n-type L
A DD layer 7 is formed.
第４図参照
ＣＶＤ法を使用して、リンを１２％程度含んだリン珪酸
ガラス（ＰＳＧ）層８を全面に約２００ｎ−厚に形成す
る。Referring to FIG. 4, a phosphosilicate glass (PSG) layer 8 containing approximately 12% phosphorus is formed to a thickness of approximately 200 nm over the entire surface using the CVD method.
第５図参照
異方性エツチングをなして、ｐ”型多結晶シリコンより
なるゲート電極６の側壁部のみにＰＳＧ帯９を残留する
。Referring to FIG. 5, anisotropic etching is performed to leave the PSG band 9 only on the side walls of the gate electrode 6 made of p'' type polycrystalline silicon.
第６図参照
ゲート電極６とＰＳＧ帯９とをマスクとしてｎ型不純物
例えばヒ素を、打ち込みイオンエネルギー７０Ｋｅ Ｖ
、ドーズ量４ Ｘｌ０ＩＳｅｌｌ−”をもってイオン注
入し、濃くドーピングされたｎ ＋−型ソース・ドレイ
ン１０を形成する。Refer to FIG. 6. Using the gate electrode 6 and PSG band 9 as a mask, an n-type impurity such as arsenic is implanted at an ion energy of 70 Ke V.
, and a dose of 4Xl0ISell-'' to form a heavily doped n + -type source/drain 10.
第１ａ図参照
ソース・ドレインの活性化も兼ねζ、窒素ガス中におい
て９５０’Ｃに加熱し、約３０分間アニールする。ＰＳ
Ｇ帯９に含まれている不純物のリンがρ゛゛多結晶シリ
コンよりなるゲート電極６中に拡散し、ゲート電極６の
ソース・ドレインとの境界をなす縁端部６２がゲート電
極の主体部６１とは反対導電型のｎ°型に転換する。Referring to FIG. 1a, the source and drain are also activated by heating to 950'C in nitrogen gas and annealing for about 30 minutes. P.S.
The impurity phosphorus contained in the G band 9 is diffused into the gate electrode 6 made of polycrystalline silicon, and the edge portion 62 forming the boundary between the source and drain of the gate electrode 6 becomes the main portion 61 of the gate electrode. It converts to n° type, which is the opposite conductivity type.
ＣＶＤ法を使用して、二酸化シリコン膜等からなるゲー
ト電極用絶縁膜１１を形成し、ソース・ドレイン領域の
二酸化シリコン膜４にソース・ドレイン電極形成用開口
を形成した後、全面にアル迅ニウム膜等を形成し、リソ
グラフィー法を使用して、これをバターニングし、ソー
ス・ドレイン電極１２を形成する。Using the CVD method, a gate electrode insulating film 11 made of a silicon dioxide film or the like is formed, and openings for forming source/drain electrodes are formed in the silicon dioxide film 4 in the source/drain regions, and then aluminum is deposited on the entire surface. A film or the like is formed and patterned using a lithography method to form source/drain electrodes 12.
このようにして、ゲート電極６の主体部６１の仕事関数
が縁端部６２の仕事関数より大きく、しかも、縁端部６
２の仕事関数は、縁端部内において同一ではなく、主体
部６１からの距離により異なる値を有するＬＤＤ型ｎチ
ャンネルＭＯ３ＦＥＴが形成される。なお、図において
、１はＰ型シリコン′）！Ｅ＋ｉであり、２はフィール
ド絶縁膜であり、３はＰ１型チャンネルカット層であり
、７はＬＤＤ層であり、１０はｎ”ソース・ドレインで
ある。In this way, the work function of the main body portion 61 of the gate electrode 6 is larger than the work function of the edge portion 62, and
An LDD type n-channel MO3FET is formed in which the work function of No. 2 is not the same within the edge portion and has different values depending on the distance from the main body portion 61. In the figure, 1 is P-type silicon')! E+i, 2 is a field insulating film, 3 is a P1 type channel cut layer, 7 is an LDD layer, and 10 is an n'' source/drain.
爪Ｉ班
第７図参照
ｎ型シリコン基板２１に、ＬＯＣＯ３用窒化シリコンマ
スク（図示せず）を使用してｎ°イオン注入をなしてチ
ャンネルカントＮ２２を形成し、ＬＯＣＯ３法を使用し
てフィールド絶縁膜２を形成して素子分離をなす。酸化
して全面に約２００人厚の二酸化シリコン膜４を形成し
、この二酸化シリコン膜４を介してしきい値電圧制御用
のイオン注入をした後、気相成長法を使用して全面に多
結晶シリコン層を形成し、ｎ型不純物例えばヒ素をイオ
ン注入してｎ”型多結晶シリコン層とし、フォトリソグ
ラフィー法を使用してバターニングし、ｎ １゛型型詰
結晶シリコンよりなるゲート電極主体部２３を形成する
。次に、スパンタリング法等を使用して全面に白金層２
４を形成する。Nail Group I Refer to Figure 7 N° ion implantation is performed on the n-type silicon substrate 21 using a silicon nitride mask for LOCO3 (not shown) to form a channel cant N22, and field insulation is performed using the LOCO3 method. A film 2 is formed to provide element isolation. After oxidizing to form a silicon dioxide film 4 approximately 200 μm thick over the entire surface, and implanting ions for threshold voltage control through this silicon dioxide film 4, a large number of silicon dioxide films are formed over the entire surface using a vapor phase growth method. A crystalline silicon layer is formed, an n-type impurity such as arsenic is ion-implanted to form an n''-type polycrystalline silicon layer, and the layer is patterned using a photolithography method to form a gate electrode mainly made of n1゛-type packed crystalline silicon. Next, a platinum layer 2 is formed on the entire surface using a sputtering method or the like.
form 4.
第８図参照
白金層２４を異方性エンチングして、ゲート電極主体部
２３の側壁部のみに白金よりなるゲート電極縁端部２６
を残留する。ｎ°゛型多結晶シリコン層よりなるゲート
電極主体部２３と白金よりなるゲート電極縁端部２６と
よりなるゲート電極２７をマスクとして、ｐ型不純物例
えばボロンをイオン注入して）考＜ドーピングされた５
００〜６００人厚のｐ−層（Ｌ Ｄ Ｉ）層）２５を形
成し、ＣＶＤ法を使用して全面に二酸化シリコン層２８
を形成する。Refer to FIG. 8, the platinum layer 24 is anisotropically etched to form a gate electrode edge portion 26 made of platinum only on the side wall portion of the gate electrode main portion 23.
remain. Using the gate electrode 27 consisting of the gate electrode main part 23 made of an n° type polycrystalline silicon layer and the gate electrode edge part 26 made of platinum as a mask, p-type impurities such as boron are ion-implanted. 5
A p-layer (LDI layer) 25 with a thickness of 0 to 600 nm is formed, and a silicon dioxide layer 28 is formed on the entire surface using the CVD method.
form.
第ｉｂ閲参照
異方性エツチングをなして白金層からなるゲート電極縁
端部２６の側壁部に二酸化シリコン帯３ｏを残留する。Referring to No. ib, anisotropic etching is performed to leave a silicon dioxide band 3o on the side wall portion of the gate electrode edge portion 26 made of a platinum layer.
ｎ”型多結晶シリコン層よりなるゲート電極主体部２３
と白金層からなるゲート電極縁端部２６と二酸化シリコ
ン帯３０とをマスクとして、ｎ型不純物例えばボロンを
イオン注入して濃くドーピングされたｐ°゛型ソース・
ドレイン２９を形成する。Gate electrode main portion 23 made of n” type polycrystalline silicon layer
Using the gate electrode edge 26 made of a platinum layer and the silicon dioxide band 30 as masks, an n-type impurity such as boron is ion-implanted to form a heavily doped p-type source.
A drain 29 is formed.
ＣＶＤ法を使用して、二酸化シリコン膜等からなるゲー
ト電極用絶縁膜１１を形成し、ソース・ドレイン領域の
二酸化シリコン膜４にソース・ドレイン電極形成用開口
を形成した後、全面にアルミニウム膜等を形成し、これ
をリソグラフィー法を使用してバターニングし、ソース
・ドレイン電極１２を形成する。白金の仕事関数はｎ
゛＋型多結晶シリコンの仕事関数より大きいので、ゲー
ト電極の主体部２３の仕事関数が縁端部２６の仕事関数
より小さく、しかも、縁端部２６の仕事関数は縁端部内
において同一であるｐチャンネルＬＤＤ型ＭＯ８ＦＥＴ
が形成される。After forming a gate electrode insulating film 11 made of a silicon dioxide film or the like using the CVD method and forming openings for forming source/drain electrodes in the silicon dioxide film 4 in the source/drain regions, an aluminum film or the like is formed on the entire surface. is formed and patterned using a lithography method to form source/drain electrodes 12. The work function of platinum is n
Since it is larger than the work function of + type polycrystalline silicon, the work function of the main part 23 of the gate electrode is smaller than the work function of the edge part 26, and the work function of the edge part 26 is the same within the edge part. p-channel LDD type MO8FET
is formed.
（発明の効果〕
以上説明ゼるとおり、本発明に係る絶縁ゲート電界効果
トランジスタにおいては、ゲート電極の正体部と縁端部
とが異なる仕事関数を有する材料をもって形成されるの
で、ゲート電極とＬＤＤとのオーバーラツプ量が現実の
オーバーラツプ量よりさらに大きく形成されたＭＯＳＦ
ＥＴと同一の効果が発揮され、ＬＤＤ内の電界強度が緩
和される。換言すれば、ＬＤＤの効果は、ゲート電極縁
端部の下部領域まで及ぶので、ホットキャリヤ効果は十
分抑制されるにもか−わらず、ＬＤＤの役割を担う絶縁
部下部の反転電荷層は、従来技術で行われるイオン注入
層よりも非常に浅いので短チャンネル効果は発生しにく
くなる。(Effects of the Invention) As explained above, in the insulated gate field effect transistor according to the present invention, since the main part and the edge part of the gate electrode are formed of materials having different work functions, the gate electrode and the LDD A MOSF with a larger overlap amount than the actual overlap amount.
The same effect as ET is exhibited, and the electric field strength within the LDD is relaxed. In other words, the LDD effect extends to the region below the edge of the gate electrode, so the hot carrier effect is sufficiently suppressed. Since the ion implantation layer is much shallower than the ion implantation layer used in the prior art, short channel effects are less likely to occur.
その結果、−例として仕事関数の異なるゲート電極縁端
部の長さをＯ，１５ｎとした場合に、ホットキャリヤ効
果が２０％減少する実験結果が得られた。As a result, an experimental result was obtained in which the hot carrier effect was reduced by 20% when the length of the edge portion of the gate electrode having different work functions was set to 0.15 nm.
また、ドレインの拡散深さは浅く形成することができる
ので、しきい値電圧を低下させる等の短チャンネル効果
の発生も有効防止されることは上記のとおりである。Furthermore, since the drain diffusion depth can be formed shallow, short channel effects such as a decrease in threshold voltage can be effectively prevented from occurring, as described above.
第１ａ図は、本発明の第１実施例に係る絶縁ゲート電界
効果トランジスタの断面図である。
第１ｂ図は、本発明の第２実施例に係る絶縁ゲート電界
効果トランジスタの断面図である。
第２〜６図は、本発明の第１実施例に係る絶縁ゲート電
界効果トランジスタの工程図である。
第７．８図は、本発明の第２実施例に係る絶縁ゲート電
界効果トランジスタの工程図である。
第９図は、従来技術に係る斜めイオン注入の説明図であ
る。
ｌ・・・ｐ型シリコン基板、
２・・・フィールド絶縁膜、
３・・・ｐ０型チャンネルカット層、
４・・・二酸化シリコン膜（ゲート絶縁膜）、５・・・
ｐ″９型多結晶シリコン層、
６・・・ゲート電極、
６１・・・ゲート電極主体部、
６２・・・ゲート電極縁端部（主体部とは反対導電型領
域）、
７・・・ＬＤＤ層（ｎ−層）、
８・・・ＰＳＧ層、
９・・・ゲート電極の側壁に形成されたＰＳＧ帯、ｌＯ
・・・ｎ０型ソース・ドレイン、
１１・・・ゲート電極用絶縁膜、
１２・・・ソース・ドレイン電極、
２１・・・ｎ型シリコン基板、
２２・・・ｎ型チャンネルカット層、
２３・・・ｎ”型ゲート電極主体部、
２４・・・白金層、
２５・・・ＬＤＤ層（ｐ−層）、
２６・・・ゲート電極縁端部（白金層）、２７・・・ゲ
ート電極、
２８・・・二酸化シリコン層、
２９・・・ｐ゛型ソース・ドレイン、
３０・・・二酸化シリコン帯、
４０・・・ゲート電極、
４１・・・半導体基板。FIG. 1a is a cross-sectional view of an insulated gate field effect transistor according to a first embodiment of the invention. FIG. 1b is a cross-sectional view of an insulated gate field effect transistor according to a second embodiment of the invention. 2 to 6 are process diagrams of an insulated gate field effect transistor according to a first embodiment of the present invention. FIG. 7.8 is a process diagram of an insulated gate field effect transistor according to a second embodiment of the present invention. FIG. 9 is an explanatory diagram of oblique ion implantation according to the prior art. l...p-type silicon substrate, 2...field insulating film, 3...p0 type channel cut layer, 4...silicon dioxide film (gate insulating film), 5...
p″9 type polycrystalline silicon layer, 6... Gate electrode, 61... Gate electrode main part, 62... Gate electrode edge part (conductivity type region opposite to main part), 7... LDD layer (n-layer), 8... PSG layer, 9... PSG band formed on the side wall of the gate electrode, lO
...n0 type source/drain, 11...insulating film for gate electrode, 12...source/drain electrode, 21...n type silicon substrate, 22...n type channel cut layer, 23...・N” type gate electrode main part, 24... Platinum layer, 25... LDD layer (p- layer), 26... Gate electrode edge part (platinum layer), 27... Gate electrode, 28 ...Silicon dioxide layer, 29...P' type source/drain, 30...Silicon dioxide band, 40...Gate electrode, 41...Semiconductor substrate.
Claims (1)
る領域に形成される主体部（６１・２３）と、前記ゲー
ト電極（６・２７）に対応する領域とソース・ドレイン
領域（１０・２９）と対応する領域との間に、前記主体
部（６１・２３）の側壁に連接して形成される縁端部（
６２・２６）とを有し、 該縁端部（６２・２６）を構成する材料の仕事関数は、
前記主体部（６１・２３）を構成する材料の仕事関数と
異なる値を有する ことを特徴とする絶縁ゲート電界効果トランジスタ。 ［２］前記絶縁ゲート電界効果トランジスタはｎチャン
ネル型であり、 前記縁端部（６２・２６）を構成する材料の仕事関数は
、前記主体部（６１・２３）を構成する材料の仕事関数
より小さい ことを特徴とする請求項１記載の絶縁ゲート電界効果ト
ランジスタ。 ［３］前記絶縁ゲート電界効果トランジスタはｐチャン
ネル型であり、 前記縁端部（６２・２６）を構成する材料の仕事関数は
、前記主体部（６１・２３）を構成する材料の仕事関数
より大きい ことを特徴とする請求項１記載の絶縁ゲート電界効果ト
ランジスタ。 ［４］前記ゲート電極（６）の縁端部（６２）の材料は
、前記ゲート電極（６）の主体部（６１）の材料と同一
であり、前記主体部（６１）の導電型とは反対導電型で
ある ことを特徴とする請求項１、２、３、または、４記載の
絶縁ゲート電界効果トランジスタ。[Claims] [1] The gate electrode (6, 27) has a main body (61, 23) formed in a region corresponding to the channel, a region corresponding to the gate electrode (6, 27), and a source. - An edge portion (which is connected to the side wall of the main body portion (61, 23) and formed between the drain region (10, 29) and the corresponding region)
62, 26), and the work function of the material constituting the edge portion (62, 26) is:
An insulated gate field effect transistor having a work function different from that of a material constituting the main body portion (61, 23). [2] The insulated gate field effect transistor is an n-channel type, and the work function of the material forming the edge portion (62, 26) is lower than the work function of the material forming the main body portion (61, 23). An insulated gate field effect transistor according to claim 1, characterized in that it is small. [3] The insulated gate field effect transistor is a p-channel type, and the work function of the material forming the edge portion (62, 26) is lower than the work function of the material forming the main body portion (61, 23). 2. The insulated gate field effect transistor of claim 1, wherein the insulated gate field effect transistor is large. [4] The material of the edge portion (62) of the gate electrode (6) is the same as the material of the main portion (61) of the gate electrode (6), and the conductivity type of the main portion (61) is 5. The insulated gate field effect transistor according to claim 1, wherein the transistor is of opposite conductivity type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5736388A JPH01232765A (en) | 1988-03-12 | 1988-03-12 | Insulated-gate field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5736388A JPH01232765A (en) | 1988-03-12 | 1988-03-12 | Insulated-gate field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01232765A true JPH01232765A (en) | 1989-09-18 |
Family
ID=13053498
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5736388A Pending JPH01232765A (en) | 1988-03-12 | 1988-03-12 | Insulated-gate field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01232765A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5210435A (en) * | 1990-10-12 | 1993-05-11 | Motorola, Inc. | ITLDD transistor having a variable work function |
| JPH06163887A (en) * | 1992-11-16 | 1994-06-10 | Victor Co Of Japan Ltd | Semiconductor device and mosfet |
| JPH06232389A (en) * | 1993-02-04 | 1994-08-19 | Nec Corp | Field-effect transistor and its manufacture |
| US5426327A (en) * | 1990-10-05 | 1995-06-20 | Nippon Steel Corporation | MOS semiconductor with LDD structure having gate electrode and side spacers of polysilicon with different impurity concentrations |
| US5446298A (en) * | 1992-07-22 | 1995-08-29 | Rohm Co., Ltd. | Semiconductor memory device including a floating gate having an undoped edge portion proximate to a source portion of the memory device |
| US5466958A (en) * | 1992-10-30 | 1995-11-14 | Kabushiki Kaisha Toshiba | MOS-type semiconductor device having electrode structure capable of coping with short-channel effect and manufacturing method thereof |
| EP0798785A1 (en) * | 1996-03-29 | 1997-10-01 | STMicroelectronics S.r.l. | High-voltage-resistant MOS transistor, and corresponding manufacturing process |
| EP0856892A2 (en) * | 1997-01-30 | 1998-08-05 | Oki Electric Industry Co., Ltd. | MOSFET and manufacturing method thereof |
| US5894157A (en) * | 1993-06-25 | 1999-04-13 | Samsung Electronics Co., Ltd. | MOS transistor having an offset resistance derived from a multiple region gate electrode |
| US5998848A (en) * | 1998-09-18 | 1999-12-07 | International Business Machines Corporation | Depleted poly-silicon edged MOSFET structure and method |
| WO2005004240A1 (en) * | 2003-06-25 | 2005-01-13 | Micron Technology, Inc. | Tailoring gate work-function in image sensors |
| CN103794501A (en) * | 2012-10-30 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
-
1988
- 1988-03-12 JP JP5736388A patent/JPH01232765A/en active Pending
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5426327A (en) * | 1990-10-05 | 1995-06-20 | Nippon Steel Corporation | MOS semiconductor with LDD structure having gate electrode and side spacers of polysilicon with different impurity concentrations |
| US5210435A (en) * | 1990-10-12 | 1993-05-11 | Motorola, Inc. | ITLDD transistor having a variable work function |
| US5446298A (en) * | 1992-07-22 | 1995-08-29 | Rohm Co., Ltd. | Semiconductor memory device including a floating gate having an undoped edge portion proximate to a source portion of the memory device |
| US5466958A (en) * | 1992-10-30 | 1995-11-14 | Kabushiki Kaisha Toshiba | MOS-type semiconductor device having electrode structure capable of coping with short-channel effect and manufacturing method thereof |
| US5756365A (en) * | 1992-10-30 | 1998-05-26 | Kabushiki Kaisha Toshiba | Method of manufacturing MOS-type semiconductor device having electrode structure capable of coping with short-channel effects |
| JPH06163887A (en) * | 1992-11-16 | 1994-06-10 | Victor Co Of Japan Ltd | Semiconductor device and mosfet |
| JPH06232389A (en) * | 1993-02-04 | 1994-08-19 | Nec Corp | Field-effect transistor and its manufacture |
| US5894157A (en) * | 1993-06-25 | 1999-04-13 | Samsung Electronics Co., Ltd. | MOS transistor having an offset resistance derived from a multiple region gate electrode |
| US5977591A (en) * | 1996-03-29 | 1999-11-02 | Sgs-Thomson Microelectronics S.R.L. | High-voltage-resistant MOS transistor, and corresponding manufacturing process |
| EP0798785A1 (en) * | 1996-03-29 | 1997-10-01 | STMicroelectronics S.r.l. | High-voltage-resistant MOS transistor, and corresponding manufacturing process |
| EP0856892A2 (en) * | 1997-01-30 | 1998-08-05 | Oki Electric Industry Co., Ltd. | MOSFET and manufacturing method thereof |
| EP0856892A3 (en) * | 1997-01-30 | 1999-07-14 | Oki Electric Industry Co., Ltd. | MOSFET and manufacturing method thereof |
| US5998848A (en) * | 1998-09-18 | 1999-12-07 | International Business Machines Corporation | Depleted poly-silicon edged MOSFET structure and method |
| US6100143A (en) * | 1998-09-18 | 2000-08-08 | International Business Machines Corporation | Method of making a depleted poly-silicon edged MOSFET structure |
| WO2005004240A1 (en) * | 2003-06-25 | 2005-01-13 | Micron Technology, Inc. | Tailoring gate work-function in image sensors |
| JP2007525003A (en) * | 2003-06-25 | 2007-08-30 | マイクロン テクノロジー インコーポレイテッド | Method for adjusting gate work function in image sensor |
| US7335958B2 (en) | 2003-06-25 | 2008-02-26 | Micron Technology, Inc. | Tailoring gate work-function in image sensors |
| CN103794501A (en) * | 2012-10-30 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
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