JPH01225509A - Dividing method for semiconductor base - Google Patents
Dividing method for semiconductor baseInfo
- Publication number
- JPH01225509A JPH01225509A JP63052282A JP5228288A JPH01225509A JP H01225509 A JPH01225509 A JP H01225509A JP 63052282 A JP63052282 A JP 63052282A JP 5228288 A JP5228288 A JP 5228288A JP H01225509 A JPH01225509 A JP H01225509A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- semiconductor
- dividing
- semiconductor substrate
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 80
- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000013078 crystal Substances 0.000 claims abstract description 20
- WGPCGCOKHWGKJJ-UHFFFAOYSA-N sulfanylidenezinc Chemical compound [Zn]=S WGPCGCOKHWGKJJ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052984 zinc sulfide Inorganic materials 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 28
- 238000005530 etching Methods 0.000 abstract description 6
- 235000012431 wafers Nutrition 0.000 description 37
- 238000003776 cleavage reaction Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000007017 scission Effects 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 229910003460 diamond Inorganic materials 0.000 description 3
- 239000010432 diamond Substances 0.000 description 3
- 239000002313 adhesive film Substances 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- YREOLPGEVLLKMB-UHFFFAOYSA-N 3-methylpyridin-1-ium-2-amine bromide hydrate Chemical compound O.[Br-].Cc1ccc[nH+]c1N YREOLPGEVLLKMB-UHFFFAOYSA-N 0.000 description 1
- 241000283986 Lepus Species 0.000 description 1
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
Landscapes
- Processing Of Stones Or Stones Resemblance Materials (AREA)
- Weting (AREA)
- Dicing (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体基板の分割方法に関し、特に詳細には、
劈開を利用した半導体基板の分割方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for dividing a semiconductor substrate, and in particular, the present invention relates to a method for dividing a semiconductor substrate.
This invention relates to a method for dividing a semiconductor substrate using cleavage.
半導体集積回路の作成は、フォトリソグラフィ技術、薄
膜生成技術を用いて、半導体基板（つ工−ハ）の表面上
に多数に集積回路を形成し、その後、個々の半導体チッ
プに分割することにより行われる。ここモ半導体ウェー
ハを個々の半導体チップに分割する方法としては、半導
体ウェーハが結晶であることより、その劈開性を利用し
て分割する方法が知られている。特にＧａＡｓ結晶のよ
うな閃亜鉛鉱型結晶では、その（１００）面基板の集積
回路形成面の面内で互いに直交する２方向にダイヤモン
ドポイントツールてケガキ線（スクライブライン）を入
れることにより容易にこのスクライブラインに沿って分
割することができる。Semiconductor integrated circuits are created by forming a large number of integrated circuits on the surface of a semiconductor substrate using photolithography technology and thin film formation technology, and then dividing them into individual semiconductor chips. be exposed. Here, as a method of dividing a semiconductor wafer into individual semiconductor chips, since the semiconductor wafer is a crystal, a method of dividing the semiconductor wafer by utilizing its cleavage property is known. In particular, for zincblende crystals such as GaAs crystals, it is easy to make scribe lines by using a diamond point tool in two directions perpendicular to each other in the plane of the integrated circuit forming surface of the (100) plane substrate. It is possible to divide along this scribe line.
そして、第３図に示すように、この互いに直交するスク
ライブライン３１ａ、３１ｂを、予め半導体ウェーハ３
１上に作成された集積回路形成面の集積回路分割ライン
３０に引いた後、半導体ウェーハ３１をローラ加圧する
ことにより、このスクライブライン３１ａ、３１ｂに沿
って劈開し矩形状に分割し、個々の半導体チップ３２を
作成していた。As shown in FIG.
1, the semiconductor wafer 31 is cleaved along the scribe lines 31a, 31b and divided into rectangular shapes by applying roller pressure to the semiconductor wafer 31. A semiconductor chip 32 was being created.
上記の従来の方法では、半導体ウエーノ１の集積回路形
成面上に、互いに直交するスクライブラインを形成し劈
開しているが、例えば、ＧａＡｓ（１００）基板では、
この劈開性を利用した分割が可能なスクライブ方向は、
ＧａＡｓ基板を溶液エツチングしたとき、そのエツチン
グ断面形状が順メサ及び逆メサ形状となる互いに直交す
る２方向に限られる。そして、この互いに直交する２方
向は以下の方法により確認することができる。この確認
方法を第４図を用いて説明する。この方法は、まず閃亜
鉛鉱型結晶基板１４の両面に保護膜１５ａ、１５ｂを形
成しく第４図（ｂ）） 、第４図（ｃ）に示すようにあ
る所定の方向に伸びる保護膜の除去パターン１６ａ、１
６ｂを形成する。In the conventional method described above, scribe lines orthogonal to each other are formed on the integrated circuit forming surface of the semiconductor wafer 1 and then cleaved.
The scribe direction that allows division using this cleavage property is
When a GaAs substrate is subjected to solution etching, the etched cross-sectional shape is limited to two directions orthogonal to each other, that is, a forward mesa shape and an inverted mesa shape. These two mutually orthogonal directions can be confirmed by the following method. This confirmation method will be explained using FIG. 4. In this method, first, protective films 15a and 15b are formed on both sides of the zinc blende crystal substrate 14, and as shown in FIG. 4(b)) and FIG. Removal pattern 16a, 1
6b is formed.
次に、この保護膜除去パターンを形成した閃亜鉛鉱型（
ＧａＡｓ）結晶基板１４を溶液によるエツチングをする
（第４図（ｄ））。このエツチングの結果、これらの保
護膜パターン１６ａ、１６ｂの方向が両開可能な方向で
あれば第５図に示すようなエツチング断面形状１７ａ、
１７ｂ、１７ｃ。Next, the zinc blende mold (
The (GaAs) crystal substrate 14 is etched using a solution (FIG. 4(d)). As a result of this etching, if the directions of these protective film patterns 16a and 16b are in the direction that allows double-opening, an etched cross-sectional shape 17a as shown in FIG.
17b, 17c.
１７ｄが得られる。ここで、このような互いに直交する
方向におけるエツチング形状の違いは結晶構造に関係し
ている。このエツチング形状の違いから判るように、こ
れらのスクライブラインの方向における結晶構造は異な
る。そのため、これらの互いに直交する方向に最適なス
クライブラインをいれるための条件は異なってしまう。17d is obtained. Here, the difference in etching shape in directions orthogonal to each other is related to the crystal structure. As can be seen from the difference in etching shape, the crystal structures in the directions of these scribe lines are different. Therefore, the conditions for inserting optimal scribe lines in these mutually orthogonal directions differ.
したがって、それぞれの方向において最適条件の下でス
クライブラインを入れるように条件を選ぶと分割工程が
複雑になってしまう。更に、この様なスクライブライン
に沿って、劈開した場合にも割れ状況もそれぞれの方向
で異なる。Therefore, if conditions are selected to insert scribe lines under optimal conditions in each direction, the dividing process becomes complicated. Furthermore, even when cleaved along such a scribe line, the state of cracking differs in each direction.
また更に、この様に同一平面上に互いに直交する２方向
にスクライブラインを入れると、その交差部で盛り上が
りが生じ、劈開の際、不都合が生じる。そのため、製品
歩留りの低下を招いていた。Furthermore, when scribe lines are drawn in two directions perpendicular to each other on the same plane, bulges occur at the intersections, causing problems during cleavage. This resulted in a decrease in product yield.
この第５図からも判るように、結晶板の上表面には順メ
サ形状の溝１７ｂと逆メサ形状１７ａの溝が形成される
が、下表面、すなわち裏面側にも、同様に順メサ形状の
溝１７ｄ及び逆メサ形状の溝１７ｃが形成される。そし
て、それら表側及び裏側の同じエツチング形状を有する
方向は互いに直交していることが判る。そこで本件発明
者は、半導体ウェーハの結晶構造より、集積回路形成面
のある所定の方向における結晶の性質と、その集積回路
形成面の裏面側における先の所定の方向に直角な方向で
の結晶の性質が同じとなることに着目し、新規かつ有用
な半導体ウェーハの分割方法を発明した。As can be seen from FIG. 5, a forward mesa-shaped groove 17b and an inverted mesa-shaped groove 17a are formed on the upper surface of the crystal plate, but the lower surface, that is, the back side, also has a forward mesa shape. A groove 17d and an inverted mesa-shaped groove 17c are formed. It can be seen that the directions in which the front and back sides have the same etched shape are orthogonal to each other. Therefore, based on the crystal structure of a semiconductor wafer, the inventor of the present invention determined the properties of the crystal in a predetermined direction on the integrated circuit forming surface, and the properties of the crystal in a direction perpendicular to the previous predetermined direction on the back side of the integrated circuit forming surface. Focusing on the fact that the properties are the same, we invented a new and useful method for dividing semiconductor wafers.
本発明の半導体基板の分割方法では、半導体基板の第１
の主表面を第１の方向にスクライブラインを入れる工程
と、前記半導体基板の主表面とは半導体基板を介して反
対の第２の主表面を前記第１の方向に直交する第２の方
向にスクライブラインを入れる工程と、前記第１及び第
２の方向に沿って、前記半導体基板を劈開し分割する工
程とを含むことを特徴とする。In the semiconductor substrate dividing method of the present invention, the first
a second main surface opposite to the main surface of the semiconductor substrate in a second direction perpendicular to the first direction; The method is characterized in that it includes a step of creating a scribe line, and a step of cleaving and dividing the semiconductor substrate along the first and second directions.
更に、上記分割方法を閃亜鉛鉱型の結晶構造を有する半
導体基板に適用する場合には、互いに直交する所定の方
向、すなわち、この半導体基板を溶液エツチングした際
、エツチング形状が順メサ又は逆メサとなる方向にスク
ライブすることを特徴とする特
〔作用〕
本発明の半導体基板の分割方法では、半導体基板の表面
及び裏面より互いに直交するスクライブラインを入れる
ことにより、同一条件のもとてスクライブラインの作成
を可能にし、同一条件のもとての劈開を可能にしている
。Furthermore, when the above-mentioned dividing method is applied to a semiconductor substrate having a zincblende crystal structure, when the semiconductor substrate is solution etched in a predetermined direction orthogonal to each other, the etched shape is either a forward mesa or a reverse mesa. In the method for dividing a semiconductor substrate of the present invention, the scribe lines are scribed perpendicularly to each other from the front and back surfaces of the semiconductor substrate under the same conditions. This makes it possible to create and cleave the original under the same conditions.
以下図面を参照しつつ本発明に従う実施例について説明
する。Embodiments according to the present invention will be described below with reference to the drawings.
同一符号を付した要素は同一機能を有するため重複する
説明は省略する。Elements with the same reference numerals have the same functions, so duplicate explanations will be omitted.
第１図は本発明に従うＧａＡｓ半導体基板の分割方法の
工程を示す。この図に示すように、この分割方法は、半
導体ウェーハ上に集積回路を形成する集積回路形成工程
１の終了後、半導体ウェーハの裏面（集積回路が形成さ
れている面の裏側）に第１のスクライブラインを形成す
る第１のスクライブ工程２と、半導体基板の表面（集積
回路が形成されている面）上に第２のスクライブライン
を形成する第２のスクライブ工程３と、先に形成した第
１及び第２のスクライブに沿って劈開分割する半導体チ
ップ分割工程４とより構成される。FIG. 1 shows the steps of a method for dividing a GaAs semiconductor substrate according to the present invention. As shown in this figure, in this dividing method, after the integrated circuit forming step 1 in which integrated circuits are formed on the semiconductor wafer, a first A first scribing step 2 for forming a scribe line, a second scribing step 3 for forming a second scribe line on the surface of the semiconductor substrate (the surface on which an integrated circuit is formed), and The method is comprised of a semiconductor chip dividing step 4 in which the semiconductor chip is divided by cleavage along the first and second scribe lines.
集積回路形成工程１はフォトリソグラフィ技術と薄膜形
成技術を利用して行われ、この形成は当業者にはよく知
られているので詳細な説明は省略する。The integrated circuit forming step 1 is performed using photolithography and thin film forming techniques, which are well known to those skilled in the art, so detailed description thereof will be omitted.
次に、第１スクライブ工程２について’Ｍ２ （ａ）図
を用いて説明する。この第２（ａ）図は、半導体ウェー
ハの裏面及び断面を示し、半導体ウェーハの裏面側にス
クライブラインが形成された状態を示している。Next, the first scribing step 2 will be explained using FIG.'M2(a). This FIG. 2(a) shows the back surface and cross section of the semiconductor wafer, and shows a state in which scribe lines are formed on the back surface side of the semiconductor wafer.
この工程２では、半導体ウェーハ２１の表面２１ａをス
テージ台に固定し、次に半導体ウェーへの表面上に形成
された集積回路分割ラインに対応する裏面側２１ｂの位
置をオリエンテーションフラット２２に直交する方向Ａ
に沿ってスクライブラインを形成する。そして、この集
積回路分割ラインは半導体ウェーへの集積回路形成面２
１ａに集積回路形成の際、同時に形成されている。この
スクライブライン形成はダイヤモンドポイントツールに
より行う。更に、このスクライブラインの形成位置は集
積回路形成面２１ａの集積回路分割ラインに対応する裏
面側での位置であり、このスクライブラインの形成位置
の決定は半導体つ工−ハ２１の固定面側、すなわち、集
積回路形成面２１ａ側より光を当て、集積回路形成面２
１ａ上に形成された集積回路分割ラインを検知し、この
検知に基づき求める。また、この固定の際、半導体ウェ
ーハの表面２１ａに形成された集積回路が破壊されない
ように注意しなければならない。In this step 2, the front surface 21a of the semiconductor wafer 21 is fixed to a stage stand, and then the position of the back surface side 21b corresponding to the integrated circuit dividing line formed on the front surface of the semiconductor wafer 21 is adjusted in a direction perpendicular to the orientation flat 22. A
Form a scribe line along. This integrated circuit dividing line forms the integrated circuit forming surface 2 on the semiconductor wafer.
It is formed at the same time when the integrated circuit is formed on 1a. This scribe line formation is performed using a diamond point tool. Furthermore, the formation position of this scribe line is a position on the back surface side corresponding to the integrated circuit dividing line of the integrated circuit forming surface 21a, and the formation position of this scribe line is determined on the fixed surface side of the semiconductor tool 21, That is, by applying light from the integrated circuit forming surface 21a side, the integrated circuit forming surface 2
The integrated circuit dividing line formed on 1a is detected, and the calculation is made based on this detection. Further, during this fixing, care must be taken not to destroy the integrated circuit formed on the surface 21a of the semiconductor wafer.
次に、第２スクライブ工程３について第２（ｂ）図を用
いて説明する。Next, the second scribing step 3 will be explained using FIG. 2(b).
この工程３では、先の工程２でステージ台に固定した半
導体ウェーハ２１をステージ台より取り外し、半導体ウ
ェーハ２１を裏返し、半導体ウェーハ２１の裏面２１ｂ
に粘着フィルムを貼付ける。In this step 3, the semiconductor wafer 21 fixed to the stage stand in the previous step 2 is removed from the stage stand, the semiconductor wafer 21 is turned over, and the back surface 21b of the semiconductor wafer 21 is
Attach adhesive film to.
次に、この半導体ウェーハ２１の裏面２１ｂ側をステー
ジ台に固定する。次に、第２（ｂ）図に示すようにオリ
エンテションフラット２２に対して平行な方向Ｂの集積
回路分割ライン上に、スクライブライン２３ｂを形成す
る。ここで、粘着フィルムに貼付けるのは、次の工程で
分割した際、分割された半導体チップがバラバラになら
ないためである。第２（ｃ）図に両面にスクライブライ
ンが形成された状態の半導体ウェーへの一部分を示す。Next, the back surface 21b side of this semiconductor wafer 21 is fixed to a stage stand. Next, as shown in FIG. 2(b), a scribe line 23b is formed on the integrated circuit dividing line in the direction B parallel to the orientation flat 22. Here, the reason for pasting it on the adhesive film is to prevent the divided semiconductor chips from falling apart when they are divided in the next step. FIG. 2(c) shows a portion of a semiconductor wafer with scribe lines formed on both sides.
次に、半導体チップ工程４では、このようにスクライブ
ライン２３ａ、２３ｂを形成した半導体ウェーハ２１を
ステージ台より離脱させ、ローラを半導体ウェーハ２１
上で転がし、このローラ荷重により半導体ウェーハ２１
を個々の半導体チップにブレーキングする。Next, in the semiconductor chip process 4, the semiconductor wafer 21 with the scribe lines 23a and 23b formed thereon is removed from the stage stand, and the roller is moved around the semiconductor wafer 21.
The semiconductor wafer 21 is rolled by this roller load.
into individual semiconductor chips.
本発明は上記実施例に限定されるものでなく、種々の変
形例が考えられ得る。The present invention is not limited to the above embodiments, and various modifications may be made.
具体的には、上記実施例では、スクライブラインを形成
する際、半導体ウェーへの集積回路形成面の裏面側より
行っているが、これとは逆に半導体ウェーハの表面側、
すなわち、集積回路が形成されている面から行ってもよ
い。Specifically, in the above embodiment, the scribe line is formed from the back side of the integrated circuit forming surface of the semiconductor wafer, but on the contrary, from the front side of the semiconductor wafer,
That is, it may be performed from the surface on which the integrated circuit is formed.
また更に、上記実施例では、集積回路形成工程終了後に
、スクライブラインの形成を行っているが、集積回路形
成工程１の最終工程で半導体ウェーハの裏面に金属等を
蒸着する工程がある場合には、半導体ウェーハの裏面側
からのスクライブライン作成は、この金属黒石前に行な
ってもよい。Furthermore, in the above embodiment, the scribe line is formed after the integrated circuit forming process is completed, but if there is a process of vapor depositing metal etc. on the back surface of the semiconductor wafer in the final process of integrated circuit forming process 1, The creation of scribe lines from the back side of the semiconductor wafer may be performed before this metal black stone is formed.
また更に、上記実施例ではスクライブラインを形成する
際、ダイヤモンドポイントツールを使用しているが、こ
れに限定されず、例えば、レーザ光等を（り用してスク
ライブラインを形成してもよい。Furthermore, although a diamond point tool is used to form the scribe line in the above embodiment, the present invention is not limited to this, and the scribe line may be formed using, for example, a laser beam.
また更に、上記実施例では、集積回路が形成された半導
体ウェーハの分割について説明してきたが、このような
半導体ウェーハに限定されず、種々の結晶基板の分割に
適用でき、特に閃亜鉛鉱型結晶構造を有する結晶の分割
にはａ用である。Furthermore, although the above embodiments have described the division of semiconductor wafers on which integrated circuits have been formed, the application is not limited to such semiconductor wafers, but can be applied to the division of various crystal substrates, and in particular, the division of zinc blende type crystals. It is used for dividing crystals having a structure.
本発明の半導体基板の分割方法では、その分割のための
スクライブラインの形成が同じ条件のもとで行うことが
できるので、スクライブライン形成の条件出しが容易に
なり、分割工程を簡略化できる。In the semiconductor substrate dividing method of the present invention, the formation of scribe lines for the division can be performed under the same conditions, so that the conditions for forming the scribe lines can be easily determined and the dividing process can be simplified.
また更に、互いに直交するスクライブラインが互いに重
ならないため、交差による盛り上がり等の不都合が生じ
ない。Furthermore, since the scribe lines that are orthogonal to each other do not overlap with each other, problems such as swelling due to intersections do not occur.
更に、特にこのようなスクライブラインを形成した半導
体ウェーハをローラ荷重によりブレーキングする際、互
いに直交するスクライブラインに作用する荷重が同一条
件で作用するため、劈開条件が同じとなり、歩留りよく
半導体ウェーハの分割が可能となる。Furthermore, when a semiconductor wafer with such scribe lines is braked by a roller load, the loads acting on the scribe lines that are orthogonal to each other are applied under the same conditions, so the cleaving conditions are the same and the semiconductor wafer can be processed with a high yield. Division becomes possible.
第１図は本発明の工程を示す図、第２（ａ）図、第２（
ｂ）図、第２（Ｃ）図は第１及び第２のスクライブ工程
における半導体ウェーハの状態を示す図、第３図は、従
来例の半導体ウェーハの分割状態を示す図、第４図は結
晶の劈開方向を確認する方法を説明する図及び第５図は
第４図の方法により確認されたエツチング形状を示す図
である。
１・・・集積回路形成工程、２・・・第１スクライブ工
程、３・・・第２スクライブ工程、４・・・半導体チッ
プ分割工程、２１．３１・・・半導体ウェーハ、２Ｌａ
・・・半導体ウェーハの表面、２１ｂ・・・半導体ウェ
ーハの裏面、２２・・・オリエンテーションフラット、
２３ ａ 、 ２３ ｂ 、 ３１ ａ 、 ３１ ｂ
−スクライブラ・ｒン。
特許出願人 住友電気工業株式会社
代理人弁理士 長谷用 芳 樹間
寺 嶋 史 朗本仝明の艮
第１区
Ａ 第１スクライブ工程
負糺 ２（ｏ）図
情へ２（ｂ）５通
スフライフ完了
第２（ｃ）図
地３図Figure 1 is a diagram showing the process of the present invention, Figure 2 (a), Figure 2 (
Figure b) and Figure 2(C) are diagrams showing the state of the semiconductor wafer in the first and second scribing steps, Figure 3 is a diagram showing the division state of the semiconductor wafer in the conventional example, and Figure 4 is the diagram showing the state of the semiconductor wafer in the first and second scribing steps. FIG. 5 is a diagram illustrating a method of confirming the cleavage direction of the substrate, and FIG. 5 is a diagram showing an etching shape confirmed by the method of FIG. 1... Integrated circuit forming process, 2... First scribing process, 3... Second scribing process, 4... Semiconductor chip dividing process, 21.31... Semiconductor wafer, 2La
...Front surface of semiconductor wafer, 21b... Back surface of semiconductor wafer, 22... Orientation flat,
23 a, 23 b, 31 a, 31 b
- Scribran. Patent applicant: Sumitomo Electric Industries, Ltd. Representative patent attorney Yoshiki Hase
Terashima Fumi Aromoto Akira's costume 1st section A 1st scribe process negative 2 (o) To the illustrations 2 (b) 5 letters Suflife completion 2 (c) Figure map 3 map
Claims (1)
ブラインを形成する工程と、 前記半導体基板の主表面とは半導体基板を介して反対の
第２の主表面を前記第１の方向に直交する第２の方向に
スクライブラインを形成する工程と、 前記第１及び第２の方向に沿って、前記半導体基板を劈
開し分割する工程とを含む半導体基板の分割方法。 ２、前記半導体基板が閃亜鉛鉱結晶構造を有し、前記第
１の主表面がその結晶構造の（１００）面であり、前記
第１の方向がその方向にパターンを形成し、溶液エッチ
ングした時、そのエッチング断面が順メサ形状になる請
求項１記載の半導体基板の分割方法。 ３、前記半導体基板が閃亜鉛鉱結晶構造を有し、前記第
１の主表面がその結晶構造の（１００）面であり、前記
第１の方向がその方向にパターンを形成し、溶液エッチ
ングした時、そのエッチング断面が逆メサ形状になる請
求項１記載の半導体基板の分割方法。[Claims] 1. Forming a scribe line in a first direction on a first main surface of a semiconductor substrate; and forming a second main surface opposite to the main surface of the semiconductor substrate with the semiconductor substrate interposed therebetween. forming a scribe line in a second direction perpendicular to the first direction; and cleaving and dividing the semiconductor substrate along the first and second directions. Method. 2. The semiconductor substrate has a zincblende crystal structure, the first main surface is the (100) plane of the crystal structure, and the first direction is a pattern formed in that direction and solution etched. 2. The method for dividing a semiconductor substrate according to claim 1, wherein the etched cross section has a forward mesa shape. 3. The semiconductor substrate has a zincblende crystal structure, the first main surface is a (100) plane of the crystal structure, and the first direction is a pattern formed in that direction and solution etched. 2. The method for dividing a semiconductor substrate according to claim 1, wherein the etched cross section has an inverted mesa shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63052282A JPH01225509A (en) | 1988-03-04 | 1988-03-04 | Dividing method for semiconductor base |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63052282A JPH01225509A (en) | 1988-03-04 | 1988-03-04 | Dividing method for semiconductor base |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01225509A true JPH01225509A (en) | 1989-09-08 |
Family
ID=12910440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63052282A Pending JPH01225509A (en) | 1988-03-04 | 1988-03-04 | Dividing method for semiconductor base |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01225509A (en) |
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-
1988
- 1988-03-04 JP JP63052282A patent/JPH01225509A/en active Pending
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