JPH01183196A - Manufacture of multilayer printed wiring board device - Google Patents

Manufacture of multilayer printed wiring board device

Info

Publication number
JPH01183196A
JPH01183196A JP63007882A JP788288A JPH01183196A JP H01183196 A JPH01183196 A JP H01183196A JP 63007882 A JP63007882 A JP 63007882A JP 788288 A JP788288 A JP 788288A JP H01183196 A JPH01183196 A JP H01183196A
Authority
JP
Japan
Prior art keywords
substrate
conductors
printed wiring
wiring board
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63007882A
Other languages
Japanese (ja)
Other versions
JP2529987B2 (en
Inventor
Shinpei Yoshioka
心平 吉岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP63007882A priority Critical patent/JP2529987B2/en
Publication of JPH01183196A publication Critical patent/JPH01183196A/en
Application granted granted Critical
Publication of JP2529987B2 publication Critical patent/JP2529987B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To simplify steps, to reduce a size, to proceed the reduction in its thickness, to enhance the conductivity of wiring conductors, and to improve reliability by adhering a plurality of substrates formed in advance with conductors as a multilayer substrate, and forming communication holes penetrating the layers and recess holes in the substrate. CONSTITUTION:Outer layer substrates 12, 13 are adhered through a both-face substrate 11 to form a multilayer substrate 10, recesses 16, 16... are formed in advance at the substrates 12, 13, and an electronic module 14 having terminals 14a and chip components 14b having electrodes 14c are buried in the recesses 16, 16. Communication holes 23' to become through holes 23 and communication holes 18 for burying the components 14b are formed at the substrate 10. The substrate 11 is formed in advance with copper foil conductors, inner layer conductors 21, 22 are formed merely by adhering the substrates 12, 13 on both side faces, and outer layer conductors 15 are formed simultaneously upon the formation of through hole connectors 26. Thus, the work of forming the conductor layer may be conducted by a simple work, its conductive performance is improved, and the reliability of a multilayer printed wiring board device is improved.

Description

【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） この発明は電子回路部品を多層配線により接続して成る
多層印刷配線板装置に係り、詳細には製造工程を簡略化
すると共に導体層の導電性の向上を図り、且つ実装した
各電子回路部品の信頼性を高めるようにした多層印刷配
線板装置の製造方法に関する。[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to a multilayer printed wiring board device in which electronic circuit components are connected by multilayer wiring, and specifically, to simplify the manufacturing process. The present invention also relates to a method of manufacturing a multilayer printed wiring board device in which the conductivity of the conductor layer is improved and the reliability of each mounted electronic circuit component is increased.

（従来の技術） 近年、メモリカード、ＩＣカードが発達し、メモリ容量
等の性能が高く、かつ小形化、薄形化されたより実装密
度の高い印刷配線技術が要求されている。(Prior Art) In recent years, with the development of memory cards and IC cards, there is a demand for printed wiring technology that has high performance such as memory capacity, is smaller and thinner, and has higher packaging density.

従来、実装密度が高くかつ薄形化が可能な印刷配線技術
として、樹脂製基板の上に配線導体と絶縁層とを順次重
ねて形成するものがある。第６図はこの技術によって構
成された従来の多層印刷配線板装置を示す断面図である
。同図において、５１は樹脂製基板（以下基体という）
　、５２．５２・・・は電極バッド５２ａを有する半導
体素子、抵抗、コンデンサ等の電子回路部品（以下チッ
プ部品とする）、５３、５５は導体層、５６は絶縁層で
ある。基体５１には凹部５１ａが穿設され、各デツプ部
品５２はその凹部５１ａ内に埋設されている。但し、電
極パッド５２ａを形成した面は凹部５１ａの外側となり
、かつ基体表面と一致するようにしである。また、導体
層５３゜５５は、ビアフィル導体５４を介して互いに接
続されている。BACKGROUND ART Conventionally, as a printed wiring technique that allows for high packaging density and thinning, there is a technique in which a wiring conductor and an insulating layer are sequentially formed on a resin substrate. FIG. 6 is a sectional view showing a conventional multilayer printed wiring board device constructed using this technique. In the same figure, 51 is a resin substrate (hereinafter referred to as the base)
, 52, 52, . . . are electronic circuit components (hereinafter referred to as chip components) such as semiconductor elements, resistors, and capacitors having electrode pads 52a, 53 and 55 are conductive layers, and 56 is an insulating layer. A recess 51a is formed in the base body 51, and each depth component 52 is embedded in the recess 51a. However, the surface on which the electrode pad 52a is formed is on the outside of the recess 51a and is aligned with the surface of the base. Further, the conductor layers 53 and 55 are connected to each other via a via fill conductor 54.

以上のような多層印刷配線板装置は、導電性樹脂ペース
トをスクリーン印刷により形成し、基体５１の表面及び
チップ部品５２の表面に導体層５３を形成して各チップ
部品５２の電極パッド５２８間を接続する。更に、回路
を多層化するため絶縁層５６を形成する。絶縁層５６は
感光性ドライフィルムを熱圧着によって貼着して形成さ
れている。この際、ビアフィル導体５４を形成するため
に、露出、現像して開口を形成する。この開口に導電性
樹脂ペーストを充填してビアフィル導体５４を形成する
。そして、更に上層導体として導体層５５を導電性樹脂
ペーストによって形成する。こうして従来の多層印刷配
線板装置は製造されるものである。In the multilayer printed wiring board device as described above, a conductive resin paste is formed by screen printing, a conductive layer 53 is formed on the surface of the base 51 and the surface of the chip component 52, and the conductive layer 53 is formed between the electrode pads 528 of each chip component 52. Connecting. Furthermore, an insulating layer 56 is formed to make the circuit multilayered. The insulating layer 56 is formed by adhering a photosensitive dry film by thermocompression bonding. At this time, in order to form the via fill conductor 54, an opening is formed by exposing and developing. This opening is filled with a conductive resin paste to form a via fill conductor 54. Further, a conductor layer 55 is formed as an upper layer conductor using a conductive resin paste. In this manner, a conventional multilayer printed wiring board device is manufactured.

このＪ：うに従来の多層化技術は、導電性樹脂ペースト
のスクリーン印刷による配線導体の形成及び感光性フィ
ルムによる絶縁層の形成を繰返して多層化を実現するた
め、製造工程が煩雑であるという欠点が有った。This J: Sea urchin The conventional multilayer technology has the drawback that the manufacturing process is complicated because multilayering is achieved by repeatedly forming wiring conductors by screen printing conductive resin paste and forming insulating layers with photosensitive film. There was.

また、導電性樹脂ペーストによる配線導体は、機械的、
或は化学的に生成した銅箔導体より６１性が劣り、これ
は実装密度向上のため導体幅を狭くすると特に顕著とな
る。このため、回路に要求される特性によっては使用に
制限をうける。In addition, wiring conductors made of conductive resin paste can be mechanically,
Alternatively, the 61 property is inferior to that of a chemically produced copper foil conductor, and this becomes particularly noticeable when the conductor width is narrowed to improve packaging density. Therefore, its use is limited depending on the characteristics required of the circuit.

（発明が解決しようとする課題） 従来の多層印刷配線板装置は、多層化工程が複雑である
と共に、下層及び上層導体の素材となる導電性樹脂ペー
ストが、銅箔導体による配線導体より導電率が劣るため
、導体幅を狭めることができず、ＩＣカード、メモリカ
ード等の小形化。(Problems to be Solved by the Invention) In conventional multilayer printed wiring board devices, the multilayering process is complicated, and the conductive resin paste that is the material for the lower and upper layer conductors has a higher conductivity than the wiring conductor made of copper foil conductors. Since the conductor width is inferior, it is not possible to narrow the conductor width, leading to miniaturization of IC cards, memory cards, etc.

薄形化を制限していた。This limited the ability to make it thinner.

この発明は上記問題点を除去したもので、製造工程が簡
素で、小形化、Ｎ形化を更に推進し、配線導体の導電性
を高め信頼性の向上を図るようにした多層印刷配線板装
置の提供を目的とする。This invention eliminates the above-mentioned problems, and has a multilayer printed wiring board device that has a simple manufacturing process, further promotes miniaturization and N-type wiring, and improves the conductivity of the wiring conductors and improves reliability. The purpose is to provide.

［発明の構成］ （課題を解決するための手段） この発明は予め導体を形成した複数の基板同志を貼設し
て多層基板にし、 この多層基板に各層を貫通する連設孔と凹孔とを形成し
、これら番孔のいずれかに多数の電子回路部品の集合体
である電子モジュールをそれらの所定電極同志を接続し
た端子部が外層基板の外側表面とほぼ一致するように埋
設して固定し、残った各連設孔にメッキ法によりスルー
ホール接続部を形成すると同時に、前記外層基板と電子
モジュールとの一致面に上層導体を形成して所定の端子
部間を接続Ｊるようにしたものである。[Structure of the Invention] (Means for Solving the Problems) The present invention includes a multilayer board by pasting together a plurality of boards on which conductors have been formed in advance, and continuous holes and recessed holes penetrating each layer in the multilayer board. An electronic module, which is an assembly of a large number of electronic circuit components, is buried and fixed in one of these holes so that the terminals connecting the predetermined electrodes are almost in line with the outer surface of the outer layer board. Then, through-hole connection parts were formed in each of the remaining continuous holes by plating, and at the same time, an upper layer conductor was formed on the matching surface of the outer layer board and the electronic module to connect between the predetermined terminal parts. It is something.

（作用） この発明による樹脂製基板に予め形成された導体は多層
化したとぎ内層導体となる。そして、各内層導体を接続
するスルーボール接続部を形成Ｊる際に、外層基板の表
面にスルーボール接続部形成方法と同じメッキ法によっ
て外層導体を形成する。したがって、導体層の形成作業
は、従来のように導電性樹脂ペーストと絶縁性樹脂ペー
ストとを繰返し形成するような工程がなく簡単な作業で
済む。また、メッキ法ににる導体層は導電率が良く導電
性能が良好となり、多層印刷配線板装置の信頼性を向上
するものである。(Function) The conductor formed in advance on the resin substrate according to the present invention becomes a multilayered inner layer conductor. Then, when forming the through-ball connection portions for connecting the inner layer conductors, the outer layer conductors are formed on the surface of the outer layer substrate by the same plating method as the method for forming the through-ball connection portions. Therefore, the formation of the conductor layer is a simple operation without the need for the conventional process of repeatedly forming a conductive resin paste and an insulating resin paste. Furthermore, the conductor layer obtained by the plating method has good conductivity and conductive performance, which improves the reliability of the multilayer printed wiring board device.

（実施例） 以下、この発明を図示の実施例によって説明する。(Example) The present invention will be explained below with reference to illustrated embodiments.

第１図はこの発明に係る多層印刷配線板装置の製造方法
の一実施例を示す工程図である。同図中、第１図ａはこ
の発明により製造される多層基板１０を示し、第１図す
は上記多層基板１０に電子回路部品を取付けた状態を示
し、第１図Ｃはこの発明により製造された多層印刷配線
板装置の完成品２０を示している。尚、第２図は両面に
導体が予め形成された両面基板、第３図ａ、ｂはガラス
エポキシ等の樹脂基板である。但し、第１図においては
基板の断面を示す斜線は省略している。FIG. 1 is a process diagram showing an embodiment of a method for manufacturing a multilayer printed wiring board device according to the present invention. In the figure, FIG. 1A shows a multilayer board 10 manufactured according to the present invention, FIG. 1A shows a state in which electronic circuit components are attached to the multilayer board 10, and FIG. A completed product 20 of the multilayer printed wiring board device is shown. Incidentally, FIG. 2 shows a double-sided substrate on which conductors are preliminarily formed on both sides, and FIGS. 3a and 3b show resin substrates such as glass epoxy. However, in FIG. 1, diagonal lines indicating the cross section of the substrate are omitted.

先ず、この発明により作成される多層印刷配線板装置の
構成を第１図Ｃを参照して説明する。First, the structure of a multilayer printed wiring board device produced according to the present invention will be explained with reference to FIG. 1C.

−〇　− 第１図Ｃにおいて、１１は第２図に示した両面基板であ
り、該基板１１の各面にはそれぞれ内層（下層）導体２
１．２２が形成されている。-〇- In Fig. 1C, 11 is the double-sided board shown in Fig. 2, and each side of the board 11 has an inner layer (lower layer) conductor 2.
1.22 is formed.

１２、１３は中間となる前記基板１１の両側に貼設され
た外層基板であり、これら外層基板１２．１３は前記両
面基板１１を間に貼設して多層基板１ｏ（第１図Ｃ参照
）を構成している。これら外層基板１２．１３には第３
図ａ、ｂに示すように、凹孔１６．　ｉｅ・・・が予め
形成されおり、これら凹孔１６．１６内に、端子部１４
ａを有する電子モジュール１４及び、電極部１４Ｃを右
するチップ部品１４ｂが埋設され、かつそれらの隙間に
は絶縁性接着用樹脂１７が充填されている。これににり
電子モジュール１４．及び電極部１４Ｃを有するチップ
部品１４ｂが固定される。尚、各電子モジュール１４及
びチップ部品１４ｂの端子部１４Ｃは外層基板１２．１
３の外側表面と一致している。Reference numerals 12 and 13 denote outer layer substrates attached to both sides of the intermediate substrate 11, and these outer layer substrates 12 and 13 are attached with the double-sided substrate 11 between them to form a multilayer substrate 1o (see FIG. 1C). It consists of These outer layer substrates 12 and 13 have a third
As shown in figures a and b, the recessed hole 16. ie... are formed in advance, and the terminal portion 14 is inserted into these recessed holes 16.16.
An electronic module 14 having a shape of 1.a and a chip component 14b on the right side of an electrode portion 14C are buried, and the gap between them is filled with an insulating adhesive resin 17. This electronic module 14. The chip component 14b having the electrode portion 14C is fixed. Note that the terminal portion 14C of each electronic module 14 and chip component 14b is connected to the outer layer substrate 12.1.
It coincides with the outer surface of 3.

２６はスルーホール接続部である。これらスルーホール
接続部２６は、各基板１１．１２．１３を貫通するスル
ーホール用孔２３に内導体２４をメッキ法により形成し
て成るものである。そして、電子モジュール１４は、チ
ップ部品１４ｂ等の電気的接続を行うため、上記スルー
ホール接続部２６の導体２４．端子部１４ａ、及び電極
部１４ｃ等を互いに接続する上層導体１５が、外層基板
１２．１３の各外側面に形成されている。26 is a through-hole connection part. These through-hole connecting portions 26 are formed by forming inner conductors 24 in through-hole holes 23 penetrating each substrate 11, 12, and 13 by plating. The electronic module 14 includes conductors 24 . An upper layer conductor 15 that connects the terminal portion 14a, the electrode portion 14c, etc. to each other is formed on each outer surface of the outer layer substrate 12.13.

尚、１４ｂ′　はチップ部品であるが、他の部品と異な
り、印刷配線基板１１．１２．１３を貫通する連設孔１
８丙に埋設され、同様の樹脂１７によって固定されてい
る。Note that 14b' is a chip component, but unlike other components, there is a continuous hole 1 that penetrates the printed wiring board 11, 12, 13.
8, and is fixed with the same resin 17.

第４図は電子モジュール１４の一例を示す断面図である
。第４図において、４１は金属製のフレームである。こ
のフレーム４１内に各種複数のチップ部品４２を配設し
絶縁性樹脂４４を充填して一体化する。FIG. 4 is a sectional view showing an example of the electronic module 14. In FIG. 4, 41 is a metal frame. A plurality of various chip components 42 are arranged within this frame 41 and are integrated by filling with an insulating resin 44.

この場合、各チップ部品４２の電極４２ａ　、　４２ａ
はフレーム表面と一致するように固定される。電極４２
ａ面とフレーム表面との一致面に、例えば導電性樹脂ペ
ーストによる印刷法、導体メッキ法、或はワイヤボンデ
ィング法等によって形成した配線導体４３が形成される
。これら配線導体４３により各チップ部品４２は電子モ
ジュールとしての電気的接続が成される。In this case, the electrodes 42a, 42a of each chip component 42
is fixed in line with the frame surface. Electrode 42
A wiring conductor 43 is formed on the same plane between the a-plane and the frame surface by, for example, a printing method using a conductive resin paste, a conductor plating method, a wire bonding method, or the like. These wiring conductors 43 electrically connect each chip component 42 as an electronic module.

次に、上記構成より成る多層印刷配線板装置の製造方法
の一実施例を説明する。Next, an embodiment of a method for manufacturing a multilayer printed wiring board device having the above structure will be described.

本実施例による多層印刷配線板装置は、第２図及び第３
図ａ、ｂに示すような基板１１．１２．１３と、第４図
に示すような電子モジュール１４を用意する。The multilayer printed wiring board device according to this embodiment is shown in FIGS. 2 and 3.
Substrates 11, 12, 13 as shown in Figures a and b and an electronic module 14 as shown in Figure 4 are prepared.

両面基板１１は上記のごとく両面印刷配線基板であり、
両面に予め形成される内層導体２１．２２は導電性樹脂
ペーストを印刷、焼成、乾燥して形成した厚膜導体でも
良く、或は両面基板１１として例えばガラスエポキシ等
の予め銅箔導体が形成された銅張積層板を用いる場合は
、エツチングによって形成しても良い。また、本実施例
の場合、外層基板１２、１３に電子モジュール１４．チ
ップ部品１４ｂを埋設するための凹孔１６をドリル、プ
レス等の手段によって予め形成しておく。この場合、凹
孔１６は実施例のように貫通孔である必要はなくプレス
によって凹ませたものでも良い。The double-sided board 11 is a double-sided printed wiring board as described above,
The inner layer conductors 21 and 22 formed in advance on both sides may be thick film conductors formed by printing, baking and drying a conductive resin paste, or the double-sided substrate 11 may be formed with a copper foil conductor made of glass epoxy or the like in advance. If a copper-clad laminate is used, it may be formed by etching. Further, in the case of this embodiment, the electronic module 14. A recessed hole 16 for embedding the chip component 14b is previously formed by means such as a drill or press. In this case, the recessed hole 16 need not be a through hole as in the embodiment, but may be recessed by pressing.

次に、各基板１１．１２．１３は、接着、熱圧着等の手
段によって貼設する。これによって得られる多層基板１
０には、第１図ａに示すように、上記貼設によってスル
ーホール用孔２３となる連設孔２３′　、及びチップ部
品１４ｂを埋設するための連設孔１８を形成する。こう
して形成した各凹孔１６．連設孔１８には、第１図すに
示すように、電子モジュール１４゜チップ部品１４ｂ　
、　１４ｂ　’を挿入し、それらの隙間に樹脂１７を充
填して各部品１４．１４ｂ　、　１４ｂ　’　を固定す
る。このとき、電子モジュール１４の端子部１４ａ、チ
ップ部品１４ｂ　、　１４ｂ　’　（７）電極部１４ｃ
が外層基板１２．１３の外側表面と一致するにうに固定
する。Next, each substrate 11, 12, 13 is attached by adhesive, thermocompression bonding, or the like. Multilayer substrate 1 obtained by this
As shown in FIG. 1A, a continuous hole 23' which becomes a through-hole hole 23 by pasting, and a continuous hole 18 for embedding the chip component 14b are formed in the hole 23', as shown in FIG. 1a. Each concave hole 16 thus formed. As shown in FIG.
, 14b' are inserted, and the gaps between them are filled with resin 17 to fix each part 14.14b, 14b'. At this time, the terminal part 14a of the electronic module 14, the chip components 14b, 14b' (7) the electrode part 14c
The outer layer substrates 12 and 13 are fixed in such a manner that they are aligned with the outer surface of the outer layer substrate 12 and 13.

次に配線工程を行う。配線工程は、銅を使用したメッキ
法により、連設孔２３′の内面を含む全ての表面に、メ
ッキによる金属（銅）層を析出させる。その後、エツチ
ングレジストを用いた通常のサブトラクティブ法でパタ
ーンニングすることで、連、段孔２３′　に内導体２４
を形成すると共に、電子モジュール１４とチップ部品１
４ｂ　　（１４ｂ　’　）間の相互接続及び回路パター
ンを成す上層導体１５を同時に形成する（第１図Ｃ参照
）。但し、スルーボール接続部２６は、上記のように３
層を貫通ずるものに限らず、両面基板１１を貫通しない
ものを形成し、回路設計に対応させることができる。Next, a wiring process is performed. In the wiring process, a metal (copper) layer is deposited on all surfaces including the inner surface of the continuous hole 23' by a plating method using copper. Thereafter, by patterning using an ordinary subtractive method using an etching resist, the inner conductor 24 is formed in the continuous step hole 23'.
At the same time, an electronic module 14 and a chip component 1 are formed.
4b (14b') and an upper layer conductor 15 forming a circuit pattern (see FIG. 1C). However, the through ball connection part 26 has three parts as described above.
It is possible to form not only one that penetrates the layer but also one that does not penetrate the double-sided substrate 11 to correspond to the circuit design.

以上の製造方法より成る多層印刷配線板装置によれば、
従来のように、層間絶縁のための煩雑な繰返し工程が不
要どなる。即ち、この実施例に用いる両面基板１１は、
銅箔導体が予め形成されており、その両面に基板１２．
１３を貼設するだ【プで内層導体（２１，２２）が形成
される。また、上層導体１５は、スルーホール接続部２
６を形成するときに同時に形成する。これらの理由によ
って、本多層印刷配線板は、多層化工程が極めて簡略化
されるものである。According to the multilayer printed wiring board device formed by the above manufacturing method,
There is no need for the complicated repeated process for interlayer insulation as in the past. That is, the double-sided substrate 11 used in this example is
A copper foil conductor is formed in advance, and a substrate 12 is formed on both sides of the copper foil conductor.
Inner layer conductors (21, 22) are formed by pasting 13. Further, the upper layer conductor 15 is connected to the through-hole connection portion 2
It is formed at the same time as forming 6. For these reasons, the present multilayer printed wiring board allows the multilayering process to be extremely simplified.

また、内層導体２１．２２．メッキ法による上層導体１
５及びスルーホール内導体２４は、導電性樹脂ペースト
による導体に比し導電性が良好であり、配線幅を狭くし
ても、導電性能が問題となることはない。このため、各
内層導体２１．２２間の間隔を従来の多層印刷配線板よ
り狭めることができる。−方、電子モジュール１４は、
内層導体２１．２２のパターンに制約されることなく高
密度にチップ部品を詰め込むことができるので、導電性
樹脂ペーストによる多層印刷配線板の同一体積内に搭載
できる数より多くすることが可能となり、回路パターン
の複雑化による多層印刷配線板の層数増加を回避し、厚
みの増大を防ぐ。In addition, the inner layer conductors 21, 22. Upper layer conductor 1 by plating method
5 and the conductor 24 in the through-hole have better conductivity than a conductor made of conductive resin paste, and even if the wiring width is narrowed, the conductivity will not be a problem. Therefore, the distance between each inner layer conductor 21, 22 can be narrower than that of a conventional multilayer printed wiring board. - On the other hand, the electronic module 14 is
Since it is possible to pack chip components at high density without being restricted by the patterns of the inner layer conductors 21 and 22, it is possible to pack more chip components than can be mounted in the same volume of a multilayer printed wiring board made of conductive resin paste. To avoid an increase in the number of layers of a multilayer printed wiring board due to the complexity of a circuit pattern, and to prevent an increase in thickness.

第５図は所定断面で切断したこの発明による多層印刷配
線板装置の概略斜視図であるが、電子回路部品の多数の
集合体である電子モジュール１４は、端子部１４ａを整
列して配設するので、個々のチップ部品間で一括して配
線する回路パターン（例えばアースパターン）は、端子
部１４ａ　、　１４ａ間を接続するだけで構成すること
ができる。更に、スルーホール接続部２６は、多層配線
のための接続スペースを削減する効果がある。FIG. 5 is a schematic perspective view of the multilayer printed wiring board device according to the present invention cut at a predetermined cross section, and the electronic module 14, which is an assembly of many electronic circuit components, has terminal portions 14a arranged in alignment. Therefore, a circuit pattern (for example, a ground pattern) for collectively wiring between individual chip components can be constructed by simply connecting the terminal portions 14a and 14a. Furthermore, the through-hole connection portion 26 has the effect of reducing connection space for multilayer wiring.

更に、電子モジュール１４によれば、個々のチップ部品
４２の信頼性試験を、本実施例の電子モジュール１４の
段階で行うことができる。したがって、不良チップ部品
を含まない信頼性の高い電子モジュールのみを多層基板
１０に組み込むことができ、電子回路装置の歩留まりが
改善される。Further, according to the electronic module 14, the reliability test of each chip component 42 can be performed at the stage of the electronic module 14 of this embodiment. Therefore, only highly reliable electronic modules that do not contain defective chip components can be incorporated into the multilayer substrate 10, and the yield of electronic circuit devices is improved.

尚、第４図における電子モジュール１４は、フレーム４
１として金属を用いたが、絶縁性樹脂でも良い。Note that the electronic module 14 in FIG.
Although metal is used as material 1, insulating resin may be used.

また、電子モジュール１４は上記の方法によって製造し
たちの以外に、フレキシブル配線基板等の薄形樹脂基板
にチップ部品を取付け、これを樹脂によって封止したも
のを用いたり、ＴＡ’Ｂ（Ｔａｐｅ　Ａ　ＵｔＯｌａｔ
ｅｄ　　３　ｏｎｄｉｎｇ）法で同一フィルム上にチッ
プ部品を混載したものを使用することができる。In addition to manufacturing the electronic module 14 by the method described above, the electronic module 14 may be manufactured by attaching chip parts to a thin resin substrate such as a flexible wiring board and sealing this with resin, or by using TA'B (Tape A). UtOlat
It is possible to use a product in which chip components are mixedly mounted on the same film using the ed 3 onding method.

また、凹孔１６は、スルーホール用孔２３を穿設する工
程で同時に形成しても良いし、第２図、第３図の状態、
即ち多層基板１０とする前の段階で形成しても良い。Further, the recessed hole 16 may be formed at the same time as the through-hole hole 23 is formed, or in the state shown in FIGS. 2 and 3,
That is, it may be formed at a stage before forming the multilayer substrate 10.

［発明の効果］ 以上説明したようにこの発明によれば、高い実装密度と
薄形化を満足した上で、導体層の導電性を向上する効果
がある。[Effects of the Invention] As described above, the present invention has the effect of improving the conductivity of the conductor layer while satisfying high packaging density and thinning.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明に係る多層印刷配線板装置の一実施例
を説明するだめの工程図、第２図及び第３図は第１図の
実施例における多層基板を説明するための断面図、第４
図は第１図の実施例に用いた電子モジュールを説明する
ため断面図、第５図はこの発明による多層印刷配線板装
置の斜視図、第６図は従来の多層印刷配線板を示す断面
図である。 １１・・・両面基板、１２．１３・・・外層基板、１４
・・・電子モジュール、１４ａ・・・端子部、１５・・
・上層導体、１６・・・凹孔、１７・・・樹脂、２０・
・・完成品、２１．２２・・・内層導体、２３・・・ス
ルーホール用孔、２４・・・スルーホール内導体、２６
・・・スルーホール接続部。 ０　　　　　ｌコ 寸　　　　　　寸FIG. 1 is a process diagram for explaining an embodiment of a multilayer printed wiring board device according to the present invention; FIGS. 2 and 3 are sectional views for explaining a multilayer board in the embodiment of FIG. 1; Fourth
The figure is a sectional view for explaining the electronic module used in the embodiment shown in FIG. 1, FIG. 5 is a perspective view of a multilayer printed wiring board device according to the present invention, and FIG. 6 is a sectional view showing a conventional multilayer printed wiring board. It is. 11...Double-sided substrate, 12.13...Outer layer substrate, 14
...Electronic module, 14a...Terminal section, 15...
・Upper layer conductor, 16... Recessed hole, 17... Resin, 20.
...Finished product, 21.22...Inner layer conductor, 23...Through hole hole, 24...Through hole inner conductor, 26
...Through hole connection. 0 l size

Claims (1)

【特許請求の範囲】 　予め導体を形成した複数の樹脂製基板を貼設して多層
基板を製作する基板貼合わせ工程と、前記多層基板に各
層を貫通する連設孔及び凹孔とを形成し、これら各孔の
いずれかに多数の電子回路部品の集合体である電子モジ
ュールをそれらの端子部が外層基板の外側表面とほぼ一
致するように埋設し固定する工程と、 残った前記各連設孔にメッキ法によりスルーホール接続
部を形成すると同時に、前記外層基板と小型電子回路部
品との一致面に上層導体を形成して所定の端子部間を接
続する配線工程とを具備することを特徴とする多層印刷
配線板装置の製造方法。[Claims] A substrate bonding step of manufacturing a multilayer substrate by bonding a plurality of resin substrates on which conductors have been formed in advance, and forming continuous holes and recessed holes penetrating each layer in the multilayer substrate. , a step of embedding and fixing an electronic module, which is an assembly of a large number of electronic circuit components, in one of these holes so that the terminal portions of the electronic modules almost coincide with the outer surface of the outer layer substrate; It is characterized by comprising a wiring step of forming a through-hole connection part in the hole by a plating method, and at the same time forming an upper layer conductor on the matching surface of the outer layer board and the small electronic circuit component to connect predetermined terminal parts. A method for manufacturing a multilayer printed wiring board device.
JP63007882A 1988-01-18 1988-01-18 Method for manufacturing multilayer printed wiring board device Expired - Lifetime JP2529987B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63007882A JP2529987B2 (en) 1988-01-18 1988-01-18 Method for manufacturing multilayer printed wiring board device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63007882A JP2529987B2 (en) 1988-01-18 1988-01-18 Method for manufacturing multilayer printed wiring board device

Publications (2)

Publication Number Publication Date
JPH01183196A true JPH01183196A (en) 1989-07-20
JP2529987B2 JP2529987B2 (en) 1996-09-04

Family

ID=11677980

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63007882A Expired - Lifetime JP2529987B2 (en) 1988-01-18 1988-01-18 Method for manufacturing multilayer printed wiring board device

Country Status (1)

Country Link
JP (1) JP2529987B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002204045A (en) * 2000-01-31 2002-07-19 Ngk Spark Plug Co Ltd Method for manufacturing circuit board
WO2011052358A1 (en) * 2009-10-30 2011-05-05 イビデン株式会社 Wiring board and method for producing same

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7547975B2 (en) 2003-07-30 2009-06-16 Tdk Corporation Module with embedded semiconductor IC and method of fabricating the module
TW200618705A (en) 2004-09-16 2006-06-01 Tdk Corp Multilayer substrate and manufacturing method thereof
JP4535002B2 (en) 2005-09-28 2010-09-01 Ｔｄｋ株式会社 Semiconductor IC-embedded substrate and manufacturing method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002204045A (en) * 2000-01-31 2002-07-19 Ngk Spark Plug Co Ltd Method for manufacturing circuit board
WO2011052358A1 (en) * 2009-10-30 2011-05-05 イビデン株式会社 Wiring board and method for producing same
JPWO2011052358A1 (en) * 2009-10-30 2013-03-21 イビデン株式会社 Wiring board and manufacturing method thereof
US8546698B2 (en) 2009-10-30 2013-10-01 Ibiden Co., Ltd. Wiring board and method for manufacturing the same

Also Published As

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