JPH0116071B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to an image signal decoding method that enables decoding of image signal information encoded by the modified Huffman method using a small fixed memory capacity. [Prior Art] Conventionally, high-speed facsimile equipment converts a modulated analog image signal sent from a facsimile terminal into an AD converter, and then converts it using a run-length method, that is, represents the number of continuous bits of white or black using a code. The signal is then decoded and demodulated into the original image signal on the receiving side via a high-speed transmission line. As such a run length encoding method,
The CCITT (International Telegraph and Telephone Consultative Committee) recommends the Modified Huffman (MH) method. This encoding method uses 54 kinds of "make-up codes" that code the run length for each of white pixels and black pixels, up to 1728 pixels every 64 pixels as shown in Table 1, and 54 types of "make-up codes" as shown in Table 2. like 64
By combining 128 kinds of "terminating codes" which are coded by carving the space between pixels from 0 to 63 for each pixel, any number of run lengths can be coded and compressed. [Problem to be solved by the invention] However, as is clear from Tables 1 and 2, the "code length of the MH code" encoded using this method is at least 2 bits including at least the "1" level bit. It consists of a bit pattern, the longest being 13 bits, and the code length varies greatly. When decoding this into a run length number on the receiving side, the received MH code is converted into a 13-bit number as is.

【table】

【table】

[Means to solve the problem]

In order to achieve the above object, the image signal decoding method of the present invention decodes a variable length MH code encoded by the Modified Huffman (MH) method into image signal information, and includes the following steps: means for forming a bit pattern in which the MH code is connected in series, and selectively outputting in parallel a serial code portion having a predetermined number of bits shorter than the maximum code length forming the MH code from the bit pattern; When the number of consecutive "0" level bits of the upper bits of the MH code is less than a predetermined number and when it is a predetermined number, an inverted bit code is input, and while counting the length of the MH code, a predetermined bit length is used as a reference. The apparatus further comprises a means for outputting a bit code output according to the count value, and a code section storing a matching code or a mismatching code for determining whether or not the number of run lengths to be decoded from the accessed address should be output. a serial code of a predetermined number of bits, which has a memory that stores the number of run lengths to be decoded, and outputs a selected part from the bit pattern in synchronization with counting the code length of the input MH code; The contents of the memory are accessed by parallel output with the bit code output according to the count value, and when the output from the code section indicates a code match, the corresponding bit code is output.
This method is characterized by decoding the run length number corresponding to the MH code. [Operation] Figures 1a to 1d are explanatory diagrams of the principle of the present invention. Figures a and b show the status of the register that generates the address for accessing the fixed memory (ROM) for run-length decoding for white and black pixels, and figure c shows the status of the register that is common to black and white used in the process of generating the above addresses. Initial values used for the initial value, d in the same figure, are stored in a fixed memory (ROM) having an 8-bit (1 byte) configuration and a bit pattern in which the number of run lengths corresponding to make-up and termination are weighted. The 10-bit pattern shown in figure a (“0011100111”, “0E7” in hexadecimal notation) is generated during or after generation from the MH code (“0111”) that outputs “white run length number = 2”. This is a decoding address of a black and white element illustrating a bit pattern address at a time. As shown in this register, if the bit positions of the generated address are 10 bits A9 to A0 from the high order, then bits A7 to A0 will function as a shift register, and these bits A6 to A0 will be assigned the bits shown in c in the same figure. Initial value of 8-bit pattern “11111110”
After setting, the code data “0111” encoded using the MH method is input from the lower register, shifted up by 4 bits, and then the upper bits are input.
“00” is written to A9 and A8 in the procedure described later, and the 10 bits from A9 to A0 (address range is hexadecimal notation “000” to “3FF”) are stored in fixed memory (ROM) as one address. If access is made and the output from bit D ₇ shown in d in the same figure in the address is "sign one = "1", the code data of the desired run length number "white 2; D ₅ ~
D ₀ = “000010” indicates termination D ₆
= “0” is output. Here, in the register a of the same figure, bit A8 is set to "0" if there are 0 to 3 consecutive "0"s from the high order in the bit array of the MH code, and there are 4 "0"s. If so, set it to “1”. Bit A9 is set to “1” if the code length of the MH code is 8 bits or more.
If it is 7 bits or less, it is set to "0". In this way, the MH code of the received variable length bit pattern is generated into a 10-bit address, but the MH code of the white pixel is 12 bits of the EOL for white.
Except for the bit pattern "000000000001", the addresses are encoded with a variable length from 4 bits to 9 bits, and when a 10-bit address is generated using the above procedure, the same MH code is encoded between different MH codes during the generation process. There may be cases where a unique address is generated. Since the address obtained in this generation process is accessed in a fixed memory (ROM) each time, there is an inconvenience that the same number of run lengths are decoded for different MH codes. In order to avoid this, as will be described later, the code match/mismatch bit is set to bit d in the figure to prevent decoded data from being output from the same fixed memory (ROM) address obtained during generation from multiple MH codes. Set it to position _D7 . Next, the 10-bit pattern (“0011100011”, “0E3” in hexadecimal notation) shown in figure b is generated during or during generation from the MH code (“0011”) that outputs “black run length number = 5”. This is an address for decoding a black pixel, which is an example of a bit pattern address at the time of completion. Here, the procedure for generating the initial value and bit positions A7 to A0 in figure b is the same as in the case of white in figure a, but the code length of the MH code of the black pixel is 2.
Since it varies widely from bit to 13 bit,
In the next bit A8, “0” and “1” for white
The difference is that in addition to the setting conditions in , it is also set to "0" when the code length of the MH code is 13 bits, and for bit A9, it is set to "1" when the code length of the MH code is 12 bits or more. Set to “0” if it is 11 bits or less. For example, "Number of black run lengths = 1728"
Since the MH code is a 13-bit pattern with the black make-up code "0000001100101", the top five "0"s are shifted out in the register, resulting in A7 to A0 = "01100101", and the code length of the MH code is Since it is 13 bits, A8="0" and
When A9="1", the address to access the fixed memory (ROM) is "1001100101", that is,
Address “265” is generated in hexadecimal representation. The fixed memory accessed using the address generated in the above procedure includes each of the addresses shown in Tables 1 and 2.
In order to output the run length number corresponding to the MH code, the number of run lengths weighted in the form shown in d of the same figure, the make-up/termination classification, and whether or not the decoded data can be output are specified in the address.
A code matching/mismatching bit indicating impossibility is stored. That is, bits _D5 to _D0 store the number of make-up or termination run lengths divided by bit _D6 , and bit _D6 is "0".
Then bits D ₅ to _{D 0} are 32, 16, 08, 04, 02, 01
If bit D ₆ is “1”, bits D ₅ to _{D 0} are 2048,
This indicates that it is a make-up code weighted in the order of 1024, 0512, 0256, 0128, 0064, and if bit _D7 is “0” as described later, it is obtained in the address generation process from a different MH code as described above. Since they are at the same address location, the run length is not output as a sign mismatch, and bit _D7 is “1”.
If so, since the generated address is unique for each MH code, the run length number is output as a code match. That is, in the case of different MH codes, for example, the run length numbers black 0 and black 22, the number of upper "0"s differs from 4 and 5 bits, respectively, and the lower 6-bit pattern is the same as "110111". . Set this bit pattern to the initial value “11111110” (in hexadecimal notation).
FE) in series from the lower bit position, shift 1 bit, delete the upper 1 bit, and convert the upper 8 bits of the remaining bit pattern (in hexadecimal notation).
FC), then repeat the procedure of similarly shifting 1 bit, deleting the upper 1 bit, and generating the upper 8 bits (F8 in hexadecimal notation) of the remaining bit pattern. In the case of black 0, the code length of the MH code is 10 bits "0000110111", so the 8-bit pattern obtained by repeating the above nine times is FC, F8, F0, E0, C1, 83 in hexadecimal notation. ,06,0D,1B
This is followed by a 2-bit “01” determined in relation to the code length of the MH code and the number of high-order “0”s.
Each 10-bit pattern (1 in hexadecimal notation) is connected in parallel (1FC, 1F8, 1F0,
1E0, 1C1, 183, 106, 10D, 11B) are part of the corresponding MH code and cannot be used as addresses, so the output data from the memory accessed using this bit pattern as an address will naturally have a code mismatch (D ₇ = “0”). ”), and the bit pattern generated after the 10th time is a memory address candidate (sign matching, D ₇ ) that outputs the run length number.
="1"). And in the 10th iteration, the MH
The remaining 8-bit pattern, in which only 2 bits of the upper “0” of the code are deleted, becomes 37 in 16 number display.
2-bit “01” (1 in hexadecimal notation) determined in relation to the code length of the MH code and the number of upper “0”s.
The 10-bit pattern that is connected in parallel is 137. On the other hand, in the case of black 22, the MH code is “00000110111”
Since the code length is 11 bits, the 8 bits generated by repeating the same procedure 11 times as above.
Each 10 bit is connected in parallel with 2-bit “01” (1 in hexadecimal notation) determined by the bit pattern of the bit, the code length of the MH code, and the number of high-order “0”s.
Since the bit pattern cannot be used as an address for the same reason as the case of black 0, the output data from the memory accessed using this bit pattern as an address is naturally not subject to decoding as a sign mismatch (D ₇ = "0"), and 11 Signs match after the times (D ₇ =
“1”) is selected as a candidate. Then, in the 11th iteration, only 3 bits of the upper "0" are deleted, and the remaining 8-bit pattern becomes 37 in hexadecimal notation, which is the same as in the case of black 0. Moreover, this 8-bit pattern
The 10-bit pattern obtained by combining two bits in parallel determined by the code length of the MH code/the number of upper "0"s is also 137. Therefore, for both black 0 and black 22, if the number of bit shifts is 10 or 11, the same address 137 will be generated, so the decoding run length number can be output from this address 137. Therefore, bit position D ₇ in this 137 must also be set to "0", which is a mismatch code. For black 0, the bit generated when the number of shifts is 11 or more, and for black 22, it is generated when the number of shifts is 12 or more. The address using the pattern becomes the address for restoring the run length number. The number of shifts mentioned above is the upper “0” of the MH code
The addresses generated in this process do not match between the addresses generated by MH codes that differ only in the number of high-order "0s" and have the same lower-order bit pattern. address, the address has the desired
This is used to set the number of run lengths for decoding the MH code. [Embodiment] FIG. 2 is an explanatory diagram showing the configuration of an embodiment of the present invention using the above-mentioned principle. In the figure, the S/P shift register 11 is in the load mode of the serial load signal input to the S/L terminal every time one MH code is decoded, and the input sections H to A are initialized to "11111110". . The transmitted MH code data is controlled by the serial mode of the serial load signal and is serially loaded bit by bit into the serial input sections A to H of the S/P shift register 11, which operates in synchronization with the input clock (CLK). , the bit pattern of the S/P shift register 11 at that time is output from the 8-bit parallel output terminals OA to OH, and white, white, and
The white signal is branched to fixed memories (ROM) 12 and 13 for black decoding, and is input to the chip selector terminal CS.
Each ROM1 is selected by switching the black selection signal.
2 and 13 input terminals A0 to A7. The input signals A0-A7 correspond to bit positions A0-A7 of the register of FIGS. 1a and 1b. On the other hand, it is set in relation to the length of the MH code.
The input terminals A8 and A9 of the ROMs 12 and 13 are set by a logic circuit that receives an input (zero set signal) from a logic circuit (not shown) that detects the number of upper "0"s of the input MH code and an output from a counter 18, which will be described later. Set by. And output terminals O0 to O7 of ROM12 and 13
, the number of run lengths D ₅ to _{D 0} shown in FIG. 1d,
Termination/make-up code classification
Output data consisting of the discrimination signals D ₆ and code match/mismatch D ₇ is obtained, the gate circuit 14 switches between white and black, and the counter circuit 15 counts the number of run lengths. Upon completion of this count, the decoding end signal is sent to the facsimile device.
Sent to CPU. Furthermore, the output end signals of the ROMs 12 and 13 are input to the input clock through the NOT circuit 17, and the flip-flop (FF) 1 operates on the falling edge of the input clock.
It is given as the output of 6. And this output is
It is applied when the code match signal from the output terminal 07 of the ROMs 12 and 13 is input to the other input terminal of the FF 16. That is, a signal indicating the code match from the ROMs 12 and 13 is output from the output terminal 07,
Until the ROM end signal appears from the FF16, the ROM12, whose address is the output from the S/P shift register 11 that operates in synchronization with the input clock,
Access to 13 is performed repeatedly. In order to generate a signal to be set at input terminal A9 in relation to the length of this MH code and a signal to be set at A8 according to the number of upper "0"s, the same input clock (CLK) applied to the S/P shift register 11 is generated. ) is placed in the counter 18 and counted. That is, after initially resetting the counter 18 and associated flip-flops (FF) 16, 19, 20, and 21 with reset signals 1, 2, and 3, synchronizing with the serial loading of MH code data to the S/P shift register 11, The input clock (CLK) is counted, and depending on the number of counts, 1, 2, 4, etc.
Outputs appear at output terminals Q _A to Q _D weighted by 8. In addition, this input individual MH code data is individually monitored by a CPU (not shown) on the facsimile side, and when the number of high-order "0"s is 4 consecutively, "1" is input as a zero set signal, which will be explained later. "1" is applied to one input terminal of the AND circuit 25. Then, the Q _A to Q _D outputs of the counter 18 are sent to the AND circuits 23, 24, FF19, 20, 2.
1. Through a logic circuit consisting of an AND circuit 25 and a NAND circuit 26, bit A in a and b in FIG.
8, this output corresponds to A9 to ROM12, 13
input as an address signal to the input terminal of the S/P
The outputs 0A to 0H of the shift register 11 are applied to the ROMs 12 and 13 together with the address inputs A7 to A0, and the run length numbers stored in the ROMs 12 and 13 are read out, and the output terminal 0 in this read data is applied to the ROMs 12 and 13.
While the code mismatch signal appears at 7, the MH code is serially loaded into the S/P shift register 11, access to the ROMs 12 and 13 is continued, and input clock counting is continued.
The number of decoded run lengths can be obtained by the appearance of the code match signal at the output terminal 07 of the ROM. This operation will be explained below with reference to FIG.
That is, the Q _A , Q _B , Q _C , and Q _D outputs of the counter 18 are weighted by 1, 2, 4, and 8, respectively, as shown in Figure a, and this 4-bit output is a count of the length of the input MH code. Becomes a value. Therefore, as shown in Figure b, the AND circuit 23 receives the Q _A output (*
1), _QC output 4 which outputs “1” while counting the length of the MH code as 4 to 7 bits or while counting 12 bits or more, and
Since the input is _QD output 8 which outputs “1” after counting as bit or more, AND
The output of the circuit 23 is "0" until it counts the length of the MH code with 12 bits, becomes "1" when counting 12 bits, and then inverts to "0" again when the count advances to 13 bits. . Subsequently, the output A of this AND circuit 23 is FF19.
As shown in c in the same figure, its output ``L'' is inverted to ``0'' at the falling edge of the AND circuit 23 output ``I'' when the length of the MH code is counted from 12 bits to 13 bits, and this inversion AND the output RO
This is the other input of the circuit 25 (g in the figure). The output of this AND circuit 25 is supplied as either "0" or "1" to the input terminal A8 of the ROMs 12 and 13 in accordance with the zero set signal "0" and "1".
On the other hand, regarding FF20 and FF21, when black is being received, FF20 is forcibly reset, and when white is being received, FF21 is forcibly reset. Next, as shown in FIG. d, the counter 18 is
The Q _C 4 output becomes “1” when the value counting the length of the MH code is between 4, 5, 6, and 7 (and 12 or more) and is supplied to the FF20, and the length of the MH code is 7.
After counting bits, when the count reaches 8 bits, the output of F20 is inverted to "0" due to the fall of the count, and becomes one input of the NAND circuit 26. In addition, as shown in the figure e, the counter 18
Put the Q _D 8 outputs and Q _B 2 outputs into the AND circuit 24,
MH code length count value is 10, 11, 1
4, 15, it outputs "1", and as shown in the figure f, this output is supplied to FF21 and MH
After counting the code length by 11 bits,
When counting up to 12 bits, the output of FF21 is inverted to "0" by the falling edge,
It becomes the other input of the NAND circuit 26. and,
The output of this NAND circuit 26 (h in the same figure) is ROM1
Either "0" or "1" is supplied to the input terminals A9 of Nos. 2 and 13. With the above configuration, the conditions shown in FIGS. 1a and 1b are satisfied. In other words, when the input MH code data corresponds to a white pixel, the length of the MH code is less than 13 bits, so the output RO of the FF19 remains "1" as shown in Figure 3c, and as shown in Figure 3c. When the MH code has four high-order "0"s like g, the zero set signal is supplied as "1", so the output of the AND circuit 25 also becomes "1" and is supplied to A8 of the ROM 12. Also, if there are 0 to 3 upper “0”s in the MH code, the zero set signal is supplied as “0”, so
The output of the AND circuit 25 becomes “0” and the ROM1
It is supplied to A8 of No. 2. On the other hand, when the input MH code data corresponds to a black pixel, when the length of the MH code is less than 13 bits, it is the same as in the case of white. If the length of the MH code is counted up to 13 bits, FF
Since the output 19 inverts and outputs "0", the output of the AND circuit 25 becomes "0" and is supplied to A8 of the ROM 13 regardless of the zero set signal. Next, the output of FF20 is as shown in figure d,
If the length of the MH code is 8 bits or more, it is “0”, so as shown in h of the figure, NAND with this as input
The output of the circuit 26 becomes “1” and the A of the ROM 12
9. Here, when the length of the MH code is 7 bits or less, the output of the FF 20 becomes "1" as shown in h of the figure, and the output of the NAND circuit 26 becomes "0" and is supplied to A9 of the ROM 12.
Also, the output ho of FF21 has a MH code length of 12
If it is more than a bit, it becomes "0", so the output of the NAND circuit 26 becomes "1" as shown in h of the figure.
It is supplied to A9 of the ROM13. [Effects of the Invention] In the present invention, the run length number corresponding to the MH code is summarized into 6 bits for each of termination/makeup, and a 1-bit flag indicating the division is used.
1 bit indicating match/mismatch of MH code decoding
The number corresponding to the MH code is stored in a fixed memory with a byte capacity, and regarding the transmitted variable length MH code,
If the code length of the MH code does not exceed 8 bits, there is a continuous "0" level between those 8 bits, and when it exceeds 8 bits, the code of 8 bits or less, and the upper 4 bits of the MH code. or not,
and the output of a logic circuit that determines whether the length of the MH code is greater than or equal to a predetermined bit length, and the bit pattern is used as an address to access the fixed memory directly and store it in the fixed memory in advance.
Since the purpose is to read the run length number corresponding to the MH code, it is complicated to compare the MH code stored in fixed memory and the input MH code for each bit input, as in the usual method. steps can be omitted. That is, a bit pattern is generated by combining a code of 8 bits or less of the input MH code with a predetermined initial value, and a logic circuit is created in which white and black conditions related to the length of the MH code are set in advance. The output is combined with the above bit pattern and used as an address to access the fixed memory. This simplifies the procedure and reduces the fixed memory capacity to about 1K bytes, making it possible to efficiently decode the number of run lengths.

[Brief explanation of drawings]

Figures 1 a to d are explanatory diagrams of the principle of the present invention, Figure 2 is an explanatory diagram showing the configuration of an embodiment of the present invention, and Figures 3 a to 3
h is an operation explanatory diagram, in which 11 is an S/P shift register, 12 and 13 are fixed memories (ROM),
14 is a gate circuit, 15 is a counter circuit, 16,
19, 20, 21 are flip-flops, 17, 2
2 is a NOT circuit, 18 is a counter, 23, 24,
25 is an AND circuit, and 26 is a NAND circuit.

Claims (1)

[Claims] 1. In a method for decoding a variable length MH code encoded by the Modified Huffman (MH) method into image signal information, a bit pattern in which the MH code is serially connected to a predetermined serial code. means for selectively outputting in parallel serial code portions having a predetermined number of bits shorter than the maximum code length forming the MH code from the bit pattern; "When the number of levels is less than a predetermined number and when there is a predetermined number, the inverted bit code is input, and
A means for outputting a bit code according to the counted value based on a predetermined bit length while counting the length of the MH code, and whether or not the number of run lengths to be decoded from the accessed address should be output. It has a code section storing a matching code or a mismatching code that determines whether the MH code is the same, and a memory storing the number of run lengths to be decoded. The contents of the memory are accessed by parallel output of a serial code of a predetermined number of bits outputted by determining the selected part of the bit code outputted according to the count value, and the output from the code part matches the code. The relevant
An image signal decoding method characterized by decoding a run length number corresponding to an MH code.