JPH01158759A - Manufacture of semiconductor memory - Google Patents
Manufacture of semiconductor memoryInfo
- Publication number
- JPH01158759A JPH01158759A JP62318012A JP31801287A JPH01158759A JP H01158759 A JPH01158759 A JP H01158759A JP 62318012 A JP62318012 A JP 62318012A JP 31801287 A JP31801287 A JP 31801287A JP H01158759 A JPH01158759 A JP H01158759A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- substrate
- slot
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 25
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 6
- 239000011521 glass Substances 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 12
- 230000015572 biosynthetic process Effects 0.000 abstract description 8
- 229910052681 coesite Inorganic materials 0.000 abstract description 6
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 6
- 239000000377 silicon dioxide Substances 0.000 abstract description 6
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 6
- 229910052682 stishovite Inorganic materials 0.000 abstract description 6
- 229910052905 tridymite Inorganic materials 0.000 abstract description 6
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 239000010408 film Substances 0.000 abstract 8
- 239000010409 thin film Substances 0.000 abstract 2
- 239000003990 capacitor Substances 0.000 description 15
- 238000010586 diagram Methods 0.000 description 10
- 239000012535 impurity Substances 0.000 description 9
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 239000007864 aqueous solution Substances 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910005091 Si3N Inorganic materials 0.000 description 2
- 229910020489 SiO3 Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要］
本発明は半導体記憶装置の製造方法、特に溝掘り技術を
応用した蓄積容量（トレンチキャパシタ）を有する高集
積、高性能のＭＯＳダイナミックランダムアクセスメモ
リ（ＤＲＡＭ）セルの溝部の形成方法に関し、
ＲＩＥ法等の異方性エツチングに依存することなく、溝
部の底部を開口し、その製造工程における余裕度の向上
を図ることを目的とし、半導体基板に溝部を選択的に形
成する工程と、前記溝部を設けた半導体基板に第１の絶
縁膜を形成する工程と、
前記溝部の底部の前記第１の！＠縁膜（１４）上に第２
の絶縁膜を形成する工程と、
前記溝部の第２の絶縁膜をマスクにして、前記第１の絶
縁膜を選択的に除去する工程と、前記半導体基板を熱処
理をして、第３の絶縁膜を形成する工程と、
前記第２の絶縁膜と第１の絶縁膜とを除去する工程と、
前記溝部（１２）内に蓄積容量（Ｃｃ）を形成する工程
とを有することを含み構成する。[Detailed Description of the Invention] [Summary] The present invention relates to a method for manufacturing a semiconductor memory device, particularly a highly integrated, high-performance MOS dynamic random access memory (DRAM) having a storage capacitor (trench capacitor) using trenching technology. Regarding the method for forming cell grooves, we have selected grooves in semiconductor substrates with the aim of opening the bottom of the groove and improving margin in the manufacturing process without relying on anisotropic etching such as RIE method. a step of forming a first insulating film on the semiconductor substrate provided with the groove, and a step of forming the first insulating film on the bottom of the groove. @Second on the membrane (14)
forming an insulating film; selectively removing the first insulating film using the second insulating film in the groove as a mask; and heat-treating the semiconductor substrate to form a third insulating film. a step of forming a film; a step of removing the second insulating film and the first insulating film;
and forming a storage capacitor (Cc) in the groove (12).
本発明は半導体記憶装置の製造方法に関するものであり
、更に詳しく言えば、溝掘り技術を応用した蓄積容量（
トレンヂギャパシク）を有する高集積、高性能のＭＯＳ
ダイナミックランダムアクセスメモリ（ＤＲＡＭ）セル
の溝部の形成方法に関するものである。The present invention relates to a method for manufacturing a semiconductor memory device, and more specifically, the present invention relates to a method for manufacturing a semiconductor memory device, and more specifically, a storage capacitor (
Highly integrated, high performance MOS with trend gap
The present invention relates to a method for forming trenches in dynamic random access memory (DRAM) cells.
〔従来の技術］ 第２．３図は従来例に係る説明図である。[Conventional technology] FIG. 2.3 is an explanatory diagram of a conventional example.
第２図（ａ）はＭＯ３ＤＲΔＭセルの電気回路。Figure 2(a) shows the electrical circuit of the MO3DRΔM cell.
図である。図において、Ｔはデータ（電荷）を転送する
Ｍｏ５ｔ〜ランジスタ等により構成される転送トランジ
スタ、Ｃは電荷を蓄積する蓄積容量（トレンヂキャパシ
タ）、ＷＩ、はワード線、Ｂ Ｌはビット線である。な
お、６は蓄積電極、Ｙは誘電体膜、８ば対向電極である
。It is a diagram. In the figure, T is a transfer transistor made up of Mo5t to transistor etc. that transfers data (charge), C is a storage capacitor (trend capacitor) that accumulates charge, WI is a word line, and BL is a bit line. . Note that 6 is a storage electrode, Y is a dielectric film, and 8 is a counter electrode.
同図（ｂ）はｎチャンネル型ＭＯ３ＤＲＡＭセル構造を
示す断面図である。図において、１はｐ型エピタキシャ
ル層等のｐ型Ｓｉ基板、２はロコス法等により形成され
るフィールド酸化膜、３．４はＡｓ”イオン等を拡散し
て形成されるｎ＋不純物拡散層であり、転送１〜ランジ
スタＴのソース又はドレインである。FIG. 2B is a cross-sectional view showing the structure of an n-channel MO3DRAM cell. In the figure, 1 is a p-type Si substrate such as a p-type epitaxial layer, 2 is a field oxide film formed by the Locos method, etc., and 3.4 is an n+ impurity diffusion layer formed by diffusing As'' ions, etc. , transfer 1 to the source or drain of transistor T.
５ａ、５ｂはワード線Ｗ Ｌの絶縁や蓄積容量Ｃの溝部
（１〜レンチ）２２を画定する絶縁膜であり、５ｉ０２
膜や５ｔ３Ｎ４膜等である。６はｐ型Ｓｉ基板１を選択
的に溝堀りした溝部２２に形成された蓄積電極であり、
ポリＳｉ膜に不純物イオンをドープして形成される電極
である。なお蓄積容量Ｃを構成する蓄積電極６である。5a and 5b are insulating films that insulate the word line WL and define the grooves (1 to wrench) 22 of the storage capacitor C, and 5i02
membrane, 5t3N4 membrane, etc. 6 is a storage electrode formed in a groove 22 that is selectively grooved in the p-type Si substrate 1;
This electrode is formed by doping a poly-Si film with impurity ions. Note that this is the storage electrode 6 that constitutes the storage capacitor C.
７ばＳｉＯ□膜や５ｉＪ４膜等の絶縁膜により形成され
る誘電体膜である。８はポリＳｉ膜に不純物イオンをド
ープして形成される電極であり、蓄積容量Ｃを構成する
対向電極である。なお対向電極８はｐ型Ｓｉ基板１に接
合されている。９は蓄積電極６と転送トランジスタＴの
ドレイン３とを電気的に接合する導電層であり、不純物
イオンをドープしたポリＳｉ膜等により形成される。１
０は導電層９を絶縁するＰＳＧ膜である。7 is a dielectric film formed of an insulating film such as a SiO□ film or a 5iJ4 film. Reference numeral 8 denotes an electrode formed by doping impurity ions into a poly-Si film, and is a counter electrode constituting the storage capacitor C. Note that the counter electrode 8 is bonded to the p-type Si substrate 1. A conductive layer 9 electrically connects the storage electrode 6 and the drain 3 of the transfer transistor T, and is formed of a poly-Si film or the like doped with impurity ions. 1
0 is a PSG film that insulates the conductive layer 9.
ＢＬは不純物イオンを含有したポリＳｉ膜や、ボリザイ
ド膜、アルミ膜等により形成されるビット線である。BL is a bit line formed of a poly-Si film containing impurity ions, a volizide film, an aluminum film, or the like.
第３図は従来例に係るＭＯ３ＤＲＡＭセルの問題点を説
明する図であり、蓄積容量Ｃを形成する溝部２２の形成
工程に係る図を示している。FIG. 3 is a diagram for explaining the problems of the MO3 DRAM cell according to the conventional example, and shows a diagram related to the formation process of the groove portion 22 that forms the storage capacitor C.
図において、まず５ｉ０２膜５ｃを設げたｐ型Ｓ１基板
１を不図示レジスト膜をマスクとして、ＲＩＥ法等の異
方性エツチングにより、溝堀りをし、溝部２２を形成す
る（同図（ａ））。In the figure, a p-type S1 substrate 1 provided with a 5i02 film 5c is first etched by anisotropic etching such as RIE using a resist film (not shown) as a mask to form a groove 22 (see figure (a). )).
次に溝部２２を設けたｐ型Ｓ１基板１の全面に溝部２２
の素子間を画定する５ｉＯｚ膜５ｄをＣＶＤ法等により
形成する。なお、Ｌｌは５ｉＯ７膜５ｃの膜厚である（
同図（ｂ））。Next, grooves 22 are formed on the entire surface of the p-type S1 substrate 1 provided with grooves 22.
A 5iOz film 5d that defines the space between the elements is formed by CVD or the like. Note that Ll is the thickness of the 5iO7 film 5c (
Figure (b)).
その後溝部２２の底部を開口するために該ｐ型Ｓｉ基板
１の全面をＲＩＥ／ｉ等により異方性エンチングして不
要のＳｉＯ２膜５ｄを除去する。なお、ｔ２はＲＩＥ法
等による異方性エンチング後のＳｉＯ□膜５ｃの膜厚で
ある。また膜厚ｔ２は膜ＪｉＸ ｔ、ｌ に比較して、
ｔＥ法等の買方性エンチングが過剰にされたためＬ２＜
ｔ、 となり、著しいときにはｔ２〈０となってＳｉ基
板１表面が荒らされてしまう。Thereafter, in order to open the bottom of the groove 22, the entire surface of the p-type Si substrate 1 is anisotropically etched by RIE/i or the like to remove unnecessary SiO2 film 5d. Note that t2 is the thickness of the SiO□ film 5c after anisotropic etching by RIE method or the like. Moreover, the film thickness t2 is compared to the film JiX t,l,
L2<
t, and in extreme cases, t2<0, and the surface of the Si substrate 1 is roughened.
これは溝部２２内のエツチング速度がＳｉ基板１の表面
より遅いことと、溝が深くなる程著しい。This is because the etching rate inside the groove 22 is slower than that on the surface of the Si substrate 1, and the deeper the groove is, the more remarkable it becomes.
ところで従来例によれば、蓄積電１ｃを形成する溝部２
２の底部は、該溝部２２を画定するＳｉＯ□膜５ｃを形
成した後、溝部２２の底部の３１０２膜５ＣをＲＩＥ法
等の異方性エツチングにより開口している。このため次
の様な問題がある。By the way, according to the conventional example, the groove portion 2 forming the storage charge 1c
After forming the SiO□ film 5c that defines the groove 22, the 3102 film 5C at the bottom of the groove 22 is opened by anisotropic etching such as RIE. This causes the following problems.
■ＲＩＥ法等の異方性エツチングが過剰になるとＳｉ基
板１の表面に形成した５ｉＯｚ膜５Ｃが薄膜化（１２＞
１．）される。その著しいときにはＳｉＯ□膜５ｃが全
面除去され、Ｓｉ基板１表面がＲＩＥ法等の異方性エツ
チングに曝されて、該表面が荒らされ、後工程における
転送トランジスタＴの形成に与えるダメージが大きい。■If anisotropic etching such as RIE becomes excessive, the 5iOz film 5C formed on the surface of the Si substrate 1 becomes thinner (12>
1. ) to be done. When this is significant, the entire SiO□ film 5c is removed, and the surface of the Si substrate 1 is exposed to anisotropic etching such as RIE, which roughens the surface and causes great damage to the formation of the transfer transistor T in the subsequent process.
■ＲＩＥ法等の異方性エツチングが不足すると、溝部２
２の底部にＳｉＯ□膜５ｃが残留し、対向電極８とＳｉ
Ｏ□膜１との電気的接合が不完全となる。■If anisotropic etching such as RIE method is insufficient, groove 2
2, the SiO□ film 5c remains on the bottom of the
The electrical connection with the O□ film 1 becomes incomplete.
このようにして、７１４部形成に係る製造工程の余裕度
が少ないという欠点があり、微細、高集積化するＭＯ３
ＤＲＡＭセルを形成することができないという問題があ
る。In this way, there is a drawback that there is little margin in the manufacturing process related to the formation of the 714 part, and as MO3 becomes finer and more integrated,
There is a problem that DRAM cells cannot be formed.
本発明は係る従来例の問題点に鑑み創作されたものであ
り、ＲＩＥ法等の異方性エツチングに依存することなく
、溝部の底部を開口し、その製造工程における余裕度の
向上を図ることを可能とする半導体記憶装置の製造方法
の提供を目的とする。The present invention was created in view of the problems of the conventional example, and aims to improve the margin in the manufacturing process by opening the bottom of the groove without relying on anisotropic etching such as RIE method. The purpose of the present invention is to provide a method for manufacturing a semiconductor memory device that makes it possible to perform the following steps.
（問題点を解決するだめの手段］
本発明の半導体記憶装置の製造方法はその一実施例を第
１図に示すように半導体基板１１に溝部１２を選択的に
形成する工程と、
前記溝部１２を設けた半導体基板１１に第１の絶縁１１
！Ｊ１４を形成する工程と、
前記溝部１２の底部の前記第１の絶縁膜（１４）上に第
２の絶縁膜１５を形成する工程と、前記溝部１２の第２
の絶縁膜１５をマスクにして、前記第１の絶縁膜１４を
選択的に除去する工程と、
前記半導体基板１１を熱処理をして、第３の絶縁膜１６
を形成する工程と、
前記第２の絶縁膜１５と第一の絶縁膜１４とを除去する
工程と、前記溝部（１２）内に蓄積容量（Ｃｏ）を形成
する工程とを有することを特徴とし、上記目的を達成す
る。(Means for Solving the Problems) An embodiment of the method for manufacturing a semiconductor memory device of the present invention includes a step of selectively forming a groove 12 in a semiconductor substrate 11, as shown in FIG. A first insulator 11 is provided on a semiconductor substrate 11 provided with
! forming a second insulating film 15 on the first insulating film (14) at the bottom of the trench 12;
selectively removing the first insulating film 14 using the insulating film 15 as a mask; heat-treating the semiconductor substrate 11 to remove the third insulating film 16;
, a step of removing the second insulating film 15 and the first insulating film 14 , and a step of forming a storage capacitor (Co) in the groove (12). , to achieve the above objectives.
（作 用〕
本発明によれば、半導体基板に溝堀りをした溝部に選択
的に薄い第１の絶縁膜と、第２の絶縁膜とを形成した後
に熱処理をして、厚い第３の絶縁膜を形成し、その後、
第２の絶縁膜、第１の絶縁膜とを等方性エツチングによ
り除去している。このため、溝部の側壁に絶縁膜を残留
させ、かつ溝部の底部を開口して、半導体基板の表面を
露出することが可能となる。(Function) According to the present invention, a thin first insulating film and a second insulating film are selectively formed in a groove portion cut in a semiconductor substrate, and then heat treatment is performed to form a thick third insulating film. Form an insulating film, then
The second insulating film and the first insulating film are removed by isotropic etching. Therefore, it is possible to leave the insulating film on the sidewalls of the trench, open the bottom of the trench, and expose the surface of the semiconductor substrate.
これにより従来のような溝部の底部を開口するためのＲ
ＩＥ法等の異方性エンチングに依存することがないので
、半導体基板の表面を所定形状に維持することが可能と
なる。This allows for R to open the bottom of the groove like in the past.
Since there is no dependence on anisotropic etching such as IE method, it is possible to maintain the surface of the semiconductor substrate in a predetermined shape.
〔実施例］
次に図を参照しながら本発明の実施例について説明する
。[Example] Next, an example of the present invention will be described with reference to the drawings.
第１図は本発明の実施例に係る半導体記憶装置の製造方
法の説明図であり、本発明の実施例に係るＭＯ８ＤＲΔ
Ｍセルの形成工程図を示している。FIG. 1 is an explanatory diagram of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention, and is an explanatory diagram of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention.
A diagram of the formation process of an M cell is shown.
図において、まずＳｉ基Ｆｉｌｌに不図示のレジス１〜
膜をマスクとして、選択的に溝部１２を形成する。なお
溝部１２は、ＲＩＥ法等の異方性エツチングにより行う
。また、そのドライエッヂング等に用いるエツチングガ
スはＣＣで４１０□等である（同図（ａ））。In the figure, first, resists 1 to 10 (not shown) are applied to the Si-based Fill.
Grooves 12 are selectively formed using the film as a mask. Note that the groove portion 12 is formed by anisotropic etching such as RIE method. Further, the etching gas used for the dry etching etc. is 410□ CC or the like (FIG. 4(a)).
次に、溝部１２を設けたＳＩ基板１１の全面に膜厚１０
０人程鹿の薄いＳｉＯ□膜１３をＣＶＤ法等により形成
する（同図（ｂ））。Next, a film with a thickness of 10
A SiO□ film 13 as thin as 0 is formed by CVD or the like (FIG. 2(b)).
さらに、５ｉＯｚ膜１３上にｍｌ熱酸化性絶縁膜として
膜厚１０００人程度人程ｉ３Ｎａ膜１４を形成する（同
図（Ｃ））。Further, on the 5iOz film 13, an i3Na film 14 is formed as a ml thermally oxidized insulating film to a thickness of about 1000 nm (FIG. 4(C)).
次いで、５ｌ−ａＮａ膜１４を形成した溝部１２に５Ｏ
Ｇ（スピン・オン・グラス）１５を塗布する。Next, 5O was added to the groove 12 in which the 5l-aNa film 14 was formed.
Apply G (spin-on glass) 15.
なお、５ＯＣ１５は液粒状の５ｉＯｚ等であり、Ｓｉ基
板１１表面に比べて、溝部１２に多く入り込む。Note that 5OC15 is liquid droplet-like 5iOz, etc., and enters the groove portion 12 more than the surface of the Si substrate 11.
その後Ｓｉ基板１１を熱処理して、ＳＯＣ；１５を固形
化する（同図（ｄ））。Thereafter, the Si substrate 11 is heat treated to solidify the SOC 15 (FIG. 1(d)).
次に、Ｓｉ基板ＩＩの全面をＨＦ（フン酸）等のエンチ
ンダ液により等方性エンチングして、５ＯＧ１５を選択
的に除去する。このとき溝部２２に５ＯＧ１５が残留す
る（同図（ｅ））。Next, the entire surface of the Si substrate II is isotropically etched with an encinder solution such as HF (hydric acid) to selectively remove 5OG15. At this time, 5OG15 remains in the groove 22 (FIG. 2(e)).
その後、５ＯＧ１５をマスクにして、Ｓｉ基板１１をリ
ン酸等の水溶液により等方性エンヂングし、Ｓｉ３Ｎ４
膜１４を選択的に除去する。このとき溝部１２内に５ｉ
３Ｎｎ膜１４が残留する。また、その後５ＯＧＬ５をＨ
Ｆ等により除去してもよい（同図（ｆ））。Thereafter, using 5OG15 as a mask, the Si substrate 11 is isotropically aged with an aqueous solution such as phosphoric acid, and Si3N4
Film 14 is selectively removed. At this time, there is 5i inside the groove 12.
The 3Nn film 14 remains. Also, after that, 5OGL5 was
It may be removed by F or the like ((f) in the same figure).
さらに、Ｓｉ基板１１を熱処理して、膜厚１０００〜１
５００人程度のＳｉＯ□膜１６膜形６する（同図（ｇ）
）。Furthermore, the Si substrate 11 is heat-treated to have a film thickness of 1000 to 1
Approximately 500 SiO□ films with 16 film shapes (6 g)
).
次いで、Ｓｉ３Ｎ４膜１４をリン酸等の水溶液に除去す
る。なお５ＯＧ１５も同時に除去することができる。そ
の後、先に形成した膜厚１００人程鹿のＳｉＯ□膜１３
をＨＦ等の水溶液によりウォッシュアウトする（同図（
ｈ））。Next, the Si3N4 film 14 is removed in an aqueous solution such as phosphoric acid. Note that 5OG15 can also be removed at the same time. After that, the previously formed SiO□ film 13 with a thickness of about 100
Wash out with an aqueous solution such as HF (see the same figure).
h)).
なお、これより後の形成工程については、特開昭６２−
２０８６６１号公報、特開昭６２−２１３２７３号公報
に記載されているように行う。従って、５ｉＯｚ膜１６
により画定された溝部１２かつ底部にＳｉ基板１１を露
出した溝部１２内に対向電極１７と、誘電体膜１８と、
蓄積電極１９とを形成して蓄積容量Ｃ６を構成する。さ
らに、転送トランジスタ形成領域を画定するフィールド
酸化膜２０と、不純物イオンを注入して形成される一対
の不純物拡散Ｎ（ソース又はドレイン）２１゜２３と、
ゲート電極Ｗ Ｌ ｏとを形成して転送トランジスタＴ
。を構成する。Regarding the formation process after this, please refer to Japanese Patent Application Laid-open No. 1986-
It is carried out as described in Japanese Patent Application Laid-open No. 208661 and Japanese Patent Application Laid-Open No. 62-213273. Therefore, the 5iOz film 16
A counter electrode 17, a dielectric film 18,
A storage electrode 19 is formed to constitute a storage capacitor C6. Further, a field oxide film 20 defining a transfer transistor formation region, a pair of impurity diffusions N (source or drain) 21 and 23 formed by implanting impurity ions,
A transfer transistor T is formed by forming a gate electrode WLo.
. Configure.
次いでゲート電極Ｗ Ｌ ｏを絶縁膜２４により絶縁し
、その後蓄積電ＮＣｏと転送１〜ランジスタＴ。Next, the gate electrode WLo is insulated by an insulating film 24, and then the storage capacitor NCo and the transfer transistor T are connected.
のドレイン２１とを導電層２５により接続し、その後Ｐ
ＳＧ膜２６により絶縁してピント線ＢＬを形成し、ＭＯ
３ＤＲＡＭセルを製造する（同図（ｊ））。is connected to the drain 21 of P by a conductive layer 25, and then P
The focus line BL is formed by insulating with the SG film 26, and the MO
A 3DRAM cell is manufactured ((j) in the same figure).
このようにして、Ｓｉ基板１１に溝堀りをした溝部１２
に選択的に薄い（膜厚１００人程鹿の ５ｉＯｚ膜１３
と、５ｉＪ４膜１４と、５ＯＧ１５とを形成した後に熱
処理をして、厚いＳｉＯ□膜１６膜形６し、その後ＨＦ
（フッ酸）やリン酸等の等方性エツチングにより、５Ｏ
Ｇ１５、Ｓｉ３Ｎ、膜１４及びＳｉＯ２膜１３を順次除
去している。このため溝部１２の側壁に５ｉＯ７膜１３
やＳｉＯ２膜１６等の絶縁膜を残留させ、かつ溝部１２
の底部を開口して、Ｓｉ基板１１の表面を露出すること
が可能となる。In this way, the groove portion 12 formed in the Si substrate 11
Selectively thin (film thickness of about 100 5iOz film 13
After forming the 5iJ4 film 14 and 5OG15, heat treatment is performed to form a thick SiO□ film 16, and then HF
By isotropic etching with (hydrofluoric acid) or phosphoric acid, 5O
G15, Si3N, film 14 and SiO2 film 13 are removed in sequence. Therefore, the 5iO7 film 13 is formed on the side wall of the groove 12.
The insulating film such as SiO2 film 16 or the like is left, and the groove portion 12 is
By opening the bottom of the Si substrate 11, it becomes possible to expose the surface of the Si substrate 11.
これにより従来のような溝部１２の底部を開口するため
のＲＩＥ法等の異方性エツチングに依存することがない
のでＳｉ基板１１の表面を所定形状に維持することが可
能となる。This eliminates the need to rely on anisotropic etching such as RIE to open the bottom of the groove 12 as in the prior art, making it possible to maintain the surface of the Si substrate 11 in a predetermined shape.
〔発明の効果］
以上説明したように本発明によれば、蓄積容量や転送ト
ランジスタを形成する溝部の底部の開口をＲ，ＩＥ法等
の異方性エツチングに依存することなく等注性エツチン
グにより開口することができる。このため所定形状の半
導体基板上に各トランジスタ素子を形成することが可能
となる。[Effects of the Invention] As explained above, according to the present invention, the opening at the bottom of the trench forming the storage capacitor and the transfer transistor can be formed by isotropic etching without relying on anisotropic etching such as R and IE methods. Can be opened. Therefore, each transistor element can be formed on a semiconductor substrate having a predetermined shape.
これにより、製造工程における余裕度の向上を図ること
ができ、超微細、高集積度の半導体記憶装置を製造する
ことが可能となる。As a result, margins in the manufacturing process can be improved, and it becomes possible to manufacture ultra-fine, highly integrated semiconductor memory devices.
第１図は本発明の実施例に係るＭＯ３ＤＲＡＭセルの形
成工程図、
第２図は従来例に係るＭＯ３ＤＲＡＭセルの説明図、
第３図は従来例に係るＭＯ３ＤＲＡＭセルの問題点を説
明する回である。
（符号の説明）
１．１１・・・ｐ型Ｓｉ基板、Ｓｉ基板（半導体基板）
２．２０・・・フィールド酸化膜（フィールド絶縁膜）
、
３．２１・・・ドレイン（不純物拡散層）、４．２３・
・・ソース（不純物拡散層）、５ ａ、 ５ ｂ、
５ ｃ、 ５ ｄ−３ｉＯｚ膜（絶縁膜）、１３．
２４・・・ＳｉＯ□膜（絶縁膜）、１４・・・Ｓｉ３Ｎ
４膜（第１の絶縁膜）、１５・・・ＳＯＧ’（第２の絶
縁膜）、１６・・・ＳｉＯ３膜（第３の絶縁膜）、６．
１９・・・蓄積電極、
７．１８・・・誘電体膜、
８．１７・・・対向電極、
９．２５・・・導電層、
１０．２６・・・ＰＳＧ膜、
２２．１２・・・溝部、
ＷＬ、ＷＬ。・・・ワード線（ゲート電極）、ＢＬ・・
・ビット線、
Ｔ、Ｔ、・・・転送トランジスタ、
Ｃ，Ｃ，・・・蓄積容量、
１、．１２・・・膜厚。
（千ノ
；千ζｊ子ごド叩ぐっ＼しｒ方るレイ９１コ１てイ剤−
るト４０ＳＤＲＡＭしじて２ＬにＤ子ｆＡ；ｒ％’Ｊ＠
第１ 図（才の２）FIG. 1 is a diagram showing the formation process of a MO3DRAM cell according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of a MO3DRAM cell according to a conventional example, and FIG. 3 is a diagram explaining problems of a MO3DRAM cell according to a conventional example. be. (Explanation of symbols) 1.11...p-type Si substrate, Si substrate (semiconductor substrate)
2.20...Field oxide film (field insulating film)
, 3.21...Drain (impurity diffusion layer), 4.23.
... Source (impurity diffusion layer), 5 a, 5 b,
5 c, 5 d-3iOz film (insulating film), 13.
24...SiO□ film (insulating film), 14...Si3N
4 film (first insulating film), 15... SOG' (second insulating film), 16... SiO3 film (third insulating film), 6.
19... Storage electrode, 7.18... Dielectric film, 8.17... Counter electrode, 9.25... Conductive layer, 10.26... PSG film, 22.12... Mizobe, WL, WL.・・・Word line (gate electrode), BL...
・Bit line, T, T, . . . Transfer transistor, C, C, . . . Storage capacitor, 1, . 12...Film thickness. (Thousand; Thousand ζ
40SDRAM and 2L
Figure 1 (Saino 2)
Claims (2)
成する工程と、 前記溝部（１２）を設けた半導体基板（１１）に第１の
絶縁膜（１４）を形成する工程と、前記溝部（１２）の
底部の前記第１の絶縁膜（１４）上に第２の絶縁膜（１
５）を形成する工程と、 前記溝部（１２）の第２の絶縁膜（１５）をマスクにし
て、前記第１の絶縁膜（１４）を選択的に除去する工程
と、 前記半導体基板（１１）を熱処理をして、第３の絶縁膜
（１６）を形成する工程と、 前記第２の絶縁膜（１５）と第１の絶縁膜（１４）とを
除去する工程と、前記溝部（１２）内に蓄積容量（Ｃｏ
）を形成する工程とを有することを特徴とする半導体記
憶装置の製造方法。(1) a step of selectively forming a groove (12) in a semiconductor substrate (11); a step of forming a first insulating film (14) in the semiconductor substrate (11) provided with the groove (12); A second insulating film (1) is formed on the first insulating film (14) at the bottom of the groove (12).
5); selectively removing the first insulating film (14) using the second insulating film (15) in the groove (12) as a mask; and the step of selectively removing the first insulating film (14); ) to form a third insulating film (16); a step of removing the second insulating film (15) and the first insulating film (14); ) is the storage capacity (Co
) A method for manufacturing a semiconductor memory device, the method comprising: forming a semiconductor memory device.
り、前記第２の絶縁膜（１５）がスピンオングラスであ
ることを特徴とする特許請求の範囲第１項に記載する半
導体記憶装置の製造方法。(2) The semiconductor memory according to claim 1, wherein the first insulating film (14) is a silicon nitride film, and the second insulating film (15) is spin-on glass. Method of manufacturing the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62318012A JPH01158759A (en) | 1987-12-15 | 1987-12-15 | Manufacture of semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62318012A JPH01158759A (en) | 1987-12-15 | 1987-12-15 | Manufacture of semiconductor memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01158759A true JPH01158759A (en) | 1989-06-21 |
Family
ID=18094506
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62318012A Pending JPH01158759A (en) | 1987-12-15 | 1987-12-15 | Manufacture of semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01158759A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0361453U (en) * | 1989-10-20 | 1991-06-17 | ||
| EP1073115A3 (en) * | 1999-07-29 | 2004-08-04 | Infineon Technologies North America Corp. | Process for manufacture of trench DRAM capacitor |
-
1987
- 1987-12-15 JP JP62318012A patent/JPH01158759A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0361453U (en) * | 1989-10-20 | 1991-06-17 | ||
| EP1073115A3 (en) * | 1999-07-29 | 2004-08-04 | Infineon Technologies North America Corp. | Process for manufacture of trench DRAM capacitor |
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