JPH01158554A - Data processing system providing dma device - Google Patents

Abstract

PURPOSE:To improve performance without damaging reliability by allowing a data buffer to hold transfer data temporarily by the transfer mode type of a DMA transfer and returning a response signal to a DMA device immediately. CONSTITUTION:A response control circuit 51 returns a response signal to indicate normal or abnormal to a DMA (direct memory access) device 3 according as it is a normal conclusion or an abnormal conclusion after the data transfer between a data transfer control circuit 5 and a main storage device 2 on a read transfer which the DMA device 3 reads out data from the main storage device 2 or on a write transfer which the DMA device 3 writes the data which do not satisfy to the data length of the main storage device 2. Then, when the DMA device 3 transfers the data which is the same length or integer times as long as the data length of the main storage device 2 to the main storage device 2, the data sent from the DMA device 3 are held temporarily in a data buffer 52, a normal response is returned to the DMA device 3 whether the data transfer with the main memory 2 is concluded or not concluded. Thus, the performance improvement of a system is attained.

Description

[Detailed Description of the Invention] [(Already required)] An object of the present invention is to efficiently improve the performance of a data processing system equipped with a direct memory access (DMA) device without impairing its reliability. , a data processing device, and an ECC with a data width of multiple bytes.
A main storage device to which a data processing device is attached and accessed by a data processing device; If DMA transfer is possible to the α device, the MA device and ECC check the contents of the main storage device.
A data processing system comprising a circuit and a data transfer control circuit for controlling data transfer between a main memory device and a DMA device, wherein the data transfer control circuit includes a response control circuit and a response control circuit for controlling data sent from the DMA device. A data buffer 7 for temporary storage is provided, and the response control circuit is D.
During read transfer, in which the MA device reads data from the main memory, and during write transfer, in which the MA device writes data that is less than the data width of the main memory, normal operation occurs after the data transfer between the data transfer control circuit and the main memory is completed. Depending on whether the termination is termination or abnormal termination, a response signal indicating normality or abnormality is returned to the DMA device, and the DMA device responds to the above 1. When transferring data to the α device that is the same as the data width of the main memory device or an integral multiple thereof, the data sent from the DMA device is temporarily held in a buffer, and the data transfer with the main memory device is completed or unfinished. Regardless of the termination, the response control circuit is configured to return a response signal indicating normality to the DMA device.

[Industrial application field]

The present invention relates to a data processing system with a direct memory access (DMA) device, and more particularly, to a data processing system having a data width of multiple bytes and an ECC (Error Code).
A main memory device with a correcting code), an ECC check circuit that checks the contents of this main memory device, and an MA that allows DMA transfer to the main memory device.
The present invention relates to a data processing system including a DMA device, a DMA device, and a data transfer control circuit provided in the data processing device to control data transfer between main storage devices.

[Conventional technology]

FIG. 6 is a block diagram of a conventional data processing system of this type. In the figure, 1 is a data processing device, 2 is a main storage device accessed by this data processing device, 3 is a DMA device that performs DMA transfer, and 4 is a main storage device 2.
This is an ECC circuit provided to improve the reliability of the ECC generator circuit 41 for adding error codes.
and ECC check collect circuit 42 for data check.
It consists of 5 is the above 1. A data transfer control circuit that controls data transfer between the α device 2 and the DMA device 3, and is provided within the data processing device 1.

[Problem to be solved by the invention]

In such a conventional configuration, when the DMA device 3 transfers data to the main storage device 2, the data transfer control circuit 5 controls the main storage device during read transfer when the DMA device 3 reads data from the main storage device 2. During a write transfer to write data that is less than the data width of (in this case, main memory 2
After reading the data from and performing an ECC check,
(It is necessary to combine read data and write data and write them together with ECC bits), 1. What mode of data is used, such as when transferring data to the α device 2 that is the same as the data width or an integral multiple thereof? Even during transfer, a response is returned to the DMA device 3 after waiting for the data transfer between the data transfer control circuit 5 and the main storage device 2 to be completed.

For this reason, when transferring a large amount of data at once, it takes time to transfer the data, which poses a problem in improving the performance of the system.

The present invention has been made in view of these points, and
It is an object of the present invention to provide a data processing system that can efficiently improve the processing performance of the system without impairing reliability.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention. In the figure,
1 is a data processing device; 2 is a main storage device that has a data width of multiple hides and has an FCC added thereto and is accessed by the data processing device 1; 3 is a DM for the main storage device 2;
If A transfer is possible, the MA device, 4, corresponds to 1. above. ECC circuit that checks the contents of α device 2, 5 is main memory device 2 and DMA
This is a data transfer control circuit that controls data transfer with the device 3.

In the data transfer control circuit 5, 51 is a response control circuit, 52 is a data buffer, and the data buffer 52 is D
Data sent from the MA device 3 is temporarily held under the control of the response control circuit 51.

[For production]

The response control circuit 51 is configured so that the DMA device 3 performs the above-mentioned 1. During a read transfer to read data from the α device 2 and a write transfer to write data that is less than the data width of the main memory device 2, normal operation occurs after the data transfer between the data transfer control circuit 5 and the main memory device 2 is completed. A response signal indicating normality or abnormality is returned to the DMA device 3 depending on the termination or abnormal termination, and the DMA
When the device 3 transfers data that is the same as the data width of the main memory device or an integral multiple thereof to the unique device 2, the data sent from the DMA device 3 is temporarily held in the data buffer 52, and the data width is transferred to the main memory device 2. Termination of data transfer with.

A normal response is returned to the DMA device 3 regardless of whether it has been completed or not.

This makes it possible to improve the performance of the system.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing the main part of an embodiment of the system of the present invention, FIG. 3 is a block diagram showing an example of the response control circuit, and FIGS. 4 and 5 are block diagrams showing the signal time of the present invention. It is a chart.

In FIG. 2, the same parts as those in FIG. 1 are designated by the same reference numerals. A data selector 11 switches the connection of each data bus DB connected to the CPU 10, main storage device 2, and data buffer 52 in the data processing device 1 under control from the data transfer control circuit 5. Reference numeral 20 denotes a memory control section that controls the main storage device 2, and access to the main storage device 2 is performed via this memory control section 20. Note that the signals a-f, i, and i will be described later.

In the response control circuit 51 shown in FIG.
A decoder decodes the access information a output from the A device 3, 01 to G4 are AND gates, and G5 is an OR gate. FLGI is the first flag that is set by the memory access request signal e output from the gate G1, and FLG2 is the second flag that is set by the output of the gate G2. Reset by memory access response signal f (R)
be done.

In this configuration, the operation of the apparatus will be explained below.

The ECC circuit 4 is provided to improve the reliability of the main memory device 2, and is designed to improve the data width of the main memory device 2 (for example, 4
There is no need to perform an ECC check for write accesses of the same size or an integer multiple of the same size (bytes), but write accesses of data sizes that are small (for example, 1 to 3 bytes) relative to the data width of the main storage device 2 Access is -
After reading the data from the α device 2 and checking the ECC in step 1 above, the read data and write data are combined and written together with the ECC bit.

The data transfer control circuit 5 controls data transfer between the main memory device 2 and the DMA device 3. That is, during data transfer, the DMA device 3 outputs access information a and a DMA request signal S. In the response control circuit 51, the decoder DEC
decodes this access information a, and if the access information indicates a write access of data that is the same as the data width of the main storage device, for example 4 bytes, or an integral multiple thereof, first, from the DMA device 3 The 4-byte write data is held in the data buffer 52, and a 4-byte store signal d is output to AND gates Gl and G2. As a result, gates Gl and G2 are opened,
A memory access request signal C is output to the memory control unit 20. This memory access request signal e also sets the first flag FLGI. Here, when the memory access response signal f is received from the memory control unit 20, the AND game)G
4 is opened, and the data transfer to the main storage device 2 is completed.

The response control circuit returns a DMA normal response signal C to the DMA device 3 regardless of whether the response has been completed or not. On the other hand, the data transfer control circuit 5 transfers the data held in the data buffer 52 to the main storage device 2.

On the other hand, in the case of a write access with a data size smaller than the data width of the main memory device 2 or any read access, the data transfer control circuit 5 terminates the data transfer between the main memory device 2 and the data transfer control circuit 5. Then, based on the check result by the FCC circuit 4, a response is returned to the DMA device 3 depending on whether it is normal or abnormal, and the process is terminated. In this case, data transfer is performed in the same way as in the conventional case.

FIG. 4 is a signal time chart of the present invention illustrating the above-described operation, and is a signal time chart in the response control circuit of FIG. 3.

As described above, the DMA device 3 first outputs the 4-byte write access information a and also outputs the DMA request signal S. Upon receiving the access information a, the decoding circuit DEC outputs the 4-byte store signal d to AND gates Gl and G2.
Output to. At this time, if the busy flag FLGI is not set, the AND gate G1 outputs the memory access request signal e to the memory control unit 20, and at the same time the busy flag FLGI is set. Also, AND
A 4-byte store mode flag FLG2 is set by the output of gate G2. On the other hand, the data transfer control circuit 5 temporarily holds the data sent from the DMA device 3 in the data buffer 52, and transmits the data acquisition completion notification signal l to the AN
The DMA response signal C is output to the D game) G3 and is returned to the DMA device 3 via the ○R agate 5. Therefore, it is possible to return the DMA response signal C before the memory access response signal f is output from the memory control section 20.

FIG. 5 is another signal time chart of the present invention, which is a signal time chart in the case of data access smaller than the data width. That is, in the case of a write access with a data size smaller than the data width of the main memory device 2 or any read access, unlike the case in FIG. 4, the 4-byte store signal d does not rise, and therefore the 4-byte store mode flag FLG2 is not set, and the memory access response signal f
is output from the memory control unit 20, a DMA response signal C is returned to the DMA device 3 via an AND gate G4 and an OR gate G5.

Through the above operations, when multiple data is transferred in a time-concentrated manner, such as in a file control device, the data to be written is temporarily held in the main storage device 2, and the data is simultaneously transferred. Data transfer performance can be improved by outputting a response signal to the DMA device.

Also, as in the case of controlling a display device,
When transferring data in character units (bytes) or reading data, the ECC is checked as before, and after the data transfer is completed, a response indicating whether the data transfer ended normally or abnormally is returned to the DMA device. Reliability can be maintained.

Although it has been explained above that only 4-byte wide data is temporarily held in the data buffer 52, it is assumed that an address buffer is also provided in addition to the data buffer, and address information is also temporarily held.

〔Effect of the invention〕

As explained in detail above, in the present invention, the transfer data is temporarily held in the data buffer depending on the transfer mode of DMA transfer, and the response signal is immediately returned to the DMA device, which may impair reliability. However, it is possible to provide a data processing system with improved performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of the configuration of an embodiment of the present invention, FIG. 3 is a block diagram of the configuration of a response control circuit, FIG. 4 is a signal time chart of the present invention, and FIG. The figure is another signal time chart of the first invention, and FIG. 6 is a block diagram of the configuration of the conventional device. 1 and 2, 1 is a data processing device, 2 is a main storage device, 3 is a DMA device, 4 is an ECC circuit, 5 is a data transfer control circuit, 51 is a response control circuit, and 52 is a buffer.

Claims (1)

[Claims] A data processing device (1), a main memory (2) having a data width of multiple bytes, to which ECC is added, and accessed by the data processing device (1).
), a DMA device (3) capable of DMA transfer to the main storage device (2), and an ECC circuit (4) that checks the contents of the main storage device (2).
), and a data transfer control circuit (5) that controls data transfer between the main storage device (2) and the DMA device (3), wherein the data transfer control circuit (5) has a response signal. Control circuit (51
) and a data buffer (52) for temporarily holding data sent out from the DMA device (3), and the response control circuit (51) is configured to allow the DMA device (3) to store data from the main storage device (2). During read transfer to read data and write transfer to write data that is less than the data width of main memory device (2), data transfer between data transfer control circuit (5) and main memory device (2) is completed. , returns a response signal indicating normality or abnormality to the DMA device (3) depending on whether the termination is normal or abnormal, and the DMA device (3) stores the data width and data width of the main memory device (2) in the main memory device (2). When transferring the same data or an integral multiple of the data, the data sent from the DMA device (3) is temporarily held in the data buffer (52) and transferred to the main memory (
2) A data processing system equipped with a DMA device, wherein the response control circuit (51) returns a response signal indicating normality to the DMA device (3) regardless of whether data transfer with the DMA device (3) is completed or not.