JPH01133357A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a semiconductor memory which may cope with high integration without forming the capacitor of a trench structure, by connecting a drain of a first transistor to a gate electrode of a second transistor and putting the second transistor in operation by applying a voltage to a control gate facing the gate electrode. CONSTITUTION:Two bit lines which transmit signals from a column decoder are connected to a source electrode 2a of a first transistor as well as a drain electrode 9a of a second transistor and two word lines which transmit the signals from a low decoder are connected to a gate electrode A3 of the first transistor as well as a control gate 10 of the second transistor and further, the source electrode B 6a is connected to a substrate or wiring. The second transistor is put in operation as a transistor by a voltage impressed on the control gate 10.

Description

[Detailed Description of the Invention] [Summary] Regarding the improvement of the structure of a memory cell of a semiconductor memory device, the present invention provides a semiconductor memory device that does not require the formation of a trench-structured capacitor and is compatible with higher integration. A memory cell is configured with two transistors, the drain A of the first transistor is connected to the gate electrode B of the second transistor, and the second transistor is connected to the gate electrode B through a dielectric film. The structure includes control gates facing each other.

[Industrial application field]

The present invention relates to semiconductor memory devices, and particularly to improvements in the structure of memory cells.

The capacity of semiconductor memory devices, such as MOS-DRAMs, has been increasing in recent years, and is about to increase from 1 Mbit to 4 Mbit.

As the degree of integration increases in this way, it becomes difficult to secure a sufficient area for the dielectric film of the capacitor, and for this reason, a trench structure is being adopted.

However, in order to form a capacitor of the required capacity, the depth of the trench must be increased, making manufacturing very difficult.

For this reason, it is thought that the trench structure can only be used up to about 16 Mbit.

Under the above circumstances, there is a demand for a semiconductor memory device that can be highly integrated, does not have a trench structure, and is easy to manufacture.

[Conventional technology]

A conventional semiconductor memory device will be explained with reference to FIG.

In FIG. 4(a), 21 is a silicon substrate, 22 is a source, 22a is a source electrode, 23 is a gate electrode, 24 is a gate oxide film, 25 is a drain, 26 is a drain electrode,
27 is a dielectric film, 28 is a counter electrode, and gate electrode 2
3 is connected to the word line of the semiconductor memory device, and the source 2
Reference numeral 2 is connected to a bit line of a semiconductor memory device, and a drain electrode 26, a dielectric film 27, and a counter electrode 28 form a capacitor.

However, if such a planar structure cannot be achieved due to the increasing degree of integration of semiconductor memory devices, the structure shown in FIG. 4 (
A trench structure as shown in b) is adopted.

In FIG. 4(b), 36 is a drain electrode, 37 is a dielectric film, and 38 is a counter electrode, these three forming a capacitor.

[Problem that the invention seeks to solve]

The problem with the conventional semiconductor memory device described above is that the capacitance 1c of the capacitor of the semiconductor memory device is C: the capacitance ε of the capacitor. : Permittivity of vacuum εS : Permittivity of dielectric film d : Thickness of dielectric film S : Area of dielectric film, so once the material of the dielectric film is determined, the capacitance C of the capacitor is equal to that of the dielectric film. Although it is determined by the area of the film and the thickness of the dielectric film, a decrease in the film thickness will result in a decrease in withstand voltage, and an increase in the area will be an obstacle to higher integration.

Moreover, when the structure of the capacitor is a trench structure,
In order to achieve high integration, the depth of the trench must be increased, which makes manufacturing extremely difficult.

In view of the above-mentioned circumstances, it is an object of the present invention to provide a semiconductor memory device that does not require the formation of a trench-structured capacitor and is capable of responding to higher integration.

[Means for solving problems]

The above problem arises when a memory cell is configured with two transistors, the drain A of the first transistor is connected to the gate electrode B of the second transistor, and the second transistor connects the gate electrode B and the dielectric film. This problem is solved by a semiconductor memory device according to the present invention, which has a structure including control gates facing each other via a semiconductor memory device.

[Effect]

That is, in the present invention, a memory cell of a semiconductor memory device is configured with two transistors, the drain A of the first transistor is connected to the gate electrode B of the second transistor, and charge is accumulated in the gate electrode B. Then, conduction is established between the source B of the second transistor and 11478.

To actually read data, a voltage must be applied to the control gate of the second transistor, the second transistor must be selected, the channel of the second transistor must be inverted so that sufficient current flows, and the conduction state must be detected. .

In this way, it becomes possible to manufacture a highly integrated semiconductor memory device very easily without using a trench-based capacitor.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

In FIG. 1, 1 is a silicon substrate, 2 is a source A, 2
a is a source electrode A, 3 is a gate electrode A, 4 is a gate oxide film A, and 5 is a drain A, and those having A at the end constitute the first transistor.

6 is source B, 7 is gate electrode B, 8 is gate oxide film B
, 9 is the drain B, 10 is the control gate 10.1
1 is a dielectric film, and those having B at the end or having neither A nor B constitute the second transistor.

FIG. 2 is a plan view schematically showing their planar arrangement, in which the drain A5 of the first transistor and the gate electrode B7 of the second transistor are connected.

Figure 3 shows the wiring connections of this embodiment, where the two bit lines transmitting signals from the column decoder are connected to the first
The two word lines, which are connected to the source electrode 2a of the transistor and the drain electrode 9a of the second transistor and transmit signals from the row decoder, are connected to the gate electrode A3 of the first transistor and the control gate 10 of the second transistor, respectively. The source electrode 86a of the second transistor is connected to the substrate or wiring.

Word line 2 and bit line 1 write to the second transistor through the first transistor, and word line 1 and bit line 2 read information from the second transistor.

In the semiconductor memory device of this embodiment having such a structure and wiring connection, since the second transistor operates as a transistor by the voltage applied to the control gate 10, the gate electrode B7 and the control gate 10
Since there is no need to increase the capacitance of the capacitor consisting of the capacitor and the dielectric film 11 therebetween, the present invention can be used in highly integrated semiconductor memory devices.

〔Effect of the invention〕

As is clear from the above explanation, when a semiconductor memory device is a capacitor type, there is a limit as the amount of charge accumulated in the memory cell decreases as the degree of integration increases. Consisting of two transistors, the first
The drain of the second transistor is connected to the gate electrode of the second transistor, and a voltage is applied to the control gate facing this gate electrode to activate the second transistor, so the amount of charge accumulated is similar to that of conventional memory cells. It has advantages such as not being necessary and easy to manufacture, and can be expected to have significant economical and reliability-improving effects, making it extremely useful industrially.

[Brief explanation of the drawing]

FIG. 1 is a side sectional view showing the structure of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a schematic plan view showing a semiconductor memory device according to an embodiment of the present invention, and FIG. 3 is a schematic plan view showing the structure of a semiconductor memory device according to an embodiment of the present invention. FIG. 4 is a schematic plan view showing wiring connections of one embodiment; FIG. 4 is a side sectional view showing the structure of a conventional semiconductor memory device; FIG. In the figure, 1 is a silicon substrate, 2 is a source A1, 3 is a gate electrode A, 4 is a gate oxide film A, 5 is a drain A1, 6 is a source B1, 7 is a gate electrode B, 8 is a gate oxide film B, 9 is a drain B1 10 is a control gate; 11 is a dielectric film; FIG. 1 is a side sectional view showing the structure of a semiconductor memory device according to an embodiment of the present invention; and FIG. Schematic plan view showing wiring connection of one embodiment FIG. 3(a) Capacitor with planar structure

Claims (1)

[Claims] The memory cell is composed of two transistors, the drain A (5) of the first transistor is connected to the gate electrode B (7) of the second transistor, and the second transistor is connected to the gate electrode B (7). A semiconductor memory device characterized by having a structure including control gates (10) facing each other with a dielectric film (11) in between.