JPH01120132A - Radio receiver - Google Patents

Abstract

PURPOSE:To evade the influence of a noise generated during the operation of a DC voltage boosting circuit by stopping the operation of the DC voltage boosting circuit during intermittent receiving operation and using charges in a capacitor during the period. CONSTITUTION:A control part 7 turns on a switch SW 62 prior to a switch SW 61 to operate a PLL circuit 2 and turns off the SW 62 while the SW 61 turns off. A switch SW 63 also turns on while the SW 62 turns on, and the DC voltage boosting circuit 3 is also starred simultaneously with the actuation of the PLL circuit 2. Further, when the SW 61 turns on and a radio signal amplifying and demodulating part 1 begins to operate, the SW 63 turns off to stop the operation of the circuit 3. A few charges are consumed by the charge pump circuit in the PLL circuit 2 after the PLL circuit 2 enters a stationary state, so charges in the capacitor 5 are used sufficiently as said charges in the short time wherein the demodulating part 1 is in operation and even when the operation of the circuit 3 is stopped, the PLL circuit 2 operates normally.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a radio receiver, and particularly to a portable radio receiver that performs intermittent reception operation.

[Conventional technology]

With advances in semiconductor device technology, prescaler ICs and phase-locked loops (hereinafter referred to as PLLs) that operate at low voltages have become available.
Circuit ICs have been developed one after another. For this reason, PLL circuits have come to be employed even in wireless receivers that operate on dry batteries, such as individual selective call receivers.

By the way, the voltage controlled oscillator (hereinafter referred to as VCO) in the PLL circuit
A semiconductor capacitive element (varactor diode) is used as the oscillation frequency control element of the
If the CO control voltage is low, the frequency variable range cannot be widened, or if the modulation sensitivity of vCo is increased to widen the frequency variable range, it becomes susceptible to disturbance noise and the C/N of the oscillation output deteriorates. There's a problem. In order to solve this problem, conventional wireless receivers use a DC booster circuit to generate a voltage higher than the battery voltage.
This high voltage is supplied to a charge pump circuit that generates the CO control voltage.

[Problem that the invention seeks to solve]

However, since the DC booster circuit generates switching noise at a high level, conventional radio receivers are affected by this switching noise and have the disadvantage that reception performance deteriorates. This drawback becomes a particularly serious problem in radio receivers that have a built-in small antenna, such as an individual selective call receiver.

SUMMARY OF THE INVENTION An object of the present invention is to provide a radio receiver that can avoid the effects of noise from a DC booster circuit when performing intermittent reception operations like an individual selective calling receiver.

[Means for solving problems]

The wireless receiver of the present invention has an output from a charge pump circuit which uses as a control input the result of phase comparison between a local oscillation signal output by a voltage controlled oscillator or a signal obtained by frequency-dividing this local oscillation signal and a reference signal. a phase-locked loop circuit that generates a control voltage for the voltage-controlled oscillator via a low-pass filter; a radio signal amplification and demodulation section that frequency-converts and demodulates a radio signal into an intermediate frequency band using the local oscillation signal; A wireless receiver equipped with a battery and performing intermittent reception operation, comprising: a DC booster circuit that boosts the output voltage of the battery and supplies it to the charge pump circuit; and a capacitor connected in parallel to the output terminal of the DC booster circuit. and means for controlling the time during which the battery supplies the output voltage to the radio signal amplification and demodulation section and the time during which the output voltage is supplied to the DC booster circuit so as not to overlap.

〔Example〕

The present invention will be described in detail below with reference to the drawings illustrating the embodiments.6 FIG. 1 is a block diagram showing an embodiment of the wireless receiver of the present invention.

The embodiment shown in FIG. 1 is an individual selective call receiver with antennas 11. High frequency amplifier 12. Bandpass filter 13. Mixer 14. Bandpass filter 15° intermediate frequency amplifier 16. Radio signal amplification and demodulation section 1 including demodulation section 17 and mixer 14
PLL circuit 2 that supplies a local oscillation signal to
A DC booster circuit 3 that generates a voltage and supplies it to the PLL circuit 2 via a diode 4 for preventing reverse current, a large-capacity capacitor 5 connected in parallel to the output terminal of the DC booster circuit 3 via the diode 4, and a switch. 61~63 and switch □ Ciro 1~
A control unit 7 that controls on/off of 63. and switch 81
, 62, 6.3, the radio signal amplification and demodulation unit 1. PLL
The circuit 2 is configured to include a battery 8 that supplies a voltage V+ to the DC booster circuit 3.

As shown in FIG. 2, the PLL circuit 2 includes a reference signal generator 21 that generates a reference signal, a phase comparator 22 that compares the phase of the reference signal and the output of the programmable frequency divider circuit 26-. A charge pump circuit 23 controlled by the output of the phase comparator 22, a low-pass filter 24, and a low-pass filter 2
The VCO 25 generates a local oscillation signal whose frequency is controlled by the output of the charge pump circuit 23 via the VCO 25, and a programmable frequency dividing circuit 26 which divides the local oscillation signal. Reference signal generator 211 Phase comparator 22
．． VCO 25 and programmable frequency divider circuit 26 have voltage V
+ is supplied to the charge pump circuit 23, and the voltage V++ is supplied to the charge pump circuit 23.
is supplied.

FIG. 3 shows the phase comparator 22. Yage pump circuit 23.
It is a circuit diagram of a low-pass filter 24-.

The phase comparator 22 includes an exclusive OR circuit (hereinafter referred to as EX-OR).
) 221, and an n-channel FET 222 whose gate is connected to the output terminal of EX-OR 221 and whose source is installed.
An open-drain circuit consisting of
EX-OR consisting of a p-channel FET 223 to which the voltage is applied and an n-channel FET 224 to which the source is grounded.
221.

The charge pump circuit 23 has a pnp transistor 231 and an emitter, to which a voltage y++ is applied.

NPN tri-registor 232 and resistor 2
33 to 235. A resistor 233 is connected between the emitter and base of the transistor 231, and the base is connected to the drain of the FET 222 via a resistor 234. The base of transistor 232 is connected to the drains of FET 223 and FET 224 via resistor 235. The collectors of transistors 231 and 232 are interconnected to form an output terminal. Low pass filter 2
4 is composed of resistors 241-243 and capacitors 244-246.

First, the operation of the PLL circuit 2 will be explained with reference to FIGS. 2 and 3.

Reference signal generator 21 output and programmable frequency divider circuit 26
The -PLL circuit 2 enters a steady state in a state where the phase with the output is shifted by π/2. In this state, the duty cycle of the EX-OR 221 output becomes 50%, and the charging time and discharging time of the charge pump circuit 23 become equal. VC
When the output frequency of O25 changes and the relative phase of the programmable frequency divider circuit 26 output (with respect to the reference signal generator 21 output) changes, the charging/discharging time ratio of the charge pump circuit 23 changes, and as a result, the low-pass filter The output voltage of VCO 24 changes to cancel out the fluctuation of the output frequency of VCO 25,
The output frequency of VC○25 is kept constant. VCO25
Since the control voltage of is obtained from the high voltage V++, VCO2
The modulation sensitivity of 5 can be lowered to avoid the influence of disturbance noise, and the C/N of the local oscillation signal which is the output of vCO25 can be reduced.
can be made good.

Next, the overall operation of the embodiment shown in FIG. 1 will be explained.

FIG. 4 is a time chart showing the on/off operations of the switches 61 to 63.

Since the wireless signal to be received is a randomly transmitted burst, the control unit 7 operates the switch 61 for several tens of milliseconds at a cycle of about 1 second.
It is turned on and the radio signal amplification/demodulation section 1 is operated intermittently to wait for a burst. When the switch 61 is turned on, the radio signal received by the antenna 11 is amplified by the high frequency amplifier 12, inputted to the mixer 14 via the bandpass filter 13, and transmitted to the P.
The frequency is converted to an intermediate frequency band using the local oscillation signal from the LL circuit 2, extracted by a bandpass filter 15, amplified by an intermediate frequency amplifier 16, and demodulated by a demodulator 17 to provide a demodulated output. When a decoder section (not shown) following the radio signal amplification and demodulation section 1 detects a preamble signal during demodulation output, the control section 7 turns on the switch 61 continuously,
Enter data reception state. The decoder section detects a frame synchronization signal following the preamble signal, performs frame synchronization, and receives the following message data if the individually selected calling number being demodulated and output is the number of the own station. When the individual selection calling number is not the own number or when the message data has been received, the control unit 7 switches the switch 6
1 is returned to the intermittent operation state again. The data reception state continues for about 1 second.

The control unit 7 controls the switch 6 before turning on the switch 610.
2 is turned on to operate the PLL circuit 2, and the switch 61 is turned on to operate the PLL circuit 2.
When the switch 62 is turned off, the switch 62 is turned off.

When the switch 620 is turned on, the switch 63 is also turned on, and the DC booster circuit 3 is also activated at the same time as the PLL circuit 2 is activated. However, when the switch 61 is turned on and the radio signal amplification/demodulation section 1 starts operating, the switch 63 is turned off and the operation of the DC booster circuit 3 is stopped. After the PLL circuit 2 reaches a steady state, the amount of charge consumed by the charge pump circuit 23 is very small due to correction of characteristic fluctuations of the VCO 25 and replenishment of leakage current of capacitors in various parts, so the wireless signal amplification and demodulation section 1 starts operating. For a short period of time, this charge can be sufficiently covered by the charge stored in the capacitor 5, and even if the operation of the DC booster circuit 3 is stopped during this period, the PLL circuit 2 will operate normally.

〔Effect of the invention〕

As explained in detail above, the wireless receiver of the present invention has vC
The operation of the DC booster circuit that generates a high voltage to be supplied to the charge pump circuit that generates the O control voltage is stopped during intermittent reception operation, and during this period the high voltage is supplied to the charge pump circuit from the capacitor connected to the output terminal of the DC booster circuit. Since the DC booster circuit is supplied with
It has a unique effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the wireless receiver of the present invention, FIG. 2 is a block diagram of a PLL circuit in the embodiment shown in FIG. 1, and FIG. 3 similarly shows a phase comparator and charger. FIG. 4 is a circuit diagram of the pump circuit and the low-pass filter, and is also a time chart showing the on/off operation of the switch. 1...Radio signal amplification and demodulation section, 2...P
LL circuit, 3...DC booster circuit, 5...
・Capacitor, 7... Control section, 8...
Battery, 21...Reference signal generator, 22...
...Phase comparator, 23...Charge pump circuit, 24...Low pass filter, 25...V
C.O. 26...Programmable frequency dividing circuit, 61 to 63
······switch. Agent Patent Attorney Uchihara Oto 1 Figure 3' $ and 9

Claims (1)

[Claims] The output of a charge pump circuit whose control input is the result of phase comparison between a local oscillation signal output by a voltage controlled oscillator or a signal obtained by frequency-dividing this local oscillation signal and a reference signal is passed through a low-pass filter. a phase-locked loop circuit that uses the local oscillation signal as a control voltage for the voltage-controlled oscillator; a radio signal amplification and demodulation section that uses the local oscillation signal to frequency-convert and demodulate a radio signal to an intermediate frequency band; and a battery for power supply. , in a radio receiver that performs intermittent reception operation, the battery includes: a DC booster circuit that boosts the output voltage of the battery and supplies it to the charge pump circuit; a capacitor connected in parallel to the output terminal of the DC booster circuit; A radio receiver comprising means for controlling a time for supplying an output voltage to the radio signal amplification and demodulation section and a time for supplying the output voltage to the DC booster circuit so that they do not overlap.