JPH01117363A - Vertical insulated gate field effect transistor - Google Patents

Abstract

PURPOSE:To realize a longitudinal IGFET wherein a parasitic transistor does not readily operate in the absence of an increase in ON-resistance by a method wherein a second semiconductor region of one conductivity type higher in impurity concentration than a first semiconductor region is formed on the lower section of a well region in contact with a drain region. CONSTITUTION:In contact with a drain region 6 positioned under a well region 2, a high-concentration second semiconductor region 1 is formed, which is same as the drain region 6 in conductivity type. In such a design, breakdown strength is lower in the second semiconductor region 1 than in the surface, which causes a breakdown current to flow not on the surface but through the second semiconductor region 1. No parasitic transistor operates because there is no current in a base resistor, which contributes to the prevention of a thermal runaway. There is no increase in ON-resistance because there is no change in the gate width.

Description

[Detailed description of the invention] [Industrial application field] The present invention is utilized in the field of semiconductor devices.

The present invention relates to a vertical insulated gate field effect transistor (hereinafter referred to as a vertical IGFET) having a drain on the back surface, and particularly to a large current vertical IGFET.

〔overview〕

The present invention provides, in a vertical IGFET having a drain electrode on the back surface, a portion in contact with the drain region below a well region of a conductivity type opposite to that of the drain region where the source region is formed.
By forming a semiconductor region having the same conductivity type as the drain region and a higher impurity concentration than the drain region, operation of the parasitic transistor can be prevented without increasing on-resistance.

[Conventional technology]

An example of the structure of a conventional vertical ICFET is shown in FIG.

The conventional example shown in FIG. 6 shows an N-channel vertical IGFET. In FIG. 6, 2 is a P well region formed in the N- epitaxial layer 6 which becomes a drain region, and 3 is a P well region.
a base region, 4 a gate electrode made of polysilicon, 5
is N, source region 7 is an insulating film, 8 is a source electrode, 9 is N
+substrate and 10 are drain electrodes.

In this conventional vertical IGFET, the drain current I is from the source electrode 8 to the source region 5 to the gate electrode 4.
It flows through the N-epitaxial layer 6, which forms the underlying channel and drain regions, and via the N-substrate 9 to the drain electrode 10.

Such vertical IGFETs are widely used for switching large currents such as in motor drives, taking advantage of their characteristics of high speed, high voltage resistance, and ability to flow large currents.

[Problem that the invention seeks to solve]

By the way, as shown in Figure 7, in large current switching operations such as motor drive mentioned above, the coil often acts as a load, so the vertical IGFET may be thermally destroyed by the back electromotive force generated in the coil. It becomes a problem. As shown in Figure 7, when the vertical IGFET changes from the on state to the off state, a large electromotive force is generated in the coil, causing the vertical IGFET to switch from the on state to the off state.
T breaks down and attempts to release the magnetic energy stored in the coil.

Normally, in a vertical IGFET, the withstand voltage at point A in FIG. 6 is lower than at point B, so the drain current In at the time of breakdown flows along a path as indicated by the broken line in FIG. Therefore, a current flows through the base resistor R of the parasitic transistor TR, the base voltage rises, and the parasitic transistor TR is turned on, leading to thermal breakdown.

In other words, in the conventional vertical IGFET, the withstand voltage at point A in FIG. 6 is low, so the parasitic transistor TR is easily turned on, and thermal runaway of the parasitic transistor TR limits the maximum current that can flow during breakdown. There are some drawbacks. Especially for vertical IGFETs whose withstand voltage is several tens of volts,
Since the depletion layer near point A in FIG. 6 is difficult to connect, the withstand voltage at point A is low and the influence is large. To avoid this, there is a method of narrowing the width of the polysilicon gate to make the depletion layer more easily connected, but this method has the disadvantage that the current path becomes narrower and the on-resistance increases.

An object of the present invention is to provide a vertical IGFET in which the parasitic transistor is difficult to turn on without increasing the on-resistance by eliminating the above-mentioned drawbacks.

[Means for solving problems]

The present invention provides a vertical insulated gate field effect transistor comprising a first semiconductor region of one conductivity type forming a drain region and a well region of an opposite conductivity type formed in the first semiconductor region. The semiconductor device is characterized in that a second semiconductor region of one conductivity type and having a higher impurity concentration than the first semiconductor region is formed in a lower part of the region in contact with the drain region.

[Effect]

Since the second semiconductor region, which is a highly doped impurity region of the same conductivity type as the drain region, is formed in contact with the drain region at the bottom of the well region, the withstand voltage is higher than that of the surface region (point A in FIG. 6). The second semiconductor region (corresponding to point B in FIG. 6) is lower in temperature, and the breakdown current flows through the second semiconductor region without passing through the surface portion.

Therefore, the parasitic transistor does not turn on without current flowing through the base resistor, and thermal runaway is prevented. Furthermore, since the gate width remains the same, the on-resistance does not increase.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic longitudinal sectional view showing a first embodiment of the present invention.
The case of N-channel type is shown. The example is an N-type substrate 9 which is a semiconductor substrate having a high impurity concentration (N).
An N-epitaxial layer 6 as a first semiconductor region of N-type low impurity concentration (N-) formed on the drain region and a P well region formed in a predetermined portion of this N-epitaxial layer 6. 2, a P base region 3 formed on both sides of this P well region 2, an N+ source region 5 formed including a part of the P base region 3 on both sides of the P+ well region 2, and a gate insulating film. the gate electrode 4 made of polysilicon formed through the gate electrode 4, the insulating film 7 covering the gate electrode 4, the source electrode 8, the drain electrode 10 formed on the lower surface of the N+ substrate 9, and the lower part of the P+ well region 2. An N'''' region 1 is formed as a second semiconductor region in a portion where an N'''' epitaxial layer 6 is formed as a drain region.

FIG. 2 is an impurity concentration distribution diagram in the YY' cross section of FIG. 1, and shows an outline of the impurity concentration distribution.

Here, the impurity concentration of the N′ region 1 is determined from the surface portion (point A in FIG. 6) and the junction between the N′ region 1 and the N− epitaxial layer 6 (point A in FIG. 6).
(corresponding to point B in FIG. 6) is selected so that the withstand voltage difference is 10 V or more.

3(a) and 3(c) show the manufacturing method of the second embodiment, and show schematic longitudinal cross-sectional views in the process of forming the N′ region 1. FIG.

First, as shown in FIG. 2(a), N'' is placed on the N+ substrate 9.
After forming the epitaxial layer 6, an insulating film 7 is formed on the N- epitaxial layer 6, and the insulating film 7 at the position where the N+ region 1 is to be formed is selectively etched and removed, and ion implantation of, for example, phosphorus is performed. By doing so, an N+ region l is formed.

Next, as shown in FIG. 3(c), boron ions are implanted and then pushed in to form a P" well region 2.

In this way, after forming the active region 1, the P base region 3, the N source region 5, the gate electrode 4, the source electrode 8, and the drain electrode 10 are formed. An IGFET is obtained.

FIG. 4 is a schematic vertical sectional view showing a second embodiment of the present invention.
The case of P channel type is shown. The second embodiment is substantially the same as the first embodiment shown in FIG. 1 except for the method of forming the P+ region 11 as the second semiconductor region.

FIGS. 5(a), 5(b), and 5(C) show the manufacturing method of the second embodiment, and are schematic longitudinal sectional views in the process of forming the P'' region 11.

First, as shown in FIG. 5(a), P is placed on the P substrate 19.
- Form the epitaxial layer 16, and form the P+ region 11 by implanting boron ions into the entire surface of the epitaxial layer 16 from its upper surface without using a mask.

Next, as shown in FIG. 5(c), phosphorus is ion-implanted into the entire surface to push it in, leaving a P+ region 11 with a predetermined thickness, and the rest being the same or similar to the P- epitaxial layer 16. A P″″ compensation epitaxial layer 16a having a slightly higher impurity concentration is formed.

Next, as shown in FIG. 5(C), an insulating film 17 is formed on the upper surface, and phosphorus is selectively implanted and pushed.
N well region 12 is formed so that its bottom surface is located within P region 11 .

After that, by forming the N base region 3, the P source region 15, the gate electrode 14, the source electrode 18, and the drain electrode 20, the vertical IGFET shown in FIG. 4 is obtained.

The second embodiment has the advantage that the concentration of the current path is increased, which is effective in reducing the on-resistance, and that no mask is required to form the P' region 11.

A feature of the present invention is that an N+ region 1 and a P'' region 11 are provided in FIGS. 1 and 2, respectively.

〔Effect of the invention〕

As explained above, according to the present invention, by forming a high impurity concentration region of the same conductivity type as the drain region under the well region, a vertical IGFET in which the parasitic transistor is difficult to turn on can be achieved without increasing the on-resistance. obtained, and the effect is great.

[Brief explanation of the drawing]

FIG. 1 is a schematic vertical sectional view showing a first embodiment of the present invention. FIG. 2 is an impurity concentration distribution diagram in the YY' cross section of FIG. FIGS. 3(a) and 3(a) are schematic vertical cross-sectional views showing the manufacturing process of the N' region 1 of the first embodiment of the present invention. FIG. 4 is a schematic vertical sectional view showing a second embodiment of the present invention. FIGS. 5A, 5C, and 5C are schematic vertical cross-sectional views showing the manufacturing process of the P' region 11 in the second embodiment. FIG. 6 is a schematic vertical sectional view showing a conventional example. FIG. 7 is an explanatory diagram of its operating circuit. 1...N+ territory area 2...P゛well area 3...P
Base region, 4.14... Gate electrode, 5... N source region 6... N- epitaxial layer, 7.17.
...Insulating film, 8...Source electrode, 9...N゛Substrate 1
0.20...Drain electrode, 11...P' region 12
...N well region 13...N base region, 15.
...P source region 16...P- epitaxial layer,
16a...P-compensation epitaxial layer, 19...P
+Substrate, ■,...drain current, R...base resistance, TR...parasitic transistor, VIlls...source-drain voltage. Patent applicant: NEC Corporation 1. . Agent Patent Attorney Nao Ide Takafu - Daigekishio υ's thousand concentration part'M 2 times 6: N-Epi 74% 4 7: Shoulder circumference recommendation 9: N''JL board Fusen - Fu material Example〇Two-legged eave plan M3 Figure 11: P” area 162P-Nipitakinyam view12: r/Usile eaves (16α:P
″″All 1 wealth epitakinya 113: Nσ-Iruri-(18
: Saw power input 114: Gate power M 19
: P”JU School 15: Biseau Matakasu flA
20: Two major punishments for power consumption nails example 11 Attack 4 times IT: p” deposit 16a: P-editing two bits and pieces 112: N” well arrogance Q 17: Narikamo Akira trap 16, P-epitarchine layer 19゛
ρ"! Process Fr side diagram of the second major example 5 times 2 P4 Ueno 1. Area 3・P - (--Foil to space 4I 6 Mouth Operation circuit of conventional example W57 Diagram

Claims (1)

[Claims] (1) Vertical type comprising a first semiconductor region (6, 16) of one conductivity type forming a drain region and a well region (2, 12) of the opposite conductivity type formed within this first semiconductor region The insulated gate field effect transistor is characterized in that a second semiconductor region (1, 11) of one conductivity type and having a higher impurity concentration than the first semiconductor region is formed in a portion below the well region in contact with the drain region. Vertical insulated gate field effect transistor.