JPH01117338A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent any defective transformation parts from occurring by a method wherein a thermal oxidation films imposing stress on the edge parts of U grooves are not formed by thermally oxidizing the surface of polycrystalline semiconductor film buried in the U-grooves but an insulating film is formed by sputtering process, liquid coating process etc. CONSTITUTION:First, an N<+>buried layer 22 and N-type epitaxial layer 23 are formed on a P-type Si substrate 21. Second, an SiO2 film 24 and an Si3N4 film 25 are formed on the overall surface of the N-type epitaxial layer 23. Then, openings 27 are made to expose the N-type epitaxial layer 23. Third, U-channel parts 28 are formed and inner wall and bottom thereof are thermal-oxidized to form the other SiO2 films 20. Fourth, nondoped polySi film 31 is grown on overall surface of the substrate 21 by low pressure CVD process to fill up the U-grooves 28 again. Fifth, the polySi film 31 is etched away using the Si3N4 film 25 as a stopper material to flatten the surface of the substrate 21. Furthermore, the Si3N4 film 25 on the SiO2 film 24 is removed. Finally, the polySi film 31 in the U grooves 28 is insulated and subsequent formation processes are performed similarly to the conventional ones.

Description

[Detailed Description of the Invention] C Summary] The present invention relates to a method for manufacturing a semiconductor device, particularly a method for forming U-groove element isolation in bipolar transistor ICs, etc. The present invention relates to a method for manufacturing a semiconductor device, particularly a method for forming U-groove element isolation, etc. in bipolar transistor ICs, etc. In order to eliminate the generation of dislocation defects due to stress caused by stress and to insulate the upper part of the poly 5illi, a process of forming an epitaxial layer on the substrate and a process of forming a heat oxidation resistant material on the entire surface of the epitaxial layer are performed. forming a first insulating film, and then selectively removing the heat oxidation-resistant first insulating film to expose the epitaxial layer and forming an opening; forming a U-groove by etching, and then forming a second insulating film on the surface of the U-groove, forming a polycrystalline semiconductor film in the U-groove, and filling the U-groove almost flat; a step of depositing a third insulating film on the substantially flat buried U-groove portion, and a step of forming an element in the first epitaxial layer surrounded by the U-groove portion. .

[Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and more specifically, to a method of forming a U-groove element isolation band of a bipolar transistor IC or the like.

[Conventional technology] FIG. 2.3 is an explanatory diagram of a conventional example.

FIG. 2 is a cross-sectional view of a semiconductor device forming a random access memory (RAM) or the like formed by the U-groove element isolation method. In the figure, 1 is a P-type Si substrate, and 2 is an N buried layer selectively formed on the P-type Si substrate l.

3 is an n-type epitaxial layer, and 4 is U which becomes an isolation band between elements.
This is a poly-Si film formed within the groove. Although the poly-Si film 4 is inferior to other insulating films, such as Si films, in terms of electrical properties such as insulation and dielectric constant, the coefficient of thermal expansion is S.
Since it is approximately equal to i, no large stress is generated during the heat treatment after embedding.

Further, 5 is a channel cut layer, and 6 is a SiO□ film for isolation between elements, which insulates the inner wall of the U-groove and each electrode. 7 is a P-type diffusion layer forming a pnp junction element constituting the load resistance of the collector; 8 is a base diffusion layer; 9 is a base compensation layer; 10 is an emitter diffusion layer; 11 is a collector compensation layer;
12 is a poly-Si film for electrode contact. In addition, R
Reference numeral 4 denotes a collector load resistance lead-out electrode for drawing out the pnp junction element constituting the collector load resistance, and El and El are emitters formed by patterning aluminum or the like, forming a multi-emitter. B is the base and C is the collector. These constitute a semiconductor device.

Note that 13 is a dislocation defect portion, which is generated from the U-groove shoulder or the high concentration diffusion region, and may penetrate through the N-type epitaxial layer 3 and the N° buried layer 2 to reach the P-type Si substrate 1.

[Problem that the invention seeks to solve]

According to the conventional example, a SiO□ film is formed by thermal oxidation on the upper part of the poly-Si film 4 which is backfilled into the U-groove for isolation between elements. Therefore, the N-type epitaxial layer, N9
Stress is applied to the buried layer and the portions of the P-type St substrate l that are close to the U-groove.

That is, as shown in the process diagram for forming a semiconductor device according to the conventional U-groove isolation method in FIG. 3, in FIG. After forming 3, the entire surface is coated with Sin, film 51,
S i , N- film 52 is formed, resist 1li53a
An opening 41 for a U-groove is formed on the substrate l using a method.

Next, a U-groove portion 42 with a depth of approximately 5 μm is formed by RIE, etc., the inside of the U-groove is oxidized, and ions for channel cut are implanted to form a channel cut N5 (FIG. 2(b)).
).

Next, a poly-Si film 4 is grown inside the U-groove 42 by low-pressure CVD or the like, and then etched. Thereafter, the poly-Si film 4 above the U-groove portion 42 is thermally oxidized to form a thermally oxidized portion 42a, and the poly-Si film 4 is insulated (FIG. 4(C)).

Furthermore, using the resist film 53b as a mask, ions 61 are implanted near the U groove 2.
is a B0 ion at an ion acceleration energy of 60KeV and a dose of IQ! '~l O"cm-".

The ion implantation in this case is for forming a Pnp junction element for the collector load resistance of a bipolar transistor constituting a RAM or the like, or a pn junction element for a Schottky diode SBD.

Next, it is activated by heat treatment (900-1200'C) to form a P-type diffusion layer 7 with a high impurity concentration. At this time, depending on the dose of the B0 ion of ion 61, the N type epitaxial III-N"b buried layer and the P
Dislocation defect portions 13 may occur within the type Si substrate 1. Note that the frequency of occurrence of dislocation defects increases as the ion dose increases.

The occurrence of this dislocation defect portion 13 induces leakage current in the pnp junction element and the multi-emitter, which inevitably leads to a decrease in the reliability of transistor characteristics and a decrease in production yield.

The present invention has been created in view of the problems of the conventional example, and eliminates the generation of dislocation defective parts due to stress caused by thermal oxidation of the upper part of the poly-Si film backfilled in the U-groove. An object of the present invention is to provide a method for manufacturing a semiconductor device that makes it possible to form an insulating film on top of a film.

[Means for solving problems]

The method for manufacturing a semiconductor device of the present invention is described in a first embodiment.
As shown in FIGS. (a) to (β), a step of forming an epitaxial N23 on the substrate 21, and a step of forming a heat oxidation-resistant first layer on the entire surface of the epitaxial layer 23 are performed.
After that, the heat oxidation-resistant first insulating film 25 is selectively removed, and the epitaxial N
23 and forming an opening 27; and forming a U-groove 28 in the opening 27 by anisotropic etching.
is formed, and then a second insulating film 2 is formed on the surface inside the U groove 28.
9, forming a polycrystalline semiconductor film 31 in the U-groove 28 and embedding the U-groove 28 almost flatly, and forming a third polycrystalline semiconductor film 31 on the U-groove 28 buried almost flatly. The method is characterized by comprising a step of depositing an insulating film, and a step of forming an element in the epitaxial layer 23 surrounded by the U-groove portion 2B, thereby achieving the above object.

[Effect]

According to the manufacturing method of the present invention, the surface of the polycrystalline semiconductor film buried in the U-groove is not subjected to thermal oxidation treatment to form a thermal oxide film that applies stress to the edge portion of the U-groove. The insulating film is deposited using a liquid coating method or the like.

This makes it possible to eliminate stress in and around the U-groove, and prevents the generation of dislocation defects even if the semiconductor substrate is heat-treated after ion implantation at a high dose near the U-groove in the subsequent process. It becomes possible to do so.

Further, according to the method of the present invention, 1.5X10"elm-
It is possible to prevent the generation of dislocation defects even in the case of a high dose amount.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is an explanatory diagram of a method of manufacturing a semiconductor device according to an embodiment of the present invention, and as an example thereof, a process diagram is shown in which a bipolar transistor having a multi-emitter and a collector load resistor are formed on the same substrate.

In the figure, first, N° buried jI is placed on the P-type Si substrate 21.
22 and N-type epitaxial Fi 23 are formed. The N' buried layer 22 is formed by selectively opening an oxide film (not shown) on the P-type St substrate 21 and thermally diffusing n-type impurities (FIG. 2(a)).

Next, the entire surface of the N-type epitaxial layer 23 is covered with a SiO2 film (
Thickness: about 300 to 1000λ) 24, and S i sN
a rf! 4 (thickness: about 300 to 2,000 people) 25.

After that, the resist film of the U groove part that isolates the elements is
The N- film 25 is patterned, the unnecessary 5rxNa film 25 and the SiO2 film 24 are removed by etching, an opening 27 is formed, and the N-type epitaxial layer 2 is etched.
3 is exposed ((b) in the same figure).

Next, by anisotropic dry etching such as RIE, the trench is excavated through the opening 27 through the N-type epitaxial layer 23 and the N2 buried layer until reaching the P-type Si substrate 21, thereby forming a U-groove 28.

Thereafter, the inner wall and bottom of the U-groove are thermally oxidized to form a SiO□ film. Further, ions are implanted into the bottom of the UWt portion 28 to form a channel cut layer 30, and the inner wall and bottom of the U groove are thermally oxidized again to form a Sin.

A film 29 is formed (FIG. 2(C)).

Next, a non-doped poly-Si film 31 is grown over the entire surface of the substrate 21 by low pressure CVD to backfill the U trench 28. Next, the poly-Si film 31 is etched using S I 3N4rPJ25 as a stopper material, and the surface of the substrate 21 is planarized. At this time, the poly-Si film 31 above the U-groove 28 is excessively etched to form a depression, and the upper part of the U-groove 28 is exposed (FIG. 2(d)).

Furthermore, the Si, N, and film 25 on the 5i02 film 24 are removed, and then the poly-Si film 31 in the U groove portion 28 is insulated. Note that the first insulation method is Sin, and CVD is applied to the entire surface of the film 24.
The second insulating method is to form a Sing film 36 with a thickness of about 63,000 oz by CVD method (see figure (fl)). degree definite form 2,
In this method, an insulating film such as a Si3Nm film (not shown) is formed only on the upper part of the U-groove portion 28 ((f 2 ) in the same figure).

The following is the same as the forming process according to the conventional example, so a brief explanation will be provided.

Furthermore, a resist film 33 is patterned on the substrate 21 having the Stow film 32 film shape 2 to open a window for the diffusion layer of the collector load resistor, and using the resist as a mask, the B° ion 34
is injected, and then the resist film 33 is removed. In addition, B
The implantation conditions for 1 ion 34 are 60 KeV and a dose of 1.
．． 0XIO1SC1-'' ((g) in the same figure).

Next, the substrate 21 is heat treated to form P° diffusion N35,
Furthermore, the resist film 36 is patterned, a window for the base diffusion layer is opened, and the B0 ion 3 is formed using the resist as a mask.
7 is injected, and then the resist film 36 is removed (see FIG.
h)).

Next, the resist film 38 is patterned, a window is opened for the cell base, and B ions 39 are implanted into the region where the multi-emitter E is formed, and then the resist film 38 is removed (
Figure (i)).

Next, the substrate 21 is heat treated (N atmosphere, 900° C.) to form a base diffusion layer 40 and a base compensation layer 43.

After that, SiO□ film 24 is coated with Si by CVD method.
A contact window for each electrode is formed on the SiO□11!24.24a through a resist film (not shown) to form an opening (FIG. 6(j)).

Furthermore, the entire surface has a poly-Si film 44 (thickness of 500 to 2000
A shape is formed, and a PSG film 45 is formed on the emitter formation window and the collector formation window through a resist film (not shown).
An emitter diffusion layer 46 and a collector diffusion layer 47 are formed in a self-aligned manner by heat treatment (FIG. 3(k)).Next, the PSG film 45 is removed and aluminum is grown on the poly-Si film 44 by sputtering or the like. Then, unnecessary aluminum growth portions and the poly-Si film 44 are removed by buttering to form an aluminum electrode 48.The aluminum electrode 48 is connected to the collector load resistance extraction electrode Rt and the emitter E.
,,E,, form the base B and collector C (see figure (1)
)).

A semiconductor device is manufactured through these formation steps.

In this way, the bo + JSi embedded in the U groove portion 28
l! The insulation on the upper part of the poly-Si film 31 is not made into Si Ox 11!32 by thermal oxidation treatment of the poly-Si film 31, but by CVD.
The Sing film 32 is formed by the method. Therefore, it is possible to eliminate stress around the U-groove portion 28 due to conventional thermal oxidation treatment.

Thereby, even if the Si substrate 2I is subjected to heat treatment after implanting the ions 34 in the vicinity of the U-groove portion 28 in a subsequent process, it is possible to prevent the generation of dislocation defect portions.

〔Effect of the invention〕

As described above, according to the present invention, the upper part of the polycrystalline semiconductor film backfilled inside the U trench is insulated by the CVD method without thermal oxidation, so that the generation of dislocation defect portions can be eliminated. This makes it possible to improve reliability of transistor characteristics and production yield.

[Brief explanation of the drawing]

FIG. 1 is a process diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of a semiconductor device according to a conventional example, and FIG. This is a process diagram. (Explanation of symbols) 1.21...P-type Si substrate (-conductivity type semiconductor substrate)
, 2.22...N0 buried WJ (buried layer of opposite conductivity type), 3.23...N type epitaxial N (epitaxial layer of opposite conductivity type), 4.12,31.44...Poly St Film (polycrystalline semiconductor II), 5.30...channel force layer, 6.51,24,29.32...Sin, film (oxide film), 7.35...P-type diffusion layer , 8.40...Base diffusion layer, 9.43...Base compensation layer, 10.46...Emitter diffusion layer, 11.47...Collector compensation layer, 13...Dislocation defect portion, 41 .27... opening, 24 a, 52. 25-3 is 04 film (heat-resistant oxidation insulating film), 53 a + 53b, 53c, 26t 33+
36+ 38-...Resist film, 42.28...U groove, 42b...Thermal oxidation part, 61.34, 37.39...B3 ion, 45...
PSG film, 48... Aluminum wiring, Rt... Collector load resistance extraction electrode, Et, Et...
・Emitter, B...Base, C...Collector. Vote 1 Diagram (〒f, 5) Color Color fb) 2/Shiba Toi II te grandson rumor body fold 1ψ shape be=reidan 533
Figure (1 in 1,000)

Claims (1)

[Claims] A step of forming an epitaxial layer (23) on a substrate (21), forming a heat oxidation-resistant first insulating film (25) on the entire surface of the epitaxial layer (23), and then selectively removing the heat oxidation-resistant first insulating film (25) to expose the epitaxial layer (23) and forming an opening (27); A step of forming a U-groove (28) by an anisotropic etching method, and then forming a second insulating film (29) on the surface inside the U-groove (28), and forming a polycrystalline semiconductor in the U-groove (28) a step of forming a film (31) and embedding the U-groove (28) almost flatly; and a step of depositing and forming a third insulating film on the U-groove (28) buried almost flatly. , the first epitaxial layer surrounded by the U groove (28) (
23) A method for manufacturing a semiconductor device, comprising the step of forming an element.