JPH01110274A - Test circuit - Google Patents

Abstract

PURPOSE:To easily test a block to be tested and the peripheral block by a reduced number of addition circuits without generating the mutual effect between said blocks, by supplying input and output signals to a plurality of three- port type FFs constituting a shift register. CONSTITUTION:A shift register 100 is constituted of eight three-port type FFs 101-108 and the output of the circuit block 10A of a front stage is connected to a circuit block 10X difficult in the setting of inherent test data and further connected to the FFs 101-108 of the shift registers 100 through bypasses 110. The output of the circuit block 10X is connected to the respective FFs 101-108. Further, the shift register 100 is connected to the shift registers 80A, 80D of front and rear stages by scanning paths 96, 97. By this constitution, the input and output data of the circuit block 10X of a ROM can be easily observed.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a test circuit suitable for LSI.

゛ [Summary of the Invention] The present invention provides input signals and output signals of a circuit block under test mounted on an LSI to each second and third data input terminal of a plurality of three-port flip-flops constituting a shift register. This is a test circuit that can reduce the number of additional circuits and easily test the circuit block under test and the peripheral circuit blocks without affecting each other.

[Conventional technology]

In large-scale integrated circuits (LSIs), a large number of unit circuits are mounted on the same chip, making it difficult to perform tests to determine whether they are good or bad.

Therefore, the inside of the LSI is divided into multiple circuit blocks,
A block isolation method has been proposed that efficiently tests the entire LSI by externally setting and observing input and output signals for each block. This block isolation method includes one that adds a selector inside the LSI, and one that adds a scan path.

In the block isolation method using selectors, as shown in FIG. 3, selectors (21) to (28) are provided on the input side of the circuit block (10) to be tested, and selectors (21) to (28) are provided on the input side of the circuit block (10) to be tested to isolate the circuit block from other circuit blocks (not shown). Input terminal (31) ~ (
For example, 8-bit normal input data Ao=Av supplied via the test input terminals (41) to (48)
For example, 8-bit unique test data To=Tv supplied via the circuit block ( 10).

The output data corresponding to the unique test data To to T7 of the circuit block (10) is outputted from the AND gates (51) to (58).
) and OR gates (61) to (68) to which output data from other circuit blocks (not shown) are supplied, to output terminals (71) to (78). This output data is compared with a predetermined data pattern to determine whether the circuit block under test (10) is good or bad.

In the block isolation method using scan paths, as shown in Figure 4, multiple (for example, three)
The circuit block (IOA > , (IOB).

(IOC) on the input side of each shift register (80A
) , (80B > , (80C) are provided, and a shift register (800) is provided on the output side of the circuit block (IOC).
0A) is, for example, patent application No. 61-5893 filed by the present applicant.
It is composed of two-port flip-flops (81A) to (88A) as described in No. 1. Other shift registers (80B”), (80C),
(ROD) is similarly configured.

In normal mode, a system clock (not shown) is supplied to each shift register (80A) to (80D), and normal input data AO to A7 from input terminals (31) to (38) are transferred to the shift register (80A). ) is supplied to the circuit block (IOA) through each flip-flop (81A) to (88A) of the circuit block (IOA).
The output of IOA) is supplied to the circuit block (IOB) via each flip-flop (81B'') to (88B) of the shift register (80B).
The output of the circuit block (IOC) is transferred to the shift register (80
0) to output terminals (71) to (78).

In the test mode, test data (not shown) is supplied to each shift register (80A) to (80 ports), and the shift register (80A>
The serial test data TD supplied to the shift register (80B) is sequentially connected in series through scan paths (92), (93) and (94).

(80C), (800), output terminal (95
) is derived.

Thereby, the input/output signals of each circuit block (10^) to (IOC) can be set and observed from the outside, and the quality of the circuit block under test can be determined.

[Problem that the invention seeks to solve]

However, the block isolation method using selectors has the problem of a large amount of wiring and is not applicable when the number of input/output signals of the circuit block under test is greater than the number of terminals of the LSI. there were.

Furthermore, the block isolation method using a scan path has the problem that the circuit scale of the shift registers to be added before and after each circuit block becomes large, resulting in a large amount of hardware.

In view of the above, an object of the present invention is to provide a test circuit that can easily test the relevant circuit block and peripheral circuit blocks without affecting each other with a small number of additional circuits.

[Means for solving problems]

The present invention provides first, second, and third terminals for a circuit block (IOX) having a plurality of input terminals and output terminals, respectively.
Data input terminal D1. A plurality of 3-port flip-flops (101'') having D2 and D3 and first, second and third clock terminals CK1, CK2 and CK3.
10B), the output terminal of the previous stage flip-flop is connected to the first data input terminal of the next stage flip-flop, and each input terminal of the circuit block is connected to the second data input terminal of each flip-flop. , by connecting each output terminal of the circuit block to a third data input terminal of each flip-flop and selectively providing a clock to the first, second, and third clock terminals of each flip-flop. This test circuit obtains input and output signals from the output terminals of the final stage of a plurality of flip-flops.

[Effect]

According to this configuration, the circuit block under test and the peripheral circuit blocks can be easily tested without affecting each other using a small number of additional circuits.

〔Example〕

An embodiment of the test circuit according to the present invention will be described below with reference to FIGS. 1 and 2.

The configuration of one embodiment of the present invention is shown in FIG. In FIG. 1, parts corresponding to those in FIG. 4 are given the same reference numerals and redundant explanation will be omitted.

In FIG. 1, (100) is a shift register, which is composed of a plurality (for example, eight) of three-port flip-flops (101> to (108)) as described later.

Normal input data from the previous stage circuit block (IOA) is supplied to a circuit block (IOX) in which it is difficult to set individual test data, such as a ROM, and is also supplied to a shift register via a bypass (110). (100) are respectively supplied to flip-flops (101) to (10B''). Also, this flip-flop (101)
~(10B) contains circuit blocks that are difficult to test (IO
The output data of each of the flip-flops (101) to (10B) is supplied to the subsequent circuit block (IOC). Furthermore, the shift register (100) is connected to the previous and subsequent shift registers (80A) and (80A) by scan paths (96) and (97).
0D) in series. The rest of the configuration is the same as that shown in FIG. 4 above.

The detailed configuration of the shift register (100) is shown in FIG.

In FIG. 2, a 3-port flip-flop (101
) to (108) are the first, second and third data input terminals D1. D2 and D3, and first, second and third clock terminals CKt, CK2 and CK3.

The output terminal Q of the first stage flip-flop (101) is connected to the first data input terminal D1 of the next stage flip-flop (102), and in the same way, the output terminal of the previous stage flip-flop is connected to the final stage flip-flop. (10B)
is connected to the first data input terminal D1 of.

Each input data of the circuit block (IOX) is connected to the terminal (11) connected to the bypass (110) (see Figure 1).
1)~(118) to each flip-flop (101)~
(10B'), and each output data Xo of the circuit block (IOX) is supplied to the second data input terminal D2 of the circuit block (IOX).
=Xv is supplied from the terminals (121') to (128) to the third data input terminal D3 of each flip-flop (101) to (108), respectively. Each flip-flop (
The output data of 101) to (10B) are respectively output to the terminal (
131) to (138) to subsequent circuit blocks (IOCs)
).

The first, second and third clock terminals CKs, CK2 and CK3 of each flip-flop (101) to (108)
have common terminals (141) and (14
2) and (143) are supplied with three types of clocks: a scan clock SCK, a test clock TCK, and a normal (system) clock NCK.

Terminals (191) and (192) are connected to scan canvases (96) and (97) (see Figure 1), respectively;
The terminal (191) is connected to the first input terminal D1 of the first stage flip-flop (101), and the terminal (192) is connected to the first input terminal D1 of the first stage flip-flop (101).
) is connected to the output terminal of the final stage flip-flop (108).

As described above, for a circuit block under test (IOX) such as a ROM, it is difficult to set unique test data for a subsequent circuit block (IOC). However, the normal input data can be set relatively easily.

The present invention has been made with attention to this point, and the operation of one embodiment thereof is as follows.

In the scan mode, the scan clock SCK from the terminal (141) is commonly supplied to each first clock terminal CK1, and the flip-flops (101) to (1
0B) respectively operate as a D flip-flop for the data supplied to the first input terminal D1. As a result, the flip-flops (101'') to (10B) are connected to a shift register, and data from the input terminal (191) is transferred to each flip-flop (101) to (10B) and taken out from the output terminal (192). .

Therefore, in the scan mode, the values of each flip-flop (101) to (10B) can be arbitrarily set from the terminal (191), and each value can be set to the terminal (191).
It can be observed from 2).

In the test mode, the test clock TCK from the terminal (142) is commonly supplied to each of the second clock terminals CK2, and the flip-flops (101) to (10B
) each operate as a D flip-flop for the data supplied to the second input terminal D2. As a result, the flip-flops (101'') to (10B) are connected to the circuit block (IOX) from the terminals (111) to (118).
Input data Ao to A7 are taken in.

After that, switch to scan mode and the terminal (19
2) to the circuit block (IOX) input data Ao”/
'v can be observed.

In normal mode, the system clock NCK from the terminal (143) is commonly supplied to each third clock terminal CK3, and the flip-flops (101) to (1
0B) each operate as a D flip-flop for the data supplied to the third input terminal D3. As a result, flip-flops (101) to (108) are connected to circuit blocks (IOX) from terminals (121) to (128).
) output data Xo''Xv is taken in.

After that, switch to scan mode and the terminal (19
2) to the output data of the circuit block (IOX)
v can be observed.

That is, in this embodiment, one set of shift registers (1
00) 3-port flip-flop knob (101) ~ (
108') to scan mode, test mode, and normal mode, the circuit block (IO
Observation of the input and output signals of Then, the circuit block (I
OX) and peripheral circuit blocks (IOC) can be easily tested without being influenced by each other.

〔Effect of the invention〕

As described in detail above, according to the present invention, the input of the circuit block under test mounted on the LSI is input to each of the second and third data input terminals of the plurality of three-port flip-flops constituting the shift register. Since the signal and the output signal are supplied respectively, a test circuit can be obtained which can easily test the circuit block under test and the peripheral circuit blocks without affecting each other while reducing the number of additional circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of a test circuit according to the present invention, FIG. 2 is a block diagram showing the configuration of main parts of an embodiment of the present invention, and FIG. 3 is a configuration of a conventional test circuit. FIG. 4 is a block diagram showing another example of the configuration of a conventional test circuit. (10), (IOA'), (IOB)
, (IOC). (IOX') is a circuit block, (101) ~ (10
B) is a 3-port flip-flop, Dl, D2. D
3 is a first, second, and third data input terminal, CK 1 . CK2. CK3 is the first, second, and third clock input terminals.

Claims (1)

[Claims] For a circuit block having a plurality of input terminals and output terminals, first, second and third data input terminals and first, second and third data input terminals respectively.
A plurality of three-port flip-flops having second and third clock terminals are arranged, and the output terminal of the previous-stage flip-flop is connected to the first data input terminal of the next-stage flip-flop. Each input terminal is connected to a second data input terminal of each of the flip-flops, each output terminal of the circuit block is connected to a third data input terminal of each of the flip-flops; The input signal and the output signal of the circuit block are obtained from the output terminal of the final stage of the plurality of flip-flops by selectively supplying a clock to the second and third clock terminals. Test circuit.