JP7529000B2 - Manufacturing method of laminated wafer - Google Patents

Description

The present invention relates to a method for manufacturing a laminated wafer.

Conventionally, it has been proposed to form a polycrystalline silicon film as a carrier trap layer on the surface of a single crystal silicon wafer in order to trap and eliminate carriers generated during high frequency operation (see, for example, Patent Documents 1 and 2).

JP 2015-211061 A JP 2021-190660 A

Japanese Patent Application Laid-Open No. 2003-233633 and Japanese Patent Application Laid-Open No. 2003-233634 disclose that warpage of a single crystal silicon wafer can be reduced by setting the film formation temperature during film formation of a polycrystalline silicon film in two stages.
However, although the techniques of Patent Documents 1 and 2 are effective as warpage reduction techniques, there is a demand for further warpage reduction. For example, in a single crystal silicon wafer having a diameter of 300 mm, the amount of warpage increases significantly, and therefore, there is a demand for further warpage improvement techniques.

An object of the present invention is to provide a method for manufacturing laminated wafers that can reduce warpage of the laminated wafers.

The method for manufacturing a laminated wafer of the present invention is a method for manufacturing a laminated wafer in which a polycrystalline silicon film is formed on a single crystal silicon wafer, and in this method, a polycrystalline silicon film is formed on an oxide film formed on the surface of the single crystal silicon wafer in a mixed atmosphere of hydrogen gas and a raw material source gas, and the single crystal silicon wafer on which the polycrystalline silicon film is formed is subjected to a heat treatment at 1000°C to 1300°C for 10 seconds to 180 seconds in a hydrogen gas atmosphere.

In the method for manufacturing a laminated wafer of the present invention, it is preferable that the heat treatment is performed after the polycrystalline silicon film is formed in the same vapor phase growth apparatus.

In the method for manufacturing a laminated wafer described in the present invention, it is preferable that the raw material source gas is trichlorosilane gas, and the content of the trichlorosilane gas relative to the hydrogen gas in the mixed atmosphere is 3% or more and 20% or less.

The method for manufacturing a laminated wafer of the present invention is a method for manufacturing a laminated wafer in which a polycrystalline silicon film is formed on the surface of a single crystal silicon wafer, and a polycrystalline silicon film is formed on an oxide film formed on the surface of the single crystal silicon wafer in a mixed atmosphere in which the content of trichlorosilane gas relative to hydrogen gas is 3% or more and 20% or less.

In the method for manufacturing a laminated wafer of the present invention, when forming the polycrystalline silicon film, it is preferable to grow a first polycrystalline silicon film on the oxide film at a temperature of 890°C or more and 900°C or less, and then grow a second polycrystalline silicon film on the first polycrystalline silicon film at a temperature of 1000°C or more and 1075°C or less.

The laminated wafer of the present invention is a laminated wafer in which a polycrystalline silicon film having a thickness of 0.3 μm or more and 3.0 μm or less is formed on a single crystal silicon wafer having a diameter of 300 mm, and the Warp-bf value is 40 μm or less.

In the laminated wafer of the present invention, it is preferable that the surface roughness RMS of the polycrystalline silicon film is 0.1 nm or more and 0.15 nm or less.

3 is a flowchart showing a method for manufacturing a bonded wafer according to the first embodiment. 2A to 2C are process diagrams showing a method for manufacturing a bonded wafer according to the first embodiment. 10 is a flowchart showing a method for manufacturing a bonded wafer according to a second embodiment. 10A to 10C are process diagrams showing a method for manufacturing a bonded wafer according to a second embodiment. 1 is a graph showing the relationship between the first and second TCS contents, heat treatment time, and Warp-bf value according to an embodiment.

[Embodiment]
Hereinafter, an embodiment of the present invention will be described. In this embodiment, a method for manufacturing a bonding wafer including a laminated wafer of the present invention will be described.

First Embodiment
First, a first embodiment of the present invention will be described.
Fig. 1 is a flowchart showing a method for manufacturing a bonded wafer according to the first embodiment. Fig. 2 is a process chart showing the method for manufacturing a bonded wafer according to the first embodiment.

As shown in Figures 1 and 2, the method for manufacturing the bonded wafer 30 according to the first embodiment includes steps S11 to S14 for manufacturing the active layer substrate 10, steps S21 to S26 for manufacturing the laminated wafer 20, and steps S31 to S33 for manufacturing the bonded wafer 30 by bonding the active layer substrate 10 and the laminated wafer 20.

The process for manufacturing the active layer substrate includes an active layer substrate main body preparation process S11, an insulating film formation process S12, an ion implantation layer formation process S13, and a pre-bonding cleaning process S14.

In the active layer substrate main body preparation step S11, an active layer substrate main body 11, which is a single crystal silicon wafer, is prepared.
In the insulating film forming step S12, the insulating film 12 (oxide film) is formed so as to cover the entire active layer substrate body 11 by, for example, thermal oxidation or CVD.
In the ion-implanted layer forming step S13, hydrogen ions or rare gas ions are implanted from above the insulating film 12 by an ion implanter to form an ion-implanted layer 13 in the active layer substrate main body 11.
In the pre-bonding cleaning step S14, pre-bonding cleaning is performed to remove particles on the bonding surface of the active layer substrate body 11.
Through the above steps, the active layer substrate 10 for the bonded wafer is manufactured.

The process for manufacturing the laminated wafer 20 includes a single crystal silicon wafer preparation process S21, an oxide film formation process S22, a polycrystalline silicon film formation process S23, a heat treatment process S24, a polishing process S25, and a pre-bonding cleaning process S26.

In the single crystal silicon wafer preparation step S21, a single crystal silicon wafer 21 is prepared. The diameter of the single crystal silicon wafer 21 is not particularly limited, but may be, for example, 200 mm, 300 mm, or 450 mm. The resistivity of the single crystal silicon wafer 21 is preferably 100 Ω·cm or more and 50,000 Ω·cm or less. As the single crystal silicon wafer 21, for example, a single crystal silicon ingot grown by the Czochralski method (CZ method) or the floating zone melting method (FZ method) may be sliced with a wire saw or the like.

In the oxide film forming step S22, an oxide film 22 (base oxide film) is formed on the surface of the single crystal silicon wafer 21. The thickness of the oxide film 22 is preferably, for example, 0.3 nm or more and 10 nm or less. By making the oxide film 22 thin, it is possible to reduce the influence on the characteristics of the RF device caused by the oxide film 22 being interposed between the single crystal silicon wafer 21 and a polycrystalline silicon film 23 described later.
The oxide film 22 can be formed by wet cleaning such as alkaline cleaning (SC1 cleaning) or acid cleaning ( _SC2 cleaning). The method of forming the oxide film 22 is not limited to wet cleaning, and thermal oxidation in an oxidizing atmosphere or oxidation heat treatment using a rapid heating/rapid cooling device can also be applied.

In the polycrystalline silicon film formation step S23, in a vapor phase growth apparatus 1 having a mixed atmosphere of hydrogen gas (carrier gas) and raw material source gas, a polycrystalline silicon film 23 is formed on an oxide film 22 formed on a surface of a single crystal silicon wafer 21. The thickness of the polycrystalline silicon film 23 is preferably more than 0.3 μm and not more than 3.0 μm.
The polycrystalline silicon film forming step S23 includes a first growth step S231 of growing a first polycrystalline silicon film 231 on the oxide film 22, and a second growth step S232 of growing a second polycrystalline silicon film 232 on the first polycrystalline silicon film 231.

In the first growth step S231, a first polycrystalline silicon film 231 is grown on the oxide film 22 in the vapor phase growth apparatus 1 in a mixed atmosphere of hydrogen gas and a source gas at a first growth temperature.
The first growth temperature is preferably 890° C. or higher and 900° C. or lower.
As the raw material source gas used in the first growth step S231 and the second growth step S232, trichlorosilane gas (SiHCl ₃ ) or dichlorosilane (SiH ₂ Cl ₂ ) gas can be used, with trichlorosilane gas being particularly preferred.
When trichlorosilane gas is used as the raw material source gas, the content of trichlorosilane gas relative to hydrogen gas in the mixed atmosphere (hereinafter, sometimes referred to as the "first TCS content") is preferably 3% or more and 20% or less, and more preferably 5% or more and 15% or less.

In the second growth step S232 performed after the first growth step S231, a second polycrystalline silicon film 232 is grown on the first polycrystalline silicon film 231 in the vapor phase growth apparatus 1 at a second growth temperature in a mixed atmosphere of hydrogen gas and raw material source gas.
The second polycrystalline silicon film 232 is preferably thicker than the first polycrystalline silicon film 231. The second growth temperature is preferably 1000° C. or higher and 1075° C. or lower, and more preferably 1050° C. or higher and 1075° C. or lower.
The raw material source gas is preferably trichlorosilane gas.
When trichlorosilane gas is used as the raw material source gas, the content of trichlorosilane gas relative to hydrogen gas in the mixed atmosphere (hereinafter, sometimes referred to as the "second TCS content") is preferably 3% to 20%, more preferably 5% to 15%. The second TCS content may be the same as or different from the first TCS content.

By forming the oxide film 22 in advance between the surface of the single crystal silicon wafer 21 and the polycrystalline silicon film 23 and setting the first growth temperature in the first growth step S231 to 890° C. or higher and 900° C. or lower in the subsequent step, it is possible to prevent the polycrystalline silicon film 23 from becoming single crystallized due to the loss of a part of the oxide film 22. It is also possible to reduce warpage after the polishing step S25.
In the second growth step S232, the second growth temperature is set to 1000° C. or higher and 1075° C. or lower to grow the second polycrystalline silicon film 232 thicker than the first polycrystalline silicon film 231, thereby forming the polycrystalline silicon film 23 quickly and efficiently to a sufficient thickness while reducing warpage of the laminated wafers 20. Moreover, by setting the second growth temperature to 1050° C. or higher, the warpage of the laminated wafers 20 can be further reduced.

By setting the first growth temperature and the second growth temperature as described above, the warping of the laminated wafer 20 can be reduced, but by setting the first TCS content in the first growth process S231 and the second TCS content in the second growth process S232 to 20% or less, respectively, the warping of the laminated wafer 20 can be further reduced.
The inventors have speculated that the reason for this is as follows: When the polycrystalline silicon film 23 is formed on the single crystal silicon wafer 21, an internal stress that causes warping of the laminated wafer 20 occurs due to the difference in thermal expansion coefficient between the single crystal silicon wafer 21 and the polycrystalline silicon film 23. The internal stress generated by the thermal expansion is subsequently reduced the longer the time held at a high growth temperature. For this reason, it is considered that the faster the growth rate is, the shorter the growth time required to obtain a polycrystalline silicon film of a predetermined thickness is, so the time held at a high growth temperature is reduced, and the amount of reduction in the internal stress is reduced.
When the first TCS content or the second TCS content exceeds 20%, the growth rate of the first polycrystalline silicon film 231 or the second polycrystalline silicon film 232 becomes too fast, which reduces the amount of reduction in internal stress and reduces the effect of reducing warpage of the laminated wafer 20. On the other hand, when the first TCS content or the second TCS content is 20% or less, it is possible to suppress the decrease in the amount of reduction in internal stress corresponding to the growth rate of the first polycrystalline silicon film 231 or the second polycrystalline silicon film 232, and it is estimated that the warpage of the laminated wafer 20 can be further reduced.

In addition, by setting the first TCS content and the second TCS content to 3% or more, respectively, it is possible to prevent the growth rate of the first polycrystalline silicon film 231 or the second polycrystalline silicon film 232 from becoming too slow, and to prevent a decrease in the productivity of the laminated wafer 20.

In the heat treatment step S24, the single crystal silicon wafer 21 on which the polycrystalline silicon film 23 has been formed is subjected to a heat treatment in a hydrogen gas atmosphere at 1000°C to 1300°C for 10 seconds to 180 seconds. In the first embodiment, the heat treatment step S24 is performed subsequent to the polycrystalline silicon film formation step S23 in the vapor phase growth apparatus 1 in which the polycrystalline silicon film formation step S23 has been performed.

In the polycrystalline silicon film formation step S23, by setting the first growth temperature and the second growth temperature as described above, or by setting the first TCS content and the second TCS content as described above, the warpage of the laminated wafers 20 can be reduced, but by performing the heat treatment step S24 subsequent to the polycrystalline silicon film formation step S23, the warpage of the laminated wafers 20 can be further reduced.
The present inventors have presumed that the reason for this is as follows: When the heat treatment step S24 is performed, the portion of the polycrystalline silicon film 23 on the side of the single crystal silicon wafer 21 is single crystallized, and the single crystallization relieves the internal stress. It has been presumed that the warpage of the laminated wafer 20 is reduced by the relaxation of the internal stress.

Furthermore, if the heat treatment temperature is less than 1000° C. or the heat treatment time is less than 10 seconds, the portion of the polycrystalline silicon film 23 on the side of the single crystal silicon wafer 21 will not be sufficiently crystallized, and internal stress will not be sufficiently relaxed, which may reduce the effect of reducing the warpage of the laminated wafer 20.
Furthermore, if the heat treatment temperature exceeds 1000° C., the thermal load on the vapor phase growth apparatus 1 will be large, and there is a risk of the vapor phase growth apparatus 1 breaking down or otherwise failing.
Furthermore, if the heat treatment time exceeds 180 seconds, the polycrystalline silicon film 23 may be excessively monocrystalline, and the carrier trapping effect of the polycrystalline silicon film 23 may be reduced.
In the first embodiment, by performing the heat treatment step S24 at the heat treatment temperature and for the heat treatment time as described above, it is possible to reduce the warping of the laminated wafer 20 without causing any malfunction such as a breakdown of the vapor phase growth apparatus 1 and without reducing the carrier trapping effect of the polycrystalline silicon film 23.

In particular, in the first embodiment, the heat treatment step S24 is performed following the polycrystalline silicon film formation step S23 in the same vapor phase growth apparatus 1. Therefore, the heat treatment step S24 can be performed after the polycrystalline silicon film formation step S23 without lowering the temperature of the single crystal silicon wafer 21, so that the heat treatment time required to reduce the warpage of the laminated wafers 20 can be prevented from becoming long, and a decrease in the productivity of the laminated wafers 20 can be prevented. In addition, there is no need to install a device separate from the vapor phase growth apparatus 1 to perform the heat treatment step S24.

In the polishing step S25, the surface of the polycrystalline silicon film 23 (second polycrystalline silicon film 232) formed on the single crystal silicon wafer 21 is polished and flattened. In the polishing step S25, it is preferable to perform polishing so that the surface roughness RMS (Root Mean Square) of the polycrystalline silicon film 23 is 0.1 nm or more and 0.15 nm or less. By making the surface roughness RMS of the polycrystalline silicon film 23 0.15 nm or less, the occurrence of blister defects in the bonded wafer 30 can be suppressed.
The surface roughness RMS is calculated based on values measured in a measurement range of 10 μm×10 μm square using, for example, an atomic force microscope (AFM).
The polishing stock removal in the polishing step S25 is not particularly limited, but from the viewpoint of reducing the surface roughness RMS detected on the surface of the polycrystalline silicon film 23, it is preferable to set it to 0.2 μm or more.

By carrying out the above-mentioned steps S21 to S25 on a single crystal silicon wafer 21 having a diameter of 300 mm, a laminated wafer 20 can be manufactured in which a polycrystalline silicon film 23 having a thickness of 0.3 μm or more and 3.0 μm or less is formed on a single crystal silicon wafer 21 having a diameter of 300 mm, and the laminated wafer 20 has reduced warpage with a Warp-bf value of 40 μm or less. The laminated wafer 20 manufactured in this manner has a polycrystalline silicon film 23 having a thickness of 0.3 μm or more, and therefore can exert a sufficient carrier trap effect. In addition, the laminated wafer 20 has a polycrystalline silicon film 23 having a thickness of 3.0 μm or less, and therefore can suppress the warpage from becoming large.
The Warp-bf value can be measured using an optical interference type flatness measuring device (KLA Corp.: Wafer Sight 2).

In the pre-bonding cleaning step S26, particles on the polished surface of the polycrystalline silicon film 23 are removed.
Through the above steps S21 to S26, the laminated wafer 20 for the bonded wafer is manufactured. Note that steps S11 to S14 and steps S21 to S26 can be carried out in parallel.

Next, a process of manufacturing the bonded wafer 30 by bonding the active layer substrate 10 and the laminated wafer 20 together will be described.
The process for manufacturing the bonded wafer 30 includes a bonding step S31, a delamination heat treatment step S32, and a bonding heat treatment step S33.

In the bonding step S31, the polished surface of the polycrystalline silicon film 23 of the laminated wafer 20 is bonded to the active layer substrate 10 via the insulating film 12. At this time, the active layer substrate 10 is bonded such that the implantation surface of the active layer substrate 10 faces the polycrystalline silicon film 23.
In the delamination heat treatment step S32, a heat treatment (delamination heat treatment) is performed to generate a microbubble layer in the ion-implanted layer 13, and delamination is performed at the generated microbubble layer. In this way, a bonded wafer 30 in which the insulating film 12 and the active layer 31 are formed on the active layer substrate 10 is manufactured. At this time, a delamination wafer 40 having a delamination surface 41 is formed.
In the bonding heat treatment step S33, the bonded wafer 30 is subjected to a bonding heat treatment to increase the bonding strength at the bonding interface.
Through the above steps S31 to S33, the bonded wafer 30 is completed.

Second Embodiment
Next, a second embodiment of the present invention will be described. Note that the same components or steps in the second embodiment as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be simplified or omitted.
Fig. 3 is a flow chart showing the method for manufacturing a bonded wafer according to the second embodiment. Fig. 4 is a process chart showing the method for manufacturing a bonded wafer according to the second embodiment.

As shown in Figures 3 and 4, the method for manufacturing the bonded wafer 30 according to the second embodiment includes the same steps as those of the first embodiment, except that the process for manufacturing the laminated wafer 20 does not include the heat treatment step S24.

As described in the first embodiment, by setting the first growth temperature in the first growth step S231 and the second growth temperature in the second growth step S232 as described above, it is possible to reduce the warpage of the laminated wafers 20. However, even if the heat treatment step S24 is not performed, it is possible to further reduce the warpage of the laminated wafers 20 by setting the first TCS content and the second TCS content to 20% or less, respectively.
In particular, by setting the first TCS content and the second TCS content to 15% or less, respectively, for a single crystal silicon wafer 21 having a diameter of 300 mm, it is possible to manufacture a laminated wafer 20 in which a polycrystalline silicon film 23 having a thickness of 0.3 μm or more and 3.0 μm or less is formed on a single crystal silicon wafer 21 having a diameter of 300 mm, and in which warpage is reduced and the Warp-bf value is 60 μm or less.

In addition, as described in the first embodiment, by setting the first TCS content and the second TCS content to 3% or more, respectively, it is possible to suppress a decrease in productivity of the laminated wafer 20.

Furthermore, as described in the first embodiment, in the polishing step S25, the surface roughness RMS of the polycrystalline silicon film 23 is set to 0.15 nm or less, thereby suppressing the occurrence of blister defects in the bonded wafer 30.

[Modification]
Although an embodiment of the present invention has been described in detail above with reference to the drawings, the specific configuration is not limited to this embodiment, and various improvements and design changes that do not deviate from the gist of the present invention are also included in the present invention.

In the first embodiment, the heat treatment step S24 may be performed in an apparatus other than the vapor phase growth apparatus 1.

In the first embodiment, at least one of the first TCS content in the first growth step S231 and the second TCS content in the second growth step S232 may be less than 3% or more than 20%. Even if at least one of the TCS contents exceeds 20%, the warpage of the laminated wafer 20 can be reduced by performing the heat treatment step S24.

In the first and second embodiments, the polycrystalline silicon film 23 is formed at two growth temperatures (first and second growth temperatures), but the polycrystalline silicon film 23 may be formed at one or three or more growth temperatures.

Next, examples of the present invention will be described. Note that the present invention is not limited to these examples.

[Configuration of evaluation sample]
Example 1
A single crystal silicon wafer having a diameter of 300 mm, a resistivity of 3000 Ω·cm, and a crystal orientation of <100> was prepared, and the steps S22 to S25 of the first embodiment were performed on the single crystal silicon wafer to produce the laminated wafer of Example 1. The conditions for each step were as follows. In the polishing step S25, polishing was performed by a chemical mechanical polishing (CMP) method.
・Oxide film forming step S22
Oxide film thickness: 5 Å (5×10 ⁻¹⁰ m)
Polycrystalline silicon film formation process S23
Carrier gas: hydrogen gas Raw material source gas: trichlorosilane gas First growth step S231
First TCS content: 5%
First growth temperature: 890℃
Thickness of the first polycrystalline silicon film: 0.3 μm
・Second growth step S232
Second TCS content: 5%
Second growth temperature: 1050℃
Thickness of the second polycrystalline silicon film: 2.7 μm
Heat treatment step S24
Carrier gas: hydrogen gas Heat treatment temperature: 1070°C
Heat treatment time: 180 seconds Polishing step S25
Thickness of polycrystalline silicon film after polishing: 2.15 μm
Surface roughness RMS after polishing: 0.15 nm

<Examples 2 and 3>
As shown in Table 1 below, laminated wafers of Examples 2 and 3 were manufactured under the same conditions as Example 1, except that the first and second TCS contents in the first and second growth steps S231 and S232 were set to 10% and 15%, respectively.

<Examples 4, 5, and 6>
The laminated wafers of Examples 4, 5, and 6 were manufactured under the same conditions as Examples 1, 2, and 3, except that the heat treatment time in the heat treatment step S24 was set to 10 seconds.

<Examples 7, 8, and 9>
Except for not performing the heat treatment step S24, the laminated wafers of Examples 7, 8, and 9 were manufactured under the same conditions as Examples 1, 2, and 3. That is, the laminated wafers of Examples 7, 8, and 9 were manufactured by performing steps S22, S23, and S25 of the second embodiment.

[evaluation]
<Relationship between the first and second TCS contents and heat treatment time and warpage>
The Warp-bf values of the laminated wafers of Examples 1 to 9 were measured using an optical interference type flatness measuring device (KLA Corp.: Wafer Sight 2). Then, the relationship between the heat treatment time and the Warp-bf value was evaluated when the first and second TCS contents were 5%, 10%, and 15%. The results are shown in FIG.

As shown in FIG. 5, it was confirmed that the lower the first and second TCS contents are or the longer the heat treatment time is, the lower the Warp-bf value is, that is, the smaller the warpage of the laminated wafer is.
Furthermore, it was confirmed that if the first and second TCS contents are 15% or less, it is possible to manufacture laminated wafers with reduced warpage, that is, a Warp-bf value of 60 μm or less, regardless of whether or not heat treatment is performed for 180 seconds or less.
In particular, it was confirmed that when the first and second TCS contents are 5%, laminated wafers with reduced warpage and a Warp-bf value of 40 μm or less can be manufactured regardless of whether or not heat treatment is performed for 180 seconds or less.
It was also confirmed that if the heat treatment time was 180 seconds, the Warp-bf value was approximately 25 μm, and the amount of warpage of the laminated wafers was approximately the same, regardless of the first and second TCS contents.
In addition, when the first and second TCS contents are 10%, heat treatment is performed for about 80 seconds or more, and when the first and second TCS contents are 15%, heat treatment is performed for about 110 seconds or more, so that it is estimated that a laminated wafer with reduced warpage and a Warp-bf value of 40 μm or less can be manufactured.

In this embodiment, a polycrystalline silicon film is formed at two growth temperatures (first growth temperature and second growth temperature). However, as described above, the lower the first and second TCS contents are, or the longer the heat treatment time is, the smaller the warpage of the laminated wafers. Therefore, even when a polycrystalline silicon film is formed at a single growth temperature, it can be estimated that the lower the first and second TCS contents are, or the longer the heat treatment time is, the smaller the warpage of the laminated wafers is.

1... vapor phase growth apparatus, 20... stacked wafer, 21... single crystal silicon wafer, 22... oxide film, 23... polycrystalline silicon film, 231... first polycrystalline silicon film, 232... second polycrystalline silicon film.

Claims (2)

A method for manufacturing a laminated wafer in which a polycrystalline silicon film is formed on a single crystal silicon wafer having a diameter of 300 mm, comprising the steps of:
forming a polycrystalline silicon film having a thickness of 0.3 μm or more and 3.0 μm or less on an oxide film formed on a surface of the single crystal silicon wafer in a mixed atmosphere in which the content of trichlorosilane gas relative to hydrogen gas is 3% or more and 20% or less ;
The method for producing a laminated wafer includes subjecting the single crystal silicon wafer having the polycrystalline silicon film formed thereon to a heat treatment at 1000° C. or higher and 1300° C. or lower for 10 seconds or higher and 180 seconds or lower in a hydrogen gas atmosphere to obtain a laminated wafer having a Warp-bf value of 40 μm or lower . 2. The method for manufacturing a laminated wafer according to claim 1 ,
When forming the polycrystalline silicon film,
A method for manufacturing a laminated wafer, comprising growing a first polycrystalline silicon film on the oxide film at a temperature of 890°C or more and 900°C or less, and then growing a second polycrystalline silicon film on the first polycrystalline silicon film at a temperature of 1000°C or more and 1075°C or less.

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