JP7065928B2 - Storage system and its control method - Google Patents

Description

The present invention relates to a storage system.

A storage system generally comprises one or more storage devices. Each of the one or more storage devices generally includes, for example, an HDD (Hard Disk Drive) or an SSD (Solid State Drive) as a storage device. The storage system is accessed from one or more higher-level devices (for example, a host computer) via a network such as a SAN (Storage Area Network) or a LAN (Local Area Network). In general, a storage device has improved reliability by using a high reliability method according to a RAID (Redundant Array of Independent (or Inexpensive) Disks) technique.

Patent Document 1 discloses an information system capable of compressing data while maintaining the data writing speed from a host computer. According to Patent Document 1, a first volume that accepts data writing from a host computer in a storage device and a second volume that compresses and manages data on the first volume are provided. When the data writing from the host computer to the first volume is completed, the storage device returns a response to the host computer assuming that the writing process is completed. After that, the storage device compresses the data and stores it in the second volume at a timing asynchronous with the data writing from the host computer.

Non-Patent Document 1 discloses a method of achieving both response and throughput by switching the processing trigger according to the operating rate of the storage device for the deduplication processing that combines the duplicated data written from the host computer into one. Has been done.

For example, Non-Patent Document 1 states that "characteristics related to IOPS and latency differ depending on the method, and by using these properly, low latency of the dedup-back method and high IOPS of the dedup-through method can be realized. In this paper, in addition to the conventional dedup-through method that performs deduplication synchronously, the dedup-back method that performs deduplication asynchronously is compared and dedup. The high IOPS performance of the -through method and the high latency due to the overhead of synchronous deduplication processing, the low latency of the dedup-back method and the decrease in IOPS due to the increase in tail latency are clarified, and the combination of these two methods is high. We proposed a hybrid method that aims to achieve both IOPS and low latency. "

That is, according to Non-Patent Document 1, when the operating rate of the storage device is low, the response time is shortened by performing the deduplication processing after the data writing from the host computer is completed, and when the operating rate is high, the data is recorded. Deduplication processing is performed at the same time as writing.

US Patent Application Publication No. 2009/01444996

Jun Kato, Hiroki Otsuji, Kosuke Suzuki, Mitsuru Sato, Eiji Yoshida: "Speeding up writing in in-memory deduplication", Research Report Computer System Symposium, November 28, 2016, p. 51-59

In order to protect data according to the RAID technique in data writing, it is necessary to collect the amount of data (parity cycle) required for redundancy. Since it is necessary to protect the data on the cache memory until the data for the parity cycle is collected, the data on the cache memory is duplicated. This is also done for the data written from the host computer and the compressed data. In such a case, the maximum speed of data writing is limited by the amount of cache access due to data reading and duplication.

As a method of reducing the amount of cache access, a method of omitting the process of duplicating the data before compression by compressing the data in synchronization with the writing can be considered. However, in order to return the processing completion response to the host computer, it is necessary to duplicate the compressed data, so the response speed slows down by the time of the compression processing.

Such a problem is not limited to the storage system having a compression function, but may also be a storage system having another data amount reduction function such as deduplication, and a storage system performing encryption or redundancy.

A typical example of the present invention for solving at least one of the above problems is as follows. That is, a storage system including a first storage control unit, a second storage control unit, and a storage drive connected to at least the first storage control unit and having a non-volatile storage medium. The first storage control unit has a first cache area for storing data and a first buffer area for storing data, and the second storage control unit stores data, respectively. It has a second cache area and a second buffer area for storing data, and the first storage control unit uses the data stored in the first cache area as the second data. It is also stored in the cache area to perform duplication, and when the first storage control unit receives a data write command from the host computer, the data subject to the write command is stored in the first storage. The data stored in the first cache area of the control unit is stored in the first cache area, and the data stored in the first cache area is stored in the second cache area of the second storage control unit to perform duplication. When completed, a response indicating the end of writing the data is transmitted to the host computer, and the first storage control unit is duplicated stored in any of the cache areas subject to the write command. Of the data, the data stored in the storage drive is not stored in the first cache area by performing compression processing on the data subject to the write instruction read from the cache area, but the first buffer. The data stored in the area, the parity is generated based on the data stored in the first buffer area by the compression process, and the data is stored in the first buffer area, and the data stored in the first buffer area. It is characterized in that the parity is read out and transmitted to the storage drive for storage.

According to one aspect of the present invention, the duplication process of the compressed data is omitted by collectively performing the process from the compression process to the storage in the storage device. By eliminating the need for duplication of compressed data, the amount of cache access can be reduced and the maximum speed of data writing can be improved. In addition, by retaining the uncompressed data in the cache memory until the storage of the compressed data in the storage device is completed, the data can be stored even if a device failure occurs during processing such as compression processing or storage in the storage device. Can be protected.

Issues, configurations and effects other than those described above will be clarified by the description of the following embodiments.

It is explanatory drawing which shows the data write procedure with data compression processing performed by the storage system of Example 1 of this invention. It is a block diagram which shows the structure of the storage apparatus of Example 1 of this invention. It is explanatory drawing which shows the configuration example of the VOL management table held by the storage apparatus of Example 1 of this invention. It is explanatory drawing which shows the configuration example of the pool composition management table held by the storage apparatus of Example 1 of this invention. It is explanatory drawing which shows the configuration example of the RAID configuration management table held by the storage apparatus of Example 1 of this invention. It is explanatory drawing which shows the configuration example of the pool allocation management table held by the storage apparatus of Example 1 of this invention. It is explanatory drawing which shows the configuration example of the drive allocation management table held by the storage apparatus of Example 1 of this invention. It is explanatory drawing which shows the structural example of the logical storage hierarchy managed by the storage apparatus of Embodiment 1 of this invention. It is explanatory drawing which shows the configuration example of the memory allocation management table held by the storage apparatus of Example 1 of this invention. It is a figure which shows the configuration example of the memory allocation in the storage apparatus of Example 1 of this invention. It is a flowchart which shows the read process which the storage apparatus of Embodiment 1 of this invention performs. It is a flowchart which shows the write process which performs the storage apparatus of Embodiment 1 of this invention. It is a flowchart which shows the destaging process which performs the storage apparatus of Embodiment 1 of this invention. It is a flowchart which shows the destaging process which changed the exclusion procedure, which is executed by the storage apparatus of Embodiment 1 of this invention.

In the following description, the "interface unit" may include at least one of a user interface unit and a communication interface unit. The user interface unit includes at least one I / O device of one or more I / O devices (for example, an input device (for example, a keyboard and a pointing device) and an output device (for example, a display device)) and a display computer. good. The communication interface unit may include one or more communication interface devices. One or more communication interface devices may be one or more communication interface devices of the same type (for example, one or more NICs (Network Interface Cards)) or two or more different types of communication interface devices (for example, NIC and HBA (Host Bus)). Adapter)) may be used.

Further, in the following description, the "memory unit" includes one or more memories. The at least one memory may be a volatile memory or a non-volatile memory. The memory unit is mainly used during processing by the processor unit.

Further, in the following description, the "processor unit" includes one or more processors. The at least one processor is typically a CPU (Central Processing Unit). The processor may include hardware circuits that perform some or all of the processing.

Further, in the following description, the information may be described by an expression such as "xxx table", but the information may be expressed by any data structure. That is, the "xxx table" can be referred to as "xxx information" in order to show that the information does not depend on the data structure. Further, in the following description, the configuration of each table is an example, and one table may be divided into two or more tables, or all or a part of two or more tables may be one table. good.

Further, in the following description, when the same type of element is not distinguished, the common code among the reference codes is used, and when the same type of element is distinguished, the reference code (or the element ID (for example, identification) is used. (Number) may be used. For example, when a plurality of storage controllers are not distinguished, it is described as "storage controller 22", and when each storage controller is distinguished, "storage controller 1-22A" and "storage controller" are used. It is described as "2_22B". Other elements (for example, cache area 203, buffer area 202, addresses 1100, 1101, 1104, etc.) are also described in the same manner.

Further, in the following description, the "storage system" includes one or more storage devices. The at least one storage device may be a general-purpose physical calculator. Further, at least one storage device may be a virtual storage device, or SDx (Software-Defined anything) may be executed. As SDx, for example, SDS (Software Defined Storage) (an example of a virtual storage device) or SDDC (Software-defined Datacenter) can be adopted.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Hereinafter, Example 1 of the present invention will be described.

<Procedure for storing compressed data in a storage device>
FIG. 1 is an explanatory diagram showing a data writing procedure accompanied by a data compression process executed by the storage system 100 of the first embodiment of the present invention.

The storage system 100 includes a host computer 30 and a storage device 11. The host computer 30 is connected to the storage device 11 via the network 31 and is managed by a management computer (not shown). The storage device 11 has one or more volumes (logical storage areas). The host computer 30 may be a physical computer or a virtual computer executed by the physical computer. The host computer 30 may be a virtual computer executed in the storage system.

Data is written from the host computer 30 to the storage controller 1_22A or the storage controller 2_22B of the storage device 11. In this storage system 100, a data write process accompanied by a compression process from the host computer 30 will be described.

In this embodiment, the case where the storage controller 1_22A receives the write instruction from the host computer 30 is shown.

Specific examples are as shown below.

(S1) The storage device 11 receives a write command from the host computer 30 via the network 31. The write instruction includes the data and the data allocation destination address 1100. When the write command is received, the write process after S2 starts.

(S2) The storage device 11 secures the exclusion of the slot indicated by the allocation destination address 1100 in response to the write command. This prevents the data in that slot from being updated by other write instructions. A "slot" is an area in a volume (VOL). Specifically, the slot of this embodiment is an area that is a unit of management such as whether or not writing to the drive 29 has been performed and whether or not transfer to the buffer area 202 has been performed. In this embodiment, this area is referred to as a "slot", but it may be referred to by another name.

"Securing slot exclusion" is an operation of preventing read and write to the slot indicated by the address specified by the read command and write command from the host computer 30, and the host computer 30 recognizes that the exclusion has been secured. Information for is managed. The type of this information does not matter as long as it can be identified such as bitmap or time information. Further, in this embodiment, the "slot" is an area in the VOL (for example, TP-VOL which is a VOL according to thin provisioning), whereas the "data area" is an area allocated to the slot (for example, in the pool). The pool area, which is the area of.

(S3) In the cache area 203A in the storage controller 1_22A of the storage device 11, data is stored in the address 1100A corresponding to the data allocation destination address 1100.

(S4) The storage controller 1_22A transfers the data stored in the cache area 203A to the storage controller 2_22B. The storage controller 2_22B stores the received data in the address 1100B in the cache area 203B corresponding to the allocation destination address 1100, and returns a response to the storage controller 1_22A to complete the duplication in the storage device 11.

(S5) After the duplication is completed, the storage device 11 responds to the host computer 30 with the write completion via the network 31. At this point, the host computer 30 recognizes that the write is completed.

(S6) The storage controller 1_22A selects data to be written from the cache area 203A to the drive, compresses the selected data, and stores the selected data at the address 1101A in the buffer area 202A. This process is executed until the data for the parity cycle is accumulated in the buffer area 202A.

Further, as will be described later, the storage controller 1_22A may store the selected data as it is at the address 1101A without compressing it, or it may perform processing other than compression (for example, deduplication or encryption) after the processing. Data may be stored in the address 1101A.

(S7) When the amount of data in the buffer area 202A reaches the parity cycle, the storage controller 1_22A generates parity data from the stored data and stores it at the address 1104A in the buffer area 202A.

(S8) The storage controller 1_22A writes the compressed data and the parity data in the buffer area 202A to the drive 29 (destage processing).

(S9) When the destage processing is completed, the storage controller 1_22A releases the exclusion of the slot secured in (S2).

The above is an example of light processing.

<Storage device>
FIG. 2 is a block diagram showing the configuration of the storage device 11 according to the first embodiment of the present invention.

The storage device 11 has one or more storage controllers 22 and a plurality of drives 29 connected to one or more storage controllers 22.

The storage controller 22 controls the FE_I / F (front-end interface device) 23 for communicating with the host computer 30, the storage I / F (storage interface device) 28 for communicating between the storage devices, and the entire device. It includes a processor 24, a memory 25 for storing programs and information used in the processor 24, a BE_I / F (back-end interface device) 27 for communicating with a drive 29, and an internal network 26 for connecting them.

The memory 25 includes a program area 201 that manages the program, a buffer area 202 that is a temporary storage area at the time of data transfer and copying, write data (data written in response to a write command) from the host computer 30, and data. It has a cache area 203 for temporarily storing read data (data read in response to a read instruction) from the drive 29, and a table management area 206 for storing various tables.

The cache area 203 has an uncompressed data storage area 204 for temporarily storing write data from the host computer 30, and a compressed data storage area 205 for storing compressed data. The table management area 206 includes a VOL management table 207 that holds information about VOL, a pool configuration management table 208 that holds information about pools, a RADIUS configuration management table 209 that holds information about RADIUS configuration, and a pool that holds information about pool allocation. It stores the allocation management table 210, the drive allocation management table 211 that holds information about drive allocation, and the memory allocation management table 212 that holds information about memory allocation.

The drive 29 is a device having a non-volatile data storage medium, and may be, for example, an SSD (Solid State Drive) or an HDD (Hard Disk Drive). A plurality of drives 29 may form a plurality of RAID groups (also referred to as parity groups). Each RAID group is composed of one or more drives 29.

FE_I / F23, BE_I / F27 and storage I / F28 are examples of the interface unit. The memory 25 is an example of the memory unit. The processor 24 is an example of a processor unit.

<VOL management table>
FIG. 3 is an explanatory diagram showing a configuration example of the VOL management table 207 held by the storage device 11 of the first embodiment of the present invention.

The VOL management table 207 has an entry for each VOL. Each entry stores information such as VOL_ID41, VOL attribute 42, VOL capacity 43 and pool ID44. Hereinafter, one VOL (“target VOL” in the description of FIG. 3) will be taken as an example.

VOL_ID41 is the ID of the target VOL. The VOL attribute 42 indicates the attribute of the target VOL (for example, whether the target VOL is a VOL to which thin provisioning is applied, whether it is a normal VOL, whether compression is effective, and the like). The VOL capacity 43 indicates the capacity of the target VOL. The pool ID 44 is the ID of the pool associated with the target VOL.

In the destage processing, the processor 24 can determine whether or not the VOL requires data compression by referring to the VOL attribute 42 of the VOL management table 207. For example, if the VOL attribute 42 “compression is valid”, the data compression process is performed.

<Configuration management table>
FIG. 4 is an explanatory diagram showing a configuration example of the pool configuration management table 208 held by the storage device 11 of the first embodiment of the present invention.

A pool is a logical storage area constructed based on one or more RAID groups. The pool configuration management table 208 has an entry for each pool. Each entry stores information such as pool ID 51, RAID group ID 52, pool capacity 53, and pool usage capacity 54. Hereinafter, one pool (“target pool” in the description of FIG. 4) will be taken as an example.

The pool ID 51 is the ID of the target pool. The RAID group ID 52 is the ID of each of the one or more RAID groups that are the basis of the target pool. The pool capacity 53 indicates the capacity of the target pool. The pool usage capacity 54 indicates the total amount of the area allocated to the VOL among the pool capacities of the target pool.

FIG. 5 is an explanatory diagram showing a configuration example of the RAID configuration management table 209 held by the storage device 11 of the first embodiment of the present invention.

The RAID configuration management table 209 has an entry for each RAID group. Each entry stores information such as RAID group ID 61, RAID level 62, drive ID 63, drive type 64, capacity 65 and used capacity 66. Hereinafter, one RAID group (“target RAID group” in the description of FIG. 5) will be taken as an example.

The RAID group ID 61 is the ID of the target RAID group. The RAID level 62 indicates the type of RAID algorithm applied to the target RAID group. The drive ID 63 is the ID of each of the one or more drives constituting the target RAID group. The drive type 64 indicates the type of drive (for example, HDD or SSD) that constitutes the target RAID group. Capacity 65 indicates the capacity of the target RAID group. The used capacity 66 indicates the used capacity among the capacities of the target RAID group.

<Assignment management table>
FIG. 6 is an explanatory diagram showing a configuration example of the pool allocation management table 210 held by the storage device 11 of the first embodiment of the present invention.

The pool allocation management table 210 has an entry for each VOL address (an address indicating a slot in the VOL). Each entry stores information such as VOL_ID71, VOL address 72, pool ID73, pool address 74, pre-compression size 75, post-compression size 76, and compression ratio 77. Hereinafter, one VOL address (“target VOL address” in the description of FIG. 6) will be taken as an example.

VOL_ID71 is the ID of the VOL to which the slot identified by the target VOL address belongs. The VOL address 72 is a target VOL address. The pool ID 73 is an ID of the pool including the data area assigned to the target VOL address. The pool address 74 is an address (an address belonging to the pool) of the data area assigned to the target VOL address. The pre-compression size 75 indicates the pre-compression size of the data according to the write instruction specifying the target pool address. The compressed size 76 indicates the compressed size of the data according to the write instruction specifying the target pool address. The compression rate 77 is a value of post-compression size 76 / pre-compression size 75.

FIG. 7 is an explanatory diagram showing a configuration example of the drive allocation management table 211 held by the storage device 11 of the first embodiment of the present invention.

The drive allocation management table 211 has an entry for each pool address. Each entry stores information such as pool ID 81, pool address 82, RAID group ID 83, drive ID 84 and drive address 85. Hereinafter, one pool address (“target pool address” in the description of FIG. 7) will be taken as an example.

The pool ID 81 is the ID of the pool to which the target pool address belongs. The pool address 82 is a target pool address. The RAID group ID 83 is the ID of the RAID group that is the basis of the data area indicated by the target pool address. The drive ID 84 is the ID of the drive that is the basis of the data area indicated by the target pool address. The drive address 85 is a drive address corresponding to the target pool address.

<Logical storage hierarchy>
FIG. 8 is an explanatory diagram showing a configuration example of a logical storage hierarchy managed by the storage device 11 of the first embodiment of the present invention.

The VOL 1000 is provided to the host computer 30. Further, due to the copy process or the deduplication process, one pool address may be pointed to from a plurality of slots in the VOL1000, and one pool address may be pointed to from a plurality of VOL slots. In the example of FIG. 8, two different slots (VOL addresses) 1100 and 1103 point to the same pool address 1101. The allocation of the pool 1001 from the VOL 1000 is managed based on the pool allocation management table 210. Further, the allocation from the pool 1001 to the drive address space 1003 (that is, the plurality of drive address spaces provided by the plurality of drives 29 constituting the RAID group 1002) is managed based on the drive allocation management table 211.

<Memory allocation management table>
FIG. 9 is an explanatory diagram showing a configuration example of the memory allocation management table 212 held by the storage device 11 of the first embodiment of the present invention.

The memory allocation management table 212 has an entry for each VOL address (address indicating a slot). Each entry stores information such as VOL_ID91, VOL address 92, buffer (BF) address 93, compressed VOL address 94, queue state 95, and BF transfer state 96. Hereinafter, one VOL address (“target VOL address” in the description of FIG. 9) will be taken as an example.

VOL_ID91 is the ID of the VOL to which the slot identified by the target VOL address belongs. The VOL address 92 is a target VOL address. The BF address 93 indicates the transfer destination BF address of the data written by designating the target VOL address. The compressed VOL address 94 indicates the transfer destination VOL address of the data that is not the target of transfer to the BF among the data written by designating the target VOL address. The queue state 95 indicates whether the data storage of the data written by designating the target VOL address in the drive 29 is completed. In FIG. 9, among the values of the queue state 95, “Dirty” indicates that the value has not been stored in the drive 29, and “Clean” indicates that the value has been stored in the drive 29. The BF transfer state 96 indicates whether or not the data written by designating the target VOL address is compressed and transferred to the BF. When the transfer to the BF is completed, the value of the BF transfer status 96 is "transferred", and when the transfer is not performed, the value is "none".

FIG. 10 is a diagram showing a configuration example of memory allocation in the storage device 11 of the first embodiment of the present invention.

The cache area 203 provides the storage controller 22 with an uncompressed data storage area 204, which is a virtual address space corresponding to the VOL, and a compressed data storage area 205 corresponding to the pool address. The uncompressed data storage area 204 corresponding to the VOL address is allocated by the write command from the host computer 30 to the storage controller 22. When the data is compressed asynchronously with the write instruction, the storage controller 22 stores the compressed data in the buffer area 202 or the compressed data storage area 205 in the cache area 203 corresponding to the pool address.

In the example of FIG. 10, the slot 1100 in the VOL in which the written data is stored points to the area 1101 on the buffer area 202 corresponding to the pool address. The allocation of the VOL address and the pool address is managed by the pool allocation management table 210. The allocation to the buffer area 202 is managed by the BF address 93 of the memory allocation management table 212, and the allocation to the compressed data storage area is managed by the compressed VOL address 94 of the memory allocation management table 212.

In the buffer area 202, when the amount of data in the buffer area reaches the size of the parity cycle, a parity 1104 that does not correspond to the uncompressed data storage area 204 is generated via the processor 24.

Hereinafter, an example of the processing performed in this embodiment will be described.

<Lead processing>
FIG. 11 is a flowchart showing a read process executed by the storage device 11 of the first embodiment of the present invention.

The read process starts when the storage device 11 receives a read command from the host computer 30 via the network 31. In the read instruction, for example, a virtual ID (for example, virtual VOL_ID), an address, and a data size are specified.

In S1201, the processor 24 secures the exclusion of the slot specified from the read instruction. When the slot exclusion is secured by another process, the processor 24 waits for a certain period of time before performing S1201.

In S1202, the processor 24 determines whether or not the read data exists in the cache area 203. If the determination result of S1202 is true, the process proceeds to S1204. If the determination result of S1202 is false, the processor 24 transfers read data from the RAID group to the buffer area 202 in S1203. At this time, the processor 24 specifies the pool ID 73, the pool address 74, and the compressed size 76 of the pool allocation management table 210 from the VOL_ID and the VOL address specified by the host computer 30, and drives the drive ID 84 from the drive allocation management table 211. And the drive address 85 to specify the data storage location and data size.

In S1204, the processor 24 determines whether or not the read data on the buffer area 202 is compressed from the compressed size 76, decompresses the compressed data in S1205, and skips S1205 if it is not compressed data. do.

In S1206, the processor 24 transfers the read data on the buffer area 202 to the host computer 30. The host computer 30 recognizes that the read process is completed when the data transfer of S1206 is completed.

After that, the processor 24 releases the reserved slot exclusion in S1205.

<Light processing>
FIG. 12 is a flowchart showing a write process executed by the storage device 11 of the first embodiment of the present invention.

The write process starts when the storage device 11 receives a write command from the host computer 30. In the following description, for example, the processor 24 of the storage controller 2_22A is described as the processor 24A, and those belonging to the storage controller 2_22A and the storage controller 2_22B are distinguished by "A" and "B" attached to reference numerals, respectively. ..

An allocation destination address is attached to the write instruction from the host computer 30. The storage device 11 secures the exclusion of the slot indicated by the allocation destination address in S1301. At the same time as the slot exclusion is secured, the processor 24A allocates the slot area of the cache area 203A to which the data is written.

In S1302, the processor 24A responds to the host computer 30 with a "Ready" indicating that the write process is ready. The processor 24A receives write data from the host computer 30 that has received "Ready". After that, in S1303, the processor 24 determines whether it is necessary to execute the compression process in synchronization with the write instruction. The load of the processor 24A, the amount of write to the storage device 11, and the data length of the write data are branched into either case 1 in which response performance is prioritized or case 2 in which throughput performance is prioritized in the storage system 100. For example, the storage device 11 holds the following conditions, and when the processor 24A receives a write instruction, it may determine whether to prioritize the response performance or the throughput performance based on the holding conditions. good.

<Case 1> Response priority There are the following conditions for prioritizing response performance. For example, it may be determined whether or not the response performance is prioritized based on only one of the following plurality of conditions or a plurality of combinations. The same applies to the conditions related to the throughput performance described later.

(1) The load of the storage controller 22 (that is, the processor 24) is lower than the predetermined reference.

(2) It is expected that the compression rate when the write data is compressed will be lower than the predetermined standard.

(3) Compressed data cannot be stored in the write destination volume

Here, in the above (1), since the fluctuation of the load becomes unstable when the determination result is frequently switched in the vicinity of the predetermined reference, the reference may be changed in multiple steps in order to prevent this. Further, the above (1) may be determined based on, for example, the amount of IO instructions for the storage device 11. For example, it may be determined that the load is low when the number of IO instructions per unit time or the amount of data written / read by the IO instruction is less than a predetermined reference.

In the above (2), for example, when the size of the write data is smaller than a predetermined reference, it may be determined that the compression rate of the write data is low, that is, data reduction by compression cannot be expected. In the above (3), for example, even if it is determined that the compressed data cannot be stored in the write destination volume when the VOL attribute 42 of the VOL management table 207 corresponding to the VOL to which the write data is written is not "compression enabled". good.

For example, when the processor 24A has a low load and priority is given to response performance, the determination in S1303 is false. In this case, the processor 24A stores the write data received in S1306 in the cache area 203A to which the write data is allocated. In S1307, the write data stored in the cache area 203A is transferred from the storage controller 1_22A to the storage controller 2_22B, and the write data is stored in the cache area 203B to perform duplication.

In S1308, the processor 24A updates the memory allocation management table 212. In this case, the write data has not been compressed yet. Therefore, there is no value of the BF address 93 and the compressed VOL address 94 corresponding to the VOL address of the slot assigned as the data write destination, and the processor 24A updates the queue state 95 to “Dirty”.

Next, in S1309, the storage device 11 returns a completion response to the host computer 30 via the network 31 assuming that the write process is completed. When the completion response is returned, the storage device 11 releases the exclusion of the slot reserved in S1310 and ends the write process.

<Case 2> Priority for throughput There are the following conditions for prioritizing throughput performance.

(4) The load of the storage controller 22 (that is, the processor 24) is higher than the predetermined reference.

(5) It is expected that the compression rate when the write data is compressed will be higher than the predetermined standard.

Here, the above (4) can be determined based on, for example, the amount of IO instructions for the storage device 11 as in the above (1). For example, when the number of IO instructions per unit time is larger than a predetermined standard, it may be determined that the load is high.

In the above (5), for example, when the size of the write data is larger than a predetermined reference, it may be determined that the compression rate of the write data is high, that is, data reduction by compression is expected.

For example, when the processor 24 has a high load and priority is given to the throughput performance, it is true in the determination of S1303. In this case, the processor 24A transfers the write data received in S1304 to the buffer area 202A. Next, in S1305, the processor 24A compresses the data in the buffer.

In S1304 and S1305, compression may be performed when the write data is stored in the buffer area 202A (that is, compression is performed before storage in the buffer area 202A, and the compressed data is stored in the buffer area 202A. It may be performed), and compression may be performed in the buffer area 202A after storage in the buffer area 202A. In either case, the compressed data is finally stored in the buffer area 202A.

Further, this compression may be performed in a storage area other than the buffer area 202A (for example, a memory in the processor 24A).

Here, compression is an example of predetermined processing performed on write data. The processor 24 may perform processing other than compression, for example, deduplication, encryption, redundancy, etc., and store the processed data in the buffer area 202A. The same applies to S1411 in FIG. 14, which will be described later.

Next, in S1306, the processor 24A stores the compressed data in the buffer area 202A in the allocated cache area 203A. In S1307, the write data stored in the cache area 203A is transferred from the storage controller 1_22A to the storage controller 2_22B, and the compressed data is duplicated by storing the write data in the cache area 203B.

In S1308, the processor 24A updates the memory allocation management table 212. In this case, the write data is compressed, and an address is assigned to the compressed data. Therefore, the compressed VOL address 94 corresponding to the VOL address of the slot assigned as the data write destination is updated. Further, there is no value of the BF address 93, and the processor 24A updates the queue state 95 to "Dirty".

Next, in S1309, the storage device 11 returns a completion response to the host computer 30 via the network 31 assuming that the write process is completed. When the completion response is returned, the storage device 11 releases the exclusion of the slot reserved in S1310 and ends the write process.

<Destage processing>
FIG. 13 is a flowchart showing a destage process executed by the storage device 11 of the first embodiment of the present invention.

The destage processing is performed asynchronously after the write instruction from the host computer 30 to the storage device 11 is completed. The destage may be started when the write command is completed, may be started periodically, or the write amount may be determined and selected from the consumption amount of the cache area 203 or the like. good.

When the destage processing is started, the storage device 11 determines in S1401 whether or not the target area of the destage processing belongs to the compressed data storage area 205 on the cache area. Case 2-1 when the determination is true (that is, when the target area belongs to the compressed data storage area 205), and when the determination is false (that is, when the target area belongs to the uncompressed data storage area 204). The processing of case 1-1 is performed.

<Case 2-1> Destage of compressed data When the determination of S1401 is true, destage processing (S1402 to S1406) is performed on the compressed data storage area 205 in the cache area 203. In S1402, the processor 24A selects data to be destaged from the compressed data storage area 205. Normally, a data string (striped column) in which data for the parity cycle is arranged is selected, and destage is performed for it.

In S1403, the processor 24 ensures the exclusion of the slot to which the destaged data belongs. After ensuring the exclusion, the processor 24A generates parity data from the target data string in S1404. In S1405, the processor 24A writes the target data string and the generated parity data to the drive. In S1406, the processor 24A updates the memory allocation management table 212. In this case, the queue state 95 is updated to "Clean". In S1407, the processor 24A releases the exclusion of the destaged range of slots and ends the process.

<Case 1-1> Compression and destage batch processing (exclusive holding during destage)
If the determination in S1401 is false, destage processing (S1408 to S1415) is performed on the uncompressed data storage area 204 in the cache area 203. In S1408, the processor 24A selects the data to be destaged from the data belonging to the slot whose queue state 95 is “Dirty” among the data stored in the uncompressed data storage area 204. Normally, a data string (striped column) in which data for the parity cycle is arranged is selected, and destage is performed for it.

In S1409, the processor 24 ensures the exclusion of the slot to which the destaged data belongs. When the destage process shown in FIG. 13 is performed with the end of the write process shown in FIG. 12 as a trigger (that is, immediately after the write process), S1310 and S1409 may be omitted.

After ensuring the exclusion, the processor 24A reads the target data in S1410 and transfers it to the buffer area 202. At the time of transfer, the processor 24 allocates the BF address 93 of the memory allocation management table 212 and the compressed VOL address 94. Further, the processor 24A updates the BF transfer state 96 to "transferred" after the transfer to the buffer area 202 is completed. Since it is clear that the VOL address 94 after compression is allocated for the parity cycle, the number of times the mapping information is updated can be reduced by allocating the area for the parity cycle in advance.

In S1411, the processor 24A compresses the transferred data. The compression process may be performed at the time of buffer transfer (that is, compression may be performed before storage in the buffer area 202, and the compressed data may be stored in the buffer area 202), and the compressed data may be stored in the buffer area 202 after transfer. You may go.

In S1412, the processor 24A determines the amount of compressed data in the buffer. If the amount of compressed data is less than the parity cycle, the processor 24 returns to S1408 to additionally select data to be destaged. When the data for the parity cycle is accumulated in the buffer area 202, the determination in S1412 is regarded as true and the process proceeds to S1413. Since the compressed data size has a variable length, the data in the buffer area 202 is not always aligned for the parity cycle, so that the processing may proceed to S1413 before the parity cycle is exceeded.

In S1413, the processor 24A generates parity data from the compressed data in the buffer area 202. In S1414, the processor 24A writes the target data string and the generated parity data to the drive 29 constituting the RAID group. In S1415, the processor 24A confirms the update of the memory allocation management table 212. In this case, the queue state 95 is updated to "Clean". In S1407, the processor 24A releases the exclusion of the destaged range of slots and ends the process.

In the above example, in S1412, it is determined whether or not the amount of compressed data in the buffer has reached the data amount of the parity cycle. However, when a predetermined amount of data is collectively stored in the drive 29 regardless of whether or not the drive 29 constitutes RAID, the processor 24A determines that the amount of compressed data in the buffer in S1412 is the predetermined amount. Determine if the quantity has been reached. The data amount of the parity cycle in S1412 of this embodiment is an example of the above-mentioned predetermined data amount.

Note that the processor 24A may execute S1402 to S1406 instead of S1408 to S1415 even if the determination of S1401 is false. For example, if the determination in S1303 in FIG. 12 is false because the VOL attribute 42 to which the write data is written is not compressed, the uncompressed data is stored in the cache area 203A. In this case, the determination of S1401 is false, but since the data is not compressed, S1402 to S1406 are executed.

In the above example, when throughput performance is prioritized, a response is returned to the host computer 30 when the compressed data is duplicated in the cache area 203 during write processing, and data compression is not required in destage processing. Become. As a result, the response performance is lowered, but the cache access during the destage processing is reduced, so that the throughput performance is improved. Such processing is an example, and when throughput performance is prioritized, more processing may be performed during write processing.

For example, the processor 24A executes S1304 to S1308 when the determination of S1303 (FIG. 12) is true, and subsequently executes the same processing as S1412 and S1404 to S1406 (FIG. 13), and then S1309. , S1310 may be executed. That is, since the compression process and the destage are collectively performed for the write instruction, the response performance is further lowered, but the throughput performance is improved.

Also in this case, the processing when the determination in S1303 (FIG. 12) is false is as described with reference to FIGS. 12 and 13 above. That is, the processor 24A executes S1306 to S1310 without executing S1304 to S1305. Further, the processor 24A executes S1408 to S1415 and S1407.

According to the above example, when destage is started, slot exclusion is secured (S1409), and then the transfer of data to the drive 29 is completed (S1414) until the mapping information is updated (S1415). , Slot exclusion is ensured (S1407). By ensuring exclusion for a long time in this way, troubles such as the inability to execute necessary IO instructions may occur. In order to avoid such troubles, the following case 1-2 is shown as an example in which the exclusion procedure in case 1-1 is changed.

FIG. 14 is a flowchart showing a destage process in which the exclusion procedure is changed, which is executed by the storage device 11 of the first embodiment of the present invention.

<Case 1-2> Compression and destage batch processing (exclusive release during destage)
In S1501, the storage device 11 makes the same determination as in S1401 of FIG. If the determination in S1501 is true, destage processing (S1502 to S1507) is performed on the compressed data storage area 205 in the cache area 203. Since these processes are the same as those of S1402 to S1407 in FIG. 13, the description thereof will be omitted.

If the determination in S1501 is false, destage processing is performed on the uncompressed data storage area 204 in the cache area 203 (S1508 to S1519). In S1508, the processor 24 selects the data to be destaged from the data belonging to the slot whose queue state 95 is “Dirty” among the data stored in the uncompressed data storage area 204. Normally, a data string (striped column) in which data for the parity cycle is arranged is selected, and destage is performed for it.

In case 1-1 described above, the slot range to be destaged is held until the destage processing is completed. However, if the compressed data size continues to hold a wide range of exclusions that reach the parity cycle, there is a high possibility that a write instruction from the host computer 30 will occur in the exclusion range, resulting in a destage wait. Therefore, the processor 24 secures the exclusion of the slot to which the data to be destaged in S1509 belongs, and then performs the buffer transfer of S1510 and the compression process of S1511. Then, the processor 24 updates the BF transfer state 96 of the memory allocation management table 212 to “transferred” in S1512 after the compression process is completed. When the update is completed, the processor 24 releases the slot exclusion in S1513.

After that, the processor 24 performs the determination of whether or not the drive transfer of S1514 is possible, the parity generation of S1515, and the drive transfer of S1516 in the same manner as in S1412, S1413, and S1414 of Case 1-1, respectively.

In S1517, the processor 24 secures slot exclusion in the destage range again, and updates the queue state 95 of the memory allocation management table 212 to “Clean” in S1518.

If an update write from the host computer 30 occurs for the slot in the destage range up to S1517, the processor 24 sets the BF transfer state 96 of the memory allocation management table 212 to “none” in S1308. Update to. In this case, it is possible to notice that the update write has occurred by determining that the BF transfer state 96 has been switched when the processor 24 updates the queue state 95 in S1518.

If the occurrence of the update write is noticed (that is, the BF transfer state 96 updated to "transferred" in S1512 is "none" at the time of S1517), the processor 24 either redoes the process or the target location. Skip the mapping information update. Specifically, the processor 24 may return to S1508 without proceeding to S1518, and may redo the destage processing for the slot in which the update write is performed. Alternatively, the processor may proceed to S1508 as it is, and proceed to S1519 without updating the queue state 95 of the slot in which the update write is performed to “Clean”. In that case, the slot is subject to destage processing from the next time onward.

Finally, in S1519, the processor 24 releases the exclusion of the destaged range of slots and ends the process.

According to the above embodiment of the present invention, when the data stored in the cache area is destaged, the compression process to the storage in the storage device (drive) are collectively performed, so that the compression data duplication process can be performed. Omitted. By eliminating the need for duplication of compressed data in the cache area, the amount of cache access can be reduced and the maximum speed of data writing can be improved.

In addition, by duplicating and holding the uncompressed data in the cache memory until the storage of the compressed data in the storage device is completed, a device failure occurs during processing such as compression processing and storage in the storage device. Can also protect your data. Similar effects can be obtained when the storage device performs processing other than compression (for example, deduplication, encryption, redundancy, etc.).

Further, when the compression process is performed at the time of destage, a region having a predetermined size such as a parity cycle can be allocated in advance, so that the number of times the mapping information is updated can be reduced.

Further, according to the embodiment of the present invention, the storage device determines which of the response performance and the throughput performance is prioritized based on a predetermined condition. Then, when the response performance is prioritized, the data before compression is duplicated and held in the cache memory before responding to the host. This improves the response performance. On the other hand, if priority is given to throughput performance, compression is performed, and the compressed data is duplicated and retained before responding to the host. As a result, the response performance is reduced, but the cache access amount at the time of destage is reduced, so that the throughput performance is improved.

For example, by determining whether to prioritize response performance or throughput performance based on the amount of IO instructions, expected compression rate, attributes of the volume to be written, etc., the optimum performance is realized according to the situation. be able to.

In addition, when destage the uncompressed data stored in the cache area, the storage of the compressed data in the storage device is completed from the time when the data is read from the cache area, and the queue state is changed to "Clean". (S1409 to S1415, S1407), the exclusion of the data area may be secured. This prevents erroneous determination that data that has not yet been destaged has been destaged.

Alternatively, the exclusive data may be temporarily released when the data is read, compressed, and transferred to the buffer area (S1513). As a result, the time for ensuring exclusion is shortened, and the trouble that the required IO cannot be executed is reduced. In this case, if new writing is performed between the time when the exclusion is temporarily released (S1513) and the time when the transfer of the data to the storage device is completed (S1516), that is recorded (that is, the BF transfer state). Is updated from "transferred" to "none"). This prevents erroneous determination that data that has not yet been destaged has been destaged.

In addition to those described in the claims, the following are typical examples of the viewpoint of the present invention.
(1) A storage system including a first storage control unit, a second storage control unit, and a storage drive connected to at least the first storage control unit and having a non-volatile storage medium.
The first storage control unit and the second storage control unit each have a cache area for storing data and a buffer area for storing data, and the data stored in the cache area. Is also stored in each other's cache area and duplicated,
When the first storage control unit receives a data write command from the host computer, the first storage control unit stores the data subject to the write command in the first cache area, which is the cache area of the first storage control unit. At the same time, the data is stored in the second cache area, which is the cache area of the second storage control unit, and duplication is performed. When the duplication is completed, the host computer is informed that the writing of the data is completed. Send a response,
The data to be written is subjected to predetermined processing and stored in the buffer area.
A storage system characterized in that data stored in the buffer area is read out and transmitted to the storage drive.
(2) The storage system according to (1) above.
The storage system is characterized in that the first storage control unit performs the predetermined processing on the data read from the first cache area, and stores the data after the predetermined processing in the buffer area.
(3) The storage system according to (1) above.
The storage system, wherein the predetermined process is any one of compression, deduplication, encryption, and redundancy of data read from the first cache area.
(4) The storage system according to (1) above.
It has a plurality of the storage drives connected to the first storage control unit, and has a plurality of the storage drives.
When the amount of data stored in the buffer area reaches a predetermined amount of data for generating parity, the first storage control unit creates parity based on the data read from the buffer area, and the first storage control unit creates parity. A storage system characterized in that data read from a buffer area and the parity are transmitted to the plurality of storage drives.
(5) The storage system according to (2) above.
The first storage control unit is
It holds a predetermined condition for determining which of the response performance and the throughput performance is prioritized in the storage system, and based on the predetermined condition, which of the response performance and the throughput performance is prioritized is determined. Judgment,
When the response performance is prioritized, the data is stored in the first and second cache areas, and then the predetermined processing is performed.
A storage system characterized in that when the throughput performance is prioritized, the data subjected to the predetermined processing is stored in the first and second cache areas.
(6) The storage system according to (5) above.
The storage system is characterized in that the first storage control unit determines that response performance is prioritized when the processing load of the first storage control unit is lower than a predetermined reference.
(7) The storage system according to (5) above.
The predetermined process is compression of the data.
The first storage control unit predicts that the compression rate of the data will be lower than a predetermined reference, or cannot store the compressed data in the volume designated as the write target of the data. In addition, a storage system characterized in that it is determined that response performance is prioritized.
(8) The storage system according to (5) above.
The first storage control unit is
For each management unit area of the volume to which the data is written, a queue state indicating whether the data written in the management unit area is stored in the storage drive is maintained.
When the data write command is received from the host computer, the data is stored in the first cache area after ensuring the exclusion of the management unit area to which the data is written.
After sending a response indicating the end of writing the data to the host computer, the exclusion of the management unit area to which the data is written is released.
Among the management unit areas, the data written in the management unit area is transferred to the management unit area after the queue state secures the exclusion of the management unit area indicating that the written data is not stored in the storage drive. Read from the first cache area, store the data after the predetermined processing in the buffer area, and store the data in the buffer area.
When the storage of the predetermined processed data read from the buffer area in the storage drive is completed, the queue state is updated to a value indicating that the written data is stored in the storage drive, and then the queue state is updated. , A storage system characterized by releasing the exclusion of the management unit area.
(9) The storage system according to (5) above.
The first storage control unit is
For each management unit area of the volume to which the data is written, a queue state indicating whether the data written in the management unit area is stored in the storage drive, and the data written in the management unit area is the buffer area. Holds the buffer transfer state indicating whether it was stored in
When the data write command is received from the host computer, the data is stored in the first cache area after ensuring the exclusion of the management unit area to which the data is written.
After sending a response indicating the end of writing the data to the host computer, the exclusion of the management unit area to which the data is written is released.
Among the management unit areas, the data written in the management unit area is transferred to the management unit area after the queue state secures the exclusion of the management unit area indicating that the written data is not stored in the storage drive. Read from the first cache area, store the data after the predetermined processing in the buffer area, and store the data in the buffer area.
After updating the buffer transfer state of the management unit area to a value indicating that the stored data is stored in the buffer area, the exclusion of the management unit area is released.
If data is written to the management unit area while the exclusion of the management unit area is released, the buffer transfer state of the management unit area and the written data are stored in the buffer area. Update to a value that indicates no,
After the predetermined processed data read from the buffer area is stored in the storage drive, the exclusive control of the management unit area is secured.
When the buffer transfer state of the management unit area indicates that the written data is stored in the buffer area, the queue state is a value indicating that the written data is stored in the storage drive. A storage system characterized in that the exclusion of the management unit area is released after updating to.
(10) The storage system according to (2) above.
The first storage control unit further has a third cache area for storing data.
The second storage control unit further has a fourth cache area for storing data.
When the first storage control unit determines that the throughput performance is prioritized based on the predetermined condition, the first storage control unit performs the predetermined processing on the data, and the data after the predetermined processing is the third. It is stored in the cache area, and the data after the predetermined processing is transmitted to the second storage control unit.
The second storage control unit stores the predetermined processed data received from the first storage control unit in the fourth cache area and performs duplication.
The first storage control unit is
When the storage of the data after the predetermined processing in the fourth cache area by the second storage control unit is completed, a response indicating the end of writing the data is transmitted to the host computer.
A storage system characterized in that data stored in the third cache area is read out and transmitted to the storage drive.

The present invention is not limited to the above-described embodiment, and includes various modifications. For example, the above-mentioned examples have been described in detail for a better understanding of the present invention, and are not necessarily limited to those having all the configurations of the description.

Further, each of the above configurations, functions, processing units, processing means and the like may be realized by hardware by designing a part or all of them by, for example, an integrated circuit. Further, each of the above configurations, functions, and the like may be realized by software by the processor interpreting and executing a program that realizes each function. Information such as programs, tables, and files that realize each function can be stored in non-volatile semiconductor memories, hard disk drives, storage devices such as SSDs (Solid State Drives), or computer-readable non-readable devices such as IC cards, SD cards, and DVDs. It can be stored in a temporary data storage medium.

In addition, the control lines and information lines indicate what is considered necessary for explanation, and do not necessarily indicate all the control lines and information lines in the product. In practice, it can be considered that almost all configurations are interconnected.

100 Storage system 11 Storage device 22, 22A, 22B Storage controller 202 Buffer area 203, 203A, 203B Cache area 204 Uncompressed data storage area 205 Compressed data storage area 29 Drive 30 Host computer 31 Network

Claims (3)

A storage system including a first storage control unit, a second storage control unit, and a storage drive connected to at least the first storage control unit and having a non-volatile storage medium.
The first storage control unit has a first cache area for storing data and a first buffer area for storing data.
The second storage control unit has a second cache area for storing data and a second buffer area for storing data, respectively.
The first storage control unit also stores the data stored in the first cache area in the second cache area to perform duplication.
When the first storage control unit receives a data write command from the host computer, the first storage control unit stores the data subject to the write command in the first cache area of the first storage control unit, and at the same time, the first storage control unit receives the data write command. The data stored in the cache area of 1 is stored in the second cache area of the second storage control unit to perform duplication, and when the duplication is completed, the host computer indicates the end of writing the data. Send a response,
The first storage control unit reads the data stored in the storage drive among the duplicated data stored in the cache area, which is the target of the write command, from the cache area. The data to be written command is compressed and stored in the first buffer area without being stored in the first cache area, and the data stored in the first buffer area by the compression process. A storage system characterized in that parity is generated based on the above and stored in the first buffer area, and data and parity stored in the first buffer area are read out and transmitted to the storage drive for storage. The storage system according to claim 1.
It has a plurality of the storage drives connected to the first storage control unit, and has a plurality of the storage drives.
When the amount of data stored in the first buffer area by the compression process reaches a predetermined amount of data for generating parity, the first storage control unit reads out from the first buffer area. A storage system characterized in that a parity is created based on the data and the data read from the first buffer area and the parity are transmitted to the plurality of storage drives. It ’s a storage system control method.
The storage system includes a first storage control unit, a second storage control unit, and a storage drive connected to at least the first storage control unit and having a non-volatile storage medium.
The first storage control unit has a first cache area for storing data and a first buffer area for storing data, and the second storage control unit stores data, respectively. It has a second cache area for storing data and a second buffer area for storing data, and the first storage control unit uses the data stored in the first cache area as the second cache area. It is designed to be stored in the cache area of and duplicated.
The control method of the storage system is
When the first storage control unit receives a data write command from the host computer, the data subject to the write command is stored in the first cache area of the first storage control unit, and the first cache area is stored. The data stored in the cache area 1 is stored in the second cache area of the second storage control unit to perform duplication, and when the duplication is completed, the host computer indicates the end of writing the data. The procedure for sending a response and
The data stored in the storage drive among the duplicated data stored in the cache area, which is the target of the write command, is read from the cache area by the first storage control unit. The data to be written is not stored in the first cache area by compression processing, but is stored in the first buffer area, and the data stored in the first buffer area by compression processing is used. It is characterized by including a procedure of generating a parity based on the above and storing it in the first buffer area, reading out the data and the parity stored in the first buffer area, transmitting the parity to the storage drive, and storing the data. How to control the storage system.

Images