JP6620601B2 - Electro-optical device and electronic apparatus - Google Patents

Description

  The present invention relates to a technical field of an electro-optical device and an electronic apparatus.

  2. Description of the Related Art In recent years, an electro-optical device using an OLED (Organic Light Emitting Diode) as a light emitting element is used in an electronic device capable of forming a virtual image such as a head-mounted display. In such an electro-optical device, as described in Patent Document 1, a method using a color filter has been proposed as one of methods for realizing color display.

  This method uses a white light emitting OLED as a light source, and obtains red, green, and blue light emission through three primary color filters of red, green, and blue. A combination of an OLED and a filter of one of the three primary colors is used as a subpixel, and a combination of the three primary color subpixels is used as a pixel. The pixels are arranged in a matrix to form a screen of the display device. As an arrangement method of the pixels, sub-pixels of the same color are arranged in the vertical direction (vertical direction) or the horizontal direction (horizontal direction) of the screen. The method is known.

  However, the light emitted from the white light emitting OLED is diffuse light. Further, a transparent layer having a thickness composed of an inorganic film or a resin film for sealing the OLED exists between the OLED and the color filter. For this reason, in a color filter type electro-optical device, part of the light emitted from the OLED of a certain sub-pixel passes through the color filter of the adjacent sub-pixel, and color mixing occurs depending on the angle at which the screen is observed. There's a problem.

  In the method in which sub-pixels of the same color are arranged in the vertical direction (vertical direction) of the screen, even if the screen is observed from an oblique direction, there is almost no color shift in the vertical direction. On the other hand, in the horizontal (left and right) direction, when the panel is observed obliquely, mixed color light such as light in which red and green are mixed, light in which red and blue are mixed, and light in which green and blue are mixed is visually recognized. Therefore, color misregistration occurs as compared with the case of observation from the front.

  In Patent Document 1, red and green sub-pixel reflective electrodes are arranged in the horizontal direction (left-right direction), and the blue sub-pixel reflective electrode is arranged in a vertical direction with respect to the red and green sub-pixel reflective electrodes ( It is proposed to arrange in the vertical direction.

JP 2013-2111147 A

  However, in the electro-optical device described in Patent Document 1, the scanning lines for the sub-pixels of each color are arranged in the vertical direction (vertical direction), and the number of scanning lines selected in one horizontal scanning period increases. It will be. As a result, the selection time of each scanning line in one horizontal scanning period is shortened, and writing from the data transfer line to the pixel may be difficult.

  Further, as in Patent Document 1, the width in the horizontal direction (left-right direction) of the reflective layer in the blue sub-pixel is the horizontal direction (left-right direction) in one pixel including the red sub-pixel and the green sub-pixel. Since it is shorter than the width, there is a possibility that the transistor characteristic is changed by irradiating the transistor with blue light.

  The present invention has been made in view of the above problems, for example, and prevents the transistor from being irradiated with light from the light emitting layer even when the subpixels of at least one color are arranged in the horizontal (left and right) direction. It is another object of the present invention to provide an electro-optical device that can prevent the selection time of each scanning line from being shortened, and an electronic apparatus including the electro-optical device.

  In order to solve the above problems, an aspect of the electro-optical device of the present invention includes a plurality of first conductive layers extending in a first direction and a plurality of second conductive layers extending in a second direction. And a plurality of sub-pixels arranged corresponding to the intersections of the plurality of first conductive layers and the plurality of second conductive layers, each of the plurality of sub-pixels emitting light A third conductive layer of the element; and a plurality of transistors, the plurality of transistors including a drive transistor, wherein the plurality of transistors have a width in the first direction that is greater than a width in the second direction. Is disposed within a narrow pixel circuit region, and one conductive layer of the plurality of first conductive layers is disposed on each of two subpixels adjacent to each other in the first direction among the plurality of subpixels. Electrically connected to at least one of the plurality of included transistors Of the plurality of subpixels, the third conductive layers of at least two subpixels have different sizes in plan view, and are the largest of the third conductive layers of the at least two subpixels. The third conductive layer has a width in the first direction larger than a width in the second direction, and overlaps a drain of at least one of the plurality of sub-pixels. And

  According to this aspect, among the third conductive layers of at least two subpixels, the third conductive layer that is the largest in plan view has a width in the first direction wider than a width in the second direction, and , And overlaps the drain of at least one driving transistor among the plurality of sub-pixels. Therefore, the light from the light emitting element is blocked by the largest third conductive layer, for example, the reflective layer in plan view, and is prevented from being irradiated to the drain of at least one drive transistor. As a result, the light emitting element is stably driven without changing the characteristics of the driving transistor.

  In one aspect of the electro-optical device described above, the plurality of first conductive layers may be scanning lines. According to this aspect, the plurality of transistors in the plurality of sub-pixels are disposed inside the pixel circuit region in which the width in the first direction is narrower than the width in the second direction, and the scanning line is in the first direction. Therefore, it is possible to share the scanning line in each sub-pixel. Therefore, the selection time of each scanning line in one horizontal scanning period is prevented from being shortened without increasing the number of scanning lines.

  In one aspect of the electro-optical device described above, the largest third conductive layer among the third conductive layers of the at least two sub-pixels is at least one of the drive transistors of the plurality of sub-pixels. It may overlap. According to this aspect, among the third conductive layers of at least two subpixels, the third conductive layer that is the largest in plan view overlaps at least one drive transistor of the plurality of subpixels. Therefore, light from the light emitting element is blocked by the largest third conductive layer, for example, the reflective layer in plan view, and is prevented from being irradiated to at least one drive transistor. As a result, the light emitting element is stably driven without changing the characteristics of the driving transistor.

  In one aspect of the electro-optical device described above, between the third conductive layer that is the largest of the third conductive layers of the at least two subpixels and the drive transistor of each of the plurality of subpixels. A fourth conductive layer may be disposed. According to this aspect, the light from the light emitting element is blocked not only by the largest third conductive layer in plan view but also by the fourth conductive layer, for example, the power supply wiring, and is applied to the driving transistor. To prevent. As a result, the light emitting element is stably driven without changing the characteristics of the driving transistor.

  In one aspect of the electro-optical device described above, the fourth conductive layer may extend along the first direction and overlap the driving transistor of each of the plurality of subpixels. According to this aspect, the light from the light emitting element is blocked not only by the largest third conductive layer in plan view but also by the fourth conductive layer extending along the first direction, for example, the power supply wiring. Thus, it is possible to prevent the driving transistors of each of the plurality of sub-pixels from being irradiated. As a result, the characteristics of the driving transistors in the plurality of subpixels are not changed, and the light emitting elements in the plurality of subpixels are stably driven.

  In one aspect of the electro-optical device described above, the fourth conductive layer may be a power supply wiring connected to the drive transistor of each of the plurality of subpixels. According to this aspect, the light from the light emitting element is also blocked by the power supply wiring, and is prevented from being irradiated to each driving transistor of the plurality of subpixels. As a result, the characteristics of the driving transistors in the plurality of subpixels are not changed, and the light emitting elements in the plurality of subpixels are stably driven.

  In one aspect of the electro-optical device described above, the plurality of transistors include light emission control transistors, and the third conductive layer that is the largest among the third conductive layers of the at least two subpixels is the plurality of the plurality of transistors. It may overlap with the drain of at least one light emission control transistor of the sub-pixels. According to this aspect, the light from the light emitting element is blocked by the largest third conductive layer in plan view and is prevented from being irradiated to the light emission control transistor. As a result, the light emitting element is stably driven without changing the characteristics of the light emission control transistor.

  In one aspect of the above-described electro-optical device, two of the third conductive layers adjacent in the second direction among the plurality of sub-pixels may have the sides facing each other in the column direction in the plan view. It may be located on the gate layer of the transistor. According to this aspect, a gap is formed between two third conductive layers adjacent in the second direction, but this gap is not located on the active region of the driving transistor but on the gate layer. To do. Therefore, the light emitting element is stably driven without changing the characteristics of the driving transistor.

  In one aspect of the electro-optical device described above, the largest third conductive layer among the third conductive layers of the at least two subpixels may be a subpixel of a blue display color. According to this aspect, the blue light is blocked by the third conductive layer, for example, the reflective layer, and is prevented from being irradiated to the driving transistor. As a result, the light emitting element is stably driven without changing the characteristics of the driving transistor.

  Next, an electronic apparatus according to the invention includes the above-described electro-optical device according to the invention. Such an electronic device uses an electro-optical device including a light-emitting element such as an OLED so that there is no color misregistration, no change in characteristics of the transistor due to light from the light-emitting layer, and writing from the data transfer line to the pixel Thus, an electronic apparatus with high image quality that is reliably performed is provided.

1 is a perspective view showing an electro-optical device according to a first embodiment of the invention. FIG. 2 is a block diagram illustrating a configuration of an electro-optical device according to the same embodiment. It is a circuit diagram which shows the structure of a pixel circuit. It is a circuit diagram which shows the structure of a pixel circuit. It is sectional drawing of the column direction of a subpixel. It is sectional drawing of the row direction of the pixel of 1 pixel unit. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. FIG. 10 is an explanatory diagram of each element formed on a substrate of an electro-optical device according to a second embodiment of the invention. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. FIG. 10 is an explanatory diagram of each element formed on a substrate of an electro-optical device according to a third embodiment of the invention. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is sectional drawing of the row direction of the pixel of 1 pixel unit. It is sectional drawing of the column direction of a subpixel. It is explanatory drawing which shows the example of an electronic device. It is explanatory drawing which shows the other example of an electronic device. It is explanatory drawing which shows the other example of an electronic device.

  Embodiments of the present invention will be described with reference to the drawings. In the following drawings, the scales are different for each layer and each member so that each layer and each member has a size that can be recognized on the drawing.

<First Embodiment>
FIG. 1 is a perspective view showing a configuration of an electro-optical device 1 according to the first embodiment of the present invention. The electro-optical device 1 is a micro display that displays an image on a head-mounted display, for example.
As shown in FIG. 1, the electro-optical device 1 includes a display panel 2 and a control circuit 3 that controls the operation of the display panel 2. The display panel 2 includes a plurality of pixel circuits and a drive circuit that drives the pixel circuits. In the present embodiment, a plurality of pixel circuits and drive circuits included in the display panel 2 are formed on a silicon substrate, and an OLED which is an example of a light emitting element is used for the pixel circuits. The display panel 2 is housed in, for example, a frame-like case 82 that opens at the display unit, and one end of an FPC (Flexible Printed Circuits) substrate 84 is connected.
On the FPC board 84, the control circuit 3 of the semiconductor chip is mounted by a COF (Chip On Film) technique, and a plurality of terminals 86 are provided, which are connected to an upper circuit (not shown).

FIG. 2 is a block diagram illustrating a configuration of the electro-optical device 1 according to the present embodiment. As described above, the electro-optical device 1 includes the display panel 2 and the control circuit 3.
Digital image data Vdata is supplied to the control circuit 3 in synchronization with a synchronization signal from an upper circuit (not shown). Here, the image data Vdata is data that defines the gradation level of pixels of an image to be displayed on the display panel 2 (strictly speaking, the display unit 100 described later) by, for example, 8 bits. The synchronization signal is a signal including a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal.

The control circuit 3 generates various control signals based on the synchronization signal and supplies them to the display panel 2. Specifically, the control circuit 3 controls the display panel 2 with the control signal Ctr, the control signals Sel (1), Sel (2), Sel (3), and the logical inversion relationship with respect to these signals. Control signals / Sel (1), / Sel (2), and / Sel (3).
Here, the control signal Ctr is a signal including a plurality of signals such as a pulse signal, a clock signal, and an enable signal.
The control signals Sel (1), Sel (2), and Sel (3) are collectively referred to as the control signal Sel, and the control signals / Sel (1), / Sel (2), and / Sel (3) are referred to as the control signal. / Sel may be collectively called.

  Further, the control circuit 3 generates an analog image signal Vid based on the image data Vdata. Specifically, the control circuit 3 is provided with a lookup table that stores the potential indicated by the image signal Vid and the luminance of a light emitting element (OLED described later) included in the display panel 2 in association with each other. Then, the control circuit 3 refers to the lookup table to generate an image signal Vid indicating a potential corresponding to the luminance of the light emitting element specified by the image data Vdata, and supplies this to the display panel 2. To do.

As shown in FIG. 2, the display panel 2 includes a display unit 100 and drive circuits (a data transfer line drive circuit 5 and a scan line drive circuit 6) that drive the display unit 100.
In the display unit 100, pixel circuits 110 corresponding to pixels of an image to be displayed are arranged in a matrix. Specifically, in the display unit 100, scanning lines 22 as first conductive layers of M rows are provided extending in the row direction (X direction) in the drawing. Further, data transfer lines 26 as second conductive layers of (3N) columns grouped every three columns extend in the column direction (Y direction) in the drawing, and are electrically connected to each scanning line 22. It is provided with proper insulation. In the present embodiment, the pixel circuits 110 are arranged in a matrix with M rows × (3N) columns.

Here, M and N are both natural numbers. In order to distinguish rows (rows) in the matrix of the scanning lines 22 and the pixel circuits 110, they may be referred to as 1, 2, 3,... (M-1), M rows in order from the top in the drawing. Similarly, in order to distinguish the columns of the data transfer line 26 and the matrix of the pixel circuit 110, they may be referred to as columns 1, 2, 3,..., (3N-1), (3N) in order from the left in the figure. is there.
Here, in order to generalize and describe the group of data transfer lines 26, if an arbitrary integer of 1 or more is expressed as n, the nth group counted from the left includes the (3n-2) th column, ( This means that the data transfer lines 26 of the 3n-1) th column and the (3n) th column belong.

  The three pixel circuits 110 corresponding to the scanning lines 22 in the same row and the three columns of data transfer lines 26 belonging to the same group have display colors of G (green), R (red), and B (blue), respectively. These three subpixels represent one dot as a pixel unit of a color image to be displayed. That is, in the present embodiment, one dot color is expressed by additive color mixing by light emission of an OLED corresponding to RGB.

The scanning line driving circuit 6 generates a scanning signal Gwr for sequentially scanning the M scanning lines 22 for each row within a period of one frame according to the control signal Ctr. Here, the scanning signals Gwr supplied to the scanning lines 22 in the 1st, 2nd, 3rd,..., Mth rows are Gwr (1), Gwr (2), Gwr (3),. ) And Gwr (M).
In addition to the scanning signals Gwr (1) to Gwr (M), the scanning line driving circuit 6 generates various control signals synchronized with the scanning signal Gwr for each row and supplies them to the display unit 100. Illustration is omitted in FIG. The frame period is a period required for the electro-optical device 1 to display an image for one cut (frame). For example, if the frequency of the vertical synchronization signal included in the synchronization signal is 120 Hz, the first period is 1. This is a period of 8.3 milliseconds corresponding to the period.

  The data transfer line driving circuit 5 includes (3N) data transfer circuits DT provided in a one-to-one correspondence with each of the (3N) columns of data transfer lines 26, and three columns of data transfer lines constituting each group. N demultiplexers DM provided for every 26 and a data signal supply circuit 70 are provided.

  The data signal supply circuit 70 generates data signals Vd (1), Vd (2),..., Vd (N) based on the image signal Vid and the control signal Ctr supplied from the control circuit 3. That is, the data signal supply circuit 70 generates the data signals Vd (1), Vd (2) based on the image signal Vid obtained by time-division multiplexing the data signals Vd (1), Vd (2),. ..., Vd (N) is generated. Then, the data signal supply circuit 70 applies the data signals Vd (1), Vd (2),..., Vd (N) to the demultiplexer DM corresponding to the first, second,. Supply each. The demultiplexer DM is turned on / off according to the control signal Sel and the control signal / Sel from the control circuit 3, and supplies the data signals to the three columns of data transfer lines 26 constituting each group in order. is there.

  FIG. 3 is a circuit diagram of the pixel circuit 110 of each subpixel located in the display unit 100. As illustrated in FIG. 3, the pixel circuit 110 includes a light emitting element 45, a drive transistor Tdr, a write control transistor Twr, a capacitor element C, a light emission control transistor Tel, and a compensation transistor Tcmp. The In the present embodiment, each transistor (Tdr, Tel, Twr, Tcmp) of the pixel circuit 110 is a P-channel type, but an N-channel type transistor can also be used.

  The light emitting element 45 is an electro-optical element in which a light emitting functional layer 46 including a light emitting layer of an organic EL material (OLED) is interposed between a first electrode (anode) E1 and a second electrode (cathode) E2. The first electrode E1 is individually formed for each pixel circuit 110, and the second electrode E2 is continuous over the plurality of pixel circuits 110. As understood from FIG. 3, the light emitting element 45 is disposed on a path connecting a first power supply conductor (hereinafter referred to as a power supply wiring) 41 as a fourth conductive layer and a second power supply conductor 42. Is done. The power supply wiring 41 is supplied with the higher power supply potential Vel. The second power supply conductor 42 is supplied with a lower power supply potential (for example, ground potential) Vct. The pixel circuit 110 according to the present embodiment can be driven by any of a so-called coupling drive method and a so-called current programming method. First, driving by the coupling driving method will be described.

  The light emission control transistor Tel functions as a switch that controls the conduction state (conduction / non-conduction) between the other (drain or source) of the pair of current ends of the drive transistor Tdr and the first electrode E1 of the light emitting element 45. The drive transistor Tdr generates a drive current having a current amount corresponding to the voltage between its gate and source. In a state where the light emission control transistor Tel is controlled to be in an on state, the drive current is supplied from the drive transistor Tdr to the light emitting element 45 via the light emission control transistor Tel, so that the light emitting element 45 corresponds to the amount of current of the drive current. Emits light with brightness. Further, in a state where the light emission control transistor Tel is controlled to be in an off state, the light emitting element 45 is turned off by interrupting the supply of the driving current to the light emitting element 45. The gate of the light emission control transistor Tel is connected to the control line 28.

  The compensation transistor Tcmp has a function of compensating for fluctuations in the threshold voltage of the drive transistor Tdr. In the state where the light emission control transistor Tel is in the off state and the write control transistor Twr and the drive transistor Tdr are controlled in the on state, the following operation is performed. When the compensation transistor Tcmp is controlled to be in an ON state, the gate potential and the drain or source potential of the driving transistor Tdr become equal, and the driving transistor Tdr is diode-connected. Therefore, the current flowing through the drive transistor Tdr charges the gate node and the data transfer line 26. Specifically, the current flows through a path of the power supply line 41 → the drive transistor Tdr → the compensation transistor Tcmp → the data transfer line 26. For this reason, when the driving transistor Tdr is controlled to be in the ON state, the data transfer line 26 and the gate node that are connected to each other rise from the potential in the initial state. However, if the threshold voltage of the driving transistor Tdr is | Vth |, the current flowing through the path becomes difficult to flow as the gate node approaches the potential (Vel− | Vth |). As a result, the data transfer line 26 and the gate node are saturated with the potential (Vel− | Vth |) until the end of the compensation period in which the compensation transistor Tcmp is turned off. Therefore, the capacitive element C holds the threshold voltage | Vth | of the drive transistor Tdr until the end of the compensation period in which the compensation transistor Tcmp is turned off.

  In the present embodiment, the horizontal scanning period has a compensation period and a writing period, and the scanning line driving circuit 6 supplies each scanning line 22 with a scanning signal so that each of the plurality of scanning lines 22 is horizontal. Selection is made sequentially for each scanning period. The write control transistor Twr of each pixel circuit 110 corresponding to the scanning line 22 selected by the scanning line driving circuit 6 is turned on. Accordingly, the drive transistor Tdr of each pixel circuit 110 is also turned on. Further, the scanning line driving circuit 6 sequentially selects each of the plurality of control lines 27 for each compensation period by supplying a control signal to each control line 27. The compensation transistor Tcmp of each pixel circuit 110 corresponding to the control line 27 selected by the scanning line driving circuit 6 is turned on. The capacitive element C holds the threshold voltage | Vth | of the drive transistor Tdr until the end of the compensation period in which the compensation transistor Tcmp is turned off. When the scanning line driving circuit 6 supplies a control signal to each control line 27 to control the compensation transistor Tcmp of each pixel circuit 110 to an off state, the path from the data transfer line 26 to the gate node of the driving transistor Tdr is Floating state. However, (Vel− | Vth |) is maintained by the capacitive element C. Next, the data transfer line driving circuit 5 applies a gradation potential (data signal) corresponding to the gradation specified by the image signal supplied from the external circuit for each pixel circuit 110 to the capacitor Cref for each writing period. Supply in parallel. The level of the grayscale potential is shifted using the capacitive element Cref, and the potential is supplied to the gate of the drive transistor Tdr of each pixel circuit 110 via the data transfer line 26 and the write control transistor Twr. The capacitor C holds a voltage corresponding to the gradation potential while compensating for the threshold voltage | Vth | of the driving transistor Tdr. On the other hand, when the selection of the scanning line 22 in the writing period is completed, the scanning line driving circuit 6 supplies a control signal to each control line 28, whereby the light emission control transistor of each pixel circuit 110 corresponding to the control line 28. Control Tel to ON state. Therefore, a driving current corresponding to the voltage held in the capacitor C in the immediately preceding writing period is supplied from the driving transistor Tdr to the light emitting element 45 via the light emission control transistor Tel. As described above, each light emitting element 45 emits light at a luminance corresponding to the gradation potential, whereby an arbitrary image specified by the image signal is displayed on the display unit 110. Since the drive current supplied from the drive transistor Tdr to the light emitting element 45 is offset by the influence of the threshold voltage, even if the threshold voltage of the drive transistor Tdr varies for each pixel circuit 110, the variation is compensated. . In addition, since a current corresponding to the gradation level is supplied to the light emitting element 45, the occurrence of display unevenness that impairs the uniformity of the display screen can be suppressed. As a result, high-quality display is possible.

  Next, driving by the current programming method will be described with reference to FIG. When the scanning signal of the scanning line 22 becomes L level, the write control transistor Twr is turned on. Further, when the control signal of the control line 27 becomes L level, the compensation transistor Tcmp is turned on. Therefore, the drive transistor Tdr has a gate potential equal to the source potential or drain potential on the connection side with the light emission control transistor Tel, and functions as a diode. When the data signal of the data transfer line 26 becomes L level, the current Idata flows through the path of the power supply line 41 → the drive transistor Tdr → the compensation transistor Tcmp → the data transfer line 26. At that time, charges corresponding to the potential of the gate node of the driving transistor Tdr are accumulated in the capacitor C.

  When the control signal of the control line 27 becomes H level, the compensation transistor Tcmp is turned off. At this time, the voltage at both ends of the capacitive element C is held at the voltage when the current Idata flows. When the control signal of the control line 28 becomes L level, the light emission control transistor Tel is turned on, and a current Ioled corresponding to the gate voltage flows between the source and drain of the drive transistor Tdr. Specifically, this current flows through a path of the power supply wiring 41 → the driving transistor Tdr → the light emission control transistor Tel → the light emitting element 45.

  Here, the current Ioled flowing through the light emitting element 45 is determined by the voltage between the gate node of the driving transistor Tdr and the drain node or the source node on the connection side with the power supply wiring 41. The voltage is a voltage held by the capacitor C when the current Idata flows through the data transfer line 26 by the L level scanning signal. For this reason, when the control signal of the control line 28 becomes L level, the current Ioled that flows through the light emitting element 45 substantially matches the current Idata that flows immediately before. As described above, in the case of driving by the current programming method, the light emission luminance is defined by the current Idata. Although the scanning line 22 is a wiring different from the control line 27, the scanning line 22 and the control line 27 may be a single wiring.

  A specific structure of the electro-optical device 1 according to the first embodiment will be described in detail below. In the drawings referred to in the following description, the dimensions and scales of the elements are different from those of the actual electro-optical device 1 for convenience of description. FIG. 5 is a cross-sectional view of the G (green) display color sub-pixel cut along line I-I ′ shown in FIG. 10. FIG. 6 is a cross-sectional view taken along the line II-II ′ shown in FIG. 7 to 12 are plan views illustrating the appearance of the surface of the substrate 10 at each stage of forming each element of the electro-optical device 1 focusing on one or two pixels in a pixel unit. It is. In FIG. 7 to FIG. 12, hatching in the same manner as FIG. 5 and FIG. 6 is added for convenience to each element common to FIG. 5 and FIG. 6 from the viewpoint of facilitating visual grasp of each element. Yes.

  As understood from FIGS. 5 to 7, an active region 10 </ b> A (source / drain) of each transistor (Tdr, Twr, Tel, Tcmp) of the pixel circuit 110 is formed on the surface of the substrate 10 made of a semiconductor material such as silicon. Region) is formed. Ions are implanted into the active region 10A. An active layer of each transistor (Tdr, Twr, Tel, Tcmp) of the pixel circuit 110 exists between the source region and the drain region, and ions of a different type from the active region 10A are implanted. It is described integrally with the region 10A. As understood from FIGS. 5 to 7, the surface of the substrate 10 on which the active region 10A is formed is covered with an insulating film L0 (gate insulating film), and the gate layer GT (GTdr, GTwr, GTel, GTcmp) of each transistor. Is formed on the surface of the insulating film L0. The gate layer GT of each transistor faces the active layer with the insulating film L0 interposed therebetween.

  In the present embodiment, as shown in FIG. 7, the plurality of transistors (Tdr, Twr, Tel, Tcmp) in the G (green), R (red), and B (blue) subpixels are arranged in the column direction. It arrange | positions along (Y direction). In FIGS. 7 to 12, a plurality of transistors in each G (green) sub-pixel are indicated as Gtr. Also, a plurality of transistors in each R (red) sub-pixel are indicated as Rtr. Further, a plurality of transistors in each B (blue) sub-pixel are indicated as Btr.

  As understood from FIGS. 5 and 6, on the surface of the insulating film L0 on which the gate layer GT of each transistor is formed, a plurality of insulating layers L (LA to LE), a plurality of conductive layers (wiring layers), and A multilayer wiring layer is formed by alternately stacking layers. Each insulating layer L is formed of an insulating inorganic material such as a silicon compound (typically silicon nitride or silicon oxide). In the following description, a relationship in which a plurality of elements are collectively formed in the same process by selective removal of a conductive layer (single layer or a plurality of layers) is referred to as “formed from the same layer”.

  The insulating layer LA is formed on the surface of the insulating film L0 on which the gate layer GT of each transistor is formed. As understood from FIGS. 5, 6, and 8, a plurality of relay electrodes QB (QB 1, QB 2, QB 3, QB 4, QB 5, QB 6, QB 7, QB 8) are on the same layer on the surface of the insulating layer LA. Formed from.

As understood from FIGS. 5 to 8, the relay electrode QB1 is electrically connected to the active region 10A forming the drain region or the source region of the driving transistor Tdr through the conduction hole HA1 penetrating the insulating film L0 and the insulating layer LA. To do.
The relay electrode QB2 is electrically connected to the gate layer GTdr of the drive transistor Tdr through a conduction hole HB1 that penetrates the insulating layer LA. The relay electrode QB2 is electrically connected to the active region 10A that forms the source region or the drain region of the write control transistor Twr through the conduction hole HA4 that penetrates the insulating layer LA and the insulating film L0.
The relay electrode QB3 is electrically connected to the active region 10A that forms the drain region or the source region of the drive transistor Tdr via the conduction hole HA2 that penetrates the insulating film L0 and the insulating layer LA. The relay electrode QB3 is also electrically connected to the active region 10A that forms the drain region or the source region of the compensation transistor Tcmp through the conduction hole HA6 that penetrates the insulating film L0 and the insulating layer LA. Further, the relay electrode QB3 is electrically connected to an active region 10A that forms a drain region or a source region of the light emission control transistor Tel through a conduction hole HA8 that penetrates the insulating film L0 and the insulating layer LA.
The relay electrode QB4 is electrically connected to the gate layer GTwr of the write control transistor Twr through a conduction hole HB2 that penetrates the insulating layer LA.

The relay electrode QB5 is electrically connected to the active region 10A that forms the drain region or the source region of the write control transistor Twr through the conduction hole HA3 that penetrates the insulating film L0 and the insulating layer LA. The relay electrode QB5 is also electrically connected to the active region 10A that forms the drain region or the source region of the compensation transistor Tcmp through the conduction hole HA5 that penetrates the insulating film L0 and the insulating layer LA.
The relay electrode QB6 is electrically connected to the gate layer GTcmp of the compensation transistor Tcmp through a conduction hole HB3 that penetrates the insulating layer LA.
The relay electrode QB7 is electrically connected to the gate layer GTel of the light emission control transistor Tel via a conduction hole HB4 penetrating the insulating layer LA.
The relay electrode QB8 is electrically connected to an active region 10A that forms a drain region or a source region of the light emission control transistor Tel through a conduction hole HA7 that penetrates the insulating film L0 and the insulating layer LA.

  5 and 6, the insulating layer LB is formed on the surface of the insulating layer LA on which the plurality of relay electrodes QB (QB1, QB2, QB3, QB4, QB5, QB6, QB7, QB8) are formed. It is formed. As understood from FIGS. 5, 6 and 9, on the surface of the insulating layer LB, the power supply wiring 41, the scanning line 22, the control line 27 of the compensation transistor Tcmp, and the control line 28 of the light emission control transistor Tel are provided. Then, a plurality of relay electrodes QC (QC1, QC2) are formed.

The power supply wiring 41 as the fourth conductive layer is electrically connected to a mounting terminal (not shown) to which a higher power supply potential Vel is supplied via a wiring (not shown) in the multilayer wiring layer. The power supply wiring 41 is formed in a display area (not shown) of the display unit 100. Although not shown, another power supply wiring is formed in the peripheral area of the display area. This power supply wiring is electrically connected to a mounting terminal (not shown) to which the lower power supply potential Vct is supplied via a wiring (not shown) in the multilayer wiring layer. The power supply wiring 41 and the power supply wiring to which the lower power supply potential Vct is supplied are made of a conductive material containing, for example, silver or aluminum and have a thickness of, for example, about 100 nm.
Further, as understood from FIG. 9, the power supply wiring 41 extends linearly in the row direction (X direction) over the plurality of pixel circuits 110. That is, the power supply wiring 41 is arranged along the row direction (X direction) so as to overlap with the driving transistor Tdr of the sub-pixel of each color in plan view.
The power supply wiring 41 is electrically connected to the active region 10A forming the drain region or the source region of the driving transistor Tdr in each color sub-pixel through the conduction hole HC1 penetrating the insulating layer LB.
The power supply wiring 41 is electrically insulated from the data transfer line 26 described later by the insulating layer LC.

  As understood from FIGS. 6 and 9, the scanning line 22 as the first conductive layer is provided so as to extend linearly in the row direction (X direction) over the plurality of pixel circuits 110. The scanning line 22 is electrically connected to the gate layer GTwr of the write control transistor Twr of each color sub-pixel through the conduction hole HC2 penetrating the insulating layer LB. The scanning line 22 is electrically insulated from the data transfer line 26 described later by the insulating layer LC.

  As understood from FIGS. 6 and 9, the control line 27 of the compensation transistor Tcmp is provided so as to extend linearly in the row direction (X direction) over the plurality of pixel circuits 110. The control line 27 is electrically connected to the gate layer GTcmp of the compensation transistor Tcmp of each color sub-pixel through the conduction hole HC4 penetrating the insulating layer LB. The control line 27 is electrically insulated from the data transfer line 26 described later by the insulating layer LC.

  As understood from FIGS. 6 and 9, the control line 28 of the light emission control transistor Tel is provided so as to extend linearly in the row direction (X direction) over the plurality of pixel circuits 110. The control line 28 is electrically connected to the gate layer GTel of the light emission control transistor Tel of the subpixel of each color through the conduction hole HC5 penetrating the insulating layer LB. The control line 28 is electrically insulated from the data transfer line 26 described later by the insulating layer LC.

  As understood from FIGS. 6 and 9, the relay electrode QC1 is electrically connected to the relay electrode QB5 through the conduction hole HC3 penetrating the insulating layer LB. Further, the relay electrode QC2 is electrically connected to the relay electrode QB8 through a conduction hole HC6 penetrating the insulating layer LB.

The insulating layer LC is an insulating layer in which a power supply line 41, a scanning line 22, a control line 27 for the compensation transistor Tcmp, a control line 28 for the light emission control transistor Tel, and a plurality of relay electrodes QC (QC1, QC2) are formed. Formed on the surface of the layer LB. As understood from FIGS. 5, 6 and 10, the data transfer line 26 and a plurality of relay electrodes QD (QD1, QD2, QD3) are formed on the surface of the insulating layer LC.
The data transfer line 26 as the second conductive layer extends linearly in the column direction (Y direction) over a plurality of pixel circuits, and is electrically isolated from reflection layers 43B, 43G, and 43R described later by the insulating layer LD. Insulated. As understood from FIG. 10, the data transfer line 26 is electrically connected to the relay electrode QC1 through the conduction hole HD2 penetrating the insulating layer LC. That is, the data transfer line 26 is connected to the drain region or source of the write control transistor Twr and the compensation transistor Tcmp via the conduction hole HD2, the relay electrode QC1, the conduction hole HC3, the relay electrode QB5, the conduction hole HA3, and the conduction hole HA5. It conducts to the active region 10A forming the region.

  As understood from FIGS. 5, 6, and 10, the relay electrode QD <b> 1 is electrically connected to the relay electrode QC <b> 2 in the B (blue) display color sub-pixel through the conduction hole HD <b> 1 penetrating the insulating layer LC. Therefore, the relay electrode QD1 is connected to the light emission control transistor Tel in the sub-pixel of B (blue) display color through the conduction hole HD1, the relay electrode QC2, the conduction hole HC6, the relay electrode QB8, and the conduction hole HA7. Conductive to the active region 10A forming the drain region or source region.

  As understood from FIGS. 5, 6, and 10, the relay electrode QD <b> 2 is electrically connected to the relay electrode QC <b> 2 in the R (red) display color sub-pixel through the conduction hole HD <b> 1 penetrating the insulating layer LC. Therefore, the relay electrode QD1 is connected to the light emission control transistor Tel in the R (red) display color sub-pixel through the conduction hole HD1, the relay electrode QC2, the conduction hole HC6, the relay electrode QB8, and the conduction hole HA7. Conductive to the active region 10A forming the drain region or source region.

  As understood from FIGS. 5, 6, and 10, the relay electrode QD <b> 3 is electrically connected to the relay electrode QC <b> 2 in the G (green) display color sub-pixel through the conduction hole HD <b> 1 penetrating the insulating layer LC. Therefore, the relay electrode QD1 is connected to the light emission control transistor Tel in the G (green) display color sub-pixel through the conduction hole HD1, the relay electrode QC2, the conduction hole HC6, the relay electrode QB8, and the conduction hole HA7. Conductive to the active region 10A forming the drain region or source region.

The insulating layer LD is formed on the surface of the insulating layer LC on which the data transfer line 26 and the plurality of relay electrodes QD (QD1, QD2, QD3) are formed. As understood from FIGS. 5, 6, and 11, reflection layers 43 </ b> B, 43 </ b> G, and 43 </ b> R as third conductive layers are formed on the surface of the insulating layer LD. The reflective layer 43B is a reflective layer in the B (blue) display color sub-pixel, and the reflective layer 43G is a reflective layer in the G (green) display color sub-pixel. The reflective layer 43R is a reflective layer in the sub-pixel of the display color R (red).
As understood from FIG. 11, the reflective layer 43B is arranged along the row direction (X direction) so as to overlap with the driving transistor Tdr of the sub-pixel of each color in plan view. Therefore, the reflective layer 43B has a driving transistor Tdr for the B (blue) subpixel, a driving transistor Tdr for the R (red) subpixel, and a driving transistor Tdr for the G (green) subpixel in the plan view, that is, a display. The color image is to be arranged along the row direction (X direction) so as to overlap with the three drive transistors Tdr constituting one pixel unit.

The reflective layer 43B is electrically connected to the relay electrode QD1 through the conductive hole HE1 that penetrates the insulating layer LD. In other words, the reflective layer 43B is a light emitting control transistor of the B (blue) sub-pixel through the conduction hole HE1, the relay electrode QD1, the conduction hole HD1, the relay electrode QC2, the conduction hole HC6, the relay electrode QB8, and the conduction hole HA7. Conduction is made to the active region 10A forming the drain region or source region of Tel.
As shown in FIG. 11, in a plan view, the reflective layers are provided in the order of the reflective layers 43B, 43G, and 43R, and the plurality of transistors of the sub-pixels of each color that overlap with the reflective layers 43B, 43G, and 43R are It becomes a plurality of transistors in a pixel of one pixel unit. Therefore, the reflective layer 43B is formed in the active region 10A that forms the drain region or the source region of the light emission control transistor Tel of the B (blue) sub-pixel in the previous pixel unit pixel in the column direction (Y direction). It will be conducted.

  The reflective layer 43R is electrically connected to the relay electrode QD2 through the conductive hole HE2 that penetrates the insulating layer LD. In other words, the reflective layer 43R includes the light emission control transistor of the R (red) sub-pixel through the conduction hole HE2, the relay electrode QD2, the conduction hole HD1, the relay electrode QC2, the conduction hole HC6, the relay electrode QB8, and the conduction hole HA7. Conduction is made to the active region 10A forming the drain region or source region of Tel.

  The reflective layer 43G is electrically connected to the relay electrode QD3 through the conductive hole HE3 that penetrates the insulating layer LD. In other words, the reflective layer 43G has the light emission control transistor of the G (green) sub-pixel through the conduction hole HE3, the relay electrode QD3, the conduction hole HD1, the relay electrode QC2, the conduction hole HC6, the relay electrode QB8, and the conduction hole HA7. Conduction is made to the active region 10A forming the drain region or source region of Tel.

  The reflective layers 43B, 43G, and 43R are formed of a light reflective conductive material containing, for example, silver or aluminum and have a thickness of, for example, about 100 nm. As shown in FIG. 11, the reflective layers 43B, 43G, and 43R are arranged so as to overlap with the transistors of the sub-pixels of each color in plan view. Therefore, the intrusion of external light is prevented by the reflective layers 43B, 43G, and 43R, and there is an advantage that current leakage of each transistor due to light irradiation can be prevented.

  In the present embodiment, the plurality of transistors in each color sub-pixel are arranged along the column direction (Y direction), but the reflective layers 43B, 43G, and 43R in each color sub-pixel are arranged in the row direction ( (X direction). Therefore, the display area of each color sub-pixel can be made horizontally long in the row direction (X direction) while the scanning line 22 is shared by the write control transistors Twr of each color sub-pixel.

The insulating layer LE is formed on the surface of the insulating layer LD on which the reflective layers 43B, 43G, and 43R are formed. A relay electrode QE1 is formed on the surface of the insulating layer LE as illustrated in FIG.
The relay electrode QE1 is electrically connected to the reflective layers 43B, 43G, and 43R through a conduction hole HF1 that penetrates the insulating layer LE. The relay electrode QE1 is one of the relay electrodes constituting the pixel electrode conducting portion. As understood from FIGS. 5 to 11, the reflective layers 43B, 43G, 43R, the plurality of relay electrodes, and the plurality of conducting holes are provided. Through the active region 10A forming the drain region or the source region of the light emission control transistor Tel.

  As illustrated in FIG. 5, the optical path adjustment layer 60 is formed on the surface of the insulating layer LE on which the relay electrode QE1 is formed. The optical path adjustment layer 60 is a light-transmitting film body that defines the resonance wavelength (that is, display color) of the resonance structure of each pixel circuit 110. In pixels with the same display color, the resonance wavelength of the resonance structure is substantially the same, and in pixels with different display colors, the resonance wavelength of the resonance structure is set to be different.

  As illustrated in FIGS. 5, 6, and 12, the first electrode E <b> 1 for each color subpixel is formed on the surface of the optical path adjustment layer 60. The first electrode E1 is formed of a light-transmitting conductive material such as ITO (Indium Tin Oxide). As described above with reference to FIGS. 3 and 4, the first electrode E <b> 1 is a substantially rectangular electrode (pixel electrode) that functions as an anode of the light emitting element 45. As understood from FIGS. 5, 6, and 12, the first electrode E <b> 1 is electrically connected to the relay electrode QE <b> 1 through the conduction hole HG <b> 1 formed in the optical path adjustment layer 60. Therefore, as understood from FIGS. 5 to 12, the first electrode E1 is connected to the light emission control transistor Tel via the optical path adjustment layer 60, the reflective layers 43B, 43G, and 43R, the plurality of relay electrodes, and the plurality of conduction holes. Conductive to the active region 10A forming the drain region or source region.

On the surface of the optical path adjustment layer 60 on which the first electrode E1 is formed, the pixel definition layer 65 is formed over the entire area of the substrate 10 as illustrated in FIGS. The pixel definition layer 65 is formed of an insulating inorganic material such as a silicon compound (typically silicon nitride or silicon oxide). As understood from FIG. 12, the pixel definition layer 65 forms an opening corresponding to the first electrode E1 in the sub-pixel of each display color.
The size of the opening is the largest for the B (blue) sub-pixel, and the size of the opening for the G (green) and R (red) sub-pixels is the same. It has become. However, the size of the opening may be different between sub-pixels having different display colors.
In the column direction (Y direction), the openings are arranged at a common pitch in the order of B (blue), G (green), and R (red) subpixels. Further, the openings of the sub-pixels of the same color are arranged at a common pitch in the row direction (X direction).

  As shown in FIGS. 5 and 6, the light emitting functional layer 46, the second electrode E2, and the sealing body 47 are laminated on the upper layer of the first electrode E1, and the surface of the substrate 10 on which the above elements are formed. A sealing substrate (not shown) is bonded to, for example, an adhesive. The sealing substrate is a light-transmitting plate member (for example, a glass substrate) for protecting each element on the substrate 10. A color filter is formed for each pixel circuit of the sub-pixel on the surface of the sealing substrate or the surface of the sealing body 47. As the color filter, a B (blue) color filter CFB, a G (green) color filter CFG, and an R (red) color filter CFR are used.

  As described above, in the present embodiment, since the plurality of transistors in each color sub-pixel are arranged along the column direction (Y direction), the scanning line 22 is used as the write control transistor Twr for each color sub-pixel. And the number of scanning lines 22 selected in one horizontal scanning period is not increased. As a result, the selection time of each scanning line 22 in one horizontal scanning period can be prevented from being shortened, and data can be reliably written from the data transfer line 26 to the first electrode E1.

  In the present embodiment, the reflective layers 43B, 43G, and 43R in the subpixels of each color are arranged in the row direction (X direction) while arranging the plurality of transistors in the subpixels of each color along the column direction (Y direction). Arrange along. Therefore, even when the design is such that the direction in which the principal ray of the electro-optical device 1 is largely inclined is the row direction (X direction), the same color can be obtained without increasing the number of scanning lines 22. The subpixels can be arranged in the row direction (X direction) of the display surface. As a result, even when the display surface is observed obliquely, the electro-optical device 1 is provided that hardly causes a color shift in the row direction (X direction).

  In the present embodiment, the reflective layers 43B, 43G, and 43R in the subpixels of each color are arranged along the row direction (X direction) so as to overlap the transistors in the subpixels of each color. Therefore, the light from the light emitting functional layer 46 can be prevented from being irradiated to the transistor, and the characteristics of the transistor are not changed. In particular, the reflective layer 43B in the blue subpixel having the largest area is disposed so as to overlap the driving transistor Tdr in each color subpixel. Therefore, irradiation of light from the light emitting functional layer 46 to the driving transistor Tdr that affects fine gradation display is surely prevented, and changes in characteristics of the driving transistor Tdr are prevented, thereby enabling accurate gradation display.

  In the present embodiment, the reflective layer 43B in the blue sub-pixel and the transistor in each color sub-pixel are arranged along the row direction (X direction) so as to overlap the driving transistor Tdr in each color sub-pixel. A power supply wiring 41 is provided. Therefore, the light from the light emitting functional layer 46 is blocked not only by the reflective layer 43B but also by the power supply wiring 41 having a relatively larger area than other wirings, so that the driving transistor Tdr is irradiated more reliably. Can be prevented. Therefore, the irradiation of light from the light emitting functional layer 46 to the driving transistor Tdr that affects fine gradation display can be prevented more reliably, and the characteristic of the driving transistor Tdr can be prevented from changing, thereby enabling accurate gradation display. To do.

  In this embodiment, the power supply wiring 41 is formed on the relay electrodes QD1, QD2, and QD3 that connect the reflective layers 43B, 43G, and 43R in the subpixels of each color and the light emission control transistor Tel in the subpixel of each color. It is formed in a layer between the layer and the layer in which the reflective layers 43B, 43G, and 43R are formed. Therefore, noise from the relay electrodes QD1, QD2, and QD3 through which a large current flows is blocked by the power supply wiring 41, and the influence of noise on the drive transistor Tdr can be suppressed.

  In the present embodiment, the area of the reflective layer 43B is different from the areas of the reflective layers 43G and 43R. The area of the reflective layer 43B is the largest, and the areas of the reflective layers 43G and 43R are the same as each other and smaller than the area of the reflective layer 43B. That is, the areas of at least two of the reflective layers 43B, 43G, and 43R are set to be different from each other. The relay electrodes QD1, QD3, and QD2 that connect the reflective layers 43B, 43G, and 43R in the sub-pixels of each color and the light emission control transistor Tel in the sub-pixel of each color are below the reflective layers 43G and 43R having the smallest area. It is formed. Therefore, the lengths of the relay electrodes QD1, QD3, QD2 can be shortened. As a result, noise from the relay electrodes QD1, QD3, and QD2 through which a large current flows can be reduced, and the influence of the noise on the driving transistor Tdr can be suppressed to a low level.

  Further, in the present embodiment, the conduction hole HD1, which is a connection portion connecting the relay electrodes QD1, QD2, QD3 and the light emission control transistor Tel, is near the reflection layers 43G, 43R which are the smallest reflection layers in plan view. Located in the lower layer. Also with this configuration, the length of the relay electrodes QD1, QD2, and QD3 can be shortened. As a result, noise from the relay electrodes QD1, QD2, and QD3 through which a large current flows can be reduced, and the influence of the noise on the drive transistor Tdr can be suppressed to a low level.

  Further, the relay electrodes QD1, QD2, and QD3 are formed in the same layer as the data transfer line 26, and are located between one data transfer line 26 adjacent in the row direction and the other data transfer line 26. . Accordingly, parasitic capacitance is formed between the data transfer line 26 and the relay electrodes QD1, QD2, and QD3. In order to reduce the parasitic capacitance, it is preferable that the relay electrodes QD1, QD2, and QD3 are located at substantially the center of one adjacent data transfer line 26 and another data transfer line 26. As a result, the time for writing data to the data transfer line 26 and the time for writing data from the data transfer line 26 to the first electrode E1 can be shortened.

  In the above-described embodiment, as can be understood from FIGS. 10 and 11, the position of the conduction hole HD1, which is a connection portion connecting the relay electrodes QD1, QD2, and QD3 and the light emission control transistor Tel, is reflected. The layer 43R is disposed at a position displaced from the center line in the row direction.

However, the present invention is not limited to such a configuration. For example, as shown in FIG. 13 and FIG. 14, the connection portion that connects the relay electrodes QD1, QD2, and QD3 and the light emission control transistor Tel is used. The position of a certain conduction hole HD1 may be arranged on the center line in the row direction of the reflective layer 43R.
13 is a diagram corresponding to FIG. 10, and FIG. 14 is a diagram corresponding to FIG. As understood from FIGS. 13 and 14, the position of the conduction hole HD1, which is a connection portion connecting the relay electrodes QD1, QD2, and QD3 and the light emission control transistor Tel, is the center line III in the row direction of the reflective layer 43R. Located on -III '. By doing in this way, the length of the relay electrode QD1 and the relay electrode QD3 can be made equal. As a result, the variation in each subpixel can be suppressed low. Further, since the lengths of the relay electrode QD1 and the relay electrode QD3 can be minimized, noise from the relay electrodes QD1, QD2, and QD3 through which a large current flows is reduced, and the influence of the noise on the driving transistor Tdr is reduced. Can be suppressed.

Second Embodiment
Next, a second embodiment of the present invention will be described with reference to FIG. 15 to 20 correspond to FIGS. 7 to 12 of the first embodiment, respectively. The parts common to the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  In the first embodiment, as shown in FIG. 7, the sub-pixels are arranged in the order of the drive transistor Tdr, the write control transistor Twr, the compensation transistor Tcmp, and the light emission control transistor Tel along the column direction (in the Y direction). The configuration in which the transistors are arranged has been described.

  However, in the second embodiment, as shown in FIG. 15, the light emission control transistor Tel, the drive transistor Tdr, the write control transistor Twr, and the compensation transistor Tcmp are arranged in the order along the column direction (in the Y direction). Sub-pixel transistors are arranged.

  In the first embodiment, as shown in FIG. 11, along the column direction (in the Y direction), the blue subpixel reflective layer 43B, the green subpixel reflective layer 43G, and the red subpixel are arranged. The reflective layers were arranged in the order of the reflective layers 43R. However, in this embodiment, as shown in FIG. 19, along the column direction (in the Y direction), the green sub-pixel reflective layer 43G, the blue sub-pixel reflective layer 43B, and the red sub-pixel The reflective layers were arranged in the order of the reflective layer 43R.

  As can be understood from FIG. 15 to FIG. 20, also in this embodiment, the plurality of transistors in the sub-pixels of each color are arranged along the column direction (Y direction). Therefore, the scanning lines 22 can be shared by the write control transistors Twr of the sub-pixels of each color, and the number of scanning lines 22 selected in one horizontal scanning period is not increased. As a result, the selection time of each scanning line 22 in one horizontal scanning period can be prevented from being shortened, and data can be reliably written from the data transfer line 26 to the first electrode E1.

  Also in this embodiment, the reflective layers 43G, 43B, and 43R in the subpixels of each color are arranged in the row direction (X direction) while arranging the plurality of transistors in the subpixels of each color along the column direction (Y direction). Arrange along. Therefore, even when the design is such that the direction in which the principal ray of the electro-optical device 1 is largely inclined is the row direction (X direction), the same color can be obtained without increasing the number of scanning lines 22. The subpixels can be arranged in the row direction (X direction) of the display surface. As a result, even when the display surface is observed obliquely, the electro-optical device 1 is provided that hardly causes a color shift in the row direction (X direction).

Furthermore, also in this embodiment, the reflective layers 43B, 43G, and 43R in the subpixels of each color are arranged along the row direction (X direction) so as to overlap the transistors in the subpixels of each color. Therefore, the light from the light emitting functional layer 46 can be prevented from being irradiated to the transistor, and the characteristics of the transistor are not changed. In particular, the reflective layer 43B in the blue subpixel having the largest area is disposed so as to overlap the driving transistor Tdr in each color subpixel. Therefore, irradiation of light from the light emitting functional layer 46 to the driving transistor Tdr that affects fine gradation display is surely prevented, and changes in characteristics of the driving transistor Tdr are prevented, thereby enabling accurate gradation display.
In the present embodiment, the areas of the reflective layers 43B, 43G, and 43R in the subpixels of the respective colors are different. The area of the reflective layer 43B in the blue subpixel is the largest, and the area of the reflective layer 43R in the red subpixel is smaller than the area of the reflective layer 43B. The area of the reflective layer 43G in the green subpixel is the smallest.

  Also in the present embodiment, the reflective layer 43B in the blue sub-pixel and the transistor in the sub-pixel of each color are arranged along the row direction (X direction) so as to overlap the driving transistor Tdr in the sub-pixel of each color. A power supply wiring 41 is provided. Therefore, the light from the light emitting functional layer 46 is blocked not only by the reflective layer 43B but also by the power supply wiring 41 having a relatively larger area than other wirings, so that the driving transistor Tdr is irradiated more reliably. Can be prevented. Therefore, the irradiation of light from the light emitting functional layer 46 to the driving transistor Tdr that affects fine gradation display can be prevented more reliably, and the characteristic of the driving transistor Tdr can be prevented from changing, thereby enabling accurate gradation display. To do.

  As understood from FIGS. 18 and 19, also in this embodiment, the relay electrodes QD1, QD2, and QD3 are composed of the layer in which the power supply wiring 41 is formed and the layer in which the reflection layers 43G, 43B, and 43R are formed. It is formed in the middle layer. Therefore, noise from the relay electrodes QD1, QD2, and QD3 through which a large current flows is blocked by the power supply wiring 41, and the influence of noise on the drive transistor Tdr can be suppressed.

As can be understood from FIG. 19, in the present embodiment, the conduction hole HD1, which is a connection portion that connects the relay electrodes QD1, QD2, and QD3 and the light emission control transistor Tel, is the reflective layer having the smallest area in plan view. It is located in the lower layer near the reflective layer 43G. Also with this configuration, the length of the relay electrodes QD1, QD2, and QD3 can be shortened. As a result, noise from the relay electrodes QD1, QD2, and QD3 through which a large current flows can be reduced, and the influence of the noise on the drive transistor Tdr can be suppressed to a low level.
Further, in this embodiment, as can be understood from FIG. 19, the conduction hole HD1, which is a connecting portion for connecting the relay electrodes QD1, QD2, and QD3 and the light emission control transistor Tel, is adjacent to the reflective layer in the column direction. It is provided at a position between 43G and the reflective layer 43B. Therefore, as shown in FIG. 18, at least the lengths of the relay electrodes QD1, QD3 can be equalized. As a result, variation due to the difference in the length of the relay electrode can be suppressed at least between adjacent subpixels.

  In the present embodiment, the drive transistor Tdr is arranged next to the light emission control transistor Tel along the column direction (in the Y direction). Therefore, the position of the conduction hole HD1, which is a connection portion connecting the relay electrodes QD1, QD2, QD3 and the light emission control transistor Tel, is arranged in the column direction of the plurality of transistors arranged in the column direction (in the Y direction) ( It is located at a place other than the end in (Y direction). This configuration is different from the first embodiment. With this configuration, the position of the conduction hole HD1 serving as the pixel contact portion can be easily matched with the arrangement of the reflective layers 43G, 43B, and 43R. As a result, it is possible to prevent light from the light emitting functional layer 46 from being applied to the drive transistor Tdr by the reflective layers 43G, 43B, and 43R within the same pixel unit.

  As can be understood from FIG. 18, also in this embodiment, the relay electrodes QD1, QD2, and QD3 are formed in the same layer as the data transfer line 26, and one data transfer line 26 adjacent in the row direction, It is located between other data transfer lines 26. Accordingly, parasitic capacitance is formed between the data transfer line 26 and the relay electrodes QD1, QD2, and QD3. In order to reduce the parasitic capacitance, it is preferable that the relay electrodes QD1, QD2, and QD3 are located at substantially the center of one adjacent data transfer line 26 and another data transfer line 26. As a result, the time for writing data to the data transfer line 26 and the time for writing data from the data transfer line 26 to the first electrode E1 can be shortened.

<Third Embodiment>
Next, a third embodiment of the present invention will be described with reference to FIG. In the present embodiment, the transistor of each subpixel is composed of three transistors: a drive transistor Tdr, a light emission control transistor Tel, and a write control transistor Twr.

FIGS. 21 to 26 are plan views for explaining each element formed on the substrate 10 in the electro-optical device 1 of the present embodiment. FIG. 27 is a cross-sectional view corresponding to the cross section including the IV-IV ′ line in FIG. 26. FIG. 28 is a cross-sectional view corresponding to the cross section including the line VV ′ in FIG. Although FIG. 21 to FIG. 26 are plan views, from the viewpoint of facilitating visual grasp of each element, the same elements as FIG. 27 and FIG. It is added for convenience.
In FIG. 21 to FIG. 26, a rectangle indicated by a dotted line represents the position of the reflective layer of each subpixel.

In this embodiment, as understood from FIG. 21, the channel length direction of the drive transistor Tdr, the light emission control transistor Tel, and the write control transistor Twr of each subpixel is the column direction (Y direction), and the light emission control transistor Tel and the write control transistor Twr are arranged in a straight line.
The light emission control transistor Tel and the write control transistor Twr are arranged in the row direction (X direction) with respect to the drive transistor Tdr of each subpixel. However, when viewed in units of G (green), R (red), and B (blue) subpixels, in this embodiment as well, the plurality of transistors in the subpixels are arranged in the column direction (Y direction). Are arranged.
In the present embodiment, the connection portion between the gate layers GTdr, GTwr, and GTel of each transistor and the control line is provided at a position shifted in the row direction (X direction), not on the channel. Yes.

  As understood from FIGS. 21, 27 and 28, the active region 10A (source / source) of each transistor (Tdr, Twr, Tel) of the pixel circuit 110 is formed on the surface of the substrate 10 made of a semiconductor material such as silicon. Drain region) is formed. Ions are implanted into the active region 10A. The active layer of each transistor (Tdr, Twr, Tel) of the pixel circuit 110 exists between the source region and the drain region, and ions of a different type from the active region 10A are implanted, but for convenience, the active region 10A. It is described as one. As understood from FIGS. 21, 27 and 28, the surface of the substrate 10 on which the active region 10A is formed is covered with an insulating film L0 (gate insulating film), and the gate layer GT (GTdr, GTwr, GTel) of each transistor. ) Is formed on the surface of the insulating film L0. The gate layer GT of each transistor faces the active layer with the insulating film L0 interposed therebetween.

  As understood from FIGS. 27 and 28, on the surface of the insulating film L0 on which the gate layer GT of each transistor is formed, a plurality of insulating layers L (LA to LF), a plurality of conductive layers (wiring layers), and A multilayer wiring layer is formed by alternately stacking layers. Each insulating layer L is formed of an insulating inorganic material such as a silicon compound (typically silicon nitride or silicon oxide). In the following description, a relationship in which a plurality of elements are collectively formed in the same process by selective removal of a conductive layer (single layer or a plurality of layers) is referred to as “formed from the same layer”.

  The insulating layer LA is formed on the surface of the insulating film L0 on which the gate layer GT of each transistor is formed. As understood from FIGS. 21, 27, and 28, on the surface of the insulating layer LA, the control line 28 of the light emission control transistor Tel, the scanning line 22, and a plurality of relay electrodes QB (QB10, QB11, QB12, QB13, QB14) are formed from the same layer.

  As understood from FIGS. 22, 27, and 28, the scanning line 22 as the first conductive layer is provided so as to extend linearly in the row direction (X direction) across the plurality of pixel circuits 110. The scanning line 22 is electrically connected to the gate layer GTwr of the write control transistor Twr of each color sub-pixel through the conduction hole HB12 that penetrates the insulating layer LA. The scanning line 22 is electrically insulated from the data transfer line 26 described later by the insulating layer LB.

  As understood from FIGS. 22, 27, and 28, the control line 28 of the light emission control transistor Tel is provided so as to extend linearly in the row direction (X direction) over the plurality of pixel circuits 110. The control line 28 is electrically connected to the gate layer GTel of the light emission control transistor Tel of the subpixel of each color through the conduction hole HB11 penetrating the insulating layer LA. The control line 28 is electrically insulated from the data transfer line 26 described later by the insulating layer LB.

As understood from FIGS. 22, 27, and 28, the relay electrode QB <b> 10 is an active region that forms the drain region or the source region of the drive transistor Tdr through the conduction hole HA <b> 11 that penetrates the insulating film L <b> 0 and the insulating layer LA. Conducts to 10A.
The relay electrode QB10 is electrically connected to an active region 10A that forms a drain region or a source region of the light emission control transistor Tel through a conduction hole HA12 that penetrates the insulating film L0 and the insulating layer LA.
The relay electrode QB11 is electrically connected to the gate layer GTdr of the drive transistor Tdr via a conduction hole HB10 that penetrates the insulating layer LA. The relay electrode QB11 is electrically connected to the active region 10A forming the source region or the drain region of the write control transistor Twr through the conduction hole HA14 that penetrates the insulating layer LA and the insulating film L0.
The relay electrode QB12 is electrically connected to an active region 10A that forms a drain region or a source region of the drive transistor Tdr through a conduction hole HA10 that penetrates the insulating film L0 and the insulating layer LA.
The relay electrode QB13 is electrically connected to an active region 10A that forms a drain region or a source region of the drive transistor Tdr through a conduction hole HA13 that penetrates the insulating film L0 and the insulating layer LA.
The relay electrode QB14 is electrically connected to the active region 10A that forms the drain region or the source region of the write control transistor Twr through the conduction hole HA15 that penetrates the insulating film L0 and the insulating layer LA.

  As understood from FIGS. 23, 27, and 28, the insulating layer LB is an insulating layer in which the control line 28, the scanning line 22, and the plurality of relay electrodes QB (QB10, QB11, QB12, QB13, QB14) are formed. It is formed on the surface of the layer LA. A data transfer line 26 and a plurality of relay electrodes QC (QC10, QC11, QC12) are formed on the surface of the insulating layer LB.

  The data transfer line 26 as the second conductive layer extends linearly in the column direction (Y direction) over a plurality of pixel circuits, and is electrically isolated from the reflection layers 43B, 43G, and 43R described later by the insulating layer LC. Insulated. As understood from FIG. 23, the data transfer line 26 is formed integrally with the relay electrode QC12 extending in the row direction (X direction) with respect to the data transfer line 26. The relay electrode QC12 is electrically connected to the active region 10A forming the source region or the drain region of the write control transistor Twr through the conduction hole HC12 penetrating the insulating layer LB.

  As understood from FIGS. 23, 27, and 28, the relay electrode QC10 is electrically connected to the relay electrode QB12 through the conduction hole HC10 penetrating the insulating layer LB. The relay electrode QC11 is electrically connected to the relay electrode QC13 through a conduction hole HC11 penetrating the insulating layer LB.

  The insulating layer LC is formed on the surface of the insulating layer LB on which the data transfer line 26 and the plurality of relay electrodes QC (QC10, QC11, QC12) are formed. As understood from FIGS. 24, 27, and 28, the power supply wiring 41 as the fourth conductive layer and the relay electrode QD10 are formed on the surface of the insulating layer LC.

  The power supply wiring 41 as the fourth conductive layer is electrically connected to a mounting terminal (not shown) to which a higher power supply potential Vel is supplied via a wiring (not shown) in the multilayer wiring layer. The power supply wiring 41 is formed in a display area (not shown) of the display unit 100. Although not shown, another power supply wiring is formed in the peripheral area of the display area. This power supply wiring is electrically connected to a mounting terminal (not shown) to which the lower power supply potential Vct is supplied via a wiring (not shown) in the multilayer wiring layer. The power supply wiring 41 and the power supply wiring to which the lower power supply potential Vct is supplied are made of a conductive material containing, for example, silver or aluminum and have a thickness of, for example, about 100 nm.

  Further, as can be understood from FIG. 24, the power supply wiring 41 is formed on the entire surface except the portion where the relay electrode QD10 is formed. That is, the power supply wiring 41 overlaps with the drive transistor Tdr, the write control transistor Twr, and the light emission control transistor Tel of the R (red), G (green), and B (blue) subpixels in plan view. In this way, each subpixel is arranged along the column direction (Y direction). In the first embodiment and the second embodiment, the power supply wiring 41 is disposed so as to overlap the driving transistor Tdr of the subpixel of each color. However, in the present embodiment, the power supply wiring 41 is disposed so as to overlap all the transistors of the sub-pixels of each color.

The power supply wiring 41 is electrically connected to the active region 10A forming the drain region or the source region of the driving transistor Tdr in each color sub-pixel through the conduction hole HD10 penetrating the insulating layer LC.
The power supply wiring 41 is electrically insulated from the data transfer line 26 by the insulating layer LC.

  As shown in FIG. 24, the power supply wiring 41 has an opening formed in the vicinity of the center, and the relay electrode QD10 is formed in the opening. The relay electrode QD10 is electrically connected to the relay electrode QC11 through a conduction hole HD11 penetrating the insulating layer LC.

  The insulating layer LD is formed on the surface of the insulating layer LC on which the power supply wiring 41 and the relay electrode QD10 are formed. As understood from FIGS. 25, 27, and 28, relay electrodes QE10, QE11, QE12 as fifth conductive layers are formed on the surface of the insulating layer LD.

  As understood from FIGS. 25, 27, and 28, the relay electrode QE10 is electrically connected to the relay electrode QD10 in the R (red) display color sub-pixel through the conduction hole HE10 penetrating the insulating layer LD. Therefore, the relay electrode QE10 has the R (red) via the conduction hole HE10, the relay electrode QD10, the conduction hole HD11, the relay electrode QC11, the conduction hole HC11, the relay electrode QB13, and the conduction hole HA13. The light emitting control transistor Tel in the display color sub-pixel is electrically connected to the drain region or the source region.

  As understood from FIGS. 25, 27, and 28, the relay electrode QE11 is electrically connected to the relay electrode QD10 in the sub-pixel of the G (green) display color through the conduction hole HE10 penetrating the insulating layer LD. Therefore, the relay electrode QE11 is connected to the G (green) via the conduction hole HE10, the relay electrode QD10, the conduction hole HD11, the relay electrode QC11, the conduction hole HC11, the relay electrode QB13, and the conduction hole HA13. The light emitting control transistor Tel in the display color sub-pixel is electrically connected to the drain region or the source region.

  As understood from FIGS. 25, 27, and 28, the relay electrode QE12 is electrically connected to the relay electrode QD10 in the sub-pixel of the display color B (blue) through the conduction hole HE10 penetrating the insulating layer LD. Therefore, the relay electrode QE12 has the B (blue) via the conduction hole HE10, the relay electrode QD10, the conduction hole HD11, the relay electrode QC11, the conduction hole HC11, the relay electrode QB13, and the conduction hole HA13. The light emitting control transistor Tel in the display color sub-pixel is electrically connected to the drain region or the source region.

The insulating layer LE is formed on the surface of the insulating layer LD on which the plurality of relay electrodes QE10, QE11, QE12 as the fifth conductive layer are formed. As understood from FIGS. 26 to 28, reflection layers 43B, 43G, and 43R as third conductive layers are formed on the surface of the insulating layer LE. The reflective layer 43B is a reflective layer in the B (blue) display color sub-pixel, and the reflective layer 43G is a reflective layer in the G (green) display color sub-pixel. The reflective layer 43R is a reflective layer in the sub-pixel of the display color R (red).
As understood from FIG. 26, the reflective layer 43B is arranged along the row direction (X direction) so as to overlap at least the drain region of the drive transistor Tdr of each color sub-pixel in plan view.
The reflective layer 43G is arranged along the row direction (X direction) so as to overlap the gate layer GTdr of the driving transistor Tdr of each color sub-pixel in plan view.
The reflective layer 43R is arranged along the row direction (X direction) so as to overlap at least the drain region of the drive transistor Tdr of each color sub-pixel in plan view.

  The reflective layer 43B is electrically connected to the relay electrode QE12 through the conductive hole HF12 that penetrates the insulating layer LE. That is, the reflective layer 43B is electrically connected to the active region 10A that forms the drain region or the source region of the light emission control transistor Tel in the sub-pixel of B (blue) display color through the plurality of conduction holes and the plurality of relay electrodes. . The plurality of conduction holes are a conduction hole HF12, a conduction hole HE10, a conduction hole HD11, a conduction hole HC11, and a conduction hole HA13. The plurality of relay electrodes are the relay electrode QE12, the relay electrode QD10, the relay electrode QC11, and the relay electrode QB13.

  The reflective layer 43G is electrically connected to the relay electrode QE11 through the conductive hole HF11 that penetrates the insulating layer LE. That is, the reflective layer 43G is electrically connected to the active region 10A that forms the drain region or the source region of the light emission control transistor Tel in the G (green) display color sub-pixel through the plurality of conduction holes and the plurality of relay electrodes. . The plurality of conduction holes are a conduction hole HF11, a conduction hole HE10, a conduction hole HD11, a conduction hole HC11, and a conduction hole HA13. The plurality of relay electrodes are the relay electrode QE11, the relay electrode QD10, the relay electrode QC11, and the relay electrode QB13.

  The reflective layer 43R is electrically connected to the relay electrode QE10 through a conduction hole HF10 that penetrates the insulating layer LE. That is, the reflective layer 43R is electrically connected to the active region 10A that forms the drain region or the source region of the light emission control transistor Tel in the sub-pixel of the display color of R (red) through the plurality of conduction holes and the plurality of relay electrodes. . The plurality of conduction holes are a conduction hole HF10, a conduction hole HE10, a conduction hole HD11, a conduction hole HC11, and a conduction hole HA13. The plurality of relay electrodes are the relay electrode QE10, the relay electrode QD10, the relay electrode QC11, and the relay electrode QB13.

  As shown in FIG. 26, in the plan view, the reflective layers are provided in the order of the reflective layers 43B, 43G, and 43R, and the plurality of transistors of the sub-pixels of each color that overlap with the reflective layers 43B, 43G, and 43R It becomes a plurality of transistors in a pixel of one pixel unit.

  The reflective layers 43B, 43G, and 43R are formed of a light reflective conductive material containing, for example, silver or aluminum and have a thickness of, for example, about 100 nm. As shown in FIG. 26, the reflective layers 43B, 43G, and 43R are arranged so as to overlap the transistors of the sub-pixels of each color in plan view. Therefore, the intrusion of external light is prevented by the reflective layers 43B, 43G, and 43R, and there is an advantage that current leakage of each transistor due to light irradiation can be prevented.

  In the present embodiment, the plurality of transistors in each color sub-pixel are arranged along the column direction (Y direction), but the reflective layers 43B, 43G, and 43R in each color sub-pixel are arranged in the row direction ( (X direction). Therefore, the display area of each color sub-pixel can be made horizontally long in the row direction (X direction) while the scanning line 22 is shared by the write control transistors Twr of each color sub-pixel.

  In this embodiment, the area of the reflective layer is the same as the areas of the reflective layer 43B and the reflective layer 43R, and the area of the reflective layer 43R is set to be the smallest.

The insulating layer LF is formed on the surface of the insulating layer LE on which the reflective layers 43B, 43G, and 43R are formed. A planarization process is performed on the surface of the insulating layer LF. For the planarization treatment, a known surface treatment technique such as chemical mechanical polishing (CMP) is arbitrarily employed. As illustrated in FIG. 27, the relay electrode QF10 is formed on the surface of the insulating layer LF highly planarized by the planarization process.
The relay electrode QF10 is electrically connected to the reflective layers 43B, 43G, and 43R through a conduction hole HG10 that penetrates the insulating layer LF. The relay electrode QF10 is one of the relay electrodes constituting the pixel electrode conducting portion. As understood from FIGS. 21 to 28, the reflective layers 43B, 43G, 43R, the plurality of relay electrodes, and the plurality of conduction holes are provided. Through the active region 10A forming the drain region or the source region of the light emission control transistor Tel.

  As illustrated in FIG. 27, the optical path adjustment layer 60 is formed on the surface of the insulating layer LF on which the relay electrode QF10 is formed. The optical path adjustment layer 60 is a light-transmitting film body that defines the resonance wavelength (that is, display color) of the resonance structure of each pixel circuit 110. In pixels with the same display color, the resonance wavelength of the resonance structure is substantially the same, and in pixels with different display colors, the resonance wavelength of the resonance structure is set to be different. In the present embodiment, as shown in FIG. 28, the optical path adjustment layer 60 is formed in three layers in the sub-pixel of the display color of R (red). Further, the optical path adjustment layer 60 is formed in two layers in the G (green) display color sub-pixel. The optical path adjustment layer 60 is formed in one layer in the sub-pixel of the B (blue) display color.

  As illustrated in FIGS. 27 and 28, the first electrode E <b> 1 for each subpixel of each color is formed on the surface of the optical path adjustment layer 60. The first electrode E1 is formed of a light-transmitting conductive material such as ITO (Indium Tin Oxide). As described above with reference to FIGS. 3 and 4, the first electrode E <b> 1 is a substantially rectangular electrode (pixel electrode) that functions as an anode of the light emitting element 45. As understood from FIG. 27, the first electrode E1 is electrically connected to the relay electrode QF10 through the conduction hole HH10 formed in the optical path adjustment layer 60. Therefore, the first electrode E1 is electrically connected to the drain region or the source region of the light emission control transistor Tel through the optical path adjustment layer 60, the reflective layers 43B, 43G, and 43R, the plurality of relay electrodes, and the plurality of conduction holes.

On the surface of the optical path adjustment layer 60 on which the first electrode E1 is formed, the pixel definition layer 65 is formed over the entire area of the substrate 10 as illustrated in FIGS. The pixel definition layer 65 is formed of an insulating inorganic material such as a silicon compound (typically silicon nitride or silicon oxide). Although not shown, the pixel definition layer 65 forms an opening corresponding to the first electrode E1 in each display color sub-pixel.
The size of the opening is the same as that of the B (blue) subpixel and the R (red) subpixel, and the opening of the G (green) and R (red) subpixels. Is the smallest. However, the size of the opening may be different between sub-pixels having different display colors.
In the column direction (Y direction), the openings are arranged at a common pitch in the order of B (blue), G (green), and R (red) subpixels. In addition, the openings of sub-pixels of the same color are arranged at a common pitch in the row direction (X direction).

  As shown in FIGS. 27 and 28, the light emitting functional layer 46, the second electrode E2, and the sealing body 47 are laminated on the upper layer of the first electrode E1, and the surface of the substrate 10 on which the above-described elements are formed. A sealing substrate (not shown) is bonded to, for example, an adhesive. The sealing substrate is a light-transmitting plate member (for example, a glass substrate) for protecting each element on the substrate 10. A color filter is formed for each pixel circuit of the sub-pixel on the surface of the sealing substrate or the surface of the sealing body 47. As the color filter, a B (blue) color filter CFB, a G (green) color filter CFG, and an R (red) color filter CFR are used.

  As described above, in the present embodiment, since the plurality of transistors in each color sub-pixel are arranged along the column direction (Y direction), the scanning line 22 is used as the write control transistor Twr for each color sub-pixel. And the number of scanning lines 22 selected in one horizontal scanning period is not increased. As a result, the selection time of each scanning line 22 in one horizontal scanning period can be prevented from being shortened, and data can be reliably written from the data transfer line 26 to the first electrode E1.

  In the present embodiment, the reflective layers 43B, 43G, and 43R in the subpixels of each color are arranged in the row direction (X direction) while arranging the plurality of transistors in the subpixels of each color along the column direction (Y direction). Arrange along. Therefore, even if the direction in which the chief ray of the electro-optical device 1 is largely inclined is the row direction (X direction), the sub-color of the same color can be obtained without increasing the number of scanning lines 22. Pixels can be arranged in the row direction (X direction) of the display surface. As a result, even when the display surface is observed obliquely, the electro-optical device 1 is provided that hardly causes a color shift in the row direction (X direction).

In the present embodiment, the reflective layers 43B, 43G, and 43R in the subpixels of each color are arranged along the row direction (X direction) so as to overlap the transistors in the subpixels of each color. Therefore, the light from the light emitting functional layer 46 can be prevented from being irradiated to the transistor, and the characteristics of the transistor are not changed. In particular, the reflective layer 43B in the blue subpixel having the largest area is disposed so as to overlap at least the drain region of the drive transistor Tdr in each color subpixel. In addition, the reflective layer 43R in the red subpixel having the same area as the reflective layer 43B of the blue subpixel is disposed so as to overlap at least the drain region of the drive transistor Tdr in the subpixel of each color. Further, the reflective layer 43G in the green subpixel having the smallest area is arranged so as to overlap the gate layer GTdr of the driving transistor Tdr in each color subpixel. Therefore, irradiation of light from the light emitting functional layer 46 to the driving transistor Tdr that affects fine gradation display is surely prevented, and changes in characteristics of the driving transistor Tdr are prevented, thereby enabling accurate gradation display.
In addition, there are gaps between the reflective layer 43B and the reflective layer 43G in the column direction and between the reflective layer 43G and the reflective layer 43R in the column direction. These gaps are formed in the active region 10A of the drive transistor Tdr. It is arranged so as to be located on the gate layer GTdr, not on the top. Therefore, even if light leaks from these gaps, the active region 10A of the driving transistor Tdr is not directly affected, so that a change in characteristics of the driving transistor Tdr is prevented and accurate gradation display is performed. Is possible.

  In the present embodiment, between the reflective layers 43B, 43G, and 43R in each color sub-pixel and the plurality of transistors in each color sub-pixel, the column direction (Y direction) overlaps with the plurality of transistors in each color sub-pixel. Power supply wirings 41R, 41G, and 41B arranged along the lines are provided. Therefore, the light from the light emitting functional layer 46 is blocked not only by the reflection layers 43B, 43G, and 43R but also by the power supply wirings 41R, 41G, and 41B, so that the drive transistor Tdr is more reliably irradiated. Can be prevented. Therefore, the irradiation of light from the light emitting functional layer 46 to the driving transistor Tdr that affects fine gradation display can be prevented more reliably, and the characteristic of the driving transistor Tdr can be prevented from changing, thereby enabling accurate gradation display. To do.

  In this embodiment, the power supply wiring 41 is formed on the relay electrodes QD1, QD2, and QD3 that connect the reflective layers 43B, 43G, and 43R in the subpixels of each color and the light emission control transistor Tel in the subpixel of each color. It is formed in a layer between the layer and the layer in which the reflective layers 43B, 43G, and 43R are formed. Therefore, noise from the relay electrodes QD1, QD2, and QD3 through which a large current flows is blocked by the power supply wiring 41, and the influence of noise on the drive transistor Tdr can be suppressed.

  In the present embodiment, the area of the reflective layer 43B is different from the areas of the reflective layers 43G and 43R. The areas of the reflective layer 43B and the reflective layer 43R are the largest, and the area of the reflective layer 43G is the smallest. That is, the areas of at least two of the reflective layers 43B, 43G, and 43R are set to be different from each other. The relay electrodes QE12, QE11, and QE10 that connect the reflective layers 43B, 43G, and 43R in each color sub-pixel and the light emission control transistor Tel in each color sub-pixel are formed below the reflective layer 43G that has the smallest area. The Therefore, the length of the relay electrodes QE12, QE11, QE10 can be shortened. As a result, noise from the relay electrodes QE12, QE11, QE10 through which a large current flows can be reduced, and the influence of the noise on the drive transistor Tdr can be suppressed to a low level.

  Further, in the present embodiment, the conduction hole HE10 that is a connection part that connects the relay electrodes QE12, QE11, and QE10 and the light emission control transistor Tel is a lower layer near the reflection layer 43G that is the smallest reflection layer in plan view. Is located. Also with this configuration, the length of the relay electrodes QE12, QE11, QE10 can be shortened. As a result, noise from the relay electrodes QE12, QE11, QE10 through which a large current flows can be reduced, and the influence of the noise on the drive transistor Tdr can be suppressed to a low level.

  In the present embodiment, the write control transistor Twr is arranged next to the light emission control transistor Tel along the column direction (in the Y direction). Therefore, the position of the conduction hole HE10, which is a connecting portion that connects the relay electrodes QE12, QE11, QE10 and the light emission control transistor Tel, is arranged in the column direction of the plurality of transistors arranged in the column direction (in the Y direction) ( It is located at a place other than the end in (Y direction). With this configuration, the position of the conduction hole HE10 serving as the pixel contact portion can be easily aligned with the arrangement of the reflective layers 43G, 43B, and 43R. As a result, it is possible to prevent light from the light emitting functional layer 46 from being applied to the drive transistor Tdr by the reflective layers 43G, 43B, and 43R within the same pixel unit.

  Further, the relay electrodes QE12, QE11, QE10 are formed in a layer different from the data transfer line 26. Therefore, a parasitic capacitance is formed between the data transfer line 26 and other layers, particularly the power supply wiring 41. In order to reduce the parasitic capacitance, it is preferable that the relay electrodes QE12, QE11, and QE10 are positioned at substantially the center of one adjacent data transfer line 26 and the other data transfer line 26. As a result, the time for writing data to the data transfer line 26 and the time for writing data from the data transfer line 26 to the first electrode E1 can be shortened.

<Modification>
The present invention is not limited to the above-described embodiments, and for example, various modifications described below are possible. Of course, each embodiment and each modification may be combined as appropriate.

(1) In the above-described embodiment, the configuration in which the optical path adjustment layer is provided between the reflective layer and the pixel electrode has been described. However, the present invention is not limited to this configuration. The configuration may be such that the optical path adjustment layer is omitted and a pixel electrode having reflectivity is used. In this case, the third conductive layer may be formed by integrating the reflective layer and the pixel electrode.

(2) In the above-described embodiment, the configuration in which the sealing film and the color filter are stacked on the OLED has been described. However, the present invention is not limited to this configuration. A configuration in which a color filter is provided on the counter substrate may be employed.

(3) In the above-described embodiment, the openings of the subpixels of each color are provided so as to extend in the row direction (X direction) in the pixel of one pixel unit, and the openings of the subpixels of the same color are further provided. Were arranged at a common pitch in the row direction (X direction) over a plurality of pixels in one pixel unit. Moreover, in the pixel of one pixel unit, it arranged so that the width | variety of the row direction (X direction) of the opening part in the sub pixel of each color might become equal. That is, the reflective layer in each color sub-pixel is arranged along the row direction (X direction) so as to overlap at least one transistor in each color sub-pixel.
However, the present invention is not limited to such a configuration. For example, the reflective layer in at least one subpixel may be arranged along the row direction (X direction) so as to overlap with at least one transistor in each color subpixel. In this case, the reflective layers in the sub-pixels of other colors are arranged so as to overlap with at least one transistor in the sub-pixels of at least one color, and the reflective layers in the different color sub-pixels are arranged in the row direction (X direction). Arranged along.
For example, the opening in the blue sub-pixel is configured to extend in the row direction (X direction) over the pixel unit, and the width in the row direction (X direction) is the largest. Then, the opening in the red subpixel and the opening in the green subpixel may be arranged side by side in the row direction (X direction) within a pixel unit.

(4) In the above-described embodiment, the power supply wiring is arranged between the reflective layer and the drive transistor. However, a metal wiring other than the power supply wiring may be arranged. By disposing the metal wiring between the reflective layer and the driving transistor, the driving transistor can be reliably shielded from light.

(5) In the above-described embodiment, the OLED is taken as an example of the electro-optical material. However, the present invention is also applied to an electro-optical device using other electro-optical materials. An electro-optical material is a material whose optical characteristics such as transmittance and luminance change when an electric signal (current signal or voltage signal) is supplied. For example, the present invention can be applied to a display panel using a light emitting element such as a liquid crystal, an inorganic EL, or a light emitting polymer as in the above embodiment. The present invention can also be applied to an electrophoretic display panel using microcapsules containing a colored liquid and white particles dispersed in the liquid as an electro-optical material, as in the above embodiment. Further, the present invention can also be applied to a twist ball display panel using twist balls painted in different colors for regions having different polarities as an electro-optical material. The present invention also applies to various electro-optical devices such as a toner display panel using black toner as an electro-optical material or a plasma display panel using a high-pressure gas such as helium or neon as an electro-optical material. Can be applied.

<Application example>
The present invention can be used in various electronic devices. 29 to 31 exemplify specific modes of electronic devices to which the present invention is applied.

  FIG. 29 is a perspective view showing an appearance of a head mounted display of a head mounted display as an electronic apparatus employing the electro-optical device of the present invention. As shown in FIG. 29, the head mounted display 300 has a temple 310, a bridge 320, and projection optical systems 301L and 301R in the same manner as general glasses. Although not shown, the left-eye electro-optical device 1 and the right-eye electro-optical device 1 are provided in the vicinity of the bridge 320 and behind the projection optical systems 301L and 301R.

  FIG. 30 is a perspective view of a portable personal computer employing an electro-optical device. The personal computer 2000 includes an electro-optical device 1 that displays various images, and a main body 2010 on which a power switch 2001 and a keyboard 2002 are installed.

  FIG. 31 is a perspective view of a mobile phone. The cellular phone 3000 includes a plurality of operation buttons 3001 and scroll buttons 3002, and the electro-optical device 1 that displays various images. By operating the scroll button 3002, the screen displayed on the electro-optical device 1 is scrolled. The present invention is also applicable to such a mobile phone.

  Note that examples of electronic devices to which the present invention is applied include personal digital assistants (PDAs) in addition to the devices illustrated in FIGS. 29 to 31. In addition, a digital still camera, a television, a video camera, a car navigation device, a vehicle-mounted display (instrument panel), an electronic notebook, electronic paper, a calculator, a word processor, a workstation, a video phone, and a POS terminal can be used. Furthermore, there are a printer, a scanner, a copying machine, a video player, a device equipped with a touch panel, and the like.

DESCRIPTION OF SYMBOLS 1 ... Electro-optical device, 2 ... Display panel, 3 ... Control circuit, 5 ... Data transfer line drive circuit, 6 ... Scanning line drive circuit, 10 ... Substrate, 10A ... Active area, 22 ... Scanning line, 26 ... Data transfer line , 27 ... control line, 28 ... control line, 41 ... first power supply conductor (power supply wiring), 42 ... second power supply conductor, 45 ... light emitting element, 46 ... light emitting functional layer, 60 ... optical path adjusting layer, 70 ... Data signal supply circuit, 82 ... case, 84 ... FPC board, 86 ... terminal, 100 ... display unit, 110 ... pixel circuit, Ctr ... control signal, DM ... demultiplexer, DT ... data transfer circuit, E1 ... first electrode , E2 ... second electrode, HA1 to HA8 ... conduction hole, HA10 to HA15 ... conduction hole, HB1 to HB4 ... conduction hole, HB10 to HB12 ... conduction hole, HC1 to HC5 ... conduction hole, HC10 to HC12 ... conduction hole, HD1 ~ HD2 Conduction hole, HD10 to HD11 ... conduction hole, HE10 ... conduction hole, HF10 to HF12 ... conduction hole, HG10 ... conduction hole, HH10 ... conduction hole, GTcmp ... gate layer, GTdr ... gate layer, GTel ... gate layer, GTwr ... gate Layer, Gwr ... Scanning signal, L0 ... Insulating film, LA-LF ... Insulating layer, QB1-QB8 ... Relay electrode, QB10-QB14 ... Relay electrode, QC1-QC2 ... Relay electrode, QC10-QC12 ... Relay electrode, QD1-QD3 ... Relay electrode, QD10 ... Relay electrode, QE1 ... Relay electrode, QE10 to QE11 ... Relay electrode, QE12 ... Relay electrode, QF10 ... Relay electrode, Sel ... Control signal, / Sel ... Control signal, Tcmp ... Compensation transistor, Tdr ... Drive Transistor, Tel ... Light emission control transistor, Twr Write control transistor, Vdat a ... image data, Vd ... data signal, Vid ... image signal.

Claims (9)

A plurality of first conductive layers extending in a first direction;
A plurality of second conductive layers extending in a second direction;
A plurality of sub-pixels arranged corresponding to respective intersections of the plurality of first conductive layers and the plurality of second conductive layers,
Each of the plurality of subpixels is
A third conductive layer of the light emitting element;
A plurality of transistors, and
The plurality of transistors include drive transistors,
The plurality of transistors are disposed inside a pixel circuit region having a width in the first direction narrower than a width in the second direction,
One conductive layer of the plurality of first conductive layers is electrically connected to at least one of the plurality of transistors included in each of two subpixels adjacent in the first direction among the plurality of subpixels. Connected,
Of the plurality of subpixels, the third conductive layers of at least two subpixels have different sizes in plan view,
Of the third conductive layers of the at least two subpixels, the largest third conductive layer has a width in the first direction wider than a width in the second direction, and at least one of the drive transistor of the sub-pixel drain and heavy Do Ri,
A fourth conductive layer is disposed between the third conductive layer, which is the largest of the third conductive layers of the at least two subpixels, and the driving transistor of each of the plurality of subpixels. Yes,
An electro-optical device. The plurality of first conductive layers are scanning lines.
The electro-optical device according to claim 1. Of the third conductive layers of the at least two subpixels, the largest third conductive layer overlaps at least one of the drive transistors of the plurality of subpixels.
The electro-optical device according to claim 1 or 2. The fourth conductive layer extends along the first direction and overlaps the driving transistor of each of the plurality of subpixels.
The electro-optical device according to any one of claims 1 to 3, wherein The fourth conductive layer is a power supply wiring connected to the drive transistor of each of the plurality of subpixels.
The electro-optical device according to claim 1 , wherein the electro-optical device is any one of the above. The plurality of transistors include light emission control transistors,
Of the third conductive layers of the at least two subpixels, the largest third conductive layer overlaps a drain of at least one of the plurality of subpixels, the emission control transistor.
The electro-optical device according to any one of claims 1 to 5, characterized in that. Among the plurality of sub-pixels, two sides of the third conductive layer adjacent in the second direction have opposite sides in the second direction positioned on the gate layer of the driving transistor in plan view. To
The electro-optical device according to any one of claims 1 to 6, characterized in that. Of the third conductive layers of the at least two subpixels, the largest third conductive layer is a subpixel of a blue display color.
The electro-optical device according to any one of claims 1 to 7 . An electronic apparatus comprising the electro-optical device according to any one of claims 1 to 8.

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