JP6476383B2 - Resolver signal error detection circuit - Google Patents

Resolver signal error detection circuit Download PDF

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JP6476383B2
JP6476383B2 JP2014242886A JP2014242886A JP6476383B2 JP 6476383 B2 JP6476383 B2 JP 6476383B2 JP 2014242886 A JP2014242886 A JP 2014242886A JP 2014242886 A JP2014242886 A JP 2014242886A JP 6476383 B2 JP6476383 B2 JP 6476383B2
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detection circuit
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JP2016105047A (en
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真一 新井
真一 新井
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Tamagawa Seiki Co Ltd
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Description

本発明は、レゾルバから出力されるレゾルバ信号に異常が生じていることを検出するレゾルバ信号異常検出回路に関する。   The present invention relates to a resolver signal abnormality detection circuit that detects that an abnormality has occurred in a resolver signal output from a resolver.

従来用いられていたこの種のレゾルバ信号異常検出回路としては、例えば下記の特許文献１等に示されている構成を挙げることができる。すなわち、従来構成は、レゾルバから出力される第１及び第２レゾルバ信号の二乗和を監視することで、第１及び第２レゾルバ信号に断線異常が生じていないか否かを監視する。   As this type of resolver signal abnormality detection circuit that has been conventionally used, for example, the configuration shown in the following Patent Document 1 can be exemplified. That is, the conventional configuration monitors whether or not a disconnection abnormality has occurred in the first and second resolver signals by monitoring the sum of squares of the first and second resolver signals output from the resolver.

特開平８−２８９５２１号公報JP-A-8-289521

レゾルバ信号の異常には、天絡異常及び地絡異常が含まれる。天絡異常は、レゾルバ信号に不必要な直流成分が付加されてしまう異常である。地絡異常は、レゾルバ信号に含まれる直流成分がグラウンド電位まで落ちてしまう異常である。レゾルバ信号の天絡異常及び地絡異常が生じると、予期しない箇所で電位差が生じて回路に損傷が生じることもある。   The resolver signal abnormality includes a power fault abnormality and a ground fault abnormality. The power fault abnormality is an abnormality in which an unnecessary DC component is added to the resolver signal. The ground fault abnormality is an abnormality in which the DC component included in the resolver signal falls to the ground potential. When a resolver signal power fault or ground fault occurs, a potential difference may occur at an unexpected location, causing damage to the circuit.

天絡異常又は地絡異常が生じた場合、レゾルバ信号の二乗和にも異常が生じる。このため、上記のような従来構成でも天絡異常又は地絡異常が生じたことを検出することはできる。しかしながら、レゾルバ信号の二乗和を監視するだけでは、生じた異常が天絡異常であるか又は地絡異常であるかを判別することは難しい。   When a power fault or ground fault occurs, an error also occurs in the sum of squares of the resolver signal. For this reason, it is possible to detect that a power fault abnormality or a ground fault abnormality has occurred even in the conventional configuration as described above. However, it is difficult to determine whether the abnormality that has occurred is a power fault or a ground fault by simply monitoring the sum of squares of the resolver signal.

本発明は、上記のような課題を解決するためになされたものであり、その目的は、レゾルバ信号の天絡異常及び地絡異常を判別して検出することができるレゾルバ信号異常検出回路を提供することである。   The present invention has been made to solve the above-described problems, and an object thereof is to provide a resolver signal abnormality detection circuit capable of discriminating and detecting a resolver signal power fault and ground fault abnormality. It is to be.

レゾルバから出力されるレゾルバ信号に異常が生じていることを検出するレゾルバ信号異常検出回路であって、レゾルバの出力巻線の第１及び第２端子の間で互いに直列に接続された第１及び第２抵抗器と、第１及び第２抵抗器の中点に接続された異常検出回路本体とを備え、異常検出回路本体には、中点の電位と地絡検出閾値とを比較する第１コンパレータと、第１コンパレータの出力を積分して、積分値が所定の閾値を超えた際に地絡異常検出信号を出力する第１積分器と、中点の電位と天絡検出閾値とを比較する第２コンパレータと、第２コンパレータの出力を積分して、積分値が所定の閾値を超えた際に天絡異常検出信号を出力する第２積分器とが含まれ、出力巻線には、第１レゾルバ信号を出力する第１出力巻線と、第２レゾルバ信号を出力する第２出力巻線とが含まれており、第１及び第２出力巻線の第２端子は共有ラインに接続されており、第１及び第２抵抗器は、第１及び第２出力巻線のいずれか一方の第１端子に接続されるとともに、共有ラインを通して第１及び第２出力巻線の第２端子に接続されている。 A resolver signal abnormality detection circuit for detecting that an abnormality has occurred in a resolver signal output from a resolver, wherein first and second terminals connected in series between first and second terminals of an output winding of a resolver A second resistor and an abnormality detection circuit main body connected to a midpoint of the first and second resistors, the abnormality detection circuit main body including a first potential for comparing the potential of the midpoint and a ground fault detection threshold; Comparing the comparator and the first integrator that integrates the output of the first comparator and outputs a ground fault abnormality detection signal when the integrated value exceeds a predetermined threshold value, and compares the midpoint potential with the power fault detection threshold value A second comparator that integrates the output of the second comparator and outputs a power fault abnormality detection signal when the integral value exceeds a predetermined threshold, and the output winding includes: A first output winding for outputting a first resolver signal and a second resolver; A second output winding for outputting a signal, a second terminal of the first and second output windings is connected to the shared line, and the first and second resistors are connected to the first and second resistors, respectively. It is connected to the first terminal of any one of the two output windings, and is connected to the second terminals of the first and second output windings through the common line .

本発明のレゾルバ信号異常検出回路によれば、異常検出回路本体は、中点の電位と地絡検出閾値とを比較する第１コンパレータと、第１コンパレータの出力を積分して、積分値が所定の閾値を超えた際に地絡異常検出信号を出力する第１積分器と、中点の電位と天絡検出閾値とを比較する第２コンパレータと、第２コンパレータの出力を積分して、積分値が所定の閾値を超えた際に天絡異常検出信号を出力する第２積分器とを含むので、レゾルバ信号の天絡異常及び地絡異常を判別して検出することができる。   According to the resolver signal abnormality detection circuit of the present invention, the abnormality detection circuit main body integrates the first comparator for comparing the midpoint potential and the ground fault detection threshold, and the output of the first comparator, and the integrated value is predetermined. Integrating a first integrator that outputs a ground fault abnormality detection signal when the threshold value of the second threshold is exceeded, a second comparator that compares the midpoint potential and the power detection threshold value, and integrating the output of the second comparator. Since the second integrator that outputs a power fault abnormality detection signal when the value exceeds a predetermined threshold value, the power fault abnormality and ground fault abnormality of the resolver signal can be determined and detected.

本発明の実施の形態１によるレゾルバ信号異常検出回路を示す回路図である。It is a circuit diagram which shows the resolver signal abnormality detection circuit by Embodiment 1 of this invention. 第１レゾルバ信号に地絡異常が生じた際の図１の各位置における信号等を示すグラフである。It is a graph which shows the signal etc. in each position of FIG. 1 when a ground fault abnormality arises in the 1st resolver signal. 第１レゾルバ信号に天絡異常が生じた際の図１の各位置における信号等を示すグラフである。It is a graph which shows the signal etc. in each position of FIG. 1 when a power fault abnormality arises in the 1st resolver signal. 本発明の実施の形態２によるレゾルバ信号異常検出回路を示す回路図である。It is a circuit diagram which shows the resolver signal abnormality detection circuit by Embodiment 2 of this invention. 本発明の実施の形態３によるレゾルバ信号異常検出回路を示す回路図である。It is a circuit diagram which shows the resolver signal abnormality detection circuit by Embodiment 3 of this invention.

以下、本発明を実施するための形態について、図面を参照して説明する。
実施の形態１．
図１は、本発明の実施の形態１によるレゾルバ信号異常検出回路を示す回路図である。図において、レゾルバ１には、励磁巻線１０、第１出力巻線１１及び第２出力巻線１２が含まれている。周知のように励磁巻線１０には励磁信号が印加されており、レゾルバ１の回転子の角度に応じて第１出力巻線１１及び第２出力巻線１２から２相の角度検出信号、すなわち第１及び第２レゾルバ信号が出力される。本実施の形態のレゾルバ信号異常検出回路は、第１出力巻線１１から出力される第１レゾルバ信号に異常が生じていることを検出するものである。 Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.
Embodiment 1 FIG.
FIG. 1 is a circuit diagram showing a resolver signal abnormality detection circuit according to Embodiment 1 of the present invention. In the figure, the resolver 1 includes an excitation winding 10, a first output winding 11, and a second output winding 12. As is well known, an excitation signal is applied to the excitation winding 10, and two-phase angle detection signals from the first output winding 11 and the second output winding 12 according to the angle of the rotor of the resolver 1, that is, First and second resolver signals are output. The resolver signal abnormality detection circuit according to the present embodiment detects that an abnormality has occurred in the first resolver signal output from the first output winding 11.

レゾルバ信号異常検出回路には、第１抵抗器２０１、第２抵抗器２０２及び異常検出回路本体２１が含まれている。第１及び第２抵抗器２０１，２０２は、第１出力巻線１１の第１端子１１ａ及び第２端子１１ｂの間で互いに直列に接続されている。また、第１及び第２抵抗器２０１，２０２は、レゾルバ１及びＲ／Ｄ変換器３の外側に設けられている。 The resolver signal abnormality detection circuit, the first resistor 20 1, the second resistor 20 2 and the abnormality detection circuit main body 21 is included. The first and second resistors 20 1 and 20 2 are connected in series between the first terminal 11 a and the second terminal 11 b of the first output winding 11. The first and second resistors 20 1 and 20 2 are provided outside the resolver 1 and the R / D converter 3.

異常検出回路本体２１は、第１及び第２抵抗器２０１，２０２の中点２０１−２に接続された回路である。異常検出回路本体２１には、第１コンパレータ２１０、第１電圧源２１１、第１積分器２１２、第２コンパレータ２１３、第２電圧源２１４及び第２積分器２１５が含まれている。 The abnormality detection circuit main body 21 is a circuit connected to the midpoint 20 1-2 of the first and second resistors 20 1 and 20 2 . The abnormality detection circuit main body 21 includes a first comparator 210, a first voltage source 211, a first integrator 212, a second comparator 213, a second voltage source 214, and a second integrator 215.

第１コンパレータ２１０の反転入力端子（−）には、第１及び第２抵抗器２０１，２０２の中点２０１−２が接続され、第１コンパレータ２１０の非反転入力端子（＋）には、第１電圧源２１１が接続されている。第１コンパレータ２１０は、第１及び第２抵抗器２０１，２０２の中点２０１−２の電位と、第１電圧源２１１の出力に対応する地絡検出閾値２１１ａとを比較する。第１積分器２１２は、第１コンパレータ２１０の出力を積分して、積分値が所定の閾値を超えた際に地絡異常検出信号２１２ａを出力する。 The inverting input terminal (−) of the first comparator 210 is connected to the midpoint 20 1-2 of the first and second resistors 20 1 and 20 2 , and is connected to the non-inverting input terminal (+) of the first comparator 210. Is connected to the first voltage source 211. The first comparator 210 compares the potential of the midpoint 20 1-2 of the first and second resistors 20 1 and 20 2 with the ground fault detection threshold 211a corresponding to the output of the first voltage source 211. The first integrator 212 integrates the output of the first comparator 210 and outputs a ground fault abnormality detection signal 212a when the integrated value exceeds a predetermined threshold.

第２コンパレータ２１３の非反転入力端子（＋）には、第１及び第２抵抗器２０１，２０２の中点２０１−２が接続され、第２コンパレータ２１３の反転入力端子（−）には、第２電圧源２１４が接続されている。第２コンパレータ２１３は、第１及び第２抵抗器２０１，２０２の中点２０１−２の電位と、第２電圧源２１４の出力に対応する天絡検出閾値２１４ａとを比較する。第２積分器２１５は、第２コンパレータ２１３の出力を積分して、積分値が所定の閾値を超えた際に天絡異常検出信号２１５ａを出力する。 The non-inverting input terminal (+) of the second comparator 213 is connected to the midpoint 20 1-2 of the first and second resistors 20 1 and 20 2 , and is connected to the inverting input terminal (−) of the second comparator 213. Is connected to the second voltage source 214. The second comparator 213 compares the potential of the midpoint 20 1-2 of the first and second resistors 20 1 and 20 2 with the power detection threshold 214a corresponding to the output of the second voltage source 214. The second integrator 215 integrates the output of the second comparator 213 and outputs a power fault abnormality detection signal 215a when the integrated value exceeds a predetermined threshold value.

以下、図２及び図３を用いて天絡異常検出信号及び地絡異常検出信号の出力動作を具体的に説明する。なお、図２及び図３では、丸で囲まれた数字を各信号等に付している。これは、図２及び図３の各信号等が、図１において同じ数字が配置された位置における信号等であることを示している。   Hereinafter, the output operation of the power fault abnormality detection signal and the ground fault abnormality detection signal will be specifically described with reference to FIGS. In FIG. 2 and FIG. 3, numbers surrounded by circles are attached to each signal and the like. This indicates that the signals and the like in FIGS. 2 and 3 are signals and the like at positions where the same numerals are arranged in FIG.

図２は、第１レゾルバ信号に地絡異常が生じた際の図１の各位置における信号等を示すグラフである。図２の（ａ）は第１出力巻線１１の第１端子１１ａの電位を示し、図２の（ｂ）は第１出力巻線１１の第２端子１１ｂの電位を示している。図２の（ｃ）に示す第１及び第２抵抗器２０１，２０２の中点２０１−２の電位は、第１端子１１ａの電位と第２端子１１ｂの電位との間の差に比例する。図２では、時点Ｔ１において地絡異常が生じている。 FIG. 2 is a graph showing signals and the like at each position in FIG. 1 when a ground fault abnormality occurs in the first resolver signal. 2A shows the potential of the first terminal 11a of the first output winding 11, and FIG. 2B shows the potential of the second terminal 11b of the first output winding 11. FIG. The potential of the middle point 20 1-2 of the first and second resistors 20 1 and 20 2 shown in FIG. 2C is the difference between the potential of the first terminal 11a and the potential of the second terminal 11b. Proportional. In Figure 2, ground fault abnormality has occurred at time T 1.

図２の（ｄ）は、第１コンパレータ２１０の出力を示している。第１コンパレータ２１０は、第１及び第２抵抗器２０１，２０２の中点２０１−２の電位が地絡検出閾値２１１ａ（図２の（ｃ）参照）以下であるときにＨレベルの信号を出力し、同電位が地絡検出閾値２１１ａよりも大きいときにＬレベルの信号を出力する。地絡検出閾値２１１ａは、第１レゾルバ信号に地絡異常が生じていないときに、第１コンパレータ２１０がＨレベルの信号を出力する期間に比べて第１コンパレータ２１０がＬレベルの信号を出力する期間が十分に短くなる値に設定されている。第１レゾルバ信号に地絡異常が生じると、Ｈレベルの期間がＬレベルの期間よりも長くなる。 FIG. 2D shows the output of the first comparator 210. The first comparator 210 is at the H level when the potential of the midpoint 20 1-2 of the first and second resistors 20 1 and 20 2 is equal to or lower than the ground fault detection threshold 211a (see (c) of FIG. 2). A signal is output, and an L level signal is output when the same potential is greater than the ground fault detection threshold 211a. The ground fault detection threshold 211a is such that the first comparator 210 outputs an L level signal compared to a period during which the first comparator 210 outputs an H level signal when no ground fault abnormality has occurred in the first resolver signal. The period is set to a value that is sufficiently short. When a ground fault abnormality occurs in the first resolver signal, the H level period becomes longer than the L level period.

図２の（ｅ）は第１積分器２１２の積分値を示し、図２の（ｆ）は第１積分器２１２から出力される地絡異常検出信号２１２ａを示している。第１積分器２１２は、第１コンパレータ２１０の出力がＨレベルであるときに積分値の加算処理を行い、第１コンパレータ２１０の出力がＬレベルであるときに積分値の減算処理を行う。そして、第１積分器２１２は、積算値が図２の（ｅ）に示す閾値２１２ｂを超えた際に、図２の（ｆ）に示す地絡異常検出信号２１２ａを出力する。第１積分器２１２は、第１レゾルバ信号に地絡異常が生じた時点Ｔ１から所定時間Ｔ２だけ遅れて、地絡異常検出信号２１２ａを出力する。 FIG. 2E shows the integrated value of the first integrator 212, and FIG. 2F shows the ground fault abnormality detection signal 212a output from the first integrator 212. The first integrator 212 performs integration value addition processing when the output of the first comparator 210 is at the H level, and performs integration value subtraction processing when the output of the first comparator 210 is at the L level. The first integrator 212 outputs a ground fault abnormality detection signal 212a shown in (f) of FIG. 2 when the integrated value exceeds the threshold value 212b shown in (e) of FIG. The first integrator 212, a delay from the time T 1 a ground fault abnormality has occurred in the first resolver signal by a predetermined time T 2, and outputs the ground fault abnormality detection signal 212a.

図３は、第１レゾルバ信号に天絡異常が生じた際の図１の各位置における信号等を示すグラフである。図３の（ａ）は第１出力巻線１１の第１端子１１ａの電位を示し、図３の（ｂ）は第１出力巻線１１の第２端子１１ｂの電位を示している。図３の（ｃ）に示す第１及び第２抵抗器２０１，２０２の中点２０１−２の電位は、第１端子１１ａの電位と第２端子１１ｂの電位との間の差に比例する。図３では、時点Ｔ３において天絡異常が生じている。 FIG. 3 is a graph showing signals and the like at each position in FIG. 1 when a power fault abnormality occurs in the first resolver signal. 3A shows the potential of the first terminal 11a of the first output winding 11, and FIG. 3B shows the potential of the second terminal 11b of the first output winding 11. The potential of the midpoint 20 1-2 of the first and second resistors 20 1 and 20 2 shown in FIG. 3C is the difference between the potential of the first terminal 11a and the potential of the second terminal 11b. Proportional. In Figure 3, supply fault abnormality has occurred at time T 3.

図３の（ｄ）は、第２コンパレータ２１３の出力を示している。第２コンパレータ２１３は、第１及び第２抵抗器２０１，２０２の中点２０１−２の電位が天絡検出閾値２１４ａ（図３の（ｃ）参照）以上であるときにＨレベルの信号を出力し、同電位が天絡検出閾値２１４ａ未満であるときにＬレベルの信号を出力する。天絡検出閾値２１４ａは、第１レゾルバ信号に天絡異常が生じていないときに、第２コンパレータ２１３がＨレベルの信号を出力する期間に比べて第２コンパレータ２１３がＬレベルの信号を出力する期間が十分に短くなる値に設定されている。第１レゾルバ信号に天絡異常が生じると、Ｈレベルの期間がＬレベルの期間よりも長くなる。 FIG. 3D shows the output of the second comparator 213. The second comparator 213 is at the H level when the potential of the midpoint 20 1-2 of the first and second resistors 20 1 and 20 2 is equal to or higher than the power supply detection threshold 214a (see (c) of FIG. 3). A signal is output, and an L level signal is output when the same potential is less than the power fault detection threshold 214a. The power supply detection threshold 214a is such that when a power supply abnormality does not occur in the first resolver signal, the second comparator 213 outputs an L level signal compared to a period during which the second comparator 213 outputs an H level signal. The period is set to a value that is sufficiently short. When a power fault abnormality occurs in the first resolver signal, the H level period becomes longer than the L level period.

図３の（ｅ）は第２積分器２１５の積分値を示し、図３の（ｆ）は第２積分器２１５から出力される天絡異常検出信号２１５ａを示している。第２積分器２１５は、第２コンパレータ２１３の出力がＨレベルであるときに積分値の加算処理を行い、第２コンパレータ２１３の出力がＬレベルであるときに積分値の減算処理を行う。そして、第２積分器２１５は、積算値が図３の（ｅ）に示す閾値２１２ｂを超えた際に、図３の（ｆ）に示す天絡異常検出信号２１５ａを出力する。第２積分器２１５は、第１レゾルバ信号に天絡異常が生じた時点Ｔ３から所定時間Ｔ４だけ遅れて、天絡異常検出信号２１５ａを出力する。 FIG. 3E shows the integrated value of the second integrator 215, and FIG. 3F shows the power fault abnormality detection signal 215a output from the second integrator 215. The second integrator 215 performs integration value addition processing when the output of the second comparator 213 is at the H level, and performs integration value subtraction processing when the output of the second comparator 213 is at the L level. The second integrator 215 outputs a power fault abnormality detection signal 215a shown in (f) of FIG. 3 when the integrated value exceeds the threshold value 212b shown in (e) of FIG. The second integrator 215, with a delay from the time T 3 to abnormal power supply fault in the first resolver signal occurs for a predetermined time period T 4, and outputs the top fault abnormality detection signal 215a.

このようなレゾルバ信号異常検出回路では、異常検出回路本体２１は、中点２０１−２の電位と地絡検出閾値２１１ａとを比較する第１コンパレータ２１０と、第１コンパレータ２１０の出力を積分して、積分値が所定の閾値を超えた際に地絡異常検出信号２１２ａを出力する第１積分器２１２と、中点２０１−２の電位と天絡検出閾値２１４ａとを比較する第２コンパレータ２１３と、第２コンパレータ２１３の出力を積分して、積分値が所定の閾値を超えた際に天絡異常検出信号２１５ａを出力する第２積分器２１５とを含むので、レゾルバ信号の天絡異常及び地絡異常を判別して検出することができる。 In such a resolver signal abnormality detection circuit, the abnormality detection circuit main body 21 includes a first comparator 210 which compares the threshold 211a out potential and ground fault midpoint 20 1-2, integrates the output of the first comparator 210 Te, a second comparator which compares the integral value is the first integrator 212 to output a ground fault abnormality detection signal 212a when it exceeds a predetermined threshold, the threshold 214a out potential and the top fault midpoint 20 1-2 213 and a second integrator 215 that integrates the output of the second comparator 213 and outputs a power fault abnormality detection signal 215a when the integrated value exceeds a predetermined threshold value. In addition, the ground fault abnormality can be determined and detected.

また、第１及び第２抵抗器２０１，２０２がレゾルバ１の外側に配置されているので、汎用のレゾルバ１に第１及び第２抵抗器２０１，２０２を後付でき、適用範囲を広げることができる。 Further, since the first and second resistors 20 1 and 20 2 are arranged outside the resolver 1, the first and second resistors 20 1 and 20 2 can be retrofitted to the general-purpose resolver 1, and the applicable range Can be spread.

なお、図１では、第１及び第２抵抗器２０１，２０２が第１出力巻線１１に接続されているように示しているが、第１及び第２抵抗器は第２出力巻線に接続されていてもよい。 In FIG. 1, the first and second resistors 20 1 and 20 2 are shown as being connected to the first output winding 11, but the first and second resistors are the second output winding. It may be connected to.

実施の形態２．
図４は、本発明の実施の形態２によるレゾルバ信号異常検出回路を示す回路図である。図において、第１及び第２出力巻線１１，１２の第２端子１１ｂ，１２ｂは共有ライン１３に接続されている。第１及び第２抵抗器２０１，２０２は、第１出力巻線１１の第１端子１１ａに接続されるとともに、共有ライン１３を通して第１及び第２出力巻線１１，１２の第２端子１１ｂ，１２ｂに接続されている。共有ライン１３には、励磁巻線１０も接続されている。その他の構成は、実施の形態１と同じである。 Embodiment 2. FIG.
FIG. 4 is a circuit diagram showing a resolver signal abnormality detection circuit according to the second embodiment of the present invention. In the figure, the second terminals 11 b and 12 b of the first and second output windings 11 and 12 are connected to the common line 13. The first and second resistors 20 1 and 20 2 are connected to the first terminal 11 a of the first output winding 11, and the second terminals of the first and second output windings 11 and 12 through the shared line 13. 11b and 12b. An excitation winding 10 is also connected to the shared line 13. Other configurations are the same as those of the first embodiment.

このように、本発明のレゾルバ信号異常検出回路は、第１及び第２出力巻線１１，１２が共有ライン１３に接続されているレゾルバ１にも適用できる。   Thus, the resolver signal abnormality detection circuit of the present invention can be applied to the resolver 1 in which the first and second output windings 11 and 12 are connected to the common line 13.

なお、図４では、第１及び第２抵抗器２０１，２０２が第１出力巻線１１の第１端子１１ａに接続されているように示しているが、第１及び第２抵抗器は第２出力巻線の第１端子に接続されていてもよい。 In FIG. 4, the first and second resistors 20 1 and 20 2 are shown as being connected to the first terminal 11 a of the first output winding 11, but the first and second resistors are You may be connected to the 1st terminal of the 2nd output winding.

実施の形態３．
図５は、本発明の実施の形態３によるレゾルバ信号異常検出回路を示す回路図である。実施の形態１では、異常検出回路本体２１がＲ／Ｄ変換器３の外側に設けられているように説明しているが、本実施の形態のレゾルバ信号異常検出回路では、異常検出回路本体２１がＲ／Ｄ変換器３に内蔵されている。その他の構成は、実施の形態１と同じである。 Embodiment 3 FIG.
FIG. 5 is a circuit diagram showing a resolver signal abnormality detection circuit according to the third embodiment of the present invention. In the first embodiment, it is described that the abnormality detection circuit main body 21 is provided outside the R / D converter 3. However, in the resolver signal abnormality detection circuit of the present embodiment, the abnormality detection circuit main body 21 is described. Is built in the R / D converter 3. Other configurations are the same as those of the first embodiment.

このようなレゾルバ信号異常検出回路では、異常検出回路本体２１がＲ／Ｄ変換器３に内蔵されているので、部品点数を少なくてきる。これにより、部品コストを低減できるとともに、設置に要するエリアを少なくできる。   In such a resolver signal abnormality detection circuit, since the abnormality detection circuit main body 21 is built in the R / D converter 3, the number of parts is reduced. Thereby, while being able to reduce component cost, the area required for installation can be reduced.

１ レゾルバ
１１，１２ 第１及び第２出力巻線
１１ａ，１２ａ 第１端子
１１ｂ，１２ｂ 第２端子
１３ 共有ライン
３ Ｒ／Ｄ変換器
２０１，２０２ 第１及び第２抵抗器
２０１−２ 中点
２１ 異常検出回路本体
２１０ 第１コンパレータ
２１２ 第１積分器
２１２ａ 地絡異常検出信号
２１３ 第２コンパレータ
２１５ 第２積分器
２１５ａ 天絡異常検出信号 First resolver 11, 12 first and second output windings 11a, 12a first terminal 11b, 12b second terminal 13 shared lines 3 R / D converter 20 1, 20 2 first and second resistors 20 1-2 Midpoint 21 Abnormality detection circuit body 210 First comparator 212 First integrator 212a Ground fault abnormality detection signal 213 Second comparator 215 Second integrator 215a Power fault abnormality detection signal

Claims (3)

レゾルバから出力されるレゾルバ信号に異常が生じていることを検出するレゾルバ信号異常検出回路であって、
前記レゾルバの出力巻線の第１及び第２端子の間で互いに直列に接続された第１及び第２抵抗器と、
前記第１及び第２抵抗器の中点に接続された異常検出回路本体と
を備え、
前記異常検出回路本体には、
前記中点の電位と地絡検出閾値とを比較する第１コンパレータと、
前記第１コンパレータの出力を積分して、積分値が所定の閾値を超えた際に地絡異常検出信号を出力する第１積分器と、
前記中点の電位と天絡検出閾値とを比較する第２コンパレータと、
前記第２コンパレータの出力を積分して、積分値が所定の閾値を超えた際に天絡異常検出信号を出力する第２積分器と
が含まれ、
前記出力巻線には、第１レゾルバ信号を出力する第１出力巻線と、第２レゾルバ信号を出力する第２出力巻線とが含まれており、
前記第１及び第２出力巻線の前記第２端子は共有ラインに接続されており、
前記第１及び第２抵抗器は、前記第１及び第２出力巻線のいずれか一方の前記第１端子に接続されるとともに、前記共有ラインを通して前記第１及び第２出力巻線の前記第２端子に接続されている
ことを特徴とするレゾルバ信号異常検出回路。 A resolver signal abnormality detection circuit for detecting that an abnormality has occurred in a resolver signal output from a resolver,
First and second resistors connected in series between first and second terminals of the output winding of the resolver;
An abnormality detection circuit main body connected to a midpoint of the first and second resistors,
In the abnormality detection circuit body,
A first comparator that compares the midpoint potential with a ground fault detection threshold;
A first integrator that integrates the output of the first comparator and outputs a ground fault abnormality detection signal when the integral value exceeds a predetermined threshold;
A second comparator for comparing the midpoint potential with a power supply detection threshold;
A second integrator that integrates the output of the second comparator and outputs a power fault abnormality detection signal when the integral value exceeds a predetermined threshold ;
The output winding includes a first output winding that outputs a first resolver signal and a second output winding that outputs a second resolver signal,
The second terminals of the first and second output windings are connected to a shared line;
The first and second resistors are connected to the first terminal of one of the first and second output windings, and the first and second output windings of the first and second output windings are connected through the shared line. A resolver signal abnormality detection circuit characterized by being connected to two terminals . 前記第１及び第２抵抗器は、前記レゾルバの外側に配置されている
ことを特徴とする請求項１記載のレゾルバ信号異常検出回路。 The resolver signal abnormality detection circuit according to claim 1, wherein the first and second resistors are arranged outside the resolver. 前記異常検出回路本体は、Ｒ／Ｄ変換器に内蔵されている
ことを特徴とする請求項１または２に記載のレゾルバ信号異常検出回路。 The abnormality detection circuit main body, the resolver signal abnormality detection circuit according to claim 1 or 2, characterized in that it is incorporated in the R / D converter.
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