JP6057927B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP6057927B2 JP6057927B2 JP2014002131A JP2014002131A JP6057927B2 JP 6057927 B2 JP6057927 B2 JP 6057927B2 JP 2014002131 A JP2014002131 A JP 2014002131A JP 2014002131 A JP2014002131 A JP 2014002131A JP 6057927 B2 JP6057927 B2 JP 6057927B2
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- sealing resin
- semiconductor element
- semiconductor
- case
- semiconductor device
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Description
図1は、本発明の実施の形態1による半導体装置の構成の一部である内部モジュール20を示す側面断面図である。図1において、セラミックスなどの絶縁基板3aの片面には、パターンを有さない単一の表面電極3bが形成され、他の面には、やはりパターンを有さない単一の裏面電極3cが形成されている。表面電極3bおよび裏面電極3cは銅などの導電性材料の薄板である。表面電極3bおよび裏面電極3cが形成された絶縁基板3aを、ここでは半導体素子基板3と称する。半導体素子基板3の表面電極3bのうちの所定の位置に、半導体素子1a、1bが導電性の接合材2を用いて固定され、半導体素子1aの一方の主電極と半導体素子1bの一方の主電極が電気的に接続される。ここで、半導体素子1aは例えばIGBT(Insulated Gate Bipolar Transistor)やMOSFET(Metal Oxide Semiconductor Field-Effect-Transistor)のようなスイッチング素子である。半導体素子1bは例えばスイッチング素子と並列に接続される還流ダイオードである。
実施の形態2では、本実施の形態1による半導体装置100の製造方法について、製造方法の工程を図示する図5および図6を参照して説明する。図5のST1に示すように、半導体素子基板3は半導体素子が配置される上面に表面電極3bを、下面にも裏面電極3cをパターン無で形成している。この半導体素子基板3の表面電極3bに半導体素子1aおよび半導体素子1bを導電性の接合材2を用いて固定する。同時もしくはその後、スイッチング素子である半導体素子1aと還流ダイオードである半導体素子1bの表面に形成された主電極と接続し外部電極となる第2の主端子5bと、表面電極3bから直接外部電
極を取り出す第1の主端子5aを形成する。
本実施の形態3では、実施の形態2とは別の半導体装置の製造方法について、製造方法の工程を図示する図7を参照して説明する。ST1からST3までの工程は図5に示す実施の形態2と同様である。ST3の後、図7に示すST11のように、第1の封止樹脂9による封止をしていない内部モジュール21を複数個、放熱板10に配置し、接合材11により接合した後、ST12に示すように、各内部モジュール21の第1のケース4の内部を第1の封止樹脂9により封止する。ST12の工程の後は、図6に示したST6およびST7の工程を実施する。このように、本実施の形態3は、実施の形態2におけるエポキシ系の第1の封止樹脂9の封止工程を、半導体素子基板を放熱板10に接合した後に実
施するものである。接合材11にて放熱板10に半導体素子基板を接合する工程で、接合材2または接合材8として、半田材のように加熱すると再溶融する可能性がある。半田が再溶融すると体積膨張が大きく、高温下でエポキシ系の第1の封止樹脂9の強度低下もあって、樹脂割れが発生する。
図4の構造の半導体装置を実施の形態3で説明した製造工程により作製し、ヒートサイクル信頼性試験に投入した。まず、半導体装置100の具体的な構成について説明する。
膨張係数の差が5ppm/Kであれば目標を満足する。
Claims (5)
- 絶縁基板の片面に表面電極が、および前記絶縁基板の他の面に裏面電極が、それぞれ形成された半導体素子基板と、前記表面電極の、前記絶縁基板とは反対側の面に接合材を介して固着された半導体素子と、前記表面電極に接合された第1の主端子および前記半導体素子の前記表面電極とは反対側の面に接合された第2の主端子と、前記半導体素子基板の周辺部の前記表面電極上に設けられ、電気信号の入出力を行うための信号端子が一体成型された第1のケースと、前記第1のケースの内部を前記半導体素子と前記半導体素子基板とを覆うように封止する第1の封止樹脂とを備えた内部モジュールが、一面に複数、それぞれの前記内部モジュールの前記裏面電極を接合して配置された放熱板と、
前記放熱板の周辺部であって、前記内部モジュールを内側に含むように設けられた第2のケースと、
前記第2のケースの内部を、前記第1の封止樹脂と前記第1のケースと前記半導体素子基板とを覆うように封止する第2の封止樹脂と、を備えた半導体装置において、
少なくとも前記第1のケース内部の前記表面電極は、前記絶縁基板全体を被覆し、かつ前記表面電極と前記裏面電極とは、前記絶縁基板に対して対称に形成されており、
前記第1の主端子および前記第2の主端子は前記第1の封止樹脂および前記第2の封止樹脂を貫通して前記第2の封止樹脂の外部に露出するとともに、
前記第2の封止樹脂の弾性率が前記第1の封止樹脂の弾性率よりも小さいことを特徴とする半導体装置。 - 前記第1の封止樹脂はフィラーを混入したエポキシ系樹脂であり、前記第2の封止樹脂はシリコーン系樹脂であることを特徴とする請求項1に記載の半導体装置。
- 前記第1の封止樹脂の熱膨張係数と、前記半導体素子基板の熱膨張係数との差が、5ppm/K以下であることを特徴とする請求項1または2に記載の半導体装置。
- 前記半導体素子がワイドバンドギャップ半導体により形成されていることを特徴とする請求項1から3のいずれか1項に記載の半導体装置。
- 前記ワイドバンドギャップ半導体は、炭化ケイ素、窒化ガリウム系材料またはダイヤモンドの半導体であることを特徴とする請求項4に記載の半導体装置。
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