JP5820291B2 - Overcurrent protection circuit - Google Patents

Description

  The present invention relates to an overcurrent protection circuit that protects a power transistor and the like of a switching drive circuit.

  In recent years, with the emergence of power MOS transistors that can be switched at high speed, the movement of switching loads such as motors, dynamic speakers, piezo vibrators, and micro electro mechanical systems (MEMS) using PWM (Pulse Width Modulation) driving methods. Is thriving.

  Switching driving with a power MOS transistor can drive a load with binary values of high / low levels compared with conventional analog driving, and therefore has good compatibility with a digital signal handled by a microcomputer or the like. Further, since the on-resistance of the power MOS transistor is very low, there is an advantage that it can be driven with high efficiency.

  In order to drive the power MOS transistor, it is necessary to configure a switching drive circuit using the power MOS transistor and perform switching drive by supplying a PWM signal or the like to the switching drive circuit.

  FIG. 7 shows a circuit configuration of a general switching drive circuit 10 (see, for example, Patent Documents 1, 2, and 3 for similar configurations). The switching drive circuit 10 includes a high-side output circuit 14H including a control logic circuit 11, a high-side level shift circuit 12H, a low-side level shift circuit 12L, a high-side pre-driver circuit 13H, a low-side pre-driver circuit 13L, and a high-side PMOS power transistor MP21. , A low-side output circuit 14L comprising a low-side NMOS power transistor MN21, a high-side output current monitor circuit 15H, a low-side output current monitor circuit 15L, and an overcurrent protection circuit 17. Reference numeral 18 denotes a load connected between the output terminal OUT and the GND terminal of the switching drive circuit 10.

  The high-side pre-driver circuit 13H and the low-side pre-driver circuit 13L are composed of circuits in which CMOS inverters each composed of a PMOS transistor and an NMOS transistor are cascade-connected in four stages. The high side output current monitor circuit 15H includes a high voltage PMOS transistor MP22 and a resistor R21, and the low side output current monitor circuit 15L includes a high voltage NMOS transistor MN22 and a resistor R22. The overcurrent protection circuit 17 includes a high side overcurrent protection circuit 17H, a low side overcurrent protection circuit 17L, an OR circuit OR21, and a D-type flip-flop DFF21.

Next, input / output terminals of the switching drive circuit 10 will be described. The switching drive circuit 10 has four types of power supply terminals and ground terminals GND. The power supply terminal is a terminal of a voltage V _DD (for example, 3.7V) supplied to a low withstand voltage digital / analog circuit, a terminal of a voltage PV _DD (for example, 25V) to be supplied to a high voltage power circuit, and a high side power MOS transistor A terminal for a voltage V _CLAMPH (for example, −10 V _{based on} PV _DD ) for supplying a gate drive voltage, and a terminal for a voltage V _CLAMPL (for example, 10 V) for supplying a gate drive voltage for a low-side power MOS transistor. The signal input terminal IN is a terminal for inputting a high level (for example, 3.3 V) / low level (for example, 0 V) binary input signal _VIN such as a PWM signal. The reset terminal RST is a terminal for setting the overcurrent protection signal V _OCP to a low level during startup or standby by inputting a low level during startup or standby of the switching drive circuit 10 and a high level during normal operation. . The output terminal OUT is a terminal that outputs a drive signal _VOUT to the load 18. The high level of the _overcurrent protection signal V _OCP is 25 V, for example, and the low level is 0 V, for example.

Hereinafter, the function of each circuit block will be described. The control logic circuit 11 is a circuit block having the following two functions. First, the ability to convert a binary signal of the input high / low level from the input terminal IN, the gate drive timing signal _{V INH} and the high-side power transistor MP21, the gate drive timing signal _{V INL} of the low-side power transistor MN21 Have Second, the function of monitoring the presence or absence of the _overcurrent protection signal V _OCP from the overcurrent protection circuit 17 and immediately turning off the high-side power transistor MP21 and the low-side power transistor MN21 when the overcurrent protection signal V _OCP is detected. Have

The high side level shifting circuit 12H is a high level signal _{V INH} output from the control logic circuit 11 to the _{PV DD} potential, has a function of outputting a signal _{V INHLS} obtained by converting the low level to the potential of _{V CLAMPH.} Low side level shifting circuit 12L is a high level signal _{V INL} outputted from the control logic circuit 11 to a potential of _{V CLAMPL,} has a function of outputting a signal _{V INLLS} obtained by converting the low level to the GND potential.

High side pre-driver circuit 13H is buffered via the four stages of inverters signals V _INHLS output from the high side level shifting circuit 12H, a function of outputting a gate drive signal V _GH of the high-side power transistors MP21 Have. Low-side pre-driver circuit 13L is buffered via the four stages of inverters the output signal V _INLLS from low side level shift circuit 12L, and outputting a gate drive signal V _GL of the low-side power transistor MN21.

  The high-side power transistor MP21 and the low-side power transistor MN21 have a function of driving the load 18 by being complementarily controlled.

The high-side output current monitor circuit 15H has a function of monitoring the output current (source-drain current) of the high-side power transistor MP21 and outputting a high-side monitor voltage V _SENSEH proportional to this current. The low-side output current monitor circuit 15L has a function of monitoring the output current (drain-source current) of the low-side power transistor MN21 and outputting a low-side monitor voltage V _SENSEL proportional to this current.

The overcurrent protection circuit 17 detects the overcurrent protection signal V when either or both of the output current I _DSH of the high side power transistor MP21 and the output current I _DSL of the low side power transistor MN21 exceed the overcurrent detection reference value. _It has a function of outputting _OCP .

Next, the driving method of the switching drive circuit 10 will be specifically described with reference to FIGS. First, a high / low level binary signal _VIN is input to the input terminal IN (FIG. 8A). Then, the signal _VIN is supplied to the control logic circuit 11, and the high side gate drive control signal V _INH (FIG. 8B) and the low side gate drive control signal _VINL (FIG. 8C) are output. Low level of high-side gate drive control signal V _INH corresponds to the on-level of the high-side power transistors MP21, a high level of low-side gate drive control signal V _INL is equivalent to turn on the level of low-side power transistor MN21. Both signals _{V INH, V INL} is outputted so as to provide a period in which the high-side power transistor MP21 and the low-side power transistor MN21 is both called dead time _{T DED} consisting off level. This is because, when the high-side power transistor MP21 and the low-side power transistor MN21 are turned on at the same time, a large current called a through current flows from the terminal of the voltage PV _DD toward the GND terminal, so that the high-side power transistor MP21 and the low-side power transistor This is because MN21 may be destroyed.

Thereafter, the high-side gate drive control signal _{V INH} is input to the high side level shifting circuit 12H, the high level to the _{PV DD} potential, low level has been level-shifted to _{V CLAMPH} potential, the high-side level shift signal _{V INHLS} Converted. On the other hand, the low-side gate drive control signal V _INL is input to the low-side level shift circuit 12L, and is converted into a low-side level shift signal V _INLLS in which the high level is level-shifted to the V _CLAMPL potential and the low level is level-shifted to the GND potential. The high side level shift signal V _INHLS is input to the high side pre-driver circuit 13H and is buffered to become the high side power transistor gate drive signal V _GH . The low side level shift signal V _INLLS is input to the low side pre-driver circuit 13L and is buffered to become the low side power transistor gate drive signal V _GL .

The high-side power transistor gate drive signal V _GH is supplied to the gate of the high-side power transistors MP21, controls the on / off. Low-side power transistor gate drive signal V _GL is supplied to the gate of the low side power transistor MN21, and controls the ON / OFF. When on / off of the high-side power transistor MP21 and the low-side power transistor MN21 is controlled, a drive signal _VOUT for driving the load 18 is output to the output terminal OUT.

  Next, a method for driving the overcurrent protection circuit 17 will be described with reference to FIGS. FIG. 9 shows a circuit configuration of the overcurrent protection circuit 17. The overcurrent protection circuit 17 includes a high side overcurrent protection circuit 17H, a low side overcurrent protection circuit 17L, an OR circuit OR21, and a D-type flip-flop DFF21.

  The high side overcurrent protection circuit 17H includes a high side overcurrent detection circuit 171 and a high side blanking circuit 172. The low side overcurrent protection circuit 17L includes a low side overcurrent detection circuit 173 and a low side blanking circuit 174.

The high-side overcurrent detection circuit 171 has a function of outputting a high-side overcurrent detection signal V _OCDCTH when the high-side monitor voltage V _SENSEH becomes a certain value or less. The high side blanking circuit 172 is an overcurrent of the output current of the high side power transistor MP21 due to ringing of the waveform of the load drive signal _VOUT generated due to an inductance component and a capacitance component that are parasitically present in the switching drive circuit 10. In order to prevent erroneous detection, the high-side overcurrent protection signal V _OCPH is output only when the high-side overcurrent detection signal V _OCDCTH continues for a certain time (high side _blanking time).

The low-side overcurrent detection circuit 173 has a function of outputting a low-side overcurrent detection signal V _OCDCTL when the low-side monitor voltage V _SENSEL becomes equal to or higher than a certain value. The low-side blanking circuit 174 generates an overcurrent error in the output current of the low-side power transistor MN21 due to ringing of the waveform of the load drive signal _VOUT generated due to an inductance component and a capacitance component that are parasitically present in the switching drive circuit 10. In order to prevent detection, the low-side overcurrent protection signal V _OCPL is output only when the low-side overcurrent detection signal V _OCDCTL continues for a certain time (low-side blanking time).

Hereinafter, the operation of the high-side overcurrent protection circuit 17H will be described with reference to FIG. 7, FIG. 9, and FIG. In proportion to the current value of the output current _{I DSH} of the high-side power transistors M21, the high-side monitor voltage _{V SENSEH} is output and input into the high-side overcurrent detection circuit 171. When the high side monitor voltage V _SENSEH becomes equal to or lower than the high side overcurrent detection reference voltage V _{DCTH, the} high side overcurrent detection circuit 171 outputs the high side overcurrent detection signal _OCDCTH and _inputs it to the high side _blanking circuit 172. The high side _blanking circuit 172 monitors the time during which the high side overcurrent detection signal V _OCDCTH is maintained at a high level, and when this time exceeds a certain time (high side _blanking time), the high side overcurrent protection signal V _OCPH is output. The high-side overcurrent protection signal V _OCPH is input to the clock input terminal of the D-type flip-flop DFF21 via the OR circuit OR21, whereby the Q output of the D-type flip-flop DFF21 is inverted to a high level and is high. The side overcurrent protection signal V _OCP is output. The high side overcurrent protection signal V _OCP is input to the control logic circuit 11, and the control logic circuit 11 immediately turns off the high side power transistor MP21 and the low side power transistor MN21.

The operation of the low-side overcurrent protection circuit 17L will be described with reference to FIGS. A low-side monitor voltage V _SENSEL is output in proportion to the current value of the output current I _DSL of the low-side power transistor MN21 and input to the low-side overcurrent detection circuit 173. The low-side overcurrent detection circuit 173 outputs a low-side overcurrent detection signal V _OCDCTL and inputs it to the low-side blanking circuit 174 when the low-side monitor voltage V _SENSEL becomes equal to or higher than the overcurrent detection reference voltage V _DCTL . The low side blanking circuit 174 monitors the time during which the low side overcurrent detection signal V _OCDCTL is maintained at a high level. When this time exceeds a certain time (low side blanking time), the low side overcurrent protection signal V _OCPL Is output. The low-side overcurrent protection signal V _OCPL is input to the clock input terminal of the D-type flip-flop DFF21 via the OR circuit OR21, whereby the Q output of the D-type flip-flop DFF21 is inverted to a high level and is overcurrent. The protection signal V _OCP is output. The overcurrent protection signal V _OCP is input to the control logic circuit 11, and the control logic circuit 11 immediately turns off the high-side power transistor MP21 and the low-side power transistor MN21.

  Next, erroneous detection of overcurrent when no blanking time is provided will be described with reference to FIG. Although the figure illustrates the high side overcurrent protection circuit 17H as an example, the same applies to the low side overcurrent protection circuit 17L.

The load drive signal V _OUT output from the output terminal OUT is affected by parasitic inductance and parasitic capacitance, and causes ringing immediately after switching (FIG. 12B). Due to the influence of the ringing of the signal _VOUT , ringing also occurs in the voltage waveform of the high side monitor voltage V _SENSEH (FIG. 12C). When the high side monitor voltage V _SENSEH becomes equal to or lower than the high side overcurrent detection reference signal V _DCTH due to the influence of ringing, the high side overcurrent detection signal V _OCCDTH is output (FIG. 13 (d)). When the high side _blanking time is not provided, the high side overcurrent detection signal V _OCDCTH is immediately latched in the D-type flip-flop DFF21, and the overcurrent protection signal V _OCP is output.

In order to prevent the overcurrent protection signal V _{OCP from} being affected by the ringing of the signal _VOUT , the high-side overcurrent detection signal V _OCDCTH reaches the D-type flip-flop DFF21 until the ringing sufficiently attenuates. It is necessary not to let it. Therefore, the time during which the high-side overcurrent detection signal V _OCDCTH signal is maintained at the high level is monitored by the blanking circuit 172, and if this time is less than the high-side blanking time, the overcurrent protection signal V _OCPH is output. Do not. By providing such a mechanism, overcurrent erroneous detection due to ringing of the signal _VOUT can be prevented.

Hereinafter, the operation of the high-side overcurrent protection circuit 17H will be described with reference to FIG. 7, FIG. 13, and FIG. FIG. 13 shows a circuit configuration of the high-side overcurrent protection circuit 17H. The high side overcurrent protection circuit 17H includes a current source I21, PMOS transistors MP23 to MP25, NMOS transistors MN23 to MN25, comparators 1711 and 1721, a level shift circuit 1712, a voltage source for the high side overcurrent detection reference voltage V _DCTH , The voltage source _includes a ranking time reference voltage V _BLNKH, a high side _blanking time control capacitor C21, and inverters INV21 and INV22. Among these, the high-side overcurrent detection reference voltage V _DCTH , the comparator 1711, and the level shift circuit 1712 constitute an overcurrent detection circuit 171. The transistors MP24, MP25, MN25, the blanking time control capacitor C21, the high side blanking time reference voltage V _BLNKH , the inverter INV22, and the comparator 1721 constitute a high side blanking circuit 172.

In the high-side overcurrent protection circuit 17H shown in FIG. 13, when the OUT terminal and the GND terminal in FIG. 7 are short-circuited (ground fault), if a current flows through the high-side power transistor MP21, the high-side monitor voltage V _SENSEH Descend. The high-side monitor voltage V _SENSEH is _compared with the high-side overcurrent detection reference voltage V _DCTH by the comparator 1711. When the high-side monitor voltage V _SENSEH becomes equal to or lower than the high-side overcurrent detection reference voltage V _DCTH , the high-side overcurrent detection reference voltage V _{DCTH is} passed through the level shift circuit 1712. The current detection signal V _OCDCTH is output. The high side overcurrent detection signal V _OCDCTH is logically inverted by the inverter INV21, and then turns the transistor MP25 on and the MN25 off. Then, the high side _blanking time control current _IBLNKH flows from the transistor MP25 into the high side _blanking time control capacitor C21. As a result, the high side blanking time control capacitor C21 is charged, and when its potential V _CHGH rises and becomes _{equal to} or higher than the high side _blanking time reference voltage V _BLNKH , the high side overcurrent protection is provided via the comparator 1721 and the inverter INV22. Signal V _OCPH is output. As a result, as described with reference to FIG. 9, the high-side power transistor MP21 and the low-side power transistor MN21 are immediately turned off.

Hereinafter, the operation of the low-side overcurrent protection circuit 17L will be described with reference to FIG. 7, FIG. 15, and FIG. FIG. 15 shows a circuit configuration of the low-side overcurrent protection circuit 17L. The low side overcurrent protection circuit 17L includes a current source I22, PMOS transistors MP26 to MP28, NMOS transistor MN26, comparators 1731 and 1741, a voltage source for the low side overcurrent detection reference voltage V _{DCTL, and} a voltage source for the low side blanking time reference voltage V _BLNKL . , A low side blanking time control capacitor C22 and inverters INV23 and INV24. Among these, the low-side overcurrent detection circuit 173 is configured by the low-side overcurrent detection reference voltage V _DCTL and the comparator 1731. Further, the transistors MP27, MP28, MN26, the blanking time control capacitor C22, the low side blanking time reference voltage V _BLNKL , the inverter _INV24 , and the comparator 1741 constitute a low side blanking circuit 174.

In the low-side overcurrent protection circuit 17L shown in FIG. 15, when the OUT terminal and the PV _DD terminal in FIG. 7 are short-circuited (power _fault ), when a current flows through the low-side power transistor MN21, the low-side monitor voltage V _SENSEL increases. . The low side monitor voltage V _SENSEL is _compared with the low side overcurrent detection reference voltage V _DCTL by the comparator 1731. When the low side monitor voltage V _SENSEL becomes equal to or higher than the low side overcurrent detection reference voltage V _DCTL , a low side overcurrent detection signal V _OCDCTL is output. The logic of the low-side overcurrent detection signal V _OCDCTL is inverted by the inverter _INV23 , and then the transistor MP28 is turned on and the MN26 is turned off. Then, the low side blanking time control current _IBLNKL flows from the transistor MP28 into the blanking time control capacitor C22. As a result, the blanking time control capacitor C22 is charged, and when its potential V _CHGL rises and becomes _{equal to} or higher than the low side blanking time reference voltage V _BLNKL , the low side overcurrent protection signal V is passed through the comparator 1741 and the inverter _{INV24. OCPL} is output. As a result, as described with reference to FIG. 9, the high-side power transistor MP21 and the low-side power transistor MN21 are immediately turned off.

JP 2009-296390 A JP 2010-011131 A JP 2011-035564 A

  In the overcurrent protection circuit 17 as described above, in order to prevent thermal destruction due to heat generation of the power transistors MP21 and MN21 generated by the overcurrent of the output current of the high-side power transistor MP21 and the output current of the low-side power transistor MN21, It is preferable to turn off the power transistors MP21 and MN21 as soon as possible after detection. That is, from the viewpoint of thermal destruction, it is necessary to set the high side blanking time and the low side blanking time as short as possible.

  However, the shorter the blanking time, the higher the possibility of erroneously detecting an overcurrent due to ringing generated at the output terminal OUT. In other words, there is an opposite relationship between the relationship between the blanking time and the resistance to thermal breakdown of the power transistor and the resistance between the blanking time and the overcurrent erroneous detection due to ringing. Therefore, there is a problem that it is difficult to achieve both the resistance of the overcurrent protection circuit 17 against ringing and the protection capability against a large current.

  Hereinafter, a phenomenon in which the power transistor is thermally destroyed during the blanking time will be described with reference to FIG. The case where an overcurrent flows through the high-side power transistor MP21 will be described with reference to FIG. The same applies when an overcurrent flows through the low-side power transistor MN21.

First, consider a case (ground fault) where the input terminal IN is at a high level and the output terminal OUT is short-circuited to the ground terminal GND. When the output terminal OUT and the ground terminal GND are short-circuited, the output current _{I DSH} of the high-side power transistor MP21 is increased. Then, the temperature of the high side power transistor MP21 rises. On the other hand, the high-side monitor voltage _{V SENSEH} is lowered in proportion to the value of the output current _{I DSH} of the high-side power transistor MP21. When the value of the high side monitor voltage V _SENSEH becomes equal to or lower than the high side overcurrent detection reference voltage V _DCTH , the high side overcurrent detection signal V _OCDCTH is output. As described above, even if the high-side overcurrent detection signal V _OCDCTH goes high, the overcurrent protection signal is not output until the high-side _blanking time ends. On the other hand, the temperature of the high side power transistor MP21 continues to rise. Before high side gutters ranking period ends, the temperature of the high-side power transistor MP21 reaches a thermal breakdown temperature T _DES, without overcurrent protection signal is output, the high-side power transistor MP21 leads to destruction.

  Furthermore, the power transistor may be destroyed even when pulses shorter than the blanking time are continued. This phenomenon will be described with reference to FIG. Here, the case where an overcurrent flows through the high-side power transistor MP21 will be described, but the same applies to the case where an overcurrent flows through the low-side power transistor MN21.

As shown in FIG. 18A, a case is considered in which a signal _VIN having a continuous high level pulse width less than the blanking time is input to the input terminal IN. At this time, the output terminal OUT is short-circuited (ground fault) with the ground terminal GND. When the input signal V _IN is input, the output signal V _OUT once rises to the voltage PV _DD when the input signal V _IN becomes high level as shown in FIG. 18B, but the output terminal OUT is grounded. Therefore, it then decreases toward the ground potential. This descending speed depends on the inductance component included in the short circuit path. Further, as shown in FIG. _{18C, the} current value of the high-side power transistor output current _IDSH increases only while the input signal _VIN is at a high level. Then, as shown in FIG. _18D , the potential of the high side monitor voltage V _SENSEH drops only while the input signal _VIN is at the high level. When the potential of the high side monitor voltage V _SENSEH becomes equal to or lower than the high level overcurrent detection reference voltage V _DCTH , the high side overcurrent detection signal V _OCDCTH is output (FIG. 18 (e)). However, _since the pulse width of the high-side overcurrent detection signal V _OCDCTH is less than the high-side _blanking time, the high-side overcurrent protection signal V _OCPH (FIG. 18 (f)), the overcurrent protection signal V _OCP (FIG. 18 (g )) Is not output. On the other hand, the temperature of the high-side power transistor MP21 rises while the input signal _VIN is at a high level and falls while it is at a low level. However, the shorter the pulse period of the input signal _VIN, the smaller the temperature drop of the high side power transistor MP21. Therefore, when the temperature rise of the high-side power transistor MP21 is above the temperature decrease, the temperature of the high-side power transistor MP21 continues to rise and reaches a thermal breakdown temperature T _DES, the high-side power transistor MP21 leads to destruction.

  An object of the present invention is to sufficiently secure a protection capability against a large current flowing in a power transistor while ensuring the tolerance of an overcurrent protection circuit against ringing.

In order to achieve the above object, an invention according to claim 1 is directed to an overcurrent detection circuit that generates an overcurrent detection signal when an output current flowing through a power transistor exceeds a first reference value, and the overcurrent detection signal. In an overcurrent protection circuit including a blanking circuit that generates an overcurrent protection signal when the overcurrent detection circuit generates the overcurrent detection signal. A blanking time control circuit for reducing the blanking time of the blanking circuit when the output current flowing through the power transistor increases, and the blanking time control circuit is proportional to the magnitude of the output current flowing through the power transistor. A time control current is generated, and the blanking circuit generates an overcurrent detection signal by the overcurrent detection circuit. A blanking time control capacitor that is charged by the blanking time control current output from the blanking time control circuit when the charging voltage of the blanking time control capacitor exceeds a second reference value. A protection signal is output .

According to the present invention, the overcurrent protection circuit is controlled so that the blanking time is shortened as the output current of the power transistor increases. Therefore, the overcurrent protection circuit is blocked by a weak output current due to ringing included in the voltage waveform of the output terminal. While the ranking time can be secured for a long time, the blanking time can be shortened for a large output current, such as when the output terminal is short-circuited. Therefore, it is possible to sufficiently secure the protection capability against a large current flowing in the power transistor while ensuring the tolerance of the overcurrent protection circuit against ringing.

Further , the blanking time control circuit generates a blanking time control current proportional to the magnitude of the output current flowing through the power transistor, so that the blanking time can be changed in inverse proportion to the blanking time control current. . Therefore, it is possible to sufficiently secure the protection capability against a large current flowing through the power transistor while ensuring the tolerance of the overcurrent protection circuit against ringing.

It is a circuit diagram of the overcurrent protection circuit of the Example of this invention. FIG. 2 is a specific circuit diagram of a high-side overcurrent protection circuit 16H in FIG. (A) is a characteristic diagram showing the relationship between the high-side monitor voltage and the high-side blanking time control current, and (b) is a characteristic diagram showing the relationship between the high-side monitor voltage and the high-side blanking time. FIG. 2 is a specific circuit diagram of a low-side overcurrent protection circuit 16L in FIG. (A) is a characteristic diagram showing the relationship between the low side monitor voltage and the low side blanking time control current, (b) is a characteristic diagram showing the relationship between the low side monitor voltage and the low side blanking time. It is an operation | movement waveform diagram of the overcurrent protection circuit of the Example of this invention. It is a circuit diagram of the conventional switching drive circuit. FIG. 8 is an operation waveform diagram of the switching drive circuit of FIG. 7. It is a circuit diagram of the conventional overcurrent protection circuit. It is an operation | movement waveform diagram of the conventional high side overcurrent protection circuit. It is an operation | movement waveform diagram of the conventional low side overcurrent protection circuit. It is an operation | movement waveform diagram of the malfunction which arises when the blanking time is not ensured in the conventional overcurrent protection circuit. It is a specific circuit diagram of a conventional high-side overcurrent protection circuit. FIG. 14 is a specific operation waveform diagram of the high-side overcurrent protection circuit of FIG. 13. It is a specific circuit diagram of a conventional low-side overcurrent protection circuit. FIG. 16 is a specific operation waveform diagram of the low-side overcurrent protection circuit of FIG. 15. In the conventional overcurrent protection circuit, it is an operation waveform diagram of an example in which the power transistor is thermally destroyed within the blanking time due to the overcurrent flowing through the high-side power transistor. In the conventional overcurrent protection circuit, when the pulse width of the output signal is less than the blanking time, it is an operation waveform diagram of an example in which the power transistor is thermally destroyed.

  FIG. 1 shows an embodiment of the overcurrent protection circuit 16 of the present invention. The overcurrent protection circuit 16 of this embodiment that replaces the overvoltage protection circuit 17 of the switching drive circuit 10 of FIG. 7 is a high side overcurrent protection circuit 16H, a low side overcurrent protection circuit 16L, an OR circuit OR1, and a D-type flip-flop DFF1. Composed. Among these, the high side overcurrent protection circuit 16H includes a high side overcurrent detection circuit 161, a high side blanking time control circuit 162, and a high side blanking circuit 163. The low side overcurrent protection circuit 16L includes a low side overcurrent detection circuit 164, a low side blanking time control circuit 165, and a low side blanking circuit 166.

FIG. 2 shows a specific circuit configuration of the high-side overcurrent protection circuit 16H. The high side overcurrent protection circuit 16H includes a current source I1, PMOS transistors MP1 to MP5, NMOS transistors MN1 to MN3 and MN6, high voltage NMOS transistors MN4 and MN5, PNP transistors QP1 and QP2, NPN transistors QN1 and QN2, and high side blanking. Time control resistor R1, high side blanking time control capacitor C1, comparators 1611 and 1631, level shift circuit 1612, inverters INV1 and INV2, voltage source of high side overcurrent detection reference voltage V _DCTH , high side _blanking time reference voltage V _BLNKH Consists of a voltage source. Among these, the high-side overcurrent detection circuit 161 is configured by the high-side overcurrent detection reference voltage V _DCTH , the comparator 1611, and the level shift circuit 1612. The high side blanking time control resistor R1 and the transistors QP1, QP2, QN1, QN2, MN3 to MN5, and MP2 to MP4 constitute a high side blanking time control circuit 162. Further, the transistors MP5, _MN6 , the high side _blanking time control capacitor C1, the high side _blanking time reference voltage V _BLNKH , the inverter INV2, and the comparator 1631 _constitute a high side _blanking circuit 163.

このうち、電流Ｉ_{ＢＬＮＫＨ１}は一定値であるが、電流Ｉ_{ＢＬＮＫＨ２}は、ハイサイドモニタ電圧Ｖ_{ＳＥＮＳＥＨ}の値によって変化する。以下、電流Ｉ_{ＢＬＮＫＨ２}とハイサイドモニタ電圧Ｖ_{ＳＥＮＳＥＨ}の関係を導出する。 In the high-side overcurrent protection circuit 16H shown in FIG. 2, consider a case where the high-side overcurrent detection circuit 161 detects an overcurrent and outputs a high-side overcurrent detection signal V _OCDCTH . When the high side overcurrent detection signal V _OCDCTH is output, the transistor MP5 is turned on and the MN6 is turned off via the inverter INV1, and the high side _blanking time control current I _BLNKH is supplied to the high side _blanking time control capacitor C1. Inflow. The Haisai Dov Index Time Control current _{I BLNKH} includes a current _{I BLNKH1} that is the current mirror from a current source I1, since the sum of the current _{I BLNKH2} output from the high side bleed ranking time control circuit 162, the relationship of formula (1) Holds.

Among these, the current I _BLNKH1 is a constant value, but the current I _BLNKH2 varies depending on the value of the high side monitor voltage V _SENSEH . Hereinafter, the relationship between the current I _BLNKH2 and the high side monitor voltage V _SENSEH is derived.

となる。また、電流Ｉ_Ｒ１は、ハイサイドモニタ電圧Ｖ_{ＳＥＮＳＥＨ}を用いて式（３）のように記述することができる。ここで、Ｖ_{ＢＥＱＰ１}はトランジスタＱＰ１のベース・エミッタ間電圧、Ｖ_{ＢＥＱＰ２}はＰＮＰトランジスタＱＰ２のベース・エミッタ間電圧である。

このとき、ＱＰ１、ＱＰ２が同一のＰＮＰトランジスタとすれば、電流Ｉ_Ｒ１は式（４）の関係が成り立つ。

よって、式（１）、式（２）、式（４）より、ハイサイドブランキング時間制御電流Ｉ_{ＢＬＮＫＨ}は次の式で表すことができる。

図３（ａ）に、ＰＶ_ＤＤ基準ハイサイドモニタ電圧「ＰＶ_ＤＤ−Ｖ_{ＳＥＮＳＥＨ}」とハイサイドブランキング時間制御電流Ｉ_{ＢＬＮＫＨ}の関係を示した。 The current flowing through the resistor R1 and _{I R1,} QN1, QN2 are the same of the NPN transistor, when the MP3, MP4 are the same PMOS transistor,

It becomes. In addition, the current I _R1 can be described as in Expression (3) using the high-side monitor voltage V _SENSEH . _{Here, V BEQP1} the base-emitter voltage of the transistor _{QP1, V BEQP2} is the base-emitter voltage of the PNP transistor QP2.

At this time, if the QP1 and QP2 are the same PNP transistor, the current I _R1 satisfies the relationship of the expression (4).

Therefore, from the equations (1), (2), and (4), the high-side _blanking time control current I _BLNKH can be expressed by the following equation.

FIG. 3A shows the relationship between the PV _DD reference high-side monitor voltage “PV _DD −V _SENSEH ” and the high-side _blanking time control current I _BLNKH .

よって、式（５）、式（６）より、ハイサイドブランキング時間ｔ_{ＢＬＮＫＨ}とハイサイドモニタ電圧Ｖ_{ＳＥＮＳＥＨ}の間には式（７）の関係が成り立つ。

図３（ｂ）に、ＰＶ_ＤＤ基準ハイサイドモニタ電圧「ＰＶ_ＤＤ−Ｖ_{ＳＥＮＳＥＨ}」とハイサイドブランキング時間ｔ_{ＢＬＮＫＨ}の関係を示した。 Since the high side _blanking time control current I _BLNKH flows into the high side _blanking time control capacitor C1, the high side _blanking time t _BLNKH can be expressed by the relationship of Expression (6).

Therefore, from the equations (5) and (6), the relationship of the equation (7) is established between the high side _blanking time t _BLNKH and the high side monitor voltage V _SENSEH .

FIG. 3B shows the relationship between the PV _DD reference high-side monitor voltage “PV _DD −V _SENSEH ” and the high-side _blanking time t _BLNKH .

Next, FIG. 4 shows a specific circuit configuration of the low-side overcurrent protection circuit 16L. The low side overcurrent protection circuit 16L includes a current source I2, PMOS transistors MP6 to MP11, NMOS transistor MN7, NPN transistors QN3 and QN4, low side blanking time control resistor R2, low side blanking time control capacitor C2, comparators 1641 and 1661, inverters INV3, INV4, a low-side overcurrent detection reference voltage V _DCTL voltage source, and a low-side blanking time reference voltage V _BLNKL voltage source. Among these, the low-side overcurrent detection circuit 164 includes the low-side overcurrent detection reference voltage V _DCTL and the comparator 1641. Further, the low side blanking time control resistor R2 and the transistors QN3, QN4, MP7 to MP10 constitute a low side blanking time control circuit 165. Further, the transistors MP11 and MN7, the low side blanking time control capacitor C2, the low side blanking time reference voltage V _BLNKL , the comparator 1661, and the inverter INV4 constitute a low side blanking circuit 166.

このうち、電流Ｉ_{ＢＬＮＫＬ１}は一定値であるが、電流Ｉ_{ＢＬＮＫＬ２}は、ローサイドモニタ電圧Ｖ_{ＳＥＮＳＥＬ}の値によって変化する。以下、電流Ｉ_{ＢＬＮＫＬ２}とローサイドモニタ電圧Ｖ_{ＳＥＮＳＥＬ}の関係を導出する。 Consider a case where in the low-side overcurrent protection circuit 16L shown in FIG. 4, the low-side overcurrent detection circuit 164 detects an overcurrent and outputs a low-side overcurrent detection signal V _DCTL . When the low-side overcurrent detection signal V _OCDCTL is output, the transistor MP11 is turned on and the MN7 is turned off via the inverter INV3, and the low-side blanking time control current _IBLNKL flows into the low-side blanking time control capacitor C2. To do. The current _{I BLNKL} includes a current _{I BLNKL1} that is the current mirror current source I2, because the sum of the current _{I BLNKL2} output from the low-side blanking time control circuit 165, the relationship of Equation (8) holds.

Among these, the current _IBLNKL1 is a constant value, but the current _IBLNKL2 varies depending on the value of the low-side monitor voltage V _SENSEL . Hereinafter, the relationship between the current I _BLNKL2 and the low-side monitor voltage V _SENSEL is derived.

となる。また、電流Ｉ_Ｒ２は、ローサイドモニタ電圧Ｖ_{ＳＥＮＳＥＬ}を用いて式（１０）のように記述することができる。ここで、Ｖ_{ＢＥＱＮ３}はトランジスタＱＮ３のベース・エミッタ間電圧、Ｖ_{ＢＥＱＮ４}はトランジスタＱＮ４のベース・エミッタ間電圧である。

このとき、ＱＮ３、ＱＮ４が同一のＮＰＮトランジスタとすれば、電流Ｉ_Ｒ２は式（１１）の関係が成り立つ。

よって、式（８）、式（９）、式（１１）より、ローサイドブランキング時間制御電流Ｉ_{ＢＬＮＫＬ}は次の式で表すことができる。

図５（ａ）に、ローサイドモニタ電圧Ｖ_{ＳＥＮＳＥＬ}とローサイドブランキング時間制御電流Ｉ_{ＢＬＮＫＬ}の関係を示した。 When the current flowing through the resistor R2 and _{I R2,} and MP8, MP10 are the same PMOS transistor,

It becomes. Further, the current I _R2 can be described as in Expression (10) using the low-side monitor voltage V _SENSEL . _{Here, V BEQN3} the base-emitter voltage of the transistor _{QN3, V BEQN4} is the base-emitter voltage of the transistor QN4.

At this time, if QN3 and QN4 are the same NPN transistor, the current I _R2 satisfies the relationship of Expression (11).

Therefore, from the equations (8), (9), and (11), the low side blanking time control current _IBLNKL can be expressed by the following equation.

FIG. 5A shows a relationship between the low-side monitor voltage V _SENSEL and the low-side blanking time control current _IBLNKL .

よって、式（１２）、式（１３）より、ローサイドブランキング時間ｔ_{ＢＬＮＫＬ}とローサイドモニタ電圧Ｖ_{ＳＥＮＳＥＬ}の間には式（１４）の関係が成り立つ。

図５（ｂ）に、ローサイドモニタ電圧Ｖ_{ＳＥＮＳＥＬ}とローサイドブランキング時間ｔ_{ＢＬＮＫＬ}の関係を示した。
図６に本発明の過電流保護回路１６において、ハイサイドパワートランジスＭＰ１に過電流が流れた場合の動作波形を示す。 Since the low side blanking time control current _IBLNKL flows into the blanking time control capacitor C2, the low side blanking time _tBLNKL can be expressed by the relationship of Expression (13).

Therefore, from the equations (12) and (13), the relationship of the equation (14) is established between the low side blanking time t _BLNKL and the low side monitor voltage V _SENSEL .

FIG. 5B shows a relationship between the low side monitor voltage V _SENSEL and the low side blanking time t _BLNKL .
FIG. 6 shows an operation waveform when an overcurrent flows through the high-side power transistor MP1 in the overcurrent protection circuit 16 of the present invention.

As described above, the present embodiment is configured such that the charging speed to the blanking time control capacitor is slower as the current value of the output current of the power transistor is smaller, so the blanking time at this time is longer. It will be time. On the other hand, since the charging speed to the blanking time control capacitor increases as the current value of the output current of the power transistor increases, the blanking time at this time becomes shorter. As a result, the blanking time can be secured for a long time with the weak output current due to ringing included in the waveform of the output voltage _VOUT , while the blanking time for a large output current such as when the output terminal is short-circuited. Can be shortened. Therefore, it is possible to sufficiently secure the protection capability against a large current flowing in the power transistor while ensuring the tolerance of the overcurrent protection circuit against ringing.

DESCRIPTION OF SYMBOLS 10: Switching drive circuit 11: Control logic circuit 12H: High side level shift circuit, 12L: Low side level shift circuit 13H: High side pre-driver circuit, 13L: Low side pre-driver circuit 14H: High side output circuit, 14L: Low side output circuit 15H: High-side output current monitor circuit, 15L: Low-side output current monitor circuit 16: Overcurrent protection circuit, 16H: High-side overcurrent protection circuit, 16L: Low-side overcurrent protection circuit, 161: High-side overcurrent detection circuit, 1611 : Comparator, 1612: level shift circuit, 162: high side blanking time control circuit, 163: high side blanking circuit, 1631: comparator, 164: low side overcurrent detection circuit, 1641: comparator 65: Low side blanking time control circuit, 166: Low side blanking circuit, 1661: Comparator 17: Overcurrent protection circuit, 17H: High side overcurrent protection circuit, 17L: Low side overcurrent protection circuit, 171: High side overcurrent detection Circuit, 1711: Comparator, 1712: Level shift circuit, 172: High side blanking circuit, 1721: Comparator, 173: Low side overcurrent detection circuit, 1721: Comparator, 174: Low side blanking circuit, 1741: Comparator 18: Load

Claims (1)

An overcurrent detection circuit that generates an overcurrent detection signal when the output current flowing through the power transistor exceeds the first reference value, and an overcurrent protection signal when the overcurrent detection signal continues beyond the blanking time In an overcurrent protection circuit including a blanking circuit that
A blanking time control circuit for reducing a blanking time of the blanking circuit when the output current flowing through the power transistor increases when the overcurrent detection circuit generates the overcurrent detection signal ;
The blanking time control circuit generates a blanking time control current proportional to the magnitude of the output current flowing through the power transistor,
The blanking circuit includes a blanking time control capacitor that is charged by the blanking time control current output from the blanking time control circuit when the overcurrent detection circuit generates the overcurrent detection signal. When the charging voltage of the blanking time control capacitor exceeds the second reference value, an overcurrent protection signal is output.
An overcurrent protection circuit characterized by that.

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