JP5605705B2 - Vertical field effect transistor - Google Patents

Description

  In the present invention, a semiconductor channel portion is extended between a source electrode and a drain electrode arranged in a pair of surface regions facing each other, and a conduction channel formed in the semiconductor channel portion is controlled by an electric field applied from the gate electrode. The present invention relates to a vertical field effect transistor.

  A vertical transistor is known as a field effect transistor capable of flowing a large current and realizing a high operation speed. An example of the vertical transistor is shown in FIG. 10 (see, for example, cited document 1). FIG. 10 is a cross-sectional view of a conventional vertical transistor.

  This vertical transistor has a structure in which a drain electrode 31, a carrier moving layer 32, and a source electrode 33 are stacked on a substrate 30. A gate electrode 35 is provided on the side of the carrier moving layer 32 with an insulating film 34 interposed therebetween. A conduction channel formed in the carrier moving layer 32 is controlled by a control voltage applied to the gate electrode 35.

  Such a vertical transistor has a structure in which current flows in the vertical direction of the conductive layer, unlike a structure in which current flows in the horizontal direction of the conductive layer in the case of a horizontal field effect transistor such as a conventional MOS transistor. Accordingly, the moving distance of the carrier can be shortened. That is, the channel length that is the current path of the transistor can be shortened to the thickness of the carrier moving layer 32. For this reason, even if a semiconductor having a low carrier mobility is used for the carrier moving layer 32, the FET has a high switching speed and a large on-state output current value.

  In addition, the structure of the vertical transistor can be easily manufactured using a simple vapor deposition method or the like. In the conventional FET, a plurality of lithography processes are required to form the source electrode, the channel, the drain electrode, and the gate electrode, whereas in this vertical transistor structure, the source electrode, the carrier moving layer (organic semiconductor) This is because the layer) and the drain electrode layer are sequentially laminated on the substrate.

  Since the vertical transistor has such characteristics, for example, it is more suitable as a control element (sometimes referred to as a switching element) for a light emitting layer such as an organic EL layer that requires high-speed response than a horizontal transistor. It is thought that

JP 2003-28284 A

  Although the above-described conventional vertical transistor improves the obtained on-current value as compared with the horizontal transistor, it cannot be said that the on-state resistance value is sufficiently low, and there is a limit to increasing the amount of on-current. Therefore, for example, as an organic transistor for switching of all organic EL display pixels, it has been difficult to obtain a sufficiently high on-off ratio necessary for high contrast.

  An object of the present invention is to solve the above-mentioned conventional problems, and to provide a vertical field effect transistor capable of increasing the amount of current at the time of ON and obtaining a high on-off ratio.

In order to solve the above problems, the vertical field effect transistor of the present invention is a resin substrate as an element for forming a single field effect transistor element structure, and has a plurality of protrusions and the protrusions on the surface thereof. An insulating substrate integrally formed with a concave-convex surface comprising concave portions between the parts, a gate electrode formed by a conductive layer provided on the concave-convex surface of the insulating substrate, and provided on the surface of the conductive layer A plurality of semiconductor channel portions formed by a semiconductor layer provided on the surface of the insulating layer continuously over at least the top region and the side wall surface region of the convex portion. A source electrode / drain electrode formed by a plurality of bottom electrode layers provided in contact with the semiconductor layer in each of the recesses and connected to each other and functioning as an integral electrode; Each having a drain electrode / source electrode formed by a plurality of top electrode layers that are provided in contact with the semiconductor layer and are connected to each other and function as an integrated electrode, and a gate voltage is applied to the gate electrode. upon application, you characterized in that electrically conductive paths are formed collectively by an electric field acting through the gate insulating portion to each of the plurality of semiconductor channel portion.

  According to the vertical field effect transistor having the above-described configuration, since the electric conduction path is formed in each of the plurality of semiconductor channel portions, it is possible to increase the cross-sectional area of the electric conduction path, thereby easily increasing the current amount. And a high on-off ratio can be obtained.

  Due to the above effects, for example, when used for driving all organic EL display pixels, the switching efficiency can be remarkably increased.

Sectional drawing of the vertical field effect transistor in Embodiment 1 FIG. 1A is a plan view of the same vertical field effect transistor shown in a cross section along the line A1-A1 in FIG. 1A. Sectional drawing of the vertical field effect transistor in Embodiment 2 FIG. 2A is a plan view of the same vertical field-effect transistor shown in a cross section along line B1-B1 Sectional drawing of the vertical field effect transistor in Embodiment 3 FIG. 3A is a plan view of the same vertical field-effect transistor shown in a section taken along line C1-C1 in FIG. 3A. Perspective view of a vertical field effect transistor according to Embodiment 4 Sectional drawing which shows the structure of the cross section along the DD line in FIG. 4A Sectional drawing which shows the other structure of the cross section along the DD line in FIG. 4A Sectional drawing which shows the other structure of the cross section along the DD line in FIG. 4A The perspective view which shows the process of the manufacturing method of the vertical field effect transistor in Embodiment 4. The perspective view which shows the process after the process of FIG. 5A of the manufacturing method The perspective view which shows the process after the process of FIG. 5B of the manufacturing method The perspective view which shows the process after the process of FIG. 5C of the manufacturing method The figure which shows the transfer characteristic of the vertical field effect transistor in Embodiment 4 Sectional drawing of the vertical field effect transistor in Embodiment 5 Sectional drawing of the vertical field effect transistor in Embodiment 6 A perspective view showing a part of a vertical field effect transistor array device according to Embodiment 7 Sectional view of a conventional vertical transistor

  The vertical field effect transistor of the present invention can take the following aspects based on the above-described configuration.

  That is, the gate insulating part can be formed of an electrolyte. By using an electrolyte for the gate insulating portion, an electric field can be easily applied to the semiconductor. Moreover, it is preferable to use an ionic liquid electrolyte as the electrolyte. Thereby, it is possible to improve the high-speed response particularly.

  In addition, the gate insulating part is configured by a combination of a dielectric and an electrolyte, and when a gate voltage is applied to the gate electrode, an electric field acting through the electrolyte collectively causes each of the plurality of semiconductor channel parts. An electric conduction path may be formed.

  In addition, the gate electrode includes a plurality of distributed gate electrodes arranged in a distributed manner between the plurality of semiconductor channel portions, and when a gate voltage is applied to the gate electrode, the gate electrode An electric conduction path can be formed collectively in each of the plurality of semiconductor channel portions by an electric field acting through the electrolyte.

  Further, the gate insulating part is made of a dielectric, and the gate electrode includes a plurality of distributed gate electrodes arranged in correspondence with each of the semiconductor channel parts, and a gate voltage is applied to the gate electrode. In this case, an electric conduction path can be collectively formed in each of the plurality of semiconductor channel portions by an electric field acting via the dielectric from each of the distributed gate electrodes.

  The gate insulating part may be interposed between the plurality of semiconductor channel parts to electrically isolate the semiconductor channel parts from each other.

  The semiconductor channel part can be formed by molecular material growth by self-organization.

  In the above basic configuration, the plurality of semiconductor channel portions extending from the source electrode to the drain electrode are preferably formed using a substrate having an uneven surface (uneven substrate) as follows.

  That is, as a first configuration using an uneven substrate, an insulating substrate having an uneven surface formed by a plurality of convex portions and concave portions between the convex portions is provided, and the gate electrode is provided on the uneven surface of the insulating substrate. The gate insulating portion is formed by an insulating layer provided on the surface of the conductive layer, and the semiconductor channel portion is at least in the top region and the side wall surface region of the convex portion. A semiconductor layer provided on the surface of the insulating layer continuously, and one of the source electrode and the drain electrode is in contact with the semiconductor layer on the surface of the insulating layer in each of the recesses. A plurality of electrode layers connected to each other and formed as a bottom electrode layer functioning as an integral electrode, and the other of the source electrode and the drain electrode is formed on each of the convex portions. Kicking a plurality of electrode layers provided in contact with the semiconductor layer in the top region is connected can be configured which is formed by the top electrode layer serving as an integral electrode.

  Further, as a second configuration using the concavo-convex substrate, an insulating substrate having a concavo-convex surface formed by a plurality of convex portions and concave portions between the convex portions is provided, and the semiconductor channel portion is at least a top region of the convex portion. And a semiconductor layer provided on the surface of the insulating layer continuously over the side wall surface region, and one of the source electrode and the drain electrode is formed on the surface of the insulating layer in each of the recesses. A plurality of electrode layers provided in contact with the semiconductor layer are connected to form a bottom electrode layer that functions as an integral electrode, and the other of the source electrode and the drain electrode is formed in a top region of each of the convex portions. A plurality of electrode layers provided in contact with the semiconductor layer are connected to form a top electrode layer functioning as an integral electrode, and the gate insulating portion is at least a front electrode Formed by an electrolyte layer provided in contact with the semiconductor layer formed on the surface of the side wall surface region of the protrusion, and the gate electrode is formed by an electrode for an electrolyte layer provided in contact with the electrolyte layer It can be set as the structure made.

  Further, as a third configuration using the concavo-convex substrate, a conductive substrate having a concavo-convex surface formed by a plurality of convex portions and concave portions between the convex portions is provided, and the gate electrode is formed by the conductive substrate. The gate insulating part is formed by an insulating layer provided on the concavo-convex surface of the conductive substrate, and the semiconductor channel part continuously extends over at least the top region and the side wall surface region of the convex part. A plurality of semiconductor layers provided on the surface of the insulating layer, wherein one of the source electrode and the drain electrode is provided in contact with the semiconductor layer on the surface of the insulating layer in each of the recesses; An electrode layer is connected to form a bottom electrode layer that functions as an integral electrode, and the other of the source electrode and the drain electrode is connected to the top region of each of the convex portions. Are connected to the plurality of electrode layers provided in contact with the body layer can be a configuration defined by the top electrode layer serving as an integral electrode.

  In any configuration using the uneven substrate, the insulating substrate is preferably formed of a flexible material. In particular, the insulating substrate is preferably formed of a resin.

  Moreover, in any configuration using the concavo-convex substrate, it is preferable that the semiconductor layer is continuously formed on at least a part of the surface of the concave portion from the side wall surface region of the convex portion.

  The top electrode layer and the bottom electrode layer are preferably formed on an upper surface of the semiconductor layer.

  Further, in any configuration using the concavo-convex substrate, a comb shape comprising a plurality of streak-like protrusions arranged in parallel to each other on the surface of the substrate and a connecting part for connecting them at one end. A raised region is provided, each of the streaky projections forms the convex portion, and each of a plurality of gaps between the streaky projections forms the concave portion, and the comb of the comb-shaped raised region A bottom connection electrode portion that connects the plurality of bottom electrode layers formed for each of the plurality of recesses is formed in a region facing the tip of the tooth of the tooth, and in the region of the connection portion of the comb-shaped ridge region, It can be set as the structure in which the top connection electrode part which connects several top electrode layers was formed.

  In this case, it is preferable that the condition of S / W ≦ 10 is satisfied, where W is the width of the streak protrusions in the surface direction of the substrate and S is the interval between the streak protrusions.

  It is preferable that the condition of H / W ≧ 0.3 is satisfied, where W is the width of the streak protrusion in the surface direction of the substrate and H is the height of the streak protrusion from the recess surface.

  Further, in any configuration using the concavo-convex substrate, a plurality of island-shaped projections spaced from each other are provided on the surface of the substrate, and each of the island-shaped projections forms the plurality of projections. The gap between the island-shaped protrusions may form the recess.

  In any one of the configurations described above, the semiconductor channel portion can be configured by an organic semiconductor.

  In addition, a transistor array device can be configured by arranging a plurality of vertical field effect transistors having any of the above configurations.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
1A is a cross-sectional view of a vertical field effect transistor according to Embodiment 1, and FIG. 1B is a plan view showing a cross section taken along line A1-A1 in FIG. 1A. 1A shows a cross section taken along line A2-A2 in FIG. 1B.

  1A and 1B show the elements that form a single vertical field effect transistor device structure. The source electrode 1 and the drain electrode 2 are respectively disposed in a pair of surface regions facing each other. A plurality of semiconductor channel portions 3 extending from the source electrode 1 to the drain electrode 2 are provided between the source electrode 1 and the drain electrode 2. That is, a group of semiconductor channel portions 3 is formed. As shown in FIG. 1B, the semiconductor channel portion 3 is two-dimensionally arranged in a region in the plane of the source electrode 1 and the drain electrode 2.

  An electrolyte 4 is interposed between the plurality of semiconductor channel portions 3 and functions as a gate insulating portion. The electrolyte 4 electrically separates the plurality of semiconductor channel portions 3 from each other. A gate electrode 5 is provided in contact with the electrolyte 4 which is a gate insulating portion. The gate electrode 5 is disposed adjacent to the side of the semiconductor channel portion 3 and can apply an electric field to the plurality of semiconductor channel portions 3 collectively via the electrolyte 4.

  That is, when a gate voltage is applied between the source electrode 1 or drain electrode 2 and the gate electrode 5 and an electric field is applied to the semiconductor channel portion 3, an electric conduction path is collectively formed in each of the plurality of semiconductor channel portions 3. It is formed. For example, when a gate voltage of about 0.5 V is applied, an electric double layer is formed near the surface of the electrolyte 4 in contact with the semiconductor channel portion 3. Due to the electric field effect due to the electric field applied to the electric double layer, a charge responsible for electric conductivity appears on the surface of the semiconductor channel portion 3 in contact with the electrolyte 2. By using the electric double layer, it is possible to apply a high electric field to the semiconductor channel portion 3 even with a small gate voltage, and accordingly, more carriers can be injected.

  Thus, based on the electric field effect by the voltage applied to the gate electrode 5, the conductivity can be collectively controlled for a plurality of electric conduction paths. By forming an electric conduction path in each of the plurality of semiconductor channel portions 3, it is possible to substantially reduce electric power compared with a vertical field effect transistor having a conventional structure having only a single semiconductor channel portion in a single element. The cross-sectional area of the conduction path is remarkably increased, and the amount of current flowing between the source electrode 1 and the drain electrode 2 can be greatly increased. Further, the current density in the region between the source electrode 1 and the drain electrode 2 is increased as compared with the conventional example.

  In the above configuration, as the semiconductor channel portion 3, an organic semiconductor such as a high molecular organic semiconductor, a low molecular organic semiconductor, or an organic semiconductor crystal, an inorganic semiconductor, an organic crystal, a charge transfer complex, a charge transfer complex crystal, a carbon nanotube, or the like is used. Can do.

  As the polymer organic semiconductor, polythiophene polymers such as poly-3-hexylthiophene (P3HT) and polybisdodecylthiophenylthienothiophene (pBTTT) can be used.

  Low molecular organic semiconductors include (1) oligoacene molecules such as pentacene, tetracene and anthracene, (2) oligoacene derivative molecules such as rubrene, tetramethylpentacene, tetrachloropentacene, diphenylpentacene and TIPS pentacene, and (3) sexithiophene. Oligothiophene molecules and their derivative molecules, (4) TCNQ (7,7,8,8-tetracyanoquinodimethane) and its derivative molecules, (5) TTF (1,4,5,8-tetrathiafulvalene) and Its derivative molecule, (6) perylene and its derivative molecule, (7) pyrene and its derivative molecule, (8) fullerene molecule such as C60 and its derivative molecule, (9) metal phthalocyanine molecule such as phthalocyanine and copper phthalocyanine and its derivative molecule (10) Porphyri And metal porphyrin molecules such as zinc porphyrin and iron porphyrin and their derivative molecules, (11) BEDT-TTF (bisethylenedithiotetrathiofulvalene) and its derivative molecules, (12) DNTT (dinaphthothienothiophene) and its derivative molecules (13) BTBT (benzothienobenzothiophene) and its derivative molecules can be used.

  As the inorganic semiconductor, silicon, germanium, gallium arsenide, cadmium selenium, IGZO (indium gallium zinc oxide), IZO (indium zinc oxide), indium oxide, nickel oxide, zinc oxide, or the like can be used.

  As the charge transfer complex, (TTF) (TCNQ), (BEDT-TTF) (TCNQ), (BEDT-TTF) 2I3, (BEDT-TTF) 2Cl3, or the like can be used.

  Since the semiconductor channel portion 3 is preferably formed at a pitch of the order of several tens of nm to several hundreds of μm, it can be manufactured by the following method, for example.

  That is, a method is used in which a fine columnar structure for holding a semiconductor is manufactured and the semiconductor is attached to the surface of the columnar structure. As the columnar structure, a fine structure such as a thick film resist (epoxy resin, acrylic resin, etc.), PDMS (polydimethylsiloxane), nanoimprint, alumina anodization, or the like can be used. As the semiconductor material, a spin coatable polymer such as the aforementioned P3HT (poly-3-hexylthiophene) can be used. Alternatively, the crystal of the semiconductor channel portion 3 may be formed on the surface or the gap of the columnar structure.

  Alternatively, as another manufacturing method of the semiconductor channel portion 3, a method of molding the semiconductor channel portion 3 using a stamp with a fine structure, a sacrificial material, or the like can be used. As the stamp material, the same materials as those for the thick film resist, PDMS, nanoimprint substrate and the like described above can be used. The structure of the semiconductor channel part 3 can be manufactured by pressing the stamp against the solution of the semiconductor channel part 3 to cure the material of the semiconductor channel part 3 and then removing the stamp.

  As yet another method of manufacturing the semiconductor channel portion 3, a method of forming a fine structure by self-organization of a semiconductor material can be used. In this case, the semiconductor channel portion 3 is fabricated by material growth by self-organization such as electric field growth or nanowire fabrication, and the gate insulating portion is formed in contact with the semiconductor channel portion 3. As a material of the semiconductor channel portion 3, a material capable of material growth such as carbon nanotube or Si nanowire is used.

  As the electrolyte, an ionic liquid, an ionic liquid gel, a polymer electrolyte, a liquid electrolyte, a gel electrolyte, or the like can be used. In particular, it is desirable to use an ionic liquid as the electrolyte 4. The ionic liquid has a low viscosity and can be expected to have a fast response.

  That is, when an ionic liquid electrolyte is used for the gate insulating portion, a sufficiently large current can be passed only by applying a low switching voltage (a voltage between the gate electrode, the source electrode and the drain electrode) to the gate electrode. Therefore, power consumption of the field effect transistor can be reduced.

  Further, by using the properties of the ionic liquid electrolyte, high frequency response and high ionic conductivity can be realized. The ionic liquid electrolyte exhibits a high capacitance even at a high frequency. That is, when an ionic liquid electrolyte is used for the gate insulating portion, it is possible to obtain a high frequency response by utilizing the high ionic conductivity inherent in the ionic liquid electrolyte.

Further, since the ionic liquid electrolyte is a liquid having a low viscosity at room temperature, it can be easily distributed in the space between the plurality of semiconductor channel portions 3 arranged two-dimensionally. In addition, the adhesion between the surface of the organic semiconductor material is improved and the carrier mobility is high. In particular, when EMI (CF ₃ SO ₂ ) ₂ N is used as the ionic liquid electrolyte, the carrier mobility can be 10 ⁻³ cm ² / Vs.

Here, an example of a method for manufacturing a vertical field effect transistor using an ionic liquid electrolyte in this embodiment will be described. The case where P3HT which is an organic semiconductor, that is, poly-3-hexylthiophene, is used as the semiconductor channel portion 3 and EMI (CF ₃ SO ₂ ) ₂ N which is an ionic liquid electrolyte is used as the electrolyte 4 is shown.

  First, a plurality of columnar structures are formed between the source electrode 1 and the drain electrode 2 by using a thick film resist made of an epoxy resin. As the epoxy resin for this purpose, for example, “SU-8”, “KMPR”, etc. manufactured by “Kayaku Microchem” can be used.

  Next, a solution in which P3HT is dissolved in toluene or chloroform is poured into a region between the source electrode 1 and the drain electrode 2 where a plurality of columnar structures are formed, and is dried, whereby the epoxy resin columnar structure is formed. A P3HT semiconductor layer is formed around each.

  Next, an ionic liquid electrolyte is filled around the columnar structure where the semiconductor layer is formed between the source electrode 1 and the drain electrode 2. Further, the vertical field effect transistor is completed by disposing the gate electrode 5 in contact with the electrolyte 4 (ionic liquid electrolyte) and not in contact with the source electrode 1, the drain electrode 2, and the P3HT semiconductor layer.

In the vertical field effect transistor thus fabricated, as the gate voltage Vg is negatively applied, positive conductive charges gradually accumulate in the P3HT organic semiconductor and flow between the source electrode 1 and the drain electrode 2. A field effect appears in which the measured current value increases. When the carrier mobility μ was determined from the increasing rate when the measured value of the current flowing between the source electrode 1 and the drain electrode 2 increased with respect to the gate voltage, it was about 10 ⁻³ cm ² / Vs. .

For example, in the case of a transistor provided as a control element of a light emitting layer of an organic EL display, it is required to obtain a current amount of about 1 μA per pixel having a size of about 50 μm × 50 μm. When converted into current density, it becomes 40 mA / cm ² . In order to obtain this amount of current, in the case of a conventional organic semiconductor field effect transistor, about Vd = 10 V is required.

  On the other hand, the amount of current obtained in the case of the vertical field effect transistor of the present embodiment is roughly estimated below.

First, assuming that μ = 10 ⁻³ cm ² / Vs and ne = 6 μF / cm ² × 1V = 6 μC / cm ² , σ = ne · μ = 6 × 10 ⁻⁹ S. If the semiconductor is cylindrical and has the same radius and height, σchannel = σ × 2π = 38 × 10 ⁻⁹ / channel.

  μ is the mobility of the semiconductor, ne is the amount of charge accumulated per unit area at the interface between the semiconductor and the gate insulator, and is equal to the product of the electric double layer capacity of the ionic liquid electrolyte and the gate voltage. σ is a surface conductivity normalized to a square, and σchannel is a conductivity per channel formed of one semiconductor.

Here, the number of semiconductors per 1 cm ² is N. When the cross-sectional diameter of the semiconductor is φ = 5 μm, N = 1000 × 1000 = 10 ⁶ / cm ² and Nσchannel = 3.8 × 10 ⁻² S / cm ² when the semiconductors are arranged at intervals of 5 μm. If Vd = 1V, then Id = 38 mA / cm ² .

As described above, according to this vertical field effect transistor, the current density required for the transistor provided as the control element of the light emitting layer of the organic EL display is 40 mA / cm ² even under the low voltage condition of Vd = 1V. Equivalent characteristics can be obtained. Therefore, compared with a conventional organic semiconductor field effect transistor that requires about Vd = 10 V, the power consumption of the transistor element can be greatly reduced and the efficiency can be improved.

Further, when a planar field effect transistor using an organic semiconductor of a conventional example is examined as a comparison target, when provided as a control element of a light emitting layer of an organic EL display, mobility μ = 0.1 to ¹ cm ² / Vs If no material is used, it is difficult to obtain a current amount of about 1 μA per pixel.

However, in the current organic material, the mobility μ = 10 ⁻¹ cm ² / Vs can be obtained with good reproducibility only when a thin film of a part of low molecular weight material such as pentacene is formed by vacuum deposition. Since a polymer material can be easily formed by coating, it can be produced much more easily than a low-molecular organic thin film formed by a vacuum evaporation method, but it is difficult to obtain a mobility of 10 ⁻¹ cm ² / Vs with good reproducibility.

On the other hand, in the case of the vertical field effect transistor of this embodiment, a polymer material having a mobility of about 10 ⁻³ cm ² / Vs can obtain a sufficient amount of current as a control element for the light emitting layer of the organic EL display. It is possible. Therefore, a polymer material that is easier to manufacture can be used as a transistor for controlling the light emitting layer of an organic EL display.

  Table 1 shows the result of comparing the characteristics of the planar field effect transistor using the conventional organic semiconductor and the vertical field effect transistor of the first embodiment. In the case of the conventional example, a low molecular film by vacuum deposition is used as the semiconductor, and in this embodiment, P3HT is used as the semiconductor. The current density is a result of measurement under the conditions of Vd = 1V and Vg = 1V.

なお、上記構成の本実施の形態の縦型電界効果トランジスタにおいて、イオン液体が、ソース電極、ドレイン電極、及びＰ３ＨＴ半導体に直接接すると、ゲート電極とソース電極、ゲート電極とドレイン電極の間に漏れ電流が生じて、消費電力が増大してしまうことがある。

Note that in the vertical field effect transistor of this embodiment having the above structure, when the ionic liquid directly contacts the source electrode, the drain electrode, and the P3HT semiconductor, leakage occurs between the gate electrode and the source electrode and between the gate electrode and the drain electrode. A current may be generated and power consumption may increase.

  In order to reduce this problem, it is effective to cover any one of the source electrode, the drain electrode, and the P3HT semiconductor with a self-assembled monomolecular film or a polymer insulating film.

Further, when φ = 250 nm, the diameter is 1/20, and therefore the figure of merit is 100 times as long as the height is 1/5 μm. As a result, N = 108 / cm ² and Nσchannel = 3.8 S / cm ² . If Vd = 1V, then Id = 3.8 A / cm ² .

Thus, if φ = 250 nm, a much higher current density can be obtained with respect to the current density required for a transistor provided as a control element of the light emitting layer of the organic EL display, 40 mA / cm ² .

In addition, since Vd = 0.1V and Vg = 0.1V and Id = about 40 mA / cm ² , the drain voltage for obtaining the same current density can be greatly reduced. Therefore, the power consumption of the transistor element can be reduced and the efficiency can be increased.

Further, the amount of current on state plus -1V a negative gate voltage determined from the experimental results, when comparing the residual current of the off state without adding a gate voltage Vg, 10 ⁴ times the off state in the on state The amount of current is obtained. This on-off ratio is much larger than the on-off ratio of the conventional vertical transistor.

  Note that the gate insulating portion can also be configured by a combination of an electrolyte and a dielectric. Even in such a case, when a gate voltage is applied to the gate electrode, an electric conduction path can be easily formed in each of the plurality of semiconductor channel portions by an electric field acting through the electrolyte.

(Embodiment 2)
2A is a cross-sectional view of the vertical field effect transistor according to Embodiment 2, and FIG. 2B is a plan view showing a cross section taken along line B1-B1 in FIG. 2A. 2A shows a cross section taken along line B2-B2 in FIG. 2B. Also, the same elements as those of the vertical field effect transistor according to the first exemplary embodiment illustrated in FIG. 1A are denoted by the same reference numerals, and description thereof is not repeated.

  In the present embodiment, a dielectric 6 is used as a gate insulator instead of the electrolyte 4 used as the gate insulating portion in the first embodiment. In addition, the gate electrode is composed of a main gate electrode 7 and a plurality of distributed gate electrodes 7 a arranged in a distributed manner between the plurality of semiconductor channel portions 3. As shown in FIG. 2B, the gate terminal electrode 7 and the distributed gate electrode 7a are electrically connected by a gate connecting portion 7b.

  According to this configuration, when a gate voltage is applied to the main gate electrode 7, an electric field acts on the semiconductor channel portion 3 from each of the distributed gate electrodes 7a via the dielectric 6, thereby a plurality of semiconductor channel portions. An electrical conduction path is formed in each of the three. As a result, as in the first embodiment, it is possible to control the conductivity based on the electric field effect due to the voltage applied to the main gate electrode 7 collectively for a plurality of electrical conduction paths. By forming an electric conduction path in each of the plurality of semiconductor channel portions 3, the cross-sectional area of the substantial electric conduction path is remarkably increased, and the amount of current flowing between the source electrode 1 and the drain electrode 2 is greatly increased. It can be increased. Further, the current density in the semiconductor channel region between the source electrode 1 and the drain electrode 2 is increased as compared with the conventional example.

  Unlike the first embodiment, the present embodiment is characterized in that a dielectric is used instead of an electrolyte for the gate insulating portion. In this case, it is necessary to compensate for the function to be obtained in the case of the electrolyte, and for this purpose, a plurality of distributed gate electrodes 7 a arranged in a distributed manner among the plurality of semiconductor channel portions 3 are used. An electric field can be appropriately applied to each of the semiconductor channel portions 3 by the distributed gate electrode 7 a provided adjacent to each of the semiconductor channel portions 3. As a result, an effect equivalent to that obtained when an electrolyte is used for the gate insulating portion can be obtained.

  The configuration in which a plurality of distributed gate electrodes 7a as described above is provided may be applied when an electrolyte is used for the gate insulating portion as in the first embodiment. That is, when a gate voltage is applied to the gate electrode 7, an electric conduction path is formed collectively in each of the plurality of semiconductor channel portions 3 by an electric field that acts from each of the dispersed gate electrodes 7 a via the electrolyte. Is easily obtained. Thereby, the high-speed response can be further improved.

(Embodiment 3)
3A is a cross-sectional view of the vertical field effect transistor according to Embodiment 3, and FIG. 3B is a plan view showing a cross section taken along line C1-C1 in FIG. 3A. 3A shows a cross section taken along line C2-C2 in FIG. 3B. Also, the same elements as those of the vertical field effect transistor according to the first exemplary embodiment illustrated in FIG. 1A are denoted by the same reference numerals, and description thereof is not repeated.

  The feature of this embodiment is that a plurality of semiconductors 8 are formed by molecular material growth by self-organization. According to this configuration, the semiconductor 8 having a small cross-sectional area can be formed with high density. Thereby, it becomes easy to obtain a high current density with respect to the area of the source electrode 1.

For example, if φ = 250 nm and the height is 1/5 of 1/5, N = 10 ⁸ / cm ² and Nσchannel = 3.8 S / cm ² as in the calculation example shown in the first embodiment. If Vd = 1V, then Id = 3.8 A / cm ² .

Thus, if φ = 250 nm, a much higher current density can be obtained with respect to the current density required for a transistor provided as a control element of the light emitting layer of the organic EL display, 40 mA / cm ² .

In addition, since Vd = 0.1V and Vg = 0.1V and Id = about 40 mA / cm ² , the drain voltage for obtaining the same current density can be greatly reduced. Therefore, the power consumption of the transistor element can be reduced and the efficiency can be increased.

(Embodiment 4)
4A is a perspective view of a vertical field effect transistor according to Embodiment 4, and FIG. 4B is a cross-sectional view taken along line DD in FIG. 4A. In the present embodiment, the configuration of the vertical field-effect transistor according to the second embodiment shown in FIGS. 2A and 2B is made more specific. In the basic configuration of the second embodiment, the structure including a plurality of semiconductor channel portions 3 extending from the source electrode 1 to the drain electrode 2, the dielectric 6 functioning as a gate insulating portion, the dispersed gate electrode 7a, etc. It is formed using an insulating substrate 10 having a surface.

  The insulating substrate 10 has an uneven surface formed by a plurality of convex portions 10a and concave portions 10b between the convex portions 10a. The plurality of convex portions 10 a are formed as a plurality of streak-like projections arranged in parallel to each other on the surface of the insulating substrate 10. The plurality of convex portions 10a are connected at one end by a connecting portion 10c, and a comb-shaped raised region is formed by the convex portion 10a and the connecting portion 10c.

  A conductive layer 11 is provided on the uneven surface of the insulating substrate 10 to form a gate electrode. The conductive layer 11 is provided over all the surfaces of the top region, the side wall surface region, and the concave portion 10b of the convex portion 10a. An insulating layer 12 is provided on the surface of the conductive layer 11 to form a gate insulating portion. The insulating layer 12 is also provided over all the surfaces of the top region, the side wall surface region, and the recessed portion 10b of the convex portion 10a.

  The semiconductor layer 13 is provided on the surface of the insulating layer 12 continuously over the top region and the side wall surface region of the convex portion 10a. The semiconductor layer 13 is not formed on the surface of the insulating layer 12 in the region of the recess 10b. A semiconductor channel portion is formed by the semiconductor layer 13.

  A bottom electrode layer 14 a is provided in contact with the semiconductor layer 13 on the insulating layer 12 in each of the recesses 10 b. Further, a bottom connection electrode portion 14b is formed in a region facing the tip of the comb teeth (convex portion 10a) in the comb-shaped raised region. The bottom connection electrode portion 14b electrically connects a plurality of bottom electrode layers 14a formed for each recess 10b. Thereby, the plurality of bottom electrode layers 14a function as an integral electrode, and form a source electrode or a drain electrode.

  A top electrode layer 15a is provided in contact with the semiconductor layer 13 in the top region of each of the convex portions 10a. Moreover, the top connection electrode part 15b is formed in the area | region of the connection part 10c. The top connection electrode part 15b electrically connects the plurality of top electrode layers 15a formed for each convex part 10a to each other. Thereby, the plurality of top electrode layers 15a function as an integral electrode, and form a drain electrode or a source electrode.

  The vertical field effect transistor having the above configuration operates in the same manner as shown in FIGS. 2A and 2B. That is, when a gate voltage is applied to the conductive layer 11, an electric field acts on the semiconductor layer 13 through the insulating layer 12 from the conductive layer 11 provided in the side wall surface region of each protrusion 10 a. Thereby, an electric conduction path is formed in each of the plurality of semiconductor layers 13. As a result, it is possible to control the conductivity based on the electric field effect due to the voltage applied to the conductive layer 11 collectively for a plurality of electrical conduction paths. By forming an electric conduction path in each of the plurality of semiconductor layers 13, the cross-sectional area of the substantial electric conduction path is remarkably increased, and the amount of current flowing between the source electrode and the drain electrode is greatly increased. Is possible.

  The insulating substrate 10 in this embodiment is not particularly limited in material, but a flexible insulating material such as a resin material such as an epoxy resin can be used. Thereby, it is suitable for constructing a driving transistor such as an organic EL display.

  As shown in FIG. 4B, the semiconductor layer 13 only needs to be provided continuously over at least the top region and the side wall surface region of the convex portion 10a. However, the semiconductor layer 13 may be formed as shown in FIG. 4C or 4D. . FIG. 4C shows an example in which the semiconductor layer 13 is formed on a part of the surface of the concave portion 10b continuously from the side wall surface region of the convex portion 10a. FIG. 4D shows an example in which the semiconductor layer 13 is formed on the entire surface of the recess 10b.

  4B shows an example in which the bottom electrode layer 14a and the top electrode layer 15a are disposed on the top surface of the semiconductor layer 13, but a configuration in which the bottom electrode layer 14a and the top electrode layer 15a are disposed below the semiconductor layer 13 is also possible. That is, the bottom electrode layer 14a and the top electrode layer 15a may be formed on the surface of the insulating layer 12, and the semiconductor layer 13 may be formed thereon.

In the vertical field effect transistor having the above configuration, when the width in the surface direction of the insulating substrate 10 of the convex portion 10a formed as the streak-like projection portion is W and the interval between the convex portions 10a is S, S / It is desirable to configure so as to satisfy the condition of W ≦ 10. Thereby, a sufficient number of semiconductor channel portions are formed per unit surface area, and 1 A / cm ² or more, which is practically sufficient as the amount of current amplified per unit surface area, is obtained.

Moreover, when the height from the surface of the recessed part 10b of the convex part 10a formed as a stripe-shaped projection part is set to H, it is desirable to comprise so that the conditions of H / W> = 0.3 may be satisfy | filled. As a result, a practically sufficient value of 10 ⁵ or more is obtained as the on / off ratio of the current controlled by the field effect.

  Next, a method for manufacturing the vertical field effect transistor having the above configuration will be described with reference to FIGS. 5A to 5E showing perspective views of the respective steps.

  First, as shown in FIG. 5A, for example, a comb-shaped ridge including a surface of an insulating substrate 10 made of, for example, an epoxy resin, a concavo-convex surface made up of a plurality of parallel convex portions 10a and concave portions 10b, and a connecting portion 10c Form a region. Any known method may be used to form the uneven surface.

  Next, as shown in FIG. 5B, a conductive layer 11 and an insulating layer 12 are sequentially formed over the entire surface of the insulating substrate 10. However, in FIG. 5B, for convenience of illustration, the conductive layer 11 and the insulating layer 12 are drawn together. The conductive layer 11 is composed of a laminated film of a Ti film and a Pt film, for example. For example, the film is formed by sequentially sputtering Ti and Pt. By conducting sputtering from two directions, the conductive layer 11 can be formed on the entire surface of the concavo-convex surface composed of the convex portions 10a and the concave portions 10b. As the insulating layer 12, a parylene film is formed by vapor deposition, for example. Thereby, the insulating layer 12 is formed on the entire surface of the conductive layer 11.

  Next, as shown in FIG. 5C, the semiconductor layer 13 is formed by obliquely depositing an organic semiconductor material from the lateral direction of the convex portion 10 a, that is, the direction orthogonal to the longitudinal direction. Thereby, the semiconductor layer 13 is formed continuously over at least the top region and the side wall surface region of the convex portion 10a.

  Next, as shown in FIG. 5D, the bottom electrode layer 14a, the bottom connection electrode portion 14b, the top electrode layer 15a, and the top connection electrode portion 15b are formed by depositing the Au film 16 by vacuum deposition. The Au film 16 is not formed on the side surface of the convex portion 10a by performing vapor deposition strictly in the direction perpendicular to the surface of the insulating substrate 10, and the bottom electrode layer 14a, the bottom connection electrode portion 14b, and the top electrode layer. 15a and the top connection electrode portion 15b are formed to be electrically separated. Therefore, the bottom electrode layer 14a, the bottom connection electrode portion 14b, the top electrode layer 15a, and the top connection electrode portion 15b can be formed by a single deposition process.

FIG. 6 shows the results of measuring the transfer characteristics of the vertical field effect transistor produced on the flexible substrate (epoxy resin) in the fourth embodiment produced by the process as described above. The horizontal axis represents the gate voltage Vg (V), the vertical axis represents the drain _ID current (μA), and shows a curve A (refer to the left vertical axis) based on the linear scale and a curve B (refer to the right vertical axis) based on the log scale. As shown in FIG. 6, a sufficiently large current amount of about 1 A / cm ² and a sufficiently large ON-OFF ratio of about 10 ⁶ are obtained. Further, this performance was not impaired even when it was repeatedly bent 10 times or more in the lateral direction of FIG. 4C (bending radius 1 cm).

  Table 2 shows the result of comparing the characteristics of a planar field effect transistor using a conventional organic semiconductor and the vertical field effect transistor of the fourth embodiment. Table 2 also shows the characteristics of the vertical field effect transistor having the structure shown in Embodiment 6 (FIG. 8) described later. Both the conventional example and the fourth and sixth embodiments are examples in which a low molecular film by vacuum deposition is used as a semiconductor. The current density is the result of measurement under the conditions of Vd = 10V and Vg = 20V.

なお、凸部１０ａは、筋状の突起に限られず、絶縁基板１０の面上に互いに離間して設けられた複数の島状突起部として形成することもできる。その場合、島状突起部の相互間の間隙が凹部を形成する。

In addition, the convex part 10a is not restricted to a streak-like protrusion, It can also be formed as a several island-like protrusion part provided mutually spaced apart on the surface of the insulating substrate 10. FIG. In that case, the gap between the island-shaped protrusions forms a recess.

(Embodiment 5)
FIG. 7 is a cross-sectional view of a vertical field effect transistor according to the fifth embodiment. This embodiment is an example of a configuration using an insulating substrate having a concavo-convex surface as in the fourth embodiment, and the overall structure is the same as that in the fourth embodiment shown in a perspective view in FIG. 4A. It is the same. FIG. 7 shows a cross-sectional structure corresponding to the position along the line DD in FIG. 4A. However, the principle of operation is the same as in Embodiment 1 shown in FIGS. 1A and 1B, and an electrolyte is used as the gate insulating portion. The same elements as those of the vertical field effect transistor according to Embodiment 4 shown in FIGS. 4A and 4B are denoted by the same reference numerals, and the description is simplified.

  In the vertical field effect transistor according to the present embodiment, the semiconductor layer 13 is directly provided on the uneven surface of the insulating substrate 10 to form a semiconductor channel portion.

  A bottom electrode layer 14a is provided on the upper surface of the semiconductor layer 13 in each of the recesses 10b. Further, similarly to FIG. 4A, a bottom connection electrode portion 14b is formed in a region facing the tip of the convex portion 10a of the comb-shaped raised region. Accordingly, the plurality of bottom electrode layers 14a function as an integrated electrode, and form a source electrode or a drain electrode.

  A top electrode layer 15 a is provided on the upper surface of the semiconductor layer 13 in the top region of each of the protrusions 10 a. Similarly to FIG. 4A, a top connection electrode portion 15b that connects the plurality of top electrode layers 15a is formed in the region of the connection portion 10c. Therefore, the plurality of top electrode layers 15a function as an integrated electrode, and form a drain electrode or a source electrode.

  An electrolyte layer 17 is provided to cover the above elements formed on the uneven surface of the insulating substrate 10 to form a gate insulating portion. An electrolyte layer electrode 18 is provided in contact with the electrolyte layer 17 to form a gate electrode.

  The vertical field effect transistor having the above configuration operates in the same manner as that shown in FIGS. 1A and 1B. That is, when a gate voltage is applied to the electrolyte layer electrode 18, an electric double layer is formed near the surface of the electrolyte layer 17 in contact with the semiconductor layer 13. It is easy to apply a high electric field to the semiconductor layer 13 by the electric field effect due to the electric field applied to the electric double layer. Thus, based on the electric field effect by the gate voltage applied to the electrolyte layer electrode 18, the conductivity can be controlled collectively for a plurality of electrical conduction paths.

  For the semiconductor layer 13 and the electrolyte layer 17, the same materials as those shown in Embodiment Mode 1 can be used. Moreover, the semiconductor layer 13 should just be formed continuously over the top area | region and side wall surface area | region of the convex part 10a, and the semiconductor layer 13 does not need to be formed in the recessed part 10b. Also, the electrolyte layer 17 may be provided in contact with the semiconductor layer 13 formed on at least the surface of the side wall surface region of the convex portion 10a, which is effective as a portion for actually forming a semiconductor channel.

(Embodiment 6)
FIG. 8 is a cross-sectional view of a vertical field effect transistor according to the sixth embodiment. The overall structure is the same as that in the fourth embodiment shown in a perspective view in FIG. 4A. FIG. 8 shows a cross-sectional structure corresponding to the position along the line DD in FIG. 4A. Also, the same elements as those of the vertical field effect transistor according to Embodiment 4 shown in FIGS. 4A and 4B are denoted by the same reference numerals, and the description is simplified.

  In the present embodiment, conductive substrate 18 having an uneven surface is used in place of insulating substrate 10 in the fourth embodiment. The conductive substrate 18 has an uneven surface formed by a plurality of protrusions 18a and recesses 18b between the protrusions 18a.

  A gate electrode is formed by the conductive substrate 18. An insulating layer 19 is provided on the uneven surface of the conductive substrate 18 to form a gate insulating portion. The semiconductor layer 13 is provided on the surface of the insulating layer 19 continuously over at least the top region and the side wall surface region of the convex portion 18a to form a semiconductor channel portion.

  A bottom electrode layer 14a is provided on the upper surface of the semiconductor layer 13 in each of the recesses 10b. Further, similarly to FIG. 4A, a bottom connection electrode portion 14b is formed in a region facing the tip of the convex portion 10a of the comb-shaped raised region. Accordingly, the plurality of bottom electrode layers 14a function as an integrated electrode, and form a source electrode or a drain electrode.

  A top electrode layer 15 a is provided on the upper surface of the semiconductor layer 13 in the top region of each of the protrusions 10 a. Similarly to FIG. 4A, a top connection electrode portion 15b that connects the plurality of top electrode layers 15a is formed in the region of the connection portion 10c. Therefore, the plurality of top electrode layers 15a function as an integrated electrode, and form a drain electrode or a source electrode.

  The vertical field effect transistor having the above configuration operates in the same manner as shown in FIGS. 2A and 2B. That is, when a gate voltage is applied to the conductive substrate 18, an electric field acts on the semiconductor layer 13 from each convex portion 10 a via the insulating layer 19. Thereby, an electric conduction path is formed in each of the plurality of semiconductor layers 13. As a result, it is possible to control the conductivity based on the electric field effect caused by the voltage applied to the conductive substrate 18 collectively for a plurality of electrical conduction paths. By forming an electric conduction path in each of the plurality of semiconductor layers 13, the cross-sectional area of the substantial electric conduction path is remarkably increased, and the amount of current flowing between the source electrode and the drain electrode is greatly increased. Is possible.

(Embodiment 7)
FIG. 9 is a perspective view showing a part of the vertical field effect transistor array device according to the seventh embodiment. In the present embodiment, a transistor array device is configured by arranging a large number of vertical FET elements 20 having a structure as shown in any of the above-described embodiments. Such an array structure can be used, for example, for driving an organic EL element in an organic EL display. However, the illustration of the organic EL element is omitted in FIG. 9 and the wiring is only conceptually shown, which is different from the actual structure.

  A pixel is provided at each intersection of a plurality of power supply lines 21 and data lines 22 arranged in a matrix, and a vertical FET element 20 is arranged and connected for each organic EL element of each pixel (not shown). In the example of FIG. 9, each of the vertical FET elements 20 of the unit element has a comb-shaped raised region having a large number of stripe-like convex portions 10a arranged in parallel as shown in FIG. 4A.

  The power supply line 21 is connected to a drain electrode 23 formed on the upper surface of the convex portion 10a. Further, although not shown, the data line 22 is connected to the gate electrode via a selection FET element. The source electrode of the vertical FET element 20 is connected to the organic EL element. Display data is supplied to the gate electrode of the vertical FET element 20 of the pixel selected by the selection FET element, and a current corresponding thereto is supplied to the organic EL element.

  As described above, by using the vertical field effect transistor of the present invention as a transistor that supplies a driving current to at least the organic EL element, an organic EL display that exhibits a good display contrast can be obtained.

  The vertical field effect transistor of the present invention can obtain a large current and a high on-off ratio, and is useful for an all organic EL display, an ultra-thin display, a flexible display, a high-density logic operation element, and the like.

DESCRIPTION OF SYMBOLS 1 Source electrode 2 Drain electrodes 3 and 8 Semiconductor channel part 4 Electrolyte 5 Gate electrode 6 Dielectric 7 Main gate electrode 7a Dispersion gate electrode 7b Gate connection part 10 Insulating substrate 10a Projection part 10b Recession part 10c Connection part 11 Conductive layer 12 Insulation layer 13 Semiconductor layer 14a Bottom electrode layer 14b Bottom connection electrode part 15a Top electrode layer 15b Top connection electrode part 16 Au film 17 Electrolyte layer 18 Conductive substrate 18a Protrusion 18b Recess 19 Insulating layer 20 Vertical FET element 21 Power line 22 Data line 23 Drain electrode 30 Substrate 31 Source electrode 32 Drain electrode 33 Semiconductor 34 Gate electrode 35 Carrier

Claims (9)

As an element forming a single field effect transistor device structure,
An insulating substrate, which is a resin substrate, and has an uneven surface formed integrally with a plurality of convex portions and concave portions between the convex portions on the surface;
A gate electrode formed by a conductive layer provided on the uneven surface of the insulating substrate;
A gate insulating part formed by an insulating layer provided on the surface of the conductive layer;
A plurality of semiconductor channel portions formed by a semiconductor layer provided on the surface of the insulating layer continuously over at least the top region and the side wall surface region of the convex portion;
A source electrode / drain electrode formed by a plurality of bottom electrode layers provided in contact with the semiconductor layer in each of the recesses and connected to each other and functioning as an integral electrode;
A drain electrode / source electrode formed by a plurality of top electrode layers that are provided in contact with the semiconductor layer in the top region of each of the convex portions and are connected to each other and function as an integral electrode;
A vertical electric field characterized in that when a gate voltage is applied to the gate electrode, an electric conduction path is collectively formed in each of the plurality of semiconductor channel parts by an electric field acting through the gate insulating part. Effect transistor.   The gate insulating part is composed of a combination of a dielectric and an electrolyte, and when a gate voltage is applied to the gate electrode, an electric field acting through the electrolyte collectively causes electrical conduction to each of the plurality of semiconductor channel parts. The vertical field effect transistor according to claim 1, wherein a path is formed. 2. The vertical field effect transistor according to claim 1, wherein the semiconductor layer is formed by molecular material growth by self-organization. The vertical field effect transistor according to claim 1, wherein the insulating substrate is formed of a flexible material. 2. The vertical field effect transistor according to claim 1, wherein the semiconductor layer is also formed on at least a part of the surface of the concave portion continuously from the side wall surface region of the convex portion. The vertical field effect transistor according to claim 1, wherein the top electrode layer and the bottom electrode layer are formed on an upper surface of the semiconductor layer. Each of the streaky protrusions is provided with a comb-shaped raised region including a plurality of streaky protrusions arranged in parallel to each other on the surface of the substrate and a connecting part that connects them at one end. Forms the convex portion, and each of the plurality of gaps between the streaky projection portions forms the concave portion,
A bottom connection electrode portion that connects the plurality of bottom electrode layers formed for each of the plurality of recesses is formed in a region facing the tip of the comb teeth of the comb-shaped raised region,
Wherein the region of the connecting portion of the comb ridge region, vertical field effect transistor of claim 1 in which the top portion connecting the electrode portion is formed for connecting the plurality of top electrode layers. The vertical field effect transistor according to claim 7 , wherein the width of the streaky protrusions in the surface direction of the substrate is W, and the distance between the streaky protrusions is S, so that the condition of S / W ≦ 10 is satisfied. When the width of the strip-form protrusions in the surface direction of the substrate is W, the height from the recessed surface of the strip-form protrusions and H, according to satisfy claim 7 H / W ≧ 0.3 Vertical field effect transistor.

Images