JP5600867B2 - Manufacturing method of semiconductor wafer - Google Patents

Description

  The present invention relates to a method of manufacturing a semiconductor wafer, and more particularly, to a method of manufacturing a double-sided mirror semiconductor wafer by cutting a thin disk-shaped semiconductor wafer from a crystalline ingot.

A conventional method for manufacturing a semiconductor wafer is as follows: (slicing process) → (first chamfering process) → (lapping process) → (second chamfering process) → (single-side grinding process) → (double-side polishing process) → (single-sided polishing process) It is comprised by each process which performs a finishing polishing process in order.
In the slicing step, a thin disk-shaped semiconductor wafer is cut out from the crystalline ingot by cutting. In the first chamfering process, chamfering is performed on the outer periphery of the cut-out semiconductor wafer to suppress cracking and chipping of the semiconductor wafer in the lapping process, which is the next process. In the lapping process, the chamfered semiconductor wafer is lapped using, for example, a # 1000 grindstone to improve the flatness of the semiconductor wafer. In the second chamfering step, chamfering is performed on the outer peripheral portion of the lapped semiconductor wafer so that the end surface of the semiconductor wafer has a predetermined chamfered shape. In the single-side grinding process, one surface of the chamfered semiconductor wafer is ground using, for example, a # 2000-8000 grindstone, and is brought close to the final thickness of the semiconductor wafer. In the double-side polishing step, both sides of the semiconductor wafer ground on one side are polished. Then, in the single-sided finish polishing step, one of the surfaces of the semiconductor wafer whose both surfaces have been polished is further subjected to final polishing.

  In the conventional method described above, a double-sided mirror-finished semiconductor wafer is obtained through two chamfering steps, a lapping step, and a single-side grinding step, so the number of steps is large, and the loss of semiconductor material due to an increase in wrapping scraps and single-side grinding waste ).

In particular, the above problem is remarkable in a large-diameter semiconductor wafer such as a silicon wafer having a diameter of 450 mm or more.
For example, when a large-diameter silicon wafer having a diameter of 450 mm is manufactured by using the same silicon material as the current mainstream silicon wafer having a diameter of 300 mm, the kerf loss of the silicon wafer is 2.25 times.

  Furthermore, when the above-described lapping process is included in a method for manufacturing a silicon wafer having a diameter of 450 mm or more, there is a concern that the lapping apparatus becomes very large, and problems may arise regarding the installation location of the lapping apparatus when constructing a production line. is there.

Patent Document 1 proposes a method for manufacturing a semiconductor wafer that includes a double-side grinding step instead of a lapping step in the above-described conventional method.
Japanese Patent No. 3328193

However, the method for manufacturing a semiconductor wafer described in Patent Document 1 solves the problem that the lapping apparatus becomes large when manufacturing a large-diameter semiconductor wafer, and can omit the first chamfering process before the double-side grinding process. Although there is an advantage, there is still a problem that a lot of silicon material is taken up because of the double-sided grinding process and the single-sided grinding process, and kerfloss still has a problem.
It was also expected to improve the flatness of semiconductor wafers, which are expected to become increasingly demanding in the future, by reducing the allowance for semiconductor wafers.

The present invention has been made in view of the above problems, and when a semiconductor wafer cut out from a crystalline ingot is made into a double-sided mirror semiconductor wafer, at least the chamfering process can be omitted and the semiconductor wafer can be performed by a simple process. It is an object of the present invention to provide a manufacturing method capable of reducing the cost of removing the silicon material, reducing the kerf loss of the semiconductor material, and obtaining a semiconductor wafer at low cost.
In particular, the present invention has a remarkable effect when the semiconductor wafer is a large-diameter silicon wafer having a diameter of 450 mm or more.

In order to solve the above problems, the inventors have reduced the number of processes and reduced the silicon kerf loss of the semiconductor wafer when compared with the conventional method when the semiconductor wafer cut out from the crystalline ingot is made into a double-sided mirror semiconductor wafer. The semiconductor wafer manufacturing method for this purpose has been intensively studied.
As a result, instead of the lapping process and single-sided grinding process in the conventional method described above, a fixed abrasive grinding process that simultaneously grinds both sides from rough grinding to finish grinding is performed, and the processing distortion of the surface and end face of the semiconductor wafer is reduced. In addition, the present inventors have found that by performing a chemical treatment process that can simultaneously perform chamfering, it is possible to reduce the number of processes and reduce the machining allowance of the semiconductor wafer as compared with the conventional method.

The present invention is based on the above findings, and the gist of the present invention is as follows.
1. A slicing step of cutting a thin disk-shaped semiconductor wafer from the crystalline ingot;
A plurality of semiconductor wafers are fitted into the round holes of a carrier having a plurality of round holes provided in a positional relationship close to each other, and then a pair of upper and lower surfaces each having a pad having fixed abrasive grains. A fixed abrasive that sandwiches the carrier between the boards, rotates the upper and lower surface plates while swinging the carrier in the same horizontal plane, and simultaneously grinds both sides of the semiconductor wafer from rough grinding to finish grinding in one step. Grain grinding process ;
And during the fixed abrasive grinding process, all of the plurality of round holes are arranged so as to fall within the circumference of the upper and lower surface plate ,
Further comprising a double-side polishing step for simultaneously polishing both sides of the semiconductor wafer, and a single-side finish polishing step for final polishing one surface of the semiconductor wafer polished by the double-side polishing step;
Between the slicing step and the double-side polishing step,
The fixed abrasive grinding step;
Semiconductors and relaxation of working strain on the surface and the end surface of the semiconductor wafer, a chemical treatment step of performing a finishing chamfering simultaneously to predetermined chamfered end faces of the semiconductor wafer, wherein Rukoto comprises no matter the order Wafer manufacturing method.

2. 2. The method for producing a semiconductor wafer according to 1 above, wherein the semiconductor wafer is a large-diameter silicon wafer having a diameter of 450 mm or more.

According to the method for manufacturing a semiconductor wafer of the present invention, a fixed abrasive grinding process and a chemical treatment process are performed between the slicing process and the double-side polishing process, thereby reducing the entire manufacturing process of the semiconductor wafer as compared with the conventional method. In addition, it is possible to obtain a semiconductor wafer at a low cost by reducing the semiconductor wafer kerf loss by reducing the machining allowance of the semiconductor wafer.
Moreover, the flatness of the semiconductor wafer can also be improved by reducing the machining allowance of the semiconductor wafer.
Further, by performing the epitaxial layer growth step between the chemical treatment step and the double-side polishing step, or after the double-side polishing step, the semiconductor wafer can be a semiconductor wafer having an epitaxial layer.
In particular, the semiconductor wafer manufacturing method of the present invention is suitable for manufacturing a large-diameter silicon wafer having a diameter of 450 mm or more.

Next, the manufacturing method of the semiconductor wafer of this invention is demonstrated in detail, referring drawings. FIG. 1 is a process flow diagram showing a first embodiment of the present invention. In the first embodiment of the present invention, the following five steps are performed in the order of (1) to (5).
(1) Slicing step of cutting out a thin disk-shaped semiconductor wafer from a crystalline ingot (2) Inserting the semiconductor wafer into the round hole of a carrier having a plurality of round holes provided in a positional relationship close to each other Thereafter, the carrier is sandwiched between a pair of upper and lower surface plates each having a pad having fixed abrasive grains, and the upper and lower surface plates are rotated while the carrier is swung in the same horizontal plane. Fixed abrasive grinding process for simultaneously processing both surfaces of a semiconductor wafer at high speed from rough grinding to finish grinding (3) Relieving the processing strain on the surface and end face of the semiconductor wafer and making the end face of the semiconductor wafer into a predetermined chamfered shape Chemical treatment process that performs finishing chamfering simultaneously (4) Double-side polishing process that simultaneously polishes both sides of the semiconductor wafer (5) Polishing by the double-side polishing process Sided finish polishing step of polishing finish the one surface of the semiconductor wafers

Next, each step in the first embodiment of the present invention will be described.
(Slicing process)
The slicing process is a process of cutting a thin disk-shaped wafer by cutting a crystalline ingot by using a circumferential blade while contacting a wire saw with a crystalline ingot while supplying a grinding liquid. is there. In order to reduce the processing load in the subsequent fixed abrasive grinding process or chemical processing process, it is preferable that the semiconductor wafer after the slicing process has as high a flatness as possible and a small surface roughness.
The crystalline ingot is typically a silicon single crystal ingot, but may be a silicon polycrystalline ingot for solar cells.

(Fixed abrasive grinding process)
The fixed abrasive grinding process is a process in which rough grinding is performed on both sides of the semiconductor wafer cut out in the slicing process to improve the flatness of the wafer and bring it close to the final thickness of the semiconductor wafer.
FIG. 2 is an explanatory view schematically showing the fixed abrasive grinding apparatus 10 used in the fixed abrasive grinding process. 2A to 2C are explanatory views schematically showing the apparatus 10 used in the fixed abrasive grinding process in a vertical sectional view, and FIG. 2B and FIG. 2 (c) is an explanatory view schematically showing the apparatus 10 used in the fixed abrasive grinding process from the upper surface in the horizontal direction. 2 (a) and 2 (c) are explanatory diagrams showing a state immediately before the fixed abrasive grinding process starts, and FIG. It is explanatory drawing which showed the state which passed for a fixed time since the fixed abrasive grinding process started.

  The fixed abrasive grinding apparatus 10 includes a carrier 12 having a plurality of round holes 11a, 11b and 11c provided in close proximity to each other, pads 13a and 13b having fixed abrasives, and pads 13a and 13b. And a pair of upper and lower surface plates 14a and 14b, and guide rollers 15a, 15b, 15c and 15d which are arranged so that the circumference of the carrier 12 is divided into four and is in contact with the side surface of the carrier 12.

  After the semiconductor wafers 16a, 16b and 16c cut out in the slicing process are fitted into the round holes 11a, 11b and 11c provided in the carrier 12, a pair of upper and lower pads including pads 13a and 13b having fixed abrasive grains The carrier 12 is sandwiched between the surface plates 14a and 14b, and the guide rollers 15a, 15b, 15c and 15d are moved to swing the carrier 12 in the same plane while rotating the upper and lower surface plates 14a and 14b. Wafers 16a, 16b and 16c are ground on both sides simultaneously.

In FIG. 2, three round holes 11a, 11b and 11c are shown, but the number of round holes is not limited to three. However, as shown in FIGS. 2B and 2C, the circular holes 11a, 11b and the carrier 12 can be moved in any position relative to the upper and lower surface plates 14a and 14b by swinging. It is important that all of 11c be arranged so as to fall within the circumference of the upper and lower surface plates 14a and 14b. This is because the pressure applied to the semiconductor wafer during the fixed abrasive grinding is made as uniform as possible, so that the semiconductor wafer during the fixed abrasive grinding is not chamfered without chamfering the outer periphery of the semiconductor wafer after the slicing process. This is for preventing flatness and improving the flatness of the semiconductor wafer after fixed abrasive grinding. When three round holes 11 have the same diameter, as shown in FIGS. 2B and 2C, if the round holes 11a, 11b, and 11c have a close positional relationship, the diameter of the surface plate 14 It is preferable that the fixed abrasive grinding apparatus 10 is not unnecessarily enlarged.
In FIG. 2, assuming that the diameter of the surface plate 14 is L1, for example, L1 in the case where three silicon wafers having a diameter of 450 mm are ground with fixed abrasive is approximately 985 mm.

  Since the pad has fixed abrasive grains, it is not necessary to supply loose abrasive slurry during fixed abrasive grinding. Therefore, it is possible to avoid a decrease in the flatness of the semiconductor wafer after grinding due to non-uniform supply of loose abrasive grains, and in particular, the diameter of the semiconductor wafer such as a large-diameter silicon wafer of 450 mm or more. Is particularly advantageous when it is difficult to uniformly supply loose abrasive grains.

For pads having fixed abrasive grains, the abrasive grain material is generally diamond, but SiC abrasive grains can also be used. Moreover, the pad roughness having fixed abrasive grains can be used in the range of # 1000 to 8000, but as described above, the pressure applied to the semiconductor wafer during the fixed abrasive grinding is uniform. In addition, since fixed abrasive grains are used instead of loose abrasive grains, the grinding action of the abrasive grains on the semiconductor wafer is uniform, so even a semiconductor wafer with a rough slice surface immediately after the slicing step is fine as about # 8000. Even if fixed abrasive grinding is started using a pad, high-speed machining from rough grinding to finish grinding can be performed at once without generating cracks or chips.
In addition, during fixed abrasive grinding, it is preferable to supply water or an alkaline solution for the purpose of washing away grinding scraps or lubrication.

  If the grinding allowance in the fixed abrasive grinding process is less than 20 μm per side, the swell of the semiconductor wafer generated during cutting becomes a problem. On the other hand, if it exceeds 50 μm, insufficient semiconductor wafer strength becomes a problem. Therefore, the machining allowance in the fixed abrasive grinding step is preferably in the range of 20 to 50 μm per side.

By the way, in order to compare the fixed abrasive grinding process performed by this invention with the lapping process performed by the conventional method, a lapping process is demonstrated easily.
FIG. 3 is an explanatory view schematically showing an apparatus used in a lapping process performed by a conventional method. The wrapping device 50 includes carriers 52a, 52b, 52c, 52d and 52e, which have round holes 51a, 51b, 51c, 51d and 51e, respectively, and gears on the side surfaces, pads 53a and 53b, and pads 53a and 53b. Provided on a pair of upper and lower surface plates 54a and 54b, outer peripheral gear 55 when the carriers 52a, 52b, 52c, 52d and 52e make planetary motions, and side surfaces of the carriers 52a, 52b, 52c, 52d and 52e The center gear 56 meshes with the gear.

  After the semiconductor wafers 57a, 57b, 57c, 57d and 57e cut out in the slicing step are fitted into the round holes 51a, 51b, 51c, 51d and 51e provided in the carriers 52a, 52b, 52c, 52d and 52e, Carriers 52a, 52b, 52c, 52d and 52e are sandwiched between a pair of upper and lower surface plates 54a and 54b having pads 53a and 53b, and free abrasive grains are supplied to wafers 57a, 57b, 57c, 57d and 57e. While rotating the center gear 56, the carriers 52a, 52b, 52c, 52d and 52e are caused to perform planetary movement along the outer peripheral gear 55, and the wafers 57a, 57b, 57c, 57d and 57e are wrapped.

  In the wrapping device 50, since the area occupied by the center gear 56 is large, the area of the surface plate 54 is increased accordingly. As a result, the entire wrapping device 50 tends to be large. When wrapping a semiconductor wafer having a large diameter, the carriers 52a, 52b, 52c, 52d and 52e increase in size, thereby increasing the force required for planetary movement of the carriers 52a, 52b, 52c, 52d, 52d and 52e. Thus, the center gear 56 becomes larger, which increases the overall size of the wrapping device 50, which is a serious problem. In FIG. 3, when the diameter of the surface plate 54 is L2, for example, when wrapping three silicon wafers having a diameter of 450 mm, L2 is approximately 2200 mm, which is much larger than L1 in the fixed abrasive grinding apparatus 10. When a silicon wafer having a diameter of 450 mm or more is manufactured by a manufacturing method including a lapping process, a very large lapping apparatus is required, and there is a concern that problems such as installation location may occur.

  Also, in the lapping process, lapping is performed while applying free abrasive grains, so the guide becomes larger and the supply range of free abrasive grains becomes wider, making uniform supply more difficult, and the flatness of the semiconductor wafer after the lapping process Not only tends to decrease, but cracks and chips are likely to occur during lapping.

(Chemical treatment process)
The chemical treatment process is a slicing process, or the process distortion applied to the surface and end face of the semiconductor wafer in both the slicing process and the fixed abrasive grinding process is reduced, and the end face of the semiconductor wafer is finished to a predetermined chamfered shape. Chamfering is performed at the same time, and either batch type or single wafer type chemical treatment can be selected.

  Batch chemical treatment involves immersing a plurality of semiconductor wafers (for example, 24 wafers) in a container containing a predetermined etching solution to alleviate processing strain applied to both surfaces and end surfaces of the semiconductor wafer, This is a process of simultaneously performing the finishing chamfering to make the end face of the sheet into a predetermined chamfer shape.

  In the single wafer chemical treatment, one semiconductor wafer is rotated while dropping the etching solution on each side of the semiconductor wafer, and the etching solution is spread over the entire bottom surface and end surface of the etching droplet of the semiconductor wafer by centrifugal force. This is a process of simultaneously performing finish chamfering to alleviate the processing distortion of the etching dropping surface and the end surface of the semiconductor wafer and to make the end surface of the semiconductor wafer into a predetermined chamfered shape. In the case of single-wafer chemical treatment, each side is etched twice, and both sides are etched. Etching conditions are set so that the end face has a predetermined shape by two etchings.

When the etching solution used for the single wafer chemical treatment is dropped onto the rotated semiconductor wafer, the etching solution reaches the etching dropping surface of the semiconductor wafer at an appropriate speed, and a uniform etching solution film is formed on the dropping surface. Since it needs to be formed, it is preferable to use a mixed acid of hydrofluoric acid, nitric acid and phosphoric acid. The mixed solution of hydrofluoric acid, nitric acid, and acetic acid that is normally used as an etchant in batch chemical processing has a low viscosity, so when the etchant is dropped onto a rotated semiconductor wafer, the etchant is etched onto the surface of the semiconductor wafer. The speed at which the film is spread is too fast, and no etching solution film is formed, resulting in uneven etching.
The mixed acid of hydrofluoric acid, nitric acid and phosphoric acid used as the etching solution in the single-wafer chemical treatment has a concentration of hydrofluoric acid, nitric acid and phosphoric acid of 5% to 20%, 5 to 40% and 30%, respectively. It is preferable to use a mixture of ˜40%.

(Double-side polishing process)
In the double-side polishing step, both surfaces of the semiconductor wafer that has undergone the fixed abrasive grinding step and the chemical treatment step are polished by supplying a polishing slurry using a polishing cloth made of urethane or the like. The type of the polishing slurry is not particularly limited, but colloidal silica having a particle size of 0.5 to 2 μm is preferable.

(Single-side finish polishing process)
In the single-sided finish polishing step, a semiconductor wafer having both surfaces polished is polished by supplying a polishing slurry using a polishing cloth made of urethane or the like on one side that finally becomes an element surface. The type of the polishing slurry is not particularly limited, but colloidal silica having a particle size of 0.5 μm or less is preferable.

Next, a second embodiment of the present invention will be described. FIG. 4 is a process flow diagram showing the second embodiment of the present invention. In FIG. 4, the same steps as those in FIG. 1 are given the same names.
Here, the second embodiment shown in FIG. 4 is different from the first embodiment shown in FIG. 1 in that the fixed abrasive grinding step and the chemical treatment step are performed between the slicing step and the double-side grinding step. However, the order of performing the fixed abrasive grinding process and the chemical treatment process is different.

As described in the explanation of the chemical treatment process, the chemical treatment process has a finishing chamfering action for making the end face of the semiconductor wafer into a predetermined chamfered shape. Therefore, after the chemical treatment process, it is advantageous to avoid the grinding process in which the thickness reduction of the semiconductor wafer is large only as the double-sided polishing process and the single-sided finishing polishing process in terms of suppressing variation in the chamfer width of the semiconductor wafer. It is.
That is, it is preferable to perform the first embodiment of the present invention shown in FIG. 1, that is, in the order of (fixed abrasive grinding step) → (chemical treatment step).
However, even when the semiconductor wafer is manufactured in the order of the second embodiment of the present invention shown in FIG. 4, that is, (chemical treatment step) → (fixed abrasive grinding step), the chamfer width of the semiconductor wafer is reduced. Although the variation slightly increases and the processing distortion generated in the fixed abrasive grinding process remains, the number of processes and the kerf loss of the semiconductor material are the same as those of the first embodiment in comparison with the conventional method. An effect is obtained. Therefore, when the variation in the chamfer width of the semiconductor wafer and the residual processing distortion are within the required quality standard of the semiconductor wafer, the second embodiment of the present invention is one of effective means for reducing the manufacturing cost of the semiconductor wafer. . In addition, when emphasizing alleviation of processing distortion at the end face of the wafer, a finishing chamfering process after the fixed abrasive grinding process can be performed.

  The above is the main step in the production method of the present invention, but one or both of the chamfered portion polishing step and the epitaxial layer growth step may be added as necessary. Hereinafter, each of the chamfered portion polishing step and the epitaxial layer growth step will be described.

(Chamfered part polishing process)
The chamfered portion polishing step is performed in order to reduce the variation in the chamfer width by polishing the chamfered portion of the semiconductor wafer after the double-sided polishing step. Using a polishing cloth made of urethane or the like, polishing slurry is supplied and the chamfered portion is polished. The type of the polishing slurry is not particularly limited, but colloidal silica having a particle size of about 0.5 μm is preferable.

(Epitaxial layer growth process)
By performing the epitaxial layer growth step between the chemical treatment step and the double-side polishing step or after the double-side polishing step, the semiconductor wafer can be a semiconductor wafer having an epitaxial layer. When growing an epitaxial layer on the surface of a semiconductor wafer, the damage to the surface of the semiconductor wafer applied during the slicing process or both the slicing process and the fixed abrasive grinding process must be removed. The step is preferably performed between the chemical treatment step and the double-side polishing step or after the double-side polishing step.

  The above description is merely an example of the embodiment of the present invention, and various modifications can be made within the scope of the claims.

Next, a semiconductor wafer was prototyped by the manufacturing method according to the present invention, and will be described below.
(Invention Example 1)
A silicon wafer having a diameter of 300 mm was prototyped according to the process flow of the first embodiment of the present invention shown in FIG.

(Invention Example 2)
A silicon wafer was prototyped by the same manufacturing method as in Invention Example 1 except that the diameter of the silicon wafer was 450 mm.

(Invention Example 3)
A silicon wafer having a diameter of 300 mm was prototyped according to the process flow of the second embodiment of the present invention shown in FIG.

(Invention Example 4)
A silicon wafer was prototyped by the same manufacturing method as Example 3 except that the diameter of the silicon wafer was 450 mm.

(Conventional example 1)
A silicon wafer having a diameter of 300 mm was prototyped by a conventional semiconductor wafer manufacturing method including a lapping step shown in FIG.

(Conventional example 2)
A silicon wafer having a diameter of 300 mm was prototyped by a semiconductor wafer manufacturing method using a double-side polishing process instead of the lapping process shown in FIG.

  For each sample thus obtained, silicon kerf loss and flatness were evaluated. Hereinafter, the evaluation method will be described.

(Silicon calfloss)
Inventive Examples 1 to 4 are semiconductor wafer thickness reduction (μm) before and after the fixed abrasive grinding process, and Conventional Example 1 is the semiconductor wafer thickness reduction (μm) before and after the lapping process and before and after the single-side grinding process. In the conventional example 2, the reduction amount of the semiconductor wafer thickness before and after the double-side grinding process (μm) and the reduction amount of the semiconductor wafer thickness before and after the single-side grinding process (μm) ) To evaluate silicon kerfloss.

(Flatness)
The flatness of each sample was measured using a capacitance thickness sensor meter and evaluated as follows.
○: Flatness is less than 0.5 μm.
Δ: Flatness is 0.5 μm or more and 1 μm or less.
X: Flatness exceeds 1 μm.

  The results of evaluating each sample are shown in Table 1.

As is clear from the table, in the invention example 1, it was confirmed that the kerf loss of silicon showed the minimum value and the flatness was also good. Since Invention Example 2 also has good results that are almost equivalent to Invention Example 1, according to the manufacturing method according to the process flow of the first embodiment of the present invention, a large-diameter silicon wafer having a diameter of 450 mm can be obtained. Was confirmed.
In addition, in Inventive Examples 3 and 4 according to the process flow of the second embodiment of the present invention, good results substantially equivalent to Inventive Examples 1 and 2 were obtained for silicon kerf loss and flatness, respectively.
On the other hand, it was confirmed that Conventional Examples 1 and 2 had a large silicon kerf loss and inferior flatness as compared with Invention Examples 1 to 4.

According to the method for manufacturing a semiconductor wafer of the present invention, a fixed abrasive grinding process and a chemical treatment process are performed between the slicing process and the double-side polishing process, thereby reducing the entire manufacturing process of the semiconductor wafer as compared with the conventional method. In addition, it is possible to obtain a semiconductor wafer at a low cost by reducing the semiconductor wafer kerf loss by reducing the machining allowance of the semiconductor wafer.
Moreover, the flatness of the semiconductor wafer can also be improved by reducing the machining allowance of the semiconductor wafer.
Further, by performing the epitaxial layer growth step between the chemical treatment step and the double-side polishing step, or after the double-side polishing step, the semiconductor wafer can be a semiconductor wafer having an epitaxial layer.
In particular, the semiconductor wafer manufacturing method of the present invention is suitable for manufacturing a large-diameter silicon wafer having a diameter of 450 mm or more.

It is a process flow figure showing a 1st embodiment of the present invention. It is explanatory drawing which shows typically the fixed abrasive grinding apparatus used for a fixed abrasive grinding process, Comprising: (a) is a vertical direction sectional view of the apparatus used for a fixed abrasive grinding process, (b) is a fixed abrasive grinding process. The figure which showed the state just before starting from a horizontal direction upper surface, and (c) are the figures which showed the state which passed for a fixed time since the fixed abrasive grinding process started from the horizontal upper surface. It is explanatory drawing which shows typically the apparatus used at the lapping process performed by the conventional method. It is a process flow figure showing a 2nd embodiment of the present invention. It is a process flow figure showing a manufacturing method of conventional example 1. It is a process flow figure showing a manufacturing method of conventional example 3.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Fixed abrasive grinding apparatus 11a, 11b, 11c Round hole 12 Carrier 13a, 13b Pad 14 which has fixed abrasive 14, 14a, 14b Surface plate 15a, 15b, 15c, 15d Guide roller 16, 16a, 16b, 16c Semiconductor wafer 50 Lapping device 51a, 51b, 51c, 51d, 51e Round hole 52a, 52b, 52c, 52d, 52e Carrier 53a, 53b Pad 54 54a, 54b Surface plate 55 Outer gear 56 Center gear 57a, 57b, 57c, 57d, 57e Semiconductor wafer DESCRIPTION OF SYMBOLS 101 Slicing process 102 Fixed abrasive grinding process 103 Chemical treatment process 104 Double-side polishing process 105 Chamfering part polishing process 106 Single-sided finishing polishing process 107 1st chamfering process 108 Lapping process 109 2nd chamfering process 110 Single-sided grinding process 1 1 double-side grinding step 112 chamfering step

Claims (2)

A slicing step of cutting a thin disk-shaped semiconductor wafer from the crystalline ingot;
A plurality of semiconductor wafers are fitted into the round holes of a carrier having a plurality of round holes provided in a positional relationship close to each other, and then a pair of upper and lower surfaces each having a pad having fixed abrasive grains. A fixed abrasive that sandwiches the carrier between the boards, rotates the upper and lower surface plates while swinging the carrier in the same horizontal plane, and simultaneously grinds both sides of the semiconductor wafer from rough grinding to finish grinding in one step. Grain grinding process ;
And during the fixed abrasive grinding process, all of the plurality of round holes are arranged so as to fall within the circumference of the upper and lower surface plate ,
Further comprising a double-side polishing step for simultaneously polishing both sides of the semiconductor wafer, and a single-side finish polishing step for final polishing one surface of the semiconductor wafer polished by the double-side polishing step;
Between the slicing step and the double-side polishing step,
The fixed abrasive grinding step;
Semiconductors and relaxation of working strain on the surface and the end surface of the semiconductor wafer, a chemical treatment step of performing a finishing chamfering simultaneously to predetermined chamfered end faces of the semiconductor wafer, wherein Rukoto comprises no matter the order Wafer manufacturing method. The method of manufacturing a semiconductor wafer according to claim 1, wherein the semiconductor wafer is a large-diameter silicon wafer having a diameter of 450 mm or more.

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