JP5367792B2 - Light emitting element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a light emitting element which prevents an electrical current from concentrating on a specific area in a semiconductor layer. <P>SOLUTION: A light emitting element includes: a support layer; a lower semiconductor layer, which is formed above the support layer and has a first conductivity type and a resistivity lower than the support layer; a luminous layer formed on the lower semiconductor layer; an upper semiconductor layer, which is formed on the luminous layer and has a second conductivity type that is opposite to the first conductivity type; a first area including an upper electrode formed on the upper semiconductor layer; a second area including the support layer, the lower semiconductor layer formed above the support layer, and a first part of a lower electrode formed on the lower semiconductor layer; and a third area including the support layer and a second part of the lower electrode formed on the support layer. <P>COPYRIGHT: (C)2012,JPO&amp;INPIT

Description

The present invention relates to a semiconductor light-emitting element.

  With reference to FIG. 22, the light emitting element which patent document 1 discloses is demonstrated. A semiconductor layer 1028 is formed over the substrate 1014 with a low-resistance semiconductor layer 1018 interposed therebetween. An electrode is connected to the semiconductor layer 1018. A reflective layer 1015 is formed under the substrate 1014. A light emitting layer 1026 is formed over the semiconductor layer 1028, and a semiconductor layer 1027 is formed over the light emitting layer 1026. Semiconductor layers 1028 and 1027 have opposite conductivity types.

  A recess 1030 is formed on the surface of the semiconductor layer 1027. The semiconductor layer 1028 is exposed on the bottom surface of the recess 1030. A translucent electrode layer 1024 made of NiO / Au is formed so as to cover the upper surface of the semiconductor layer 1027. A translucent electrode layer 1024 is not formed on the inner surface of the recess 1030.

  The depression 1030 is formed by removing the semitransparent electrode layer 1024, the semiconductor layer 1027, the light emitting layer 1026, and the semiconductor layer 1028 by reactive ion etching (RIE) after forming the semitransparent electrode layer 1024 on the semiconductor layer 1027. It is formed.

  Light emitted from the light emitting layer 1026 passes through the inner surface of the translucent electrode layer 1024 or the recess 1030 and is extracted above the light emitting element. A part of the light passing through the semitransparent electrode layer 1024 is absorbed by the semitransparent electrode layer 1024. The light extracted from the inner surface of the recess 1030 is not absorbed by the translucent electrode layer 1024. For this reason, the depression 1030 increases the amount of light extracted from the light emitting element.

  Next, a light-emitting element having a grid electrode will be described with reference to FIG. FIG. 20A is a schematic plan view of the light emitting element.

  This light-emitting element includes an n-type nitride semiconductor layer 102, a light-emitting layer formed on the n-type nitride semiconductor layer, and a p-type nitride semiconductor layer 104 formed on the light-emitting layer. On the surface of the p-type nitride semiconductor layer 104, a light emitting region 950 having a shape in which a central portion of one side of a square is cut out is defined. The p-type nitride semiconductor layer 104 in the region surrounding the light-emitting region 950, the light-emitting layer, and the upper layer of the n-type nitride semiconductor layer 102 are removed, so that the n-type nitride semiconductor layer 102 is exposed on the bottom surface. 911 is formed.

  A p-side electrode 905 is formed on the light emitting region 950. The p-side electrode 905 includes a lattice portion 905a and a p-side pad portion 905b. The lattice portion 905a has a lattice structure. A p-side pad portion 905b is formed in the vicinity of the center of the side facing the notched side so as to cover the lattice-shaped portion 905a. An n-side electrode 907 is formed on the bottom surface of the recess 911. The n-side electrode 907 is disposed in a portion where the light emitting region 950 is cut out. The n-side electrode 907 is used as a pad.

  By applying a predetermined voltage between the p-side electrode 905 and the n-side electrode 907, light is emitted from the light emitting layer. As the material of the p-side electrode 905, a material that is not transparent to the light emitted from the light emitting layer can be used. Light can be extracted outside the element from the region where the p-side electrode 905 is not formed on the upper surface of the light-emitting element.

US Pat. No. 6,885,034

  In the light emitting element of Patent Document 1, a region where the recess 1030 is not formed in the upper surface of the semiconductor layer 1027 is covered with the semitransparent electrode layer 1024. Light extracted through the translucent electrode layer 1024 is attenuated due to absorption by the translucent electrode layer 1024. For this reason, it is difficult to improve the light extraction efficiency.

  In the light-emitting element described with reference to FIG. 20A, a strong electric field is easily generated in the vicinity of the n-side electrode 907, and a current easily flows at a high current density. When a current flows at a high current density, the light emitting layer tends to deteriorate.

  An object of the present invention is to provide a light-emitting element having a novel structure with improved light extraction efficiency and a method for manufacturing the same.

  Another object of the present invention is to provide a light-emitting element that suppresses current concentration in a specific region in a semiconductor layer.

According to a first aspect of the present invention, a support layer, a lower semiconductor layer formed above the support layer, having a first conductivity type and having a lower resistivity than the support layer, and the lower layer A light emitting layer formed on the side semiconductor layer, an upper semiconductor layer formed on the light emitting layer and having a second conductivity type opposite to the first conductivity type, and formed on the upper semiconductor layer A first region including a formed upper electrode; the support layer; the lower semiconductor layer formed above the support layer; and a first lower electrode formed on the lower semiconductor layer. the portion and a second region including; the a supporting layer, and a third region including a second portion of said lower electrode formed on the support layer; have a, the first to When the third region is viewed from above, the first region has a shape in which one corner of a quadrangle is cut out, and the cut out part of the first region is The second region of the lower electrode that overlaps the third region and is formed in the third region is used as a pad, at a corner adjacent to the notched corner of the first region. There is provided a light emitting device in which a portion of the upper electrode used as a pad is disposed .

  In the light emitting device according to the first aspect, the first portion of the lower electrode is formed on the lower semiconductor layer, and the second portion is on the support layer having a higher resistivity than the lower semiconductor layer. It is formed. Thereby, it can suppress that an electric current concentrates in the vicinity of the 2nd part of a lower electrode.

FIG. 1A is a schematic plan view of the light emitting device according to the first embodiment, and FIG. 1B is a schematic cross-sectional view taken along the line AA ′ in FIG. 2A to 2C are schematic cross-sectional views (part 1) for explaining the method for manufacturing the light-emitting element according to the first embodiment. FIGS. 3A to 3C are schematic cross-sectional views (part 2) for explaining the method for manufacturing the light-emitting element according to the first embodiment. 4A is a schematic cross-sectional view in the vicinity of the recess, and FIGS. 4B and 4C are schematic plan views in the vicinity of the recess. FIG. 5 is a cross-sectional view schematically showing an optical path of light taken out from the bottom surface of the depression in the light emitting element of the first embodiment. 6A and 6B are cross-sectional views schematically showing an optical path of light extracted from the side surface of the depression to the outside of the light emitting element of the first embodiment. FIG. 7A is a schematic cross-sectional view in the vicinity of the dent when the taper is not provided, and FIG. 7B is a schematic cross-sectional view in the vicinity of the dent with the taper. FIG. 8 is a cross-sectional view schematically showing an optical path of light extracted from the inner surface of the tapered recess to the outside of the element. FIG. 9A is a schematic plan view of the light emitting device according to the second embodiment, and FIGS. 9B and 9C show the operation of the lattice portion of the light emitting device of the second embodiment. It is a schematic plan view for explaining the effect. FIG. 10A is a schematic plan view of a light emitting device according to a modification of the second embodiment, and FIG. 10B shows an operation of the lattice portion of the light emitting device according to the modification of the second embodiment. It is a schematic plan view for explaining the effect. FIG. 11A is a schematic plan view of a light emitting device according to the third embodiment. FIGS. 11B and 11C are respectively a line A-A ′ in FIG. It is a schematic sectional drawing in alignment with BB 'line. FIG. 12A is a schematic plan view of the light emitting device according to the fourth embodiment. FIGS. 12B and 12C are respectively taken along line AA ′ in FIG. It is a schematic sectional drawing in alignment with BB 'line. FIG. 13A is a schematic cross-sectional view for explaining a method for manufacturing a light emitting device according to the third embodiment, and FIG. 13B shows a method for manufacturing the light emitting device according to the fourth embodiment. It is a schematic sectional drawing for. FIG. 14A is a schematic plan view of the light emitting device according to the fifth embodiment. FIGS. 14B and 14C are respectively a line A-A ′ in FIG. It is a schematic sectional drawing in alignment with BB 'line. FIG. 15A is a schematic plan view of a light emitting device according to the sixth embodiment. FIGS. 15B and 15C are respectively a line AA ′ in FIG. It is a schematic sectional drawing in alignment with BB 'line. FIG. 16 is a table summarizing light emission wavelengths and light emission outputs of the light emitting elements of the first to sixth examples and the comparative example. FIG. 17A is a photograph showing a light emitting state of the light emitting element according to the fourth example, and FIG. 17B is a photograph showing a light emitting state of the light emitting element according to the sixth example. FIG. 18 is a graph showing the experimental results of examining the effect of the protective film. FIG. 19 is a schematic cross-sectional view of a nitride semiconductor wafer. FIG. 20A shows a schematic plan view of a light-emitting element according to a comparative example, and FIG. 20B shows a schematic cross-sectional view along the line AA ′ in FIG. FIG. 21A shows a schematic cross-sectional view of the vicinity of the lattice portion of the p-side electrode of the light emitting element of the comparative example, and FIG. 21B shows an LED lamp using the light emitting element of the comparative example from It is sectional drawing which shows schematically the optical path until the emitted light is taken out of a light emitting element. FIG. 22 is a perspective view showing a light-emitting element disclosed in Patent Document 1. As shown in FIG.

  First, with reference to FIG. 19, a nitride semiconductor wafer as a material for a light emitting device according to an embodiment of the present invention will be described. A buffer layer 101 is formed on the substrate 100. The substrate 100 is made of, for example, sapphire, silicon nitride, silicon, gallium oxide, zinc oxide, or the like.

  An n-type contact layer 102a made of an n-type nitride semiconductor (eg, gallium nitride) is formed on the buffer layer 101, and an n-type nitride semiconductor (eg, aluminum gallium nitride) is made on the n-type contact layer 102a. An n-type cladding layer 102b is formed. The n-type nitride semiconductor layer 102 is configured including the n-type contact layer 102a and the n-type cladding layer 102b.

  A light emitting layer 103 is formed on the n-type cladding layer 102b. The light emitting layer 103 is made of, for example, indium gallium nitride. The light emitting layer 103 may have any known configuration, and may be, for example, a single layer thick film or a multiple quantum well (MQW) structure in which thin films are stacked.

  A p-type cladding layer 104b made of a p-type nitride semiconductor (eg, aluminum gallium nitride) is formed on the light emitting layer 103, and a p-type nitride semiconductor (eg, gallium nitride) is made on the p-type cladding layer 104b. A p-type contact layer 104a is formed. A p-type nitride semiconductor layer 104 is configured including the p-type contact layer 104a and the p-type cladding layer 104b.

  The p-type nitride semiconductor layer 104, the light emitting layer 103, the n-type nitride semiconductor layer 102, and the buffer layer 101 are collectively referred to as a nitride semiconductor layer. The thickness of the nitride semiconductor layer is, for example, 4.60 μm. The total thickness of the p-type nitride semiconductor layer 104 and the light emitting layer 103 is, for example, 0.35 μm. The thickness of the substrate 100 is, for example, 300 to 500 μm. For example, sapphire substrates having a thickness of 330 μm or 430 μm are commercially available.

  In general, there are various types of laminated structures of nitride semiconductor wafers used for light-emitting elements, but the minimum functional layers required for manufacturing the light-emitting elements are an n-type nitride semiconductor layer, a light-emitting layer, and a p-type nitride semiconductor layer. 3 layers.

Note that the nitride semiconductor wafer may include other functional layers. Here, the other functional layer is, for example, a strain relaxation layer inserted between the n-type contact layer and the n-type clad layer, and this is, for example, an InGaN layer or a superlattice made of (InGaN / GaN) _n. And a superlattice layer made of (AlGaN / InGaN) _n . For example, an undoped-GaN layer may be inserted as a defect reduction layer between the n-type cladding layer and the light emitting layer.

  The n-type cladding layer 102b and the p-type cladding layer 104b are formed in order to suppress the leakage of carriers from the light emitting layer 103. However, these are not necessarily functionally required, and the n-type cladding layer 104b and the n-type cladding layer 104b The type cladding layer 102b can be omitted, and the p-type cladding layer 104b can be omitted from the p-type nitride semiconductor layer. A nitride semiconductor wafer without a buffer layer is also being studied.

  Each layer on the substrate 100 is formed by, for example, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), metal organic molecular beam epitaxy (MOMBE), vapor phase epitaxy (VPE), or the like.

  Next, a light emitting device according to a first embodiment of the present invention will be described with reference to FIGS. 1 (A) and 1 (B). FIG. 1A shows a schematic plan view of the light emitting device according to the first embodiment, and FIG. 1B shows the AA ′ line in FIG. 1A of the light emitting device according to the first embodiment. The schematic sectional drawing in alignment with is shown.

  The light emitting device of this example is made of the nitride semiconductor wafer described with reference to FIG. On the surface of the p-type nitride semiconductor layer 104, a light emitting region 150 having a shape in which one corner of a square is cut out is defined. By removing the p-type nitride semiconductor layer 104, the light-emitting layer 103, and the upper layer of the n-type nitride semiconductor layer 102 in the region surrounding the light-emitting region 150, the n-type nitride semiconductor layer 102 is exposed on the bottom surface. A recess 111 (contour groove 111) is formed.

  A p-side electrode 105 is formed on the light emitting region 150. The p-side electrode 105 includes a lattice portion 105a and a p-side pad portion 105b. The lattice portion 105a has a lattice structure, and the shape of the section surrounded by each lattice of the lattice portion 105a is a square. A p-side pad portion 105b is formed at a corner adjacent to the cut-out corner on the light emitting region 150 so as to cover the lattice-like portion 105a. The p-side electrode 105 is in ohmic contact with the p-type nitride semiconductor layer 104.

  One recess 106 is formed inside each lattice of the lattice-like portion 105a. However, in the region where the p-side pad portion 105b is formed, the recess 106 is not formed inside each lattice of the lattice-like portion 105a.

  Each recess 106 has a circumferential edge at the opening and a bottom surface reaching the n-type nitride semiconductor layer 102. The side surface of each recess 106 has a taper such that the recess becomes wider from the bottom to the top.

  An n-side electrode 107 is formed on the bottom surface of the contour groove 111. The n-side electrode 107 includes a linear portion 107a and an n-side pad portion 107b. The n-side pad portion 107b is disposed in a portion where the light emitting region 150 is cut out, and the linear portion 107a is connected to the n-side pad portion 107b and has an elongated shape in a direction parallel to one side of the light emitting region 150. Have The n-side electrode 107 is in ohmic contact with the n-type nitride semiconductor layer 102.

  Light is emitted from the light emitting layer 103 by applying a predetermined voltage between the p-side electrode 105 and the n-side electrode 107. The wavelength of light emitted from the light emitting layer 103 is, for example, about 480 nm. As the material of the p-side electrode 105, a material that is not transparent to the light emitted from the light emitting layer 103 can be used. Light can be extracted outside the device from a region where the p-side electrode 105 is not formed on the top surface of the light-emitting device.

  For example, the protective film 110 made of silicon oxide covers the entire upper surface of the light emitting element except for the upper surface of the p-side pad portion 105b and a part of the upper surface of the n-side pad portion 107b. The protective film 110 is insulative and transparent to light emitted from the light emitting layer 103.

  Next, with reference to FIGS. 2A to 2C and FIGS. 3A to 3C, a method for manufacturing a light-emitting element according to the first embodiment will be described. The nitride semiconductor wafer described with reference to FIG. 19 is prepared.

  First, as shown in FIG. 2A, a resist mask R111 having an opening corresponding to the contour groove 111 is formed by photolithography. Next, by using dry etching, the p-type nitride semiconductor layer 104, the light emitting layer 103, and the upper layer of the n-type nitride semiconductor layer 102 in the opening of the resist mask R111 are removed, so that the n-type is formed on the bottom surface. A contour groove 111 in which the nitride semiconductor layer 102 is exposed is formed. Next, the resist mask R111 is removed by washing.

  The depth of the contour groove 111 is, for example, 0.65 μm. A large number of light emitting elements are formed on the nitride semiconductor wafer. The contour groove 111 defines the boundary between the light emitting elements formed on the nitride semiconductor wafer.

  Next, as shown in FIG. 2B, a resist mask R106 having an opening corresponding to the depression 106 is formed by photolithography. Next, by using dry etching, the p-type nitride semiconductor layer 104, the light emitting layer 103, and the upper layer of the n-type nitride semiconductor layer 102 in the opening of the resist mask R106 are removed, so that the n-type is formed on the bottom surface. A recess 106 in which the nitride semiconductor layer 102 is exposed is formed. As dry etching, for example, reactive ion etching (RIE) using chlorine gas plasma is used. After dry etching, the resist mask R106 is removed by washing.

  By performing dry etching on the side surface of the opening of the resist mask R106 so that the opening becomes wider from the bottom to the top, the recess 106 having a taper shape reflecting the taper shape of the resist mask R106 is formed. Can be formed. The inclination angle of the taper of the recess 106 can be adjusted by changing the selectivity between the resist mask R106 and the nitride semiconductor layer. The selectivity between the resist mask R106 and the nitride semiconductor layer can be changed by the pressure condition of dry etching, gas type, RF power, and the like.

  Resist residues, crystal residues, and the like are attached to the surface of the recess 106 formed by dry etching. Therefore, the nitride semiconductor wafer after dry etching is wet etched with an aqueous solution of sulfuric acid / hydrogen peroxide or (and) an aqueous solution of hydrochloric acid / hydrogen peroxide. Thereby, the denatured organic residue and crystal residue of the resist are removed from the surface of the recess 106.

  With dry etching in which the depression 106 is formed, a layer in which the crystal arrangement is disordered or a damage layer in which gas atoms or molecules used in the dry etching have entered the crystal can be formed on the inner wall surface of the depression 106. As a result, the reliability of the light emitting element may be reduced. In addition to the wet etching described above, the reliability of the light emitting element can be improved by performing wet etching for removing the inner wall surface layer of the recess 106. This wet etching is performed at room temperature to 120 ° C. (for example, 100 ° C.) for 3 minutes to 30 minutes using, for example, phosphoric acid, sulfuric acid, or a mixed solution of phosphoric acid and sulfuric acid as an etchant.

  Next, as shown in FIG. 2C, a resist mask R105a having openings corresponding to the lattice-like portions 105a of the p-side electrode 105 is formed by photolithography. By electron beam (EB) evaporation, Pt and Au layers are sequentially deposited with thicknesses of 100 nm and 1000 nm, respectively, with the Pt layer as a lower layer. Next, the lattice-like portion 105a is formed by removing the vapor deposition material deposited on portions other than the opening of the resist mask R105a by using a lift-off method.

  Next, as shown in FIG. 3A, a resist mask R107 having openings corresponding to the linear portion 107a and the n-side pad portion 107b of the n-side electrode 107 is formed by photolithography.

  By EB vapor deposition, Al, Rh, Ti, Pt, Au, Pt, and Au layers are sequentially deposited with thicknesses of 10 to 90 nm, 100 nm, 100 nm, 100 nm, 200 nm, 100 nm, and 200 nm, with the Al layer as the bottom layer. Next, by using a lift-off method, the vapor deposition material deposited on portions other than the opening of the resist mask R107 is removed, thereby forming the linear portion 107a and the n-side pad portion 107b of the n-side electrode 107 at the same time. In this way, the n-side electrode 107 is formed.

  Next, as shown in FIG. 3B, a resist mask R105b having an opening corresponding to the p-side pad portion 105b of the p-side electrode 105 is formed by photolithography. A part of the lattice portion 105a is exposed in the opening corresponding to the p-side pad portion 105b.

  By EB vapor deposition, Ni and Au layers are sequentially deposited with thicknesses of 100 nm and 1000 nm, respectively, with the Ni layer as the lower layer. Next, by using a lift-off method, the p-side pad portion 105b is formed by removing the vapor deposition material deposited on portions other than the opening of the resist mask R105b. The p-side pad portion 105b is formed so as to cover a part of the lattice portion 105a and to be connected to the lattice portion 105a.

Next, as shown in FIG. 3C, a silicon oxide film (SiO ₂ film) M having a thickness of 100 nm to 500 nm is formed on the entire upper surface of the light emitting element by sputtering.

  For example, a silicon oxide film M having a thickness of 300 nm is formed by depositing three layers of a silicon oxide film having a thickness of 100 nm. Since a complicated stress is applied to the silicon oxide film deposited on the inner surface of the depression 106, when a film having a thickness of 300 nm is formed at a time, the silicon oxide film is peeled off from the depression 106 during the cooling period after the film formation. Or there is a concern that cracks may occur. By forming the film in a plurality of times, such a problem is suppressed.

  A resist mask R110 having openings on the upper surfaces of the p-side pad portion 105b and the n-side pad portion 107b is formed on the silicon oxide film M by photolithography. Next, the upper surface of the p-side pad portion 105b and the n-side pad portion 107b is exposed by removing the silicon oxide film M in the opening of the resist mask R110 using wet etching. Next, the resist mask R110 is removed by washing. Thus, the protective film 110 made of silicon oxide is formed.

  After forming the protective film 110, the nitride semiconductor wafer is fixed to a holding substrate (for example, a ceramic substrate or a silicon substrate) with wax or the like. The nitride semiconductor wafer fixed to the holding substrate is thinned by grinding and polishing, and the thickness is set to about 100 μm to 200 μm. After cleaning the polished surface while being held on the holding substrate, for example, a Ti layer and an Al layer are deposited on the lower surface of the substrate 100 by EB vapor deposition with a thickness of 3 nm and 200 nm, respectively. This metal layer functions as a reflective layer that reflects light emitted from the light emitting layer 103.

  Next, a scribe groove is formed on the lower surface of the substrate 100. After forming the scribe groove, the knife edge of the braking device is pressed against the surface of the contour groove 111 to separate the light emitting elements. Through the steps described above, the light-emitting element illustrated in FIGS. 1A and 1B is manufactured.

  The individually separated light emitting elements are bonded to a frame, a stem, a wiring board, a heat sink and the like. As the bonding method, bonding with silver paste or resin, solder welding, ultrasonic bonding using bumps, thermocompression bonding using a eutectic connection member, or the like is used. Thereafter, for each of the p-side pad portion 105b and the n-side pad portion 107b, the lead electrode corresponding to the polarity and the pad portion are connected by a gold wire or the like. Finally, resin sealing or can packaging is applied to complete a light emitting diode (LED) lamp.

  The depression 106 is arranged inside each lattice of the lattice-like portion 105a. If the electrode material constituting the lattice-like portion 105a moves to the light emitting layer 103 exposed on the side surface of the depression 106 or the n-type nitride semiconductor layer 102 by electromigration or electrochemical migration with moisture interposed, A short circuit occurs.

According to the study by the present inventors, it has been found that the migration is suppressed by using at least one of Pt, Pd, Ir, and Rh as the material of the lattice-like portion 105a. Moreover, if these electrode materials are used, a favorable contact resistivity (for example, 5 × 10 ⁻³ Ωcm ⁻² or less) can be obtained.

  In the above example, the layer in contact with the p-type nitride semiconductor layer 104 (the layer below the Au layer) of the lattice-like portion 105a is the Pt layer. However, this layer may be a Pd layer, an Rh layer, or an Ir layer. Good. By forming the Pt layer, Pd layer, Ir layer, or Rh layer, the contact resistivity can be lowered and the reflectance can be increased. Here, the reflectance is the reflectance at the interface with the p-type nitride semiconductor layer 104 with respect to the wavelength of the light emitted from the light emitting layer 103.

  In the LED lamp using the light emitting element of the embodiment, the light reflected by the lower surface of the lattice-like portion 105a is reflected from the reflective layer formed on the lower surface of the substrate 100, thereby extracting the light from the upper surface of the light emitting element. Can do. For this reason, the one where the reflectance of the lower surface of the grid-like part 105a is higher is preferable.

  As yet another configuration example, Ag, which is a metal that has higher reflectivity than Pt, Pd, Ir, and Rh but easily causes electromigration and electrochemical migration, can also be used for the lattice portion 105a. In the case of using Ag, for example, the Pt and Ag layers are sequentially stacked so that the Pt layer is the lower layer so as to have a width of 60 to 80% of the design electrode width. Furthermore, a layer made of Pt, Pd, Ir, or Rh may be stacked so as to cover this with a design electrode width. Instead of the Ag layer, a layer made of an alloy containing Ag can also be used.

  It should be noted that the Ti layer is omitted from the n-side electrode 107 described above, and Al, Rh, Pt, Au, Pt, and Au layers are stacked, or the Ti and Pt layers are omitted, and Al, Rh, A structure in which Au, Pt, and Au layers are stacked may be used, or a structure in which the Ti, Pt, Au, and Pt layers are omitted and the layers of Al, Rh, and Au are stacked may be used. When the Ti layer is omitted, the thickness of the uppermost Au layer is set to 300 nm. When the Ti and Pt layers are omitted, the thickness of the uppermost Au layer is set to 400 nm, and the Ti, Pt, Au, and Pt layers are Is omitted, it is desirable to supplement the thickness of the omitted layer by setting the thickness of the uppermost Au layer to 700 nm.

  The p-side pad portion 105b has a structure in which Ni, Rh, and Au layers are sequentially stacked with the Ni layer as a lowermost layer, a structure in which Ti and Au are sequentially stacked with a Ti layer as a lower layer, and Ti, Rh, and Au. Can also be made into the structure laminated | stacked in order by making Ti layer into the lowest layer. Moreover, Al, Sn, and Pb can also be used as a metal material constituting the lowermost layer of the p-side pad portion 105b.

The p-side electrode 105 and the n-side electrode 107 formed by the above-described method have a low contact resistivity without being alloyed, and the contact resistivity of the p-side electrode 105 is 1 × 10 ⁻³ Ωcm ^{2 to} 5 × 10 ^{−. 3} [Omega] cm is ² mm, the contact resistivity of the n-side electrode 107 is ^{5 × 10 -6 Ωcm 2 ~3 ×} 10 -5 Ωcm 2 or so. By not alloying, the electrode material does not diffuse due to alloying, and therefore the electrode material is suppressed from moving to the side surface of the recess 106. In addition, if it is up to 500 degreeC, even if it alloy-treats, a problem will not arise easily.

  Note that if the p-side electrode 105 or the n-side electrode 107 is formed before the formation of the recess 106, the electrode material easily adheres to the side surface of the recess 106 due to dry etching at the time of forming the recess 106 and subsequent wet etching. Become. In addition, when the electrode material is already formed on the surface of the semiconductor layer, strong acid, strong alkali, and strong oxidizing liquid cannot be used as the etching solution, so that it is possible to sufficiently remove the denatured organic residue and crystal residue of the resist. This will cause a malfunction. However, in the above-described method, since the p-side electrode 105 and the n-side electrode 107 are formed after the depression 106 is formed, such a problem is prevented.

As a material for the protective film 110, in addition to silicon oxide, titanium oxide (TiO ₂ , TiO ₃ , Ti ₂ O ₅ ), aluminum oxide (Al ₂ O ₃ ), zirconia oxide (ZrO ₂ ), hafnium oxide ( HfO ₂ ), neodymium oxide (Nd ₂ O ₃ ), erbium oxide (Er ₂ O ₃ ), cerium oxide (Ce ₂ O ₃ ), or the like, which is transparent and insulating with respect to the emission wavelength of the light-emitting element is used. be able to.

  The protective film 110 prevents a contaminant from adhering to the side surface of the recess 106 and causing a short circuit. As the contaminant, for example, a conductive substance (polymerization residue or polymerization catalyst having an alkene or alkyne group) contained in the resin for sealing the light emitting element, moisture, or the like can be considered.

  Note that, for example, if the protective film 110 is peeled off due to the following causes, moisture or the like may enter under the protective film 110 and reach the side surface of the depression, thereby causing a short circuit. There is a possibility that the protective film 110 may be peeled off from the pad portion by heat and ultrasonic vibration when wire bonding is performed on the p-side pad portion 105b and the n-side pad portion 107b. Furthermore, there is a possibility that the protective film 110 may be peeled off near the lattice portion 105a of the p-side electrode due to heat generated when the LED lamp emits light.

  Prior to the formation of the protective film 110, on the outermost surfaces of the lattice portion 105a, the p-side pad portion 105b, the linear portion 107a of the n-side electrode, and the n-side pad portion 107b, for example, a Ti layer (3 nm to 100 nm thick) By preferably depositing a Ti layer having a thickness of 30 nm to 50 nm, the adhesion between the p-side and n-side electrodes 105 and 107 and the protective film 110 can be improved. In particular, the lattice-shaped portion 105a and the protective film 110 are in close contact with each other so that the interior of each lattice (each section) of the lattice-shaped portion 105a is hermetically sealed, so that moisture or the like can be prevented from entering the side surfaces of the depressions in the lattice. Is done. In this way, it is possible to suppress the diffusion of contaminants on the lower surface of the protective film 110. Moreover, generation | occurrence | production of a crack etc. are suppressed.

  In addition, since the Ti layer is etched during the wet etching for forming the opening of the protective film 110 on the p-side pad portion 105b and the n-side pad portion 107b, the Au layer is exposed at the bottom of the opening of the protective film 110. . In addition, although the example which vapor-deposits Ti layer was demonstrated, the improvement of adhesiveness is aimed at also using other metals (for example, Al and Ni) which are easy to oxidize.

  Further, prior to the formation of the protective film 110, if a ring-shaped metal weir having a Ti, Al, or Ni layer formed on the uppermost layer is provided along the outer periphery of the contour groove 111, the protective film is in close contact with the ring-shaped metal weir. 110 is formed. Thereby, invasion of contaminants from the interface between the ring-shaped metal weir and the protective film 110 is suppressed.

  Next, with reference to FIG. 4 (A) and FIG. 4 (B), the magnitude | size etc. of the hollow 106 are demonstrated. FIG. 4A is a schematic cross-sectional view in the vicinity of the recess 106, and FIG. 4B is a schematic plan view in the vicinity of the recess 106. As shown in FIG. 4A, the protective film 110 covers the upper surface of the p-type nitride semiconductor layer 104 and the lattice portion 105a, and covers the side surfaces and the bottom surface of the recess 106.

  The line width V of the grid-like portion 105a is 3 μm, for example, and the distance between the centers of a pair of opposite sides of each grid is 15 μm, for example, and the portion sandwiched between a pair of opposite sides of each grid The interval W (referred to as the wiring interval W) is, for example, 12 μm.

  The line width V of the lattice portion 105a is set within a range of 1 to 5 μm. When the line width V is 5 μm or less, the light extraction efficiency from the upper surface of the light emitting element is less reduced due to light shielding by the grid-like portion 105a. Further, in order to pass a current over a wide range on the p-type nitride semiconductor layer 104 and to ensure productivity, the line width V is preferably 1 μm or more.

The wiring interval W is expressed by the equation W = V × N with the line width V as a unit, and N is called a wiring interval coefficient. An appropriate value of the wiring interval coefficient N varies depending on the specific resistance of the p-type nitride semiconductor layer 104. When the specific resistance of the p-type nitride semiconductor layer 104 is 0.5 Ωcm to 3 Ωcm, the wiring spacing coefficient N is suitably 3 to 5, and the specific resistance of the p-type nitride semiconductor layer 104 is 1 × 10 ⁻³ Ωcm to In the case of 1 × 10 ⁻¹ Ωcm, 5 to 10 is appropriate for the wiring interval coefficient N.

  A recess 106 is arranged at the center of each lattice of the lattice-like portion 105a. The diameter H of the opening edge of the recess 106 is, for example, 1 μm or more (for example, 5.5 μm), and the depth of the recess 106 is, for example, 2.36 μm.

  The inclination angle γ of the side surface of the recess 106 with respect to the normal line of the upper surface of the p-type nitride semiconductor layer 104 is, for example, 8.1 °. It should be noted that the side surface of the recess 106 may not be tapered. The inclination angle γ is preferably in the range of 0 ° to 12 °. In addition, when the inclination angle of the taper is not uniform on the side surface, the inclination angle is defined for the fitting line of the entire inclination.

  The shortest distance (distance from one side of the lattice to the edge of the opening) from the lattice-like portion 105a to the opening edge of the recess 106 is 2 μm from the viewpoint of suppressing migration of the wiring material into the recess 106 and improving the manufacturing yield. The above is preferable. It is assumed that the diameter H of the opening is expressed by the equation H = W × M with the wiring interval W as a unit. M is referred to as a depression width coefficient. The dent width coefficient M is preferably in the range of 0.3 to 0.7.

  The ratio of the opening area of the recess 106 to the internal area of one lattice of the lattice-like portion 105a (the area of the portion surrounded by the lattice-like portion 105a) (hereinafter referred to as the opening ratio) is 7% to 50%. It is preferable to set it as the range. The opening ratio is more preferably in the range of 10% to 40%, and further preferably in the range of 12% to 35%.

  The depth of the recess is preferably about 0.3 to 0.7 times the diameter H of the opening. In addition, the distance t from the bottom of the recess 106 to the substrate 100 is preferably 1 μm or more. Note that the depression 106 may have a depth at which the bottom surface reaches the upper surface of the substrate 100. The shape of the bottom surface of the recess 106 may be any of a flat surface, a concave surface recessed downward, and a convex surface rising upward, but is preferably a convex surface.

  In addition, the opening shape of a hollow can also be made into various shapes other than circular. For example, as shown in FIG. 4C, the shape of the opening of the recess can be made substantially rectangular.

  Next, a light-emitting element according to a comparative example will be described with reference to FIG. This is a light emitting device according to the prior art. 20A is a schematic plan view of a light-emitting element according to a comparative example, and FIG. 20B is a schematic cross-sectional view along the line AA ′ in FIG. 20A of the light-emitting element according to the comparative example. Indicates.

  The light emitting element of the comparative example is also made of the nitride semiconductor wafer described with reference to FIG. In the light emitting device of the comparative example, no depression is formed in the p-type nitride semiconductor layer 104. Further, the shape of the light emitting region and the arrangement of the p-side and n-side pad portions are different from those of the first embodiment. This will be described in detail below.

  In the light emitting device of the comparative example, a light emitting region 950 having a shape in which a central portion of one side of a square is cut out is defined on the surface of the p-type nitride semiconductor layer 104. By removing the p-type nitride semiconductor layer 104, the light-emitting layer 103, and the upper layer of the n-type nitride semiconductor layer 102 in the region surrounding the light-emitting region 950, the n-type nitride semiconductor layer 102 is exposed on the bottom surface. A recess 911 (contour groove 911) is formed.

  A p-side electrode 905 is formed on the light emitting region 950. The p-side electrode 905 includes a lattice portion 905a and a p-side pad portion 905b. The lattice portion 905a has a lattice structure, and each lattice is square. A p-side pad portion 905b is formed in the vicinity of the center of the side facing the notched side so as to cover the lattice-shaped portion 905a.

  An n-side electrode 907 is formed on the bottom surface of the contour groove 911. Unlike the n-side electrode 107 of the embodiment, the n-side electrode 907 does not have a linear portion and is configured only by the n-side pad portion 907b. The n-side pad portion 907b is disposed in a portion where the light emitting region 950 is cut out.

  Next, an experiment in which the light emission output of the light emitting elements according to the first example and the comparative example is measured will be described. The light emitting elements of the first example and the comparative example were each mounted on a TO-46 stem, and the total luminous flux was measured with an integrating sphere. The light emission output of the light emitting device of the first example was compared with that of the comparative example. The light output measured in mW was compared.

  The light emission wavelength of the light emitting device of the first example was 478 nm, and the light emission wavelength of the light emitting device of the comparative example was 480 nm. When the light emission output of the light emitting device of the comparative example was 100%, the light emission output of the light emitting device of the first example was 140%. Thus, the light emitting device of the first example shows higher light output than the light emitting device of the comparative example. FIG. 16 summarizes the light emission wavelengths and the light emission outputs of the light emitting elements of the first to sixth examples and the comparative example.

  Next, the function and effect of the recess 106 formed in the light emitting device of the first embodiment will be considered. First, problems of the light emitting element of the comparative example will be considered.

FIG. 21A is a schematic cross-sectional view of the vicinity of the lattice portion 905a of the p-side electrode of the light emitting element of the comparative example. In general, since the p-type nitride semiconductor layer 104 has a high specific resistance (for example, about 1 × 10 ⁻² Ωcm to 3 Ωcm), the p-type nitride semiconductor layer 104 is formed thin (for example, 1 μm or less) in order to suppress series resistance. Is done. As a result, as indicated by the arrow in FIG. 21A, the current starting from the p-side electrode 905a is not sufficiently diffused in the p-type nitride semiconductor layer 104 and is transferred to the n-type nitride semiconductor layer 102. Flowing.

  Due to this, the light emitting layer 103 contributes to light emission only in the vicinity of the portion arranged directly below the lattice portion 905a (hereinafter referred to as the light emitting portion). In the figure, the light emitting part is surrounded by a broken line. The light emitting layer 103 other than the light emitting portion will function as an absorbing layer that absorbs light emitted from the light emitting portion.

  FIG. 21B is a cross-sectional view schematically showing an optical path until the light emitted from the light emitting portion X is taken out of the light emitting element in the LED lamp using the light emitting element of the comparative example. The illustrated optical path is an example.

  A reflection layer 120 that reflects light emitted from the light emitting layer 103 is formed on the lower surface of the substrate 100. The light emitting element is sealed in the translucent resin 130. The light emitted from the light emitting part X is taken out of the device (in the translucent resin 130) through various optical paths. The refractive index of the nitride semiconductor layer is higher than the refractive index of the translucent resin 130, and the refractive index of the nitride semiconductor layer is higher than the refractive index of the substrate 100.

  The optical path from the light emitting part X to the outside of the element can be classified into the following three types. The first type of optical path is an optical path of light extracted from the upper surface of the nitride semiconductor layer to the outside of the element (optical paths L1, L2, and L3 in the drawing).

  The second type of optical path is the light that is totally reflected at the interface between the nitride semiconductor layer and the translucent resin 130 and is extracted from the end face of the light emitting element to the outside of the element, at the interface between the nitride semiconductor layer and the substrate 100. This is an optical path of light that is not totally reflected (optical paths L4 and L5 in the figure). That is, the light passing through the second type optical path is reflected by the interface between the nitride semiconductor layer and the translucent resin 130 and the reflection layer 120 and extracted from the end face of the light emitting element. The light passing through such an optical path is referred to as intra-element propagation light.

  In the example shown in FIG. 21B, since the length of the light emitting element in the in-plane direction of the nitride semiconductor layer is short, the light passing through the optical path L4 is reflected by the reflective layer 120 and then the nitride semiconductor layer. Before being reflected at the interface between the element and the resin outside the element, the light extracted from the end face of the element and passing through the optical path L5 is reflected at the interface between the nitride semiconductor layer and the translucent resin 130, and then the reflection layer 120. Before being reflected by the element.

  The third type optical path is also reflected at the interface between the nitride semiconductor layer and the translucent resin 130, and is also reflected at the interface between the nitride semiconductor layer and the substrate 100 out of the light extracted from the end face of the light emitting element. This is an optical path of light that is totally reflected (optical paths L6 and L7 in the figure). That is, the light passing through the third type optical path is reflected at the interface between the nitride semiconductor layer and the translucent resin 130 and the interface between the nitride semiconductor layer and the substrate 100, and from the end surface of the nitride semiconductor layer. It is taken out. The light passing through such an optical path will be referred to as the propagation light in the nitride semiconductor layer.

  In any of the above optical paths, the light emitted from the light emitting layer 103 is absorbed by a portion of the light emitting layer 103 that does not contribute to light emission, or due to defects in the nitride semiconductor layer. It attenuates by.

  Since the nitride semiconductor layer is thinner than the entire thickness of the light emitting element, it is considered that the propagation light in the nitride semiconductor layer has a larger number of reflections until reaching the end face of the element than the propagation light in the element. Due to this, it is considered that the light propagated in the nitride semiconductor layer is more easily attenuated than the light propagated in the element.

  FIG. 5 is a cross-sectional view schematically showing an optical path of light taken out from the bottom surface of the recess 106 in the light emitting element of the first embodiment. The illustrated optical path is an example. In the light emitting device of the first embodiment, the recess 106 is formed in a region where the lattice-like portion 105a of the p-type nitride semiconductor layer 104 is not formed. That is, at least a part of the light-emitting layer 103 that is not disposed below the p-side electrode grid portion 105a and is considered not to contribute to light emission is removed.

  For example, light extracted from the bottom surface of the depression 106 does not pass through the n-type nitride semiconductor layer 102, the light emitting layer 103, and the p-type nitride semiconductor layer 104 that are removed along with the formation of the depression 106. For this reason, in the light emitting device of the first embodiment, compared to the case where no depression is formed, attenuation due to absorption in the nitride semiconductor layer can be suppressed and light can be extracted outside the device.

  FIG. 6A is a cross-sectional view schematically showing an optical path of light taken out from the side surface of the recess 106 in the light emitting element of the first embodiment. For example, consider the propagation light in the nitride semiconductor layer. As shown in FIG. 6A, the propagation light in the nitride semiconductor layer can be taken out of the element from the side surface of the recess 106 before reaching the end face of the nitride semiconductor layer. As described above, when the light emitting device of the first embodiment is used, light extracted from the end face of the device can be extracted from the side surface of the recess 106 when the recess 106 is not formed. Attenuation occurring before reaching the end face of the light emitting element can be suppressed, and light can be extracted outside the element.

  Note that the amount of light emitted from the light emitting element to the upper surface side (the amount of light in the normal direction of the upper surface of the p-type nitride semiconductor layer 104) is increased by refraction of light on the side surface of the recess 106 and changing the path upward. Can be made.

  As shown in FIG. 6B, after exiting the element from the side surface of a certain depression 106, entering the element again from the bottom surface of the depression 106, and then taking it out from the side surface of the depression 106 adjacent thereto. The optical path of light is also conceivable. Note that the optical paths shown in FIGS. 6A and 6B are examples.

  Next, with reference to FIG. 7 (A) and FIG. 7 (B), the effect | action and effect which the taper attached to the side surface of the hollow 106 have are considered.

  FIG. 7A shows a schematic cross-sectional view of the vicinity of a recess (this is referred to as a recess 106A) in the case where no taper is provided. The side surface of the recess 106 </ b> A is perpendicular to the upper surface of the p-type nitride semiconductor layer 104. The edge of the opening and the edge of the bottom surface of the recess 106A are circumferential, and the shape of the space surrounded by the inner surface of the recess 106 is cylindrical. A cross section passing through the center of the edge of the opening of the recess 106A and perpendicular to the upper surface of the p-type nitride semiconductor layer 104 is shown. Here, the line of intersection between the cut surface and the side surface of the recess 106A is simply referred to as a side surface.

  The diameter of the recess 106A is L and the depth is D. The refractive index of the nitride semiconductor layer is n1, and the refractive index of the medium outside the element is n2. The refractive index n2 is smaller than n1. Consider the light that passes through the n-type nitride semiconductor layer 102 and enters the incident point P located at the lowermost portion of the one side surface S1.

  The incident angle of light incident on the incident point P is defined by an angle formed with the normal line of the side surface S1. In addition, the refraction angle of the light that has entered the incident point P and then exited toward the depression 106A is defined by the angle formed with the normal of the side surface S1.

  Let βdia be the refraction angle of the light emitted from the incident point P toward the point Q on the edge of the opening of the other side surface S2. Let αdia be the incident angle of incident light corresponding to light emitted at a refraction angle βdia. Let αcrt be the critical angle at which total reflection occurs at the incident point P. A refraction angle of outgoing light corresponding to light incident at an incident angle αcrt is βcrt. The refraction angle βcrt is 90 °.

  The refraction angle range of the light that is incident on the incident point P, is emitted to the dent 106A side, and is taken out of the element as it is is from βdia to βcrt. Corresponding to this, the incident angle range of the light that is incident on the incident point P, is emitted to the depression 106A side, and is taken out of the device as it is is from αdia to αcrt. The difference between the refraction angles βcrt and βdia is defined as the effective emission angle amount Δβeff, and the difference between the incident angles αcrt and αdia is defined as the effective incidence angle amount Δαeff.

Snell's law for light with incident angle α and refraction angle β
... (1)
Holds. Based on Snell's law (1), the incident angles αctr and αdia are
... (2)
... (3)
It is calculated from the formula.

Βcrt in equation (2) is 90 °. Βdia in equation (3) is
... (4)
It is calculated from the formula. Here, the ratio D / L of the depth D to the diameter L of the dent is represented by d.

  For example, the ratio d is 0.5, the refractive index n1 of the nitride semiconductor layer is 2.4, and the refractive index n2 of the medium outside the element is 1.0. In this case, from the expressions (2) and (3), αcrt is 24.6 °, and αdia is 10.7 °. Accordingly, the effective incident angle amount Δαeff is 13.9 °.

  Under the same conditions, when the refractive index n2 of the medium outside the element is 1.5, αdia is 16.2 ° and αcrt is 38.7 °. Accordingly, the effective incident angle amount Δαeff is 22.5 °. It can be seen that the effective angle of incidence increases as the refractive index of the medium outside the element increases.

  FIG. 7B shows a schematic cross-sectional view in the vicinity of the tapered recess 106. The depression 106 has a shape that widens from the bottom to the top. The edge of the opening and the bottom edge of the recess 106 are circumferential, and the shape of the space surrounded by the inner surface of the recess 106 is a truncated cone. A cross section passing through the center of the edge of the opening of the recess 106 and perpendicular to the upper surface of the p-type nitride semiconductor layer 104 is shown. The inclination angle of the side surface of the depression 106 is γ. Here, the line of intersection between the cut surface and the side surface of the recess 106 is simply referred to as a side surface.

  The diameter of the edge of the bottom surface of the recess 106 is L, and the depth is D. Consider the light that passes through the n-type nitride semiconductor layer 102 and enters the incident point Pt located at the lowermost portion of the one side surface St1.

  The incident angle of light incident on the incident point Pt is defined by an angle formed with the normal line of the side surface St1. In addition, the refraction angle of the light that has entered the incident point Pt and then exited toward the depression 106 is defined by the angle formed with the normal of the side surface St1.

  Let βtdia be the refraction angle of light emitted from the incident point Pt toward the point Qt on the edge of the opening of the other side surface St2. An incident angle of incident light corresponding to light emitted at a refraction angle βtdia is αtdia. Let αtcrt be the critical angle at which total reflection occurs at the incident point Pt. Let βtcrt be the refraction angle of outgoing light corresponding to light incident at an incident angle αtcrt. The refraction angle βtcrt is 90 °.

  The refraction angle range of the light that is incident on the incident point Pt, is emitted to the dent 106 side, and is taken out of the element as it is is from βtdia to βtcrt. Corresponding to this, the incident angle range of the light that is incident on the incident point Pt, is emitted to the dent 106 side, and is taken out of the device as it is is from αtdia to αtcrt. The difference between the refraction angles βtcrt and βtdia is defined as the output effective angle amount Δβteff, and the difference between the incident angles αtcrt and αtdia is defined as the incident effective angle amount Δαteff.

Based on Snell's law (1), the incident angles αtctr and αtdia are respectively
... (5)
... (6)
It is calculated from the formula. Here, the refractive index of the nitride semiconductor layer is n1, and the refractive index of the medium outside the element is n2.

In the formula (5), βtcrt is 90 °. Βtdia in equation (6) is
... (7)
It is calculated by the formula. Here, d is the ratio D / L.

  The taper inclination angle γ is set to 8.0 °, for example. As for the other conditions, as in the example described with reference to FIG. 7A, the ratio d is set to 0.5, the refractive index n1 of the nitride semiconductor layer is set to 2.4, and the refraction of the medium outside the element is set. The rate n2 is set to 1.0. In this case, αtcrt is 24.6 ° from the equation (5). This coincides with αcrt in the example described with reference to FIG. Further, from the equation (6), αtdia is 7.0 °. Accordingly, the effective incident angle amount Δαteff is 17.6 °.

  The incident effective angle amount Δαteff (17.6 °) with the taper is larger than the effective incident angle amount Δαeff (13.9 °) with no taper. As described above, by tapering the side surface of the depression, the range of incident angles on the side surface of the depression is widened for the light emitted from the depression side surface and extracted as it is outside the element. That is, it becomes easy to take out light from the hollow side surface by the taper.

  Qualitatively, when the taper is provided, the upper part of the dent is wider than the lower part, and light emitted from the dent side surface is less likely to enter the element from the upper part of the dent side surface. It can be said. This also applies to light extracted from the bottom surface of the depression.

  In addition, as shown in FIG. 8, the light (light shown by the optical paths L11 to L13 in the figure) reflected by the tapered hollow side surface propagates downward in the light emitting element, and this light is reflected by the reflection layer. The effect of being reflected by 120 and being easily taken out of the device from the upper surface of the p-type nitride semiconductor layer 104 and the bottom surface of the recess 106 is also expected. In addition, the incidence angle of the light emitted from the side surface of the depression to the outside of the element (light indicated by the optical path L14 in the figure) incident on the side surface of the depression is reduced by the taper, and the effect of reducing the reflection loss on the side surface of the depression is also expected. The

  Here, in particular, the propagation light in the nitride semiconductor layer will be considered. It is assumed that the nitride semiconductor layer has a refractive index of 2.4 and the substrate 100 is made of sapphire and has a refractive index of 1.77. The critical angle of light incident from the nitride semiconductor layer side and totally reflected at the interface between the nitride semiconductor layer and the substrate 100 is 47.5 ° from Snell's law (1). The propagation light in the nitride semiconductor layer has an incident angle with respect to the substrate 100 of 47.5 ° or more.

  Consider the case where the side surface of the dent is vertical (not tapered). The maximum incident angle of the light propagating in the nitride semiconductor layer incident on the side surface of the depression is 42.5 °, which is a residual angle of 47.5 °.

  When the incident critical angle αcrt exceeds 42.5 °, there is no propagating light in the nitride semiconductor layer incident on the side surface of the recess at an incident angle in the range from 42.5 ° to the incident critical angle αcrt. The range of incident angles of light that is incident and taken out of the device as it is becomes narrower. In this case, the upper limit of the incident angle of light that is incident on the side surface of the hollow and is taken out of the device as it is is 42.5 °.

  In the example described with reference to FIG. 7A, when the refractive index of the medium outside the element is 1.0 and 1.5, the incident critical angle αcrt is 24.6 ° and 38.7 °, respectively. It was. Since these incident critical angles αcrt are smaller than 42.5 °, they are included in an angle range in which the light propagating in the nitride semiconductor layer can enter the side surface of the depression.

  Next, consider a case where the side surface of the recess is tapered. The inclination angle of the taper is γ. The maximum incident angle of the light propagating in the nitride semiconductor layer incident on the side surface of the dent is 42.5 ° −γ obtained by subtracting γ from 42.5 °, which is the remainder angle of 47.5 °.

  When 42.5 ° -γ is smaller than the incident critical angle αcrt, there is no light propagating in the nitride semiconductor layer incident on the side surface of the depression at an incident angle in the range of 42.5 ° -γ to the incident critical angle αcrt. The range of the incident angle of light that is incident on the side surface of the depression and is taken out of the device as it is becomes narrower. The maximum inclination angle γ at which the range of the incident angle does not occur is an angle at which 42.5 ° −γ becomes equal to the incident critical angle αcrt. That is, such an inclination angle γ can be obtained from an expression of 42.5 ° −αcrt.

  In the example described with reference to FIG. 7B, when the refractive index of the medium outside the element is 1.0 and 1.5, the incident critical angles αcrt are 24.6 ° and 38.7 °, respectively. It was. When the refractive index of the medium outside the element is 1.0, the maximum tilt angle becomes 17.9 ° from 42.5 ° -24.6 °, and when the refractive index of the medium outside the element is 1.5, the maximum The inclination angle of 3.8 ° is 3.8 ° from 42.5 ° -38.7 °.

  As described above, the propagation light in the nitride semiconductor layer has been particularly considered. However, the light emitted from the light emitting layer and extracted from the depression to the outside of the device can pass through various optical paths.

  According to the experience of the inventors of the present application, generally, the inclination angle of the taper is preferably in the range of 0 ° to 12 °. In particular, in consideration of the propagation light in the nitride semiconductor layer, it is effective to reduce the inclination angle of the taper as the refractive index of the medium outside the element increases.

  When the refractive index of the medium outside the element is in the range of 1.0 to 1.3, the inclination angle of the taper of the recess is preferably 3 ° to 18 °, more preferably 5 ° to 12 °. When the refractive index of the medium outside the element is in the range of 1.3 to 1.6, the taper inclination angle is preferably 0 ° to 12 °, more preferably 0 ° to 7 °. Further, when the refractive index of the medium outside the element is in the range of 1.6 to 2.0, the taper inclination angle is preferably 0 ° to 7 °, more preferably 0 ° to 3 °.

  Next, the relationship between the diameter of the opening of the depression and the depth of the depression will be considered. The ratio of the depth of the depression to the diameter of the opening of the depression is defined as the depression depth ratio. As the depth ratio of the depression increases, light emitted from the vicinity of the bottom of the depression to the outside of the element becomes easier to enter the element again from the side surface of the depression. As the dent depth ratio becomes smaller, the side area of the dent becomes narrower, and the amount of light taken out from the side surface of the dent decreases. According to the experience of the inventors of the present application, a preferable range of the recess depth ratio is 0.3 to 0.7, and a more preferable range is 0.35 to 0.55.

  Next, the distance from the bottom of the recess to the substrate 100 will be described. The distance from the bottom of the recess to the substrate 100 is preferably 1 μm or more. Thereby, for example, it is considered that light that is incident on the interface between the nitride semiconductor layer and the substrate 100 from the nitride semiconductor layer side and reflected upward is easily extracted from the bottom surface of the recess 106.

  The shape of the bottom surface of the recess may be any of a flat surface, a concave surface recessed downward, and a convex surface rising upward, but is preferably a convex surface. When the surface is convex, for example, the incident angle to the bottom surface of the recess is smaller than that when the bottom surface of the recess is flat with respect to light reflected from the nitride semiconductor layer side and incident on the interface between the nitride semiconductor layer and the substrate 100. Become. Thereby, improvement of light extraction efficiency is expected.

  Next, with reference to FIG. 9A, a light-emitting element according to the second embodiment will be described. FIG. 9A shows a schematic plan view of a light emitting device according to the second embodiment. The shape of the grid-like portion of the p-side electrode and the corresponding arrangement of the recesses are different from those of the first embodiment. Other configurations are the same as those of the first embodiment.

  The p-side electrode 205 includes a lattice portion 205a and a pad portion 205b. The lattice-like portion 205a is a linear portion that connects a plurality of square-shaped circumferential portions arranged in a matrix (referred to as quadrilateral portions) and square portions that are adjacent to each other in the row or column direction. (This will be referred to as a connecting portion). Each side of the rectangular part is parallel to the row direction or the column direction of the matrix. The vicinity of the center of a pair of opposing sides of the quadrangular portions adjacent to each other is connected by a coupling portion.

  Consider four quadrilaterals respectively arranged on four vertices of one grid of a matrix. By connecting these four quadrangular portions at the coupling portion, a cross-shaped section (decagonal section) surrounded by the four quadrangular sections and the coupling section is defined.

  One depression 206 is formed inside each quadrangular portion, and one depression 206 is also formed inside each cross-shaped section. The depression 206 inside each square part is arranged at the extended line length of the coupling part connected to each square part.

  The line width of the rectangular portion is 3 μm, for example. The length of one side of the square part (the distance between the centers of a pair of opposite sides of the square part) is, for example, 15 μm. The arrangement interval of the rectangular portions (center interval between adjacent rectangular portions) is, for example, 26.6 μm. The line width of the coupling portion is, for example, 3 μm.

  The manufacturing method of the light emitting device of the second embodiment is the same as the manufacturing method of the light emitting device of the first embodiment. However, the resist mask opening pattern for forming the recess 206 and the resist mask opening pattern for forming the lattice-like portion 205a correspond to the second embodiment.

  Next, an experiment in which the light emission output of the light emitting device of the second example is measured will be described. A method similar to the experiment in which the light emission output of the light emitting device of the first example was measured was used. The light emission output was compared with that of the comparative example as in the first example. The light emitting wavelength of the light emitting device of the second example was 481 nm, and the light emission output was 145% of that of the light emitting device of the comparative example.

  Next, with reference to FIG. 9B, the operation and effect of the lattice-like portion 205a of the light emitting element of the second embodiment will be considered.

  Consider light emitted from a region of the light emitting layer 103 disposed below the coupling portion of the lattice-like portion 205a. This region is considered by dividing it into several parts with respect to the length direction of the coupling portion. By adding the light emitted from each of the divided parts in the length direction of the coupling part, the light emitted in the length direction of the coupling part is considered to be stronger than the light emitted in the other direction. It is done. The light emitted in the length direction of the linear portion from the region disposed below the linear portion of the p-side electrode is referred to as electrode parallel light.

  The depression 206 disposed inside the quadrangular portion to which the coupling portion is connected is disposed on an extension line of the coupling portion. Accordingly, it is considered that the electrode parallel light corresponding to the coupling portion is easily extracted from the side surface of the recess 206.

  The coupling portion defines a side shared by two cross-shaped sections adjacent to each other. The electrode parallel light corresponding to the coupling portion can be taken out from the depression 206 in the section surrounded by the rectangular portion adjacent to both of the two cross-shaped sections.

  Note that the wiring interval W of the quadrangular portion is defined in the same way as the square lattice p-side electrode of the first embodiment (see FIG. 4). For the cross-shaped region, the interval between the vertices of two rectangular portions arranged diagonally among the four rectangular portions surrounding the cross-shaped region is defined as a wiring interval W.

  In addition, the opening shape of a hollow can also be made into various shapes other than circular. For example, as shown in FIG. 9C, the shape of the opening of the recess can be made substantially rectangular. Consider a recess that is located within a cross-shaped region and has a substantially rectangular opening. It is necessary to arrange the depression so as not to overlap the quadrangular portion surrounding the cross-shaped region.

  When the side of the opening of the depression is parallel to the row direction or the column direction in which the quadrangular portions are arranged, it is necessary to make the opening fit within the portion where the cross intersects. In this case, the corner portion of the recess opening easily interferes with the quadrangular portion, and it is difficult to enlarge the recess opening. If the sides of the depression openings are inclined with respect to the row direction or the column direction in which the quadrangular portions are arranged (for example, an angle of 45 ° is formed), the depression openings can be easily enlarged.

  Next, a modification of the second embodiment will be described with reference to FIG. FIG. 10A is a schematic plan view of the light emitting element of this modification. In this modification, the shape of the lattice-like portion 205aA of the p-side electrode 205A is a hexagonal lattice, and depressions 206A are formed in each lattice.

  As shown in FIG. 10 (B), the depression 206A in the hexagonal lattice LAT is arranged on the extension line of the side connected to each vertex of the hexagonal lattice LAT of the six hexagonal lattices adjacent to a certain hexagonal lattice LAT. ing. Accordingly, it is considered that the electrode parallel light corresponding to the side connected to each vertex of the hexagonal lattice LAT is easily extracted from the side surface of the recess 206A in the hexagonal lattice LAT.

  The electrode parallel light corresponding to the side shared by the two hexagonal sections adjacent to each other can be extracted from the depression 206A in the hexagonal section adjacent to both of the two hexagonal sections.

  Next, a light emitting device according to a third embodiment will be described with reference to FIGS. FIG. 11A is a schematic plan view of the light emitting device according to the third embodiment, and FIGS. 11B and 11C are respectively a line AA ′ in FIG. The schematic sectional drawing in alignment with the BB 'line is shown.

  In the light emitting device of this example, a nitride semiconductor wafer different from the light emitting devices of the first and second examples and the comparative example is used. This nitride semiconductor wafer has a high resistance nitride semiconductor layer 312 between the buffer layer 101 and the n-type nitride semiconductor layer 102. The high resistance nitride semiconductor layer 312 has a higher resistivity than the n-type nitride semiconductor layer 102 and does not make ohmic contact with the n-side electrode. The high resistance nitride semiconductor layer 312 is formed by the same film formation method as that for forming the n-type nitride semiconductor layer 102 and the like.

  A region 313 (n-side pad placement region 313) in which the pad portion 307b of the n-side electrode 307 is disposed in the contour groove 311 is dug to a depth at which the high-resistance nitride semiconductor layer 312 is exposed, and the n-side pad portion. 307 b is formed on the high-resistance nitride semiconductor layer 312.

  On the surface of the p-type nitride semiconductor layer 104, a light emitting region 350 having a shape in which one corner of a square is cut out is defined as in the light emitting elements of the first and second embodiments. As shown in FIG. 11A, the notched portion of the light emitting region 350 overlaps with the n-side pad arrangement region 313. The n-side pad portion 307b is disposed at a portion where the light emitting region 350 is cut out.

  The linear portion 307 a of the n-side electrode 307 is formed on the n-type nitride semiconductor layer 102. Note that a portion of the linear portion 307 a that is connected to the pad portion 307 b is formed on the high-resistance nitride semiconductor layer 312. Other configurations are the same as those of the light emitting device of the first embodiment.

  Next, a method for manufacturing a light emitting device according to the third embodiment will be described. The contour groove 311 is formed in the same manner as the method described with reference to FIG. 2A in the first embodiment. However, at this stage, the n-side pad arrangement region 313 is also the same depth as the other regions of the contour groove 311 (the depth at which the n-type nitride semiconductor layer 102 is exposed on the bottom surface). Next, a recess 306 is formed in the same manner as described with reference to FIG.

  Next, as shown in FIG. 13A, a resist mask R313 having an opening corresponding to the n-side pad arrangement region 313 is formed by photolithography. Next, the high resistance nitride semiconductor layer 312 is exposed by removing the n-type nitride semiconductor layer 102 in the opening of the resist mask R313 using dry etching. Next, the resist mask R313 is removed by washing.

  Next, in the same manner as described with reference to FIG. 2C, the lattice-like portion 305a of the p-side electrode 305 is formed.

  Next, in the same manner as described with reference to FIG. 3A, an electrode material is deposited to form the linear portion 307a and the n-side pad portion 307b of the n-side electrode 307. An n-side pad portion 307 b is formed on the high resistance nitride semiconductor layer 312, and a linear portion 307 a is formed on the n-type nitride semiconductor layer 102.

  Thereafter, in the same manner as described with reference to FIGS. 3B and 3C, the p-side pad portion 305b and the protective film 310 are formed.

  Next, an experiment in which the light emission output of the light emitting device of the third example is measured will be described. A method similar to the experiment in which the light emission output of the light emitting device of the first example was measured was used. The light emission output was compared with that of the comparative example as in the first example. The light emitting wavelength of the light emitting device of the third example was 479 nm, and the light emission output was 170% of that of the light emitting device of the comparative example.

  In the light emitting device of the third embodiment, the n-side pad portion is formed on the high resistance nitride semiconductor layer. For this reason, compared with the light emitting elements of the first and second embodiments, the current does not concentrate near the n-side pad portion, and the current flowing between the linear portion of the n-side electrode and the p-side electrode increases. I think that.

  Accordingly, it is considered that the light emission output is increased because the region contributing to light emission is expanded in the in-plane direction of the light emitting layer, compared with the case where the current is concentrated near the n-side pad portion. In addition, since the current is made uniform in the in-plane direction of the light emitting layer, the light emission state is made uniform and light emission unevenness is reduced.

  A region having a high current density in the light emitting layer tends to be deteriorated. Since the light emitting element of the third embodiment can disperse the current in the light emitting layer, the deterioration of the light emitting element can be suppressed.

  Next, with reference to FIGS. 12A to 12C, a light-emitting element according to the fourth embodiment will be described. FIG. 12A is a schematic plan view of a light emitting device according to the fourth embodiment, and FIGS. 12B and 12C are respectively a line AA ′ in FIG. The schematic sectional drawing in alignment with the BB 'line is shown. In the light emitting device of this example, a nitride semiconductor wafer similar to the light emitting devices of the first and second examples and the comparative example is used.

  In the light emitting element of this embodiment, a region 413 (n-side pad placement region 413) in which the pad portion 407b of the n-side electrode 407 is disposed in the contour groove 411 is dug up to a depth at which the substrate 100 is exposed. An n-side pad portion 407 b is formed on the substrate 100. The substrate 100 is made of, for example, sapphire and is insulative. The linear portion 407 a of the n-side electrode 407 is formed on the n-type nitride semiconductor layer 102. Note that a portion of the linear portion 407 a that is connected to the pad portion 407 b is formed on the substrate 100. Other configurations are the same as those of the light emitting device of the first embodiment.

  Next, a method for manufacturing a light emitting device according to the fourth embodiment will be described. The recess 406 is formed in the same procedure as the light emitting device of the third embodiment.

  Next, as shown in FIG. 13B, a resist mask R413 having an opening corresponding to the n-side pad arrangement region 413 is formed by photolithography. Next, the substrate 100 is exposed by removing the n-type nitride semiconductor layer 102 and the buffer layer 101 in the opening of the resist mask R413 using dry etching. Next, the resist mask R413 is removed by washing.

  Next, a lattice-like portion 405a of the p-side electrode 405 is formed in the same manner as described with reference to FIG. Next, in the same manner as the method described with reference to FIG. 3A, an electrode material is deposited to form the linear portion 407a and the n-side pad portion 407b of the n-side electrode 407. An n-side pad portion 407 b is formed on the substrate 100 and a linear portion 407 a is formed on the n-type nitride semiconductor layer 102.

  Thereafter, the p-side pad portion 405b and the protective film 410 are formed in the same manner as the method described with reference to FIGS. 3B and 3C.

  Next, an experiment in which the light emission output of the light emitting device of the fourth example is measured will be described. A method similar to the experiment in which the light emission output of the light emitting device of the first example was measured was used. The light emission output was compared with that of the comparative example as in the first example. The light emitting wavelength of the light emitting device of the fourth example was 480 nm, and the light emission output was 240% of that of the light emitting device of the comparative example.

  In the light emitting device of the fourth example, it is considered that the current flowing between the linear portion of the n-side electrode and the p-side electrode increases as in the light emitting device of the third example. As a result, a region contributing to light emission in the in-plane direction of the light emitting layer is widened, so that the light emission output is considered to increase. Further, similarly to the third embodiment, it is possible to reduce light emission unevenness and suppress deterioration of the light emitting layer. In the light emitting device of the fourth embodiment, it is not necessary to form a high resistance nitride semiconductor layer on the nitride semiconductor wafer.

  Next, with reference to FIGS. 14A to 14C, a light-emitting element according to the fifth embodiment will be described. FIG. 14A shows a schematic plan view of the light emitting device according to the fifth embodiment, and FIGS. 14B and 14C show the A-A ′ line in FIG. The schematic sectional drawing in alignment with the BB 'line is shown. The light emitting device of the fifth embodiment is different from the fourth embodiment in the shape of the light emitting region and the arrangement of the p-side and n-side pad portions. This will be described in detail below.

  In the light emitting device of the fifth embodiment, a light emitting region 550 having a shape in which a central portion of one side of a square is cut out is defined on the surface of the p-type nitride semiconductor layer 104. An n-side pad portion 507b is disposed in a portion where the light emitting region 550 is cut out. A region 513 (n-side pad placement region 513) where the n-side pad portion 507b is placed is dug up to a depth at which the substrate 100 is exposed, as in the fourth embodiment. The linear portion 507a of the n-side electrode 507 is connected to the n-side pad portion 507b and has an elongated shape in a direction parallel to one side of the light emitting region 550. N-side pad portion 507 b is formed on substrate 100, and linear portion 507 a is formed on n-type nitride semiconductor layer 102.

  The p-side pad portion 505b is disposed in the vicinity of the center of the side facing the notched side on the light emitting region 550. The lattice portion 505 a of the p-side electrode 505 has a shape corresponding to the light emitting region 550. A recess 506 is formed inside each lattice of the lattice portion 505a.

  The light emitting device of the fifth example is manufactured by the same method as the light emitting device of the fourth example. However, the contour groove 511 and the depressions 506 that define the light emitting region 550, the lattice-like portion 505a and the p-side pad portion 505b of the p-side electrode 505, the n-side pad arrangement region 513, the linear portion 507a and the pad portion of the n-side electrode 507 The opening pattern of the resist mask for forming 507b corresponds to that of the fifth embodiment.

  Next, an experiment in which the light emission output of the light emitting device of the fifth example is measured will be described. A method similar to the experiment in which the light emission output of the light emitting device of the first example was measured was used. The light emission output was compared with that of the comparative example as in the first example. The light emitting wavelength of the light emitting device of the fifth example was 482 nm, and the light emission output was 210% of that of the light emitting device of the comparative example. The light emitting element of the fifth example has a slightly lower light emission output than the light emitting element of the fourth example.

  In the light emitting element of the fifth example, it is considered that the current flowing between the linear portion of the n-side electrode and the p-side electrode increases as in the light emitting elements of the third and fourth examples. As a result, the region contributing to light emission is expanded in the in-plane direction of the light emitting layer, so that the light emission output is considered to increase. Further, similarly to the third and fourth embodiments, it is possible to reduce light emission unevenness and to suppress deterioration of the light emitting layer.

  Next, with reference to FIGS. 15A and 15B, a light-emitting element according to the sixth embodiment will be described. FIG. 15A is a schematic plan view of the light emitting device of the sixth embodiment, and FIG. 15B is a schematic cross-sectional view along the line AA ′ in FIG. The light emitting device of the sixth example has a configuration in which the recess 106 is removed from the light emitting device of the fourth example. In the light emitting element manufacturing process of the sixth embodiment, the step of forming the depression 406 is omitted from the light emitting element manufacturing process of the fourth embodiment.

  Next, an experiment in which the light emission output of the light emitting device of the sixth example is measured will be described. A method similar to the experiment in which the light emission output of the light emitting device of the first example was measured was used. The light emission output was compared with that of the comparative example as in the first example. The light emission wavelength of the light emitting device of the sixth example was 480 nm, and the light emission output was 120% of that of the light emitting device of the comparative example.

  In the light emitting device of the sixth example, it is considered that the current flowing between the linear portion of the n-side electrode and the p-side electrode increases as in the light emitting device of the fourth example. As a result, the region contributing to light emission is expanded in the in-plane direction of the light emitting layer, so that the light emission output is considered to increase. In addition, it is possible to reduce light emission unevenness and suppress deterioration of the light emitting layer.

  FIG. 17A is a photograph showing a light emitting state of the light emitting device according to the fourth example, and a lower photograph of FIG. 17A is a photograph of the light emitting element shown in the upper photograph of FIG. It is an enlarged photograph near a hollow. FIG. 17B is a photograph showing a light emitting state of the light emitting device according to the sixth example. The light emitting device of the sixth example is obtained by removing the depression from the light emitting device of the fourth example. The luminance in the upper surface direction of the light emitting device according to the fourth embodiment is stronger than that of the light emitting device according to the sixth embodiment. As can be seen from the enlarged photograph shown at the lower side of FIG. 17A, light is emitted upward from the recessed side surface of the light emitting device according to the fourth embodiment.

  Next, with reference to FIG. 18, an experiment for examining the effect of the protective film will be described. With respect to the light-emitting element of the fourth example and the light-emitting element having a configuration obtained by removing the protective film from the light-emitting element of the fourth example, the temporal change of the light emission output was examined.

  The horizontal axis of the graph shown in FIG. 18 indicates time, and the vertical axis indicates light emission output. Curve C1 shows the results with the protective film, and curve C2 shows the results without the protective film. In the case without the protective film, the light emission output decreased to about 70% of the initial value after about 400 hours. In the case of the protective film, the light emission output was 95% or more of the initial value even after 1000 hours. As described above, the deterioration of the light emission output with time is suppressed by the protective film.

  Note that the p-type nitride semiconductor is formed such that the end surface of the light-emitting element from which the p-type nitride semiconductor layer 104, the light-emitting layer 103, and the n-type nitride semiconductor layer 102 are exposed becomes narrower as the light-emitting element goes from the bottom to the top. The light is effectively extracted by inclining 3 ° to 13 ° with respect to the normal direction of the upper surface of the layer 104.

  In the above-described embodiment, the shape of each section surrounded by the lattice-like portion of the p-side electrode is a polygon such as a square, but each section may have a shape other than the polygon. The lattice portion only needs to have a mesh shape that divides the surface of the p-type nitride semiconductor layer into a plurality of sections. A recess is formed in the compartment defined by the grid portion so that the edge of the opening is separated from the grid portion. In addition, it is also possible to make the number of the depressions arranged inside one section into a plurality.

  In the first to fourth and sixth embodiments described above, the shape of the light emitting region viewed from above is a shape in which one corner of a square is cut out, but the shape of the light emitting region is limited to a square. Instead, it may be a rectangle including a rectangle or a parallelogram.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

100 substrate 101 buffer layer 102 n-type nitride semiconductor layer 103 light-emitting layer 104 p-type nitride semiconductor layer 105 p-side electrode 105a lattice-like portion 105b p-side pad portion 106 depression 107 n-side electrode 107a linear portion 107b n-side pad portion 111 Contour groove 150 Light emitting area

Claims (7)

A support layer, a lower semiconductor layer formed above the support layer, having a first conductivity type and having a lower resistivity than the support layer, and a light emitting layer formed on the lower semiconductor layer A first region including an upper semiconductor layer formed on the light emitting layer and having a second conductivity type opposite to the first conductivity type, and an upper electrode formed on the upper semiconductor layer When;
A second region including the support layer, the lower semiconductor layer formed above the support layer, and a first portion of the lower electrode formed on the lower semiconductor layer;
A third region including the support layer and a second portion of the lower electrode formed on the support layer ;
I have a,
When the first to third regions are viewed from above, the first region has a shape in which one corner of a quadrangle is cut out, and the cut out part of the first region is the first region. 3, the second portion of the lower electrode formed in the third region is used as a pad, and the corner adjacent to the notched corner of the first region, A light emitting device in which a portion of the upper electrode used as a pad is arranged . The upper electrode has a mesh shape, and the mesh shape divides the surface of the upper semiconductor layer into a plurality of sections surrounded by the upper electrode,
2. The light emitting device according to claim 1, further comprising a recess having a bottom surface reaching at least an upper surface of the lower semiconductor layer in at least one of the plurality of sections. Furthermore, it has an insulating film which is formed so as to cover the lower semiconductor layer, the light emitting layer, and the upper semiconductor layer at least on the side surface of the depression and is transparent to light emitted from the light emitting layer. 2. The light emitting device according to 2 . The light emitting device according to claim 3 , wherein the insulating film has a thickness of 100 nm to 500 nm. The insulating film is a silicon oxide, titanium oxide, aluminum oxide, zirconium oxide, hafnium oxide, neodymium oxide, erbium oxide, and a light-emitting element according to claim 3 or 4 comprising at least one of cerium oxide. The insulating film is formed so as to cover the lower electrode except for a part of the upper surface of the lower pad part and to cover the upper electrode except for a part of the upper surface of the upper pad part. The light emitting element according to claim 5 , wherein the outermost layer of the side electrode and the upper electrode covered with the insulating film contains at least one of titanium, nickel, and aluminum. Said lower semiconductor layer, light emitting layer, and an upper semiconductor layer is made of nitride semiconductor, it claims 1-6, wherein the lower semiconductor layer and the upper semiconductor layer has an n-type and p-type conductivity, respectively 1 The light emitting element according to item.