JP5289241B2 - Wiring board and manufacturing method thereof - Google Patents

Description

  The present invention relates to a wiring board used for mounting electronic components such as semiconductor elements.

  Conventionally, a wiring board formed by a build-up method is known as a wiring board for mounting an electronic component such as a semiconductor element. FIG. 15 is a schematic cross-sectional view showing an example of a conventional wiring board for mounting a semiconductor element as an electronic component.

  As shown in FIG. 15, a conventional wiring board 100 has a plurality of build-up insulating layers 102 laminated on the upper and lower surfaces of a core insulating plate 101.

  A plurality of through holes 103 are formed from the upper surface to the lower surface of the core insulating plate 101, and a through hole conductor 104 made of a copper plating layer is attached to the inner surface of the through hole 103. A first conductor layer 105 made of copper foil connected to the through-hole conductor 104 is attached to the upper and lower surfaces of the insulating plate 101. Further, the through hole 103 is filled with an embedded resin 106, and a second conductor layer 107 made of a copper plating layer is deposited on the embedded resin 106 and the first conductor layer 105. The through-hole conductor 104, the first conductor layer 105, and the second conductor layer 107 form a core wiring conductor.

  A plurality of via holes 108 are formed in each of the build-up insulating layers 102, and a build-up wiring conductor 109 made of a copper plating layer is formed on the surface of each insulating layer 102 and the inner surface of the via hole 108. Is deposited. The build-up wiring conductor 109 is connected to the second conductor layer 107 in the core wiring conductor via the via hole 108. Further, a part of the build-up wiring conductor 109 deposited on the outermost insulating layer 102 on the upper surface side of the wiring substrate 100 is connected to the electrode terminal T of the electronic component E via the conductive bump B1. Circular electronic component connection pads 110 that are electrically connected are formed, and a plurality of these electronic component connection pads 110 are formed in a lattice pattern. In addition, a part of the lower surface side of the wiring board 120 that is deposited on the outermost insulating layer 102 is a circular external connection pad 111 that is electrically connected to the wiring conductor of the external electric circuit board. A plurality of connection pads 111 are formed in a grid.

  Further, a solder resist layer 112 that exposes the electronic component connection pads 110 and the external connection pads 111 is deposited on the outermost insulating layer 102 and the wiring conductor 109 thereon. Then, the electrode terminal T of the electronic component E is electrically connected to the exposed portion of the electronic component connection pad 110 via the conductive bump B1 made of solder, gold, or the like, and external electric power (not shown) is connected to the exposed portion of the external connection pad 111. The wiring conductor of the circuit board is electrically connected through the solder ball B2. The solder resist layer 112 protects the outermost wiring conductor 109 and defines exposed portions of the electronic component connection pads 110 and the external connection pads 111.

  A method for manufacturing such a conventional wiring board 100 will be described with reference to FIGS. First, as shown in FIG. 16A, the copper foil 105P for the first conductor layer 105 is laminated on the upper and lower surfaces of the resin substrate 101P for the insulating plate 101 made of an electrically insulating material such as glass-epoxy resin. A double-sided copper-clad plate 120 is prepared. The thickness of the resin substrate 101P is, for example, about 50 to 800 μm, and the thickness of the copper foil 105P is, for example, about 2 to 18 μm.

  Next, as shown in FIG. 16B, a through hole 103 is formed by drilling or laser processing from the upper surface to the lower surface of the double-sided copper-clad plate 120 to obtain the core insulating plate 101 having the through hole 103. The diameter of the through hole 103 is about 50 to 300 μm.

  Next, as shown in FIG. 17C, a through-hole conductor 104 formed by sequentially depositing an electroless copper plating layer and an electrolytic copper plating layer over the entire inner wall of the through hole 103 and the entire surface of the copper foil 105P. A copper plating layer 104P to be formed is formed. The thickness of the electroless copper plating layer constituting the copper plating layer 104P is about 0.1 to 1.0 μm, and the thickness of the electrolytic copper plating layer is about 5 to 30 μm.

  Next, as shown in FIG. 17D, a hole-filling resin 106 is filled into the through hole 103 to which the copper plating layer 104P is deposited.

  Next, as shown in FIG. 18 (e), the upper and lower ends and upper and lower copper plating layers 104 </ b> P of the hole filling resin 106, and the copper foil 105 </ b> P layer on the upper and lower surfaces of the insulating plate 101 with a thickness of about 2 to 8 μm. Polish and planarize so that it remains. At this time, the through-hole conductor 104 made of a copper plating layer remains in the through-hole 103 while being electrically connected to the copper foil 105P.

  Next, as shown in FIG. 18 (f), an electroless copper plating layer and an electrolytic copper plating layer are formed over the entire surface of the remaining copper foil 105P, the end face of the through-hole conductor 104, and the end face of the hole-filling resin 106. A copper plating layer 107P for the second conductor layer 107, which is sequentially deposited, is formed. The thickness of the electroless copper plating layer constituting the copper plating layer 107P is about 0.1 to 1.0 μm, and the thickness of the electrolytic copper plating layer is about 10 to 30 μm.

  Next, as shown in FIG. 19 (g), a copper plating is applied to the etching resist layer 121 having a predetermined pattern including a mask pattern for land formation covering the region corresponding to the periphery of the through hole 103 in the copper plating layer 107P. It is deposited on the surface of the layer 107P.

  Next, as shown in FIG. 19H, the copper plating layer 107P exposed from the etching resist layer 121 and the layer of the copper foil 105P thereunder are removed by etching. As a result, a wiring conductor having a shape corresponding to the etching resist layer 121 is formed.

  Next, as shown in FIG. 20I, the etching resist layer 121 is peeled off from the second conductor layer 107. As a result, a core wiring conductor composed of the through-hole conductor 104, the first conductor layer 105, and the second conductor layer 107 is formed.

  Next, as shown in FIG. 21J, a resin layer 102P for the insulating layer 102 is laminated on the upper and lower surfaces of the core insulating plate 101 on which the core wiring conductor is formed. The resin layer 102P is a resin-based electrical insulating material containing a thermosetting resin such as an epoxy resin and an inorganic insulating filler such as silica, and has a thickness of about 20 to 50 μm.

  Next, as shown in FIG. 21K, the insulating layer 102 is formed by drilling a via hole 108 having the second conductor layer 107 as a bottom by performing laser processing on the resin layer 102P.

  Next, as shown in FIG. 21L, a build-up wiring conductor 109 connected to the second conductor layer 107 is formed in the via hole 108 and on the surface of the insulating layer 102. The buildup wiring conductor 109 is formed by sequentially depositing an electroless plating layer and an electrolytic copper plating layer, and is formed using a known semi-additive method.

  Next, as shown in FIG. 21 (m), a predetermined number of next insulating layers 102 and wiring conductors 109 are formed as necessary, and finally, as shown in FIG. A solder resist layer 112 is deposited on the layer 102 and the wiring conductor 109 to complete the conventional wiring substrate 100.

  Recently, the electronic component E has been rapidly integrated, and a wiring board on which the electronic component E is mounted is required to have high-density fine wiring. In order to meet the demand for such high-density fine wiring, not only the build-up wiring conductor 109 to which the electronic component E is connected, but also the core wiring conductor has a width and interval of 30 μm or less. There is a growing demand to make things.

  However, in the above-described conventional wiring substrate 100, the pattern on the insulating plate 101 in the core wiring conductor has a thickness of 15 to 15 on the copper foil 105P having a thickness of about 2 to 18 μm laminated on the insulating plate 101. After the copper plating layer 107P of about 30 μm is deposited, the copper foil 105P and the copper plating layer 107P exposed from the etching resist layer 121 formed thereon are formed by a subtractive method by etching away to a predetermined pattern. Then, during etching, the copper foil 105P and the copper plating layer 107P are etched extremely greatly in the lateral direction according to the thickness thereof, so that the width and the adjacent interval are fine, for example, 30 μm or less on the upper and lower surfaces of the insulating plate 101. It has been difficult to form a core wiring conductor including a wiring pattern.

JP-A-11-274730

  An object of the present invention is to provide a wiring board having a high-density fine wiring with a width and interval of, for example, 30 μm or less not only in a build-up wiring conductor but also in a core wiring conductor in a wiring board on which a semiconductor element is mounted. It is to provide a substrate and a manufacturing method thereof.

  The wiring board of the present invention includes an insulating plate having a through-hole penetrating vertically, a through-hole conductor composed of a plated conductor mounted on an inner wall of the through-hole of the insulating plate, and the upper and lower surfaces of the insulating plate on the upper and lower surfaces. A first conductor layer including a through-hole land deposited so as to be electrically connected to the through-hole conductor; a hole-filling resin filled in the through-hole coated with the through-hole conductor; A first resin layer covering portions other than the first conductor layer on the upper and lower surfaces of the insulating plate at the same height as the first conductor layer; and the surfaces of the first conductor layer, the hole-filling resin, and the first resin layer And a second conductor layer formed by a semi-additive method.

  In the method for manufacturing a wiring board according to the present invention, a through-hole conductor made of a plating conductor is formed on an inner wall of the through-hole of an insulating plate having a through-hole penetrating vertically, and the through-hole conductor is formed on the upper and lower surfaces of the insulating plate. Forming a first conductor layer including a through-hole land electrically connected to the inner surface, filling the through-hole in which the through-hole conductor is deposited with a hole-filling resin, and on the upper and lower surfaces of the insulating plate A step of depositing a first resin layer having the same height as the first conductor layer on a portion other than the first conductor layer; and a semi-finished surface on the first conductor layer, the hole filling resin, and the first resin layer. And a step of forming a second conductor layer by an additive method.

  According to the wiring board and the manufacturing method thereof of the present invention, the portions other than the first conductor layer on the upper and lower surfaces of the insulating plate are covered with the first resin layer having the same height as the first conductor layer, and the surface of the first resin layer In addition, since the second conductor layer is formed by the semi-additive method, a fine wiring conductor for the core can be formed by the second conductor layer formed by the semi-additive method.

FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. 2A and 2B are schematic cross-sectional views for each step for explaining the method for manufacturing the wiring board shown in FIG. 3C and 3D are schematic cross-sectional views for each process for explaining the method of manufacturing the wiring board shown in FIG. 4E and 4F are schematic cross-sectional views for each process for explaining the method of manufacturing the wiring board shown in FIG. FIGS. 5G and 5H are schematic cross-sectional views for each process for explaining the method for manufacturing the wiring board shown in FIG. FIGS. 6 (i) and 6 (j) are schematic cross-sectional views for each process for explaining the method for manufacturing the wiring board shown in FIG. 1. FIGS. 7K and 7L are schematic cross-sectional views for each process for explaining the method for manufacturing the wiring board shown in FIG. 8 (m) and 8 (n) are schematic cross-sectional views for each step for explaining the method of manufacturing the wiring board shown in FIG. FIG. 9O is a schematic cross-sectional view for each step for explaining the method for manufacturing the wiring board shown in FIG. 10 (p) to 10 (t) are schematic cross-sectional views for each process for explaining the method of manufacturing the wiring board shown in FIG. FIG. 11 is a schematic cross-sectional view showing another example of the embodiment of the wiring board of the present invention. 12A and 12B are schematic cross-sectional views for each step for explaining another example in the method for manufacturing a wiring board of the present invention. 13C and 13D are schematic cross-sectional views for each process for explaining another example in the method for manufacturing a wiring board of the present invention. 14E and 14F are schematic cross-sectional views for each process for explaining another example in the method for manufacturing a wiring board of the present invention. FIG. 15 is a schematic cross-sectional view showing a conventional wiring board. 16 (a) and 16 (b) are schematic cross-sectional views for explaining a conventional manufacturing method for manufacturing the wiring board shown in FIG. 17C and 17D are schematic cross-sectional views for explaining a conventional manufacturing method for manufacturing the wiring board shown in FIG. 18E and 18F are schematic cross-sectional views for explaining a conventional manufacturing method for manufacturing the wiring board shown in FIG. 19G and 19H are schematic cross-sectional views for explaining a conventional manufacturing method for manufacturing the wiring board shown in FIG. FIG. 20I is a schematic cross-sectional view for explaining a conventional manufacturing method for manufacturing the wiring board shown in FIG. FIGS. 21J to 21N are schematic cross-sectional views for explaining a conventional manufacturing method for manufacturing the wiring board shown in FIG.

Hereinafter, a wiring board and a manufacturing method thereof according to the present invention will be described in detail with reference to the drawings.
FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention, and shows a case where an area array type semiconductor element as an electronic component is mounted by flip-chip connection.

  As shown in FIG. 1, the wiring substrate 20 of this example has a plurality of build-up insulating layers 2 stacked on the upper and lower surfaces of a core insulating plate 1.

  The core insulating plate 1 has a thickness of about 50 to 800 μm, and is made of, for example, an electrically insulating material in which a glass cloth in which glass fiber bundles are woven vertically and horizontally is impregnated with a thermosetting resin such as bismaleimide triazine resin or epoxy resin. Become.

  A plurality of through holes 3 having a diameter of 50 to 300 μm are formed from the upper surface to the lower surface of the core insulating plate 1, and a through hole conductor 4 made of a copper plating layer is attached to the inner surface of the through hole 3. Yes. Further, a first conductor layer 5 forming a through-hole land 5A connected to the through-hole conductor 4 is deposited on the upper and lower surfaces of the insulating plate 1. The first conductor layer 5 is formed of the same copper plating layer as the through-hole conductor 4 and is formed by the semi-additive method simultaneously with the through-hole conductor 4. The diameter of the through hole land 5 </ b> A is about 70 to 150 μm larger than the diameter of the through hole 3.

  Furthermore, the inside of the through hole 3 is filled with a hole-filling resin 6 made of a thermosetting resin such as an epoxy resin, and portions other than the first conductor layer 5 on the upper and lower surfaces of the insulating plate 1 are defined as first conductor layers. A first resin layer 7 made of a thermosetting resin such as an epoxy resin covering at the same height is applied. If the hole-filling resin 6 and the first resin layer 7 are formed of the same resin material, filling the hole-filling resin 6 and depositing the first resin layer 7 can be performed simultaneously as will be described later. . Therefore, it is preferable to form the hole filling resin 6 and the first resin layer 7 from the same resin material. The first resin layer 7 functions as a base insulating layer for forming a second conductor layer 8 described later on the upper and lower surfaces of the insulating plate 1 in a fine pattern, and the second conductor layer 8 having a fine pattern is formed on the surface thereof. In order to enable the formation, the 10-point average roughness Rz of the surface is 0.1 to 5.0 μm. By covering the portions other than the first conductor layer 5 on the upper and lower surfaces of the insulating plate 1 with such a first resin layer 7, the insulating plate 1 other than the portion where the first conductor layer 5 is formed. The second conductor layer 8 having a fine pattern can be formed on the upper and lower surfaces of the first conductor layer 7 via the first resin layer 7.

  Then, on the surface of the through-hole land 5A, the hole-filling resin 6 and the first resin layer 7, the second conductor layer 8 made of a copper plating layer having a thickness of about 15 to 30 μm has a width and an interval by a semi-additive method to be described later. It is formed so as to have a fine pattern of 30 μm or less. Since the second conductor layer 8 is formed by a semi-additive method, it is possible to form a fine pattern with a width and interval of 30 μm or less on both surfaces of the insulating substrate 1. Therefore, it is possible to provide a wiring board having high-density fine wiring in which the wiring width and interval in the core wiring conductor are 30 μm or less. In this example, the second conductor layer 8 is formed so as to cover all the through-hole lands 5A, but a part of the through-hole lands 5A may exist without being covered with the second conductor layer 8. Absent.

  The build-up insulating layer 2 has a thickness of about 20 to 50 μm, and a plurality of via holes 9 each having a diameter of about 35 to 100 μm are formed on the surface of each insulating layer 2 and the inner surface of the via hole 9. A wiring conductor 10 for build-up is deposited. The buildup wiring conductor 10 is connected to the second conductor layer 8 through a part of the via hole 9. Further, a part of the build-up wiring conductor 10 deposited on the outermost insulating layer 2 on the upper surface side of the wiring substrate 20 is connected to the electrode terminal T of the electronic component E via the conductive bump B1. Circular semiconductor element connection pads 11 that are electrically connected by flip-chip connection are formed, and a plurality of these electronic component connection pads 11 are formed in a lattice pattern. These electronic component connection pads 11 are covered with a solder resist layer 12 at the outer peripheral portion thereof, and the central portion of the upper surface is exposed from the solder resist layer 12. The electrode terminal T of E is electrically connected through a conductive bump B1 made of solder, gold or the like.

  On the other hand, a part deposited on the outermost insulating layer 2 on the lower surface side of the wiring board 20 is a circular external connection pad 13 electrically connected to the wiring conductor of the external electric circuit board. A plurality of connection pads 13 are formed in a lattice pattern. The external connection pad 13 is covered with a solder resist layer 12 at the outer periphery thereof, and the central portion of the lower surface is exposed from the solder resist layer 12, and an external electric circuit (not shown) is exposed on the exposed portion of the external connection pad 13. The wiring conductor of the board is electrically connected via the solder ball B2. The solder resist layer 13 protects the outermost wiring conductor 10 and defines exposed portions of the electronic component connection pads 11 and the external connection pads 13.

  Next, the manufacturing method which manufactures an example of the wiring board mentioned above is demonstrated based on FIGS. First, as shown in FIG. 2A, a copper foil 5P is laminated on the upper and lower surfaces of a resin substrate 1P for an insulating plate 1 made of an electrically insulating material such as glass-epoxy resin or glass-bismaleimide triazine resin. A double-sided copper-clad plate 30 is prepared. The thickness of the resin substrate 1P is, for example, about 50 to 800 μm, and the thickness of the copper foil 5P is, for example, about 2 to 18 μm. Further, the surface of the copper foil 5P that is in close contact with the resin substrate 1P is a rough surface having a ten-point average height Rz of 0.1 to 7.0 μm. As such a double-sided copper-clad board 30, what is generally sold for printed wiring board applications may be used.

  Next, as shown in FIG. 2B, the copper foil 5P laminated on the upper and lower surfaces of the double-sided copper-clad plate 30 is removed by etching. An etching solution containing cupric chloride, ferric chloride, or the like may be used for etching the copper foil 5P. At this time, the surface of the insulating plate 1 has irregularities with a 10-point average height Rz of 0.1 to 7.0 μm corresponding to the rough surface of the copper foil 5P. This unevenness functions as an anchor that strengthens the adhesion between the insulating plate 1 and the first conductor layer 5 when the first conductor layer 5 described later is formed.

  Next, as shown in FIG. 3C, the insulating plate 1 is formed by forming the through hole 3 by drilling or laser processing from the upper surface to the lower surface of the resin substrate 1P. The diameter of the through hole 3 is about 50 to 300 μm. After forming the through hole 3, it is preferable to desmear the inner wall of the through hole 3 with an aqueous solution containing potassium permanganate or sodium permanganate.

  Next, as shown in FIG. 3 (d), an electroless copper plating layer 4 a is deposited over the entire inner wall of the through hole 3 and the entire upper and lower surfaces of the insulating plate 1. The electroless copper plating layer 4a has a thickness of about 0.1 to 1.0 μm and is deposited by using a known electroless plating solution.

  Next, as shown in FIG. 4E, an electroless copper plating resist layer 31 having a circular opening pattern exposing the upper and lower surfaces corresponding to the inside and the periphery of the through hole 3 in the electroless copper plating layer 4a is formed. It is deposited on the surface of the plating layer 4a. The plating resist layer 31 is formed by sticking a dry film resist made of a photosensitive resin on the electroless copper plating layer 4a and exposing and developing the predetermined pattern.

  Next, as shown in FIG. 4 (f), an electrolytic copper plating layer 4 b is deposited on the electroless copper plating layer 4 a exposed from the plating resist layer 31. The electrolytic copper plating layer 4b has a thickness of about 15 to 30 μm and is deposited by using a known electrolytic plating solution.

  Next, as shown in FIG. 5G, the plating resist layer 31 is peeled off from the second electroless copper plating layer 4a. An alkaline stripping solution may be used for stripping the plating resist layer 30.

  Next, as shown in FIG. 5 (h), the electroless copper plating layer 4a exposed on the insulating plate 1 is removed by etching, and a through-hole conductor composed of the remaining electroless copper plating layer 4a and electrolytic copper plating layer 4b. 4 and the first conductor layer 5 are formed. In this example, only the through-hole land 5A is formed as the first conductor layer 5, but the first conductor layer 5 may include a pattern other than the through-hole land 5A. Note that a known etching solution containing hydrogen peroxide, sodium persulfate, or the like may be used for etching.

  Next, as shown in FIG. 6 (i), the resin 6 </ b> P is filled in the through-hole 3 to which the through-hole conductor 4 is deposited, and at the same time, the first conductor layer 5 is covered on the upper and lower surfaces of the insulating plate 1. Resin 6P is applied. The resin 6P is made of a resin-based insulating material in which an inorganic insulating filler such as silica is dispersed in a thermosetting resin such as an epoxy resin, and the inorganic insulating filler such as silica is dispersed in a thermosetting resin composition such as an epoxy resin. The resin paste formed is printed from the upper and lower surfaces of the insulating plate 1 by a screen printing method and thermally cured. Alternatively, the resin 6P is formed by sticking and pressing a resin film obtained by dispersing an inorganic insulating filler such as silica in a thermosetting resin composition such as an epoxy resin on the upper and lower surfaces of the insulating plate 1 and thermosetting it. It is attached by.

  Next, as shown in FIG. 6 (j), the resin 6P and the first conductor layer 5 deposited on the upper and lower surfaces of the insulating plate 1 are formed so that the first conductor layer 5 has a thickness of 5 to 15 μm. Polish and planarize so as to remain on the upper and lower surfaces. Thereby, the hole filling resin 4 is formed in the through hole 3 and the first resin layer 7 having the same height as the first conductor layer 5 is formed on the upper and lower surfaces of the insulating plate 1 other than the first conductor layer 5. The The first resin layer 7 is a base layer for forming the fine second conductor layer 8 on the upper and lower surfaces of the insulating plate 1, so that a fine conductor pattern having a width and interval of 30 μm or less can be formed. It is preferable to finely roughen so that the ten-point average height Rz is in the range of 0.1 to 5.0 μm. For the roughening of the first resin layer 7, an aqueous solution containing potassium permanganate, sodium permanganate or the like is used.

  Next, as shown in FIG. 7 (k), electroless copper is formed on the surface of the first resin layer 7, the surface of the first conductor layer 5 and the surface of the hole-filling resin 6 deposited on the upper and lower surfaces of the insulating plate 1. The plating layer 8a is deposited. The electroless copper plating layer 8a has a thickness of about 0.1 to 1.0 μm and is deposited by using a known electroless plating solution.

  Next, as shown in FIG. 7L, a plating resist layer 32 having an opening pattern having a shape corresponding to the second conductor layer 8 is deposited on the surfaces of the upper and lower electroless copper plating layers 8a. The plating resist layer 32 may be deposited by the same method as the plating resist layer 31 described above.

  Next, as shown in FIG. 8 (m), the electrolytic copper plating layer 8 b is deposited on the electroless copper plating layer 8 a exposed from the plating resist layer 32. The electrolytic copper plating layer 8b has a thickness of about 15 to 30 μm and is deposited by using a known electrolytic plating solution.

  Next, as shown in FIG. 8 (n), the plating resist layer 32 is peeled off from the electroless copper plating layer 8a. An alkaline stripping solution may be used for stripping the plating resist layer 32.

  Next, as shown in FIG. 9 (o), the electroless copper plating layer 8a exposed on the first resin layer 7 is removed by etching, and the remaining electroless copper plating layer 8a and electrolytic copper plating layer 8b are formed. Two conductor layers 8 are formed. Thus, the formation method of the 2nd conductor layer 8 is a method called what is called a semi-additive method, and should just etch only the thickness of the electroless copper plating layer 8a in the case of the etching for forming the 2nd conductor layer 8. Therefore, the electrolytic copper plating layer 8b is not greatly etched in the lateral direction. Further, the surface of the first resin layer 7 is a fine roughened surface having a ten-point average height Rz of about 0.1 to 5.0 μm, and therefore, a fine wiring pattern having a width and interval of 30 μm or less is provided in the first resin layer 7. It can be formed satisfactorily while ensuring sufficient adhesion with the resin layer 7. Accordingly, the second conductor layer 8 formed on the first resin layer 7 deposited on the core insulating plate 1 allows the width and interval of the wirings to be 30 μm or less above and below the core insulating plate 1. It is possible to form a wiring conductor for a core with high density. In addition, when the thickness of the electroless copper plating layer 8a is less than 0.1 μm, it is difficult to satisfactorily deposit the electrolytic copper plating layer 8b on the surface of the electroless copper plating layer 8a, and the thickness exceeds 1.0 μm. In addition, when the exposed portion of the electroless copper plating layer 8a is removed by etching, the amount of the electrolytic copper plating layer 8b that is etched in the lateral direction increases, and fine wiring having a width and interval of 30 μm or less can be satisfactorily formed. It tends to be difficult. Therefore, the thickness of the electroless copper plating layer 8a is preferably 0.1 to 1.0 μm. Note that a known etching solution containing hydrogen peroxide, sodium persulfate, or the like may be used for etching.

  Next, as shown in FIG. 10 (p), the resin layer 2 </ b> P for the insulating layer 2 is laminated on the first resin layer 7 and the second conductor layer 8. The resin layer 2P is a resin-based electrical insulating material containing a thermosetting resin such as an epoxy resin and an inorganic insulating filler such as silica, and has a thickness of about 20 to 50 μm. Such a resin layer 2P includes, for example, an uncured resin sheet containing a thermosetting resin composition such as an epoxy resin and an inorganic insulating filler such as silica on the first resin layer 7 and the second conductor layer 8. It is formed by sticking and thermosetting. The resin layer 2P may contain glass cloth.

  Next, as shown in FIG. 10 (q), the insulating layer 2 is formed by drilling a via hole 9 having the second conductor layer 8 as a bottom by applying laser processing to the resin layer 2P. The diameter of the via hole 9 is about 35 to 100 μm. Some of the via holes 9 have a bottom portion at the center of the second conductor layer 8 deposited on the hole-filling resin 6.

  Next, as shown in FIG. 10 (r), a build-up wiring conductor 10 connected to the second conductor layer 8 is formed in the via hole 9 and on the surface of the insulating layer 2. The wiring conductor 10 is formed by sequentially depositing an electroless copper plating layer having a thickness of about 0.1 to 1.0 μm and an electrolytic copper plating layer having a thickness of about 10 to 20 μm, and is formed using a semi-additive method. Good.

  Next, as shown in FIG. 10 (s), the next insulating layer 2 and the wiring conductor 10 are formed in a predetermined number of layers as required. Finally, as shown in FIG. 10 (t), the outermost insulating layer is formed. A solder resist layer 12 is deposited on the layer 2 and the wiring conductor 10 to complete the wiring board 20 according to the present invention. The solder resist layer 12 is a resin-based electrical insulating material containing a photosensitive thermosetting resin such as an acrylic-modified epoxy resin and an inorganic insulating filler such as silica, and has a thickness of about 10 to 25 μm. Such a solder resist layer 12 is composed of, for example, an uncured photosensitive resin sheet or resin paste containing a thermosetting resin composition such as an acrylic-modified epoxy resin and an inorganic insulating filler such as silica, and the outermost insulating layer 2. Further, it is formed by depositing on the wiring conductor 10 and exposing and developing to a predetermined pattern, followed by thermosetting.

  Thus, according to the method for manufacturing a wiring board of the present invention, it is possible to provide the wiring board 20 having high-density fine wiring in which the wiring width and interval in the core wiring conductor are 30 μm or less. The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention. For example, in one example of the above-described embodiment, the insulating plate 1 Although an example in which only the through hole land 5A is formed by the first conductor layer 5 deposited on the upper and lower surfaces of the first conductor layer 5 is shown, as shown in FIG. 11, the first conductor layer 5 is used for grounding in addition to the through hole land 5A. Alternatively, the wiring pattern 5B for power supply may be included. In this case, the grounding or power supply wiring pattern 5B, which does not require a relatively fine wiring, is directly formed on the surface of the insulating plate 1 in a wide pattern, and the second conductor layer 8 is further stacked thereon. Thus, it is possible to provide a wiring board having good electrical characteristics by reducing the inductance in the grounding or power supply wiring pattern.

  Furthermore, in the manufacturing method in the example of the above-described embodiment, the copper foils 5P laminated on the upper and lower surfaces of the double-sided copper-clad plate 30 are all removed by etching, and the electroless copper plating layer 4a and the electrolysis are formed on the upper and lower surfaces of the exposed insulating plate 1. Although the first conductor layer 5 made of the copper plating layer 4a is formed, the copper foil 5P laminated on the upper and lower surfaces of the double-sided copper-clad plate 30 is patterned on the upper and lower surfaces of the insulating plate 1 by the subtractive method, for example. The first conductor layer 5 may be formed by leaving at least a part of the first conductor layer 5.

  In this case, first, as shown in FIG. 12A, the resin for the insulating plate 1 made of an electrical insulating material such as glass-epoxy resin or glass-bismaleimide triazine resin, as in the above-described example of the embodiment. A double-sided copper-clad plate 30 is prepared in which copper foils 5P for the first conductor layer 5 are laminated on the upper and lower surfaces of the substrate 1P. In addition, when the copper foil 5P is thicker than 5 μm, it is preferable to reduce the thickness to 5 μm or less by polishing or etching. Thus, by setting the thickness of the upper and lower copper foils 5P in the double-sided copper-clad plate 30 to 5 μm or less, the formation of the through hole 3 is facilitated in the step of forming the through hole 3 to be described later.

    Next, as shown in FIG. 12B, the through hole 3 is formed by drilling or laser processing from the upper surface to the lower surface of the double-sided copper-clad plate 30. The diameter of the through hole 3 is about 50 to 300 μm. After forming the through hole 3, it is preferable to desmear the inner wall of the through hole 3 with an aqueous solution containing potassium permanganate or sodium permanganate.

  Next, as shown in FIG. 13 (c), an electroless copper plating layer 4a and an electrolytic copper plating layer 4b are sequentially deposited over the entire inner wall of the through hole 3 and the entire surface of the copper foil 5P, thereby plating the conductive layer 4P. Form. The thickness of the electroless copper plating layer 4a is about 0.1 to 1.0 μm, and the thickness of the electrolytic copper plating layer 4b is about 15 to 30 μm. A known plating solution may be used as a plating solution for performing these platings.

  Next, as shown in FIG. 13 (d), an etching resist layer 33 having a predetermined pattern for forming the through-hole land 5A covering the through-hole 3 on the plated conductor layer 4P and the region corresponding to the periphery thereof is applied to the plated conductor. It is deposited on the surface of the layer 4P. The etching resist layer 33 is formed by sticking a dry film resist made of a photosensitive resin on the plated conductor layer 4P and exposing and developing the predetermined pattern.

  Next, as shown in FIG. 14 (e), the plating conductor layer 4P and the copper foil 5P that are exposed from the etching resist layer 33 are etched away by a subtractive method. For etching the plated conductor layer 4P and the copper foil 5P, an etching solution containing cupric chloride or ferric chloride may be used. At this time, in this example, only the plated conductor layer 4P and the copper foil 5P deposited on the portions corresponding to the inner wall of the through hole 3 and the through hole land 5A remain.

  Next, as shown in FIG. 14F, the etching resist 33 is removed. The etching resist layer 33 may be removed by stripping using an alkaline resist stripper.

  Hereinafter, the same steps as those described with reference to FIGS. 6I to 10T in the example of the embodiment described above may be performed.

DESCRIPTION OF SYMBOLS 1 Insulating board for cores 2 Insulating layer for buildup 3 Through hole 4 Through hole conductor 5 1st conductor layer 5A Through hole land 6 Filling resin 7 1st resin layer 8 2nd conductor layer

Claims (6)

  An insulating plate having a through-hole penetrating vertically, a through-hole conductor made of a plated conductor mounted on the inner wall of the through-hole of the insulating plate, and the through-hole conductor electrically on the upper and lower surfaces of the insulating plate A first conductor layer including a through-hole land deposited so as to be connected; a hole-filling resin filled in the through-hole coated with the through-hole conductor; and the upper and lower surfaces of the insulating plate A first resin layer that covers a portion other than the first conductor layer at the same height as the first conductor layer, and is formed on the surface of the first conductor layer, the hole-filling resin, and the first resin layer by a semi-additive method. And a second conductor layer.   2. The wiring board according to claim 1, wherein the first conductor layer includes a grounding or power supply conductor layer electrically connected to the through-hole land.   The wiring board according to claim 1, wherein the hole-filling resin and the first resin layer are formed of the same resin material.   A through-hole conductor made of a plating conductor is formed on the inner wall of the through-hole of the insulating plate having a through-hole penetrating vertically, and through-hole lands electrically connected to the through-hole conductor are formed on the upper and lower surfaces of the insulating plate. Forming a first conductor layer including the first conductor layer, filling the through hole in which the through hole conductor is deposited with a hole-filling resin, and forming the first conductor layer on portions of the upper and lower surfaces of the insulating plate other than the first conductor layer. A step of depositing a first resin layer having the same height as one conductor layer, and a step of forming a second conductor layer on the surface of the first conductor layer, the hole-filling resin and the first resin layer by a semi-additive method A method for manufacturing a wiring board, comprising:   5. The method of manufacturing a wiring board according to claim 4, wherein a grounding or power supply conductor layer electrically connected to the through hole land is formed on the first conductor layer together with the through hole land.   6. The method for manufacturing a wiring board according to claim 4, wherein the hole-filling resin and the first resin layer are formed of the same resin material.

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