JP5088376B2 - Circuit member connecting adhesive and semiconductor device - Google Patents

Circuit member connecting adhesive and semiconductor device Download PDF

Info

Publication number
JP5088376B2
JP5088376B2 JP2009543887A JP2009543887A JP5088376B2 JP 5088376 B2 JP5088376 B2 JP 5088376B2 JP 2009543887 A JP2009543887 A JP 2009543887A JP 2009543887 A JP2009543887 A JP 2009543887A JP 5088376 B2 JP5088376 B2 JP 5088376B2
Authority
JP
Japan
Prior art keywords
adhesive
resin
circuit member
circuit
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2009543887A
Other languages
Japanese (ja)
Other versions
JPWO2009069783A1 (en
Inventor
朗 永井
泰典 川端
茂樹 加藤木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Showa Denko Materials Co Ltd
Resonac Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd, Showa Denko Materials Co Ltd, Resonac Corp filed Critical Hitachi Chemical Co Ltd
Priority to JP2009543887A priority Critical patent/JP5088376B2/en
Publication of JPWO2009069783A1 publication Critical patent/JPWO2009069783A1/en
Application granted granted Critical
Publication of JP5088376B2 publication Critical patent/JP5088376B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J11/00—Features of adhesives not provided for in group C09J9/00, e.g. additives
    • C09J11/02—Non-macromolecular additives
    • C09J11/04—Non-macromolecular additives inorganic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08K—Use of inorganic or non-macromolecular organic substances as compounding ingredients
    • C08K3/00—Use of inorganic substances as compounding ingredients
    • C08K3/18—Oxygen-containing compounds, e.g. metal carbonyls
    • C08K3/20—Oxides; Hydroxides
    • C08K3/22—Oxides; Hydroxides of metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29399—Coating material
    • H01L2224/294—Coating material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81208—Compression bonding applying unidirectional static pressure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83885—Combinations of two or more hardening methods provided for in at least two different groups from H01L2224/83855 - H01L2224/8388, e.g. for hybrid thermoplastic-thermosetting adhesives
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01011—Sodium [Na]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01041—Niobium [Nb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01045—Rhodium [Rh]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01056—Barium [Ba]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Organic Chemistry (AREA)
  • Adhesives Or Adhesive Processes (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

本発明は、回路部材接続用接着剤及びこれを用いた半導体装置に関する。   The present invention relates to an adhesive for connecting circuit members and a semiconductor device using the same.

半導体チップをフェイスダウンボンディング方式により直接回路基板に実装する方式として、半導体チップの電極部分にはんだバンプを形成し回路基板にはんだ接続する方式や、半導体チップに設けた突起電極に導電性接着剤を塗布し回路基板電極に電気的接続を行う方法が知られている。これらの方式では、各種環境下に曝した場合、接続するチップと基板の熱膨張係数差に基づくストレスが接続界面で発生するため接続信頼性が低下するという問題がある。   As a method of mounting a semiconductor chip directly on a circuit board by a face-down bonding method, a solder bump is formed on the electrode part of the semiconductor chip and soldered to the circuit board, or a conductive adhesive is applied to the protruding electrode provided on the semiconductor chip. A method of applying and electrically connecting to circuit board electrodes is known. In these systems, when exposed to various environments, there is a problem that connection reliability is lowered because stress based on the difference in thermal expansion coefficient between the chip to be connected and the substrate is generated at the connection interface.

このため、接続界面のストレスを緩和する目的でチップと基板の間隙をエポキシ樹脂等のアンダーフィル材で充填する方式が検討されている。アンダーフィル材の充填方式としてはチップと基板を接続した後に低粘度の液状樹脂を注入する方式と、基板上にアンダーフィル材を置いた後にチップを搭載する方式とがある。あらかじめアンダーフィル材を基板に設置した後にチップを搭載する方法としては液状樹脂を塗布する方法とフィルム状樹脂を貼付ける方法とがある。   For this reason, a method of filling the gap between the chip and the substrate with an underfill material such as an epoxy resin has been studied for the purpose of reducing the stress at the connection interface. The underfill material filling method includes a method of injecting a low-viscosity liquid resin after connecting the chip and the substrate, and a method of mounting the chip after placing the underfill material on the substrate. As a method of mounting a chip after an underfill material is previously installed on a substrate, there are a method of applying a liquid resin and a method of attaching a film-like resin.

しかしながら、液状樹脂の塗布においてはディスペンサーによる精密な塗布量コントロールが困難であり、近年のチップ薄型化において、多すぎる塗布によってボンディング時にしみ出した樹脂がチップの側面を這い上がり、ボンディングツールを汚染するため、ツールの洗浄が必要となり、量産時の工程が煩雑になる原因となっている。   However, in the application of liquid resin, it is difficult to precisely control the application amount with a dispenser, and in recent years of chip thinning, the resin exuded during bonding due to too much application creeps up the side of the chip and contaminates the bonding tool. Therefore, it is necessary to clean the tool, which causes a complicated process during mass production.

一方、フィルム状樹脂の場合、フィルムの厚みをコントロールすることによって樹脂量の最適化が容易となる反面、フィルムを基板に貼付ける際、仮圧着工程と呼ばれるフィルムの貼付工程が必要となる。この場合、実装時のチップと基板の位置ずれを補正するために基板に貼付けられるフィルムはチップサイズより大きくすることが一般的であり、高密度化実装の妨げとなることが課題であった。この課題を解決するため、チップサイズと同サイズの接着剤を供給する方法として、チップに個片化する前のウェハ状態で接着剤を供給した後、ダイシング等によってチップ加工と同時に接着剤の加工を行い、接着剤付きのチップを得る方法が提案されている（特許文献１、２参照）。
特許第２８３３１１１号公報 特開２００６−４９４８２号公報 On the other hand, in the case of a film-like resin, it is easy to optimize the amount of resin by controlling the thickness of the film. However, when the film is attached to the substrate, a film attaching step called a temporary press-bonding step is required. In this case, in order to correct the positional deviation between the chip and the substrate at the time of mounting, the film attached to the substrate is generally larger than the chip size, which has been a problem that hinders high-density mounting. In order to solve this problem, as a method of supplying an adhesive having the same size as the chip size, after supplying the adhesive in a wafer state before being singulated into chips, the adhesive is processed simultaneously with chip processing by dicing or the like. And a method for obtaining a chip with an adhesive has been proposed (see Patent Documents 1 and 2).
Japanese Patent No. 2833111 JP 2006-49482 A

しかしながら、従来提案されてきたウェハ先置き型のアンダーフィル方法（チップに個片化する前にウェハにアンダーフィル剤を供給する加工方法をいう。）は下記のような問題があり、市場において一般化されていない。   However, the previously proposed wafer-first underfill method (which is a processing method for supplying an underfill agent to a wafer before it is divided into chips) has the following problems and is generally used in the market. It has not been converted.

特許文献１の方法は、ウェハにフィルム状接着剤を貼付けた後にダイシングで個片化して接着フィルム付のチップを得る方法である。本方法では、ウェハ／接着剤／セパレータの積層体を作製し、これを切断後、セパレータをはく離して接着剤付きのチップを得るが、積層体を切断する際に接着剤とセパレータとが剥離する場合があり、個片化された半導体チップが飛散、流出することが懸念される。   The method of Patent Document 1 is a method of obtaining a chip with an adhesive film by pasting a film adhesive on a wafer and then dicing it into pieces. In this method, a wafer / adhesive / separator laminate is prepared, and after cutting this, the separator is peeled off to obtain a chip with an adhesive. When the laminate is cut, the adhesive and the separator are peeled off. In some cases, there is a concern that the separated semiconductor chips may scatter and flow out.

特許文献２は粘着材層と接着剤層を有するウェハ加工用テープに関する方法に関し、ウェハをウェハ加工用テープに貼付けた後にダイシング、ピックアップを行い、個片化されたチップを基板にフリップチップ接続する方法が開示されている。一般にフリップチップ実装ではチップ回路面のバンプと呼ばれる端子と、相対する基板側の端子とを接続するため、チップ側のアライメントマーク（位置合わせマーク）と基板側のアライメントマークとをフリップチップボンダーで位置合わせし、貼付ける。しかしながら、チップの回路面に接着剤を貼付けた場合には接着剤が回路面のアライメントマークを覆ってしまうため、接着剤を透過してアライメントマークを認識する必要がある。これに対して特許文献２ではこの問題に対する解決策は提供していない。   Patent Document 2 relates to a method related to a wafer processing tape having an adhesive layer and an adhesive layer, and after dicing and picking up the wafer after pasting the wafer on the wafer processing tape, flip-chip connection of the separated chips to the substrate is performed. A method is disclosed. In general, in flip-chip mounting, terminals called bumps on the chip circuit surface are connected to opposite board-side terminals, so the chip-side alignment mark (alignment mark) and board-side alignment mark are positioned using a flip-chip bonder. Match and paste. However, when an adhesive is applied to the circuit surface of the chip, the adhesive covers the alignment mark on the circuit surface, so that it is necessary to permeate the adhesive and recognize the alignment mark. On the other hand, Patent Document 2 does not provide a solution to this problem.

本発明の目的は、半導体チップと基板との接続信頼性に優れると共に、半導体チップと基板の位置合わせに用いられるアライメントマークの認識性を実用上十分なレベルまで向上させた回路部材接続用接着剤を提供することにある。本発明の目的はまた、この回路部材接続用接着剤を用いた半導体装置を提供することにある。   SUMMARY OF THE INVENTION An object of the present invention is to provide an adhesive for connecting a circuit member that has excellent connection reliability between a semiconductor chip and a substrate, and has improved recognition of an alignment mark used for alignment of the semiconductor chip and the substrate to a practically sufficient level. Is to provide. Another object of the present invention is to provide a semiconductor device using the adhesive for connecting circuit members.

本発明は、相対向する回路基板を接続するための回路部材接続用接着剤であって、熱可塑性樹脂、熱硬化性樹脂及び硬化剤を含む樹脂組成物と、該組成物中に分散された金属水酸化物粒子とからなる、回路部材接続用接着剤を提供する。なお、「相対向する回路基板の接続」には、電気的な接続及び／又は回路基板の固定が含まれる。   The present invention is an adhesive for connecting circuit members for connecting opposite circuit boards, a resin composition containing a thermoplastic resin, a thermosetting resin and a curing agent, and dispersed in the composition An adhesive for connecting circuit members, comprising metal hydroxide particles. It should be noted that “connection of circuit boards facing each other” includes electrical connection and / or fixing of the circuit board.

本発明の回路部材接続用接着剤は、半導体チップと基板との間の優れた接続信頼性と、アライメントマークの認識を可能にする高い光透過性という、従来両立が不可能と言われてきた特性を実現するものである。   The adhesive for connecting circuit members according to the present invention has been said to be impossible in the past: excellent connection reliability between a semiconductor chip and a substrate and high light transmission that enables recognition of alignment marks. It realizes the characteristics.

接続信頼性としては、チップと基板の熱膨張係数差に基づいて発生する応力に対応する高接着化、リフロー温度に対応するための高耐熱性、高温環境化に対応するための低熱膨張性、高温高湿環境下に対応するための低吸湿性等が要求されている。これらの特性向上させるため、高耐熱性と高接着性を達成することが可能なエポキシ樹脂に、線膨張係数の小さいシリカフィラーを添加することが考えられるが、このような系では。シリカフィラーとエポキシ樹脂の界面での散乱等に基づいて透明性を得ることはできない。   As connection reliability, high adhesion corresponding to stress generated based on the difference in thermal expansion coefficient between chip and substrate, high heat resistance to cope with reflow temperature, low thermal expansion to cope with high temperature environment, There is a demand for low hygroscopicity to cope with high temperature and high humidity environment. In order to improve these properties, it is conceivable to add a silica filler having a low coefficient of linear expansion to an epoxy resin capable of achieving high heat resistance and high adhesion, but in such a system. Transparency cannot be obtained based on scattering at the interface between the silica filler and the epoxy resin.

一方、透明ガラス粒子を添加することで透明性を確保することが考えられるが（例えば、特許第３４０８３０１号公報）、ガラス粒子が透明な場合でも、ガラス粒子を分散させる樹脂との屈折率差や界面の密着性不良等に基づいて透明性が損なわれる場合があり、ガラス粒子の脆弱性や熱膨張係数差に基づいて、接続信頼性が得られないことも多い。   On the other hand, it is conceivable to ensure transparency by adding transparent glass particles (for example, Japanese Patent No. 3408301), but even when the glass particles are transparent, the difference in refractive index from the resin that disperses the glass particles or Transparency may be impaired based on poor adhesion at the interface, etc., and connection reliability is often not obtained based on the fragility of glass particles and the difference in thermal expansion coefficient.

このような状況に対し、本発明の回路部材接続用接着剤では、基材を熱可塑性樹脂、熱硬化性樹脂及び硬化剤で構成させたこと、またこの基材に金属水酸化物粒子を添加させて分散させたことで、優れた接続信頼性と高い光透過性の両立を可能としている。   For such a situation, in the adhesive for connecting circuit members of the present invention, the base material is composed of a thermoplastic resin, a thermosetting resin, and a curing agent, and metal hydroxide particles are added to the base material. Thus, it is possible to achieve both excellent connection reliability and high light transmittance.

本発明の回路部材接続用接着剤は、未硬化時の可視光並行透過率が、１５〜１００％であることが好ましい。可視光並行透過率をこの範囲内とすることで、フリップチップボンダーでのアライメントマークの認識が更に容易となる。   The adhesive for connecting circuit members of the present invention preferably has a visible light parallel transmittance of 15 to 100% when uncured. By making the visible light parallel transmittance within this range, it becomes easier to recognize the alignment mark with the flip chip bonder.

樹脂との屈折率差を小さくでき、未硬化状態時の回路部材接続用接着剤の光散乱を最小限に抑えることができることから、金属水酸化物粒子の屈折率は、１．５〜１．７が好ましい。   Since the difference in refractive index with the resin can be reduced and the light scattering of the adhesive for connecting circuit members in an uncured state can be minimized, the refractive index of the metal hydroxide particles is 1.5 to 1. 7 is preferred.

金属水酸化物粒子の粒径については、平均粒径が０．１μｍ〜１０μｍの範囲内となる
ようにすることが好適である。金属水酸化物粒子の平均粒径をこの範囲にすることで、その分散性や樹脂の流動性を向上させることができ、樹脂の補強効果も期待できる。As for the particle size of the metal hydroxide particles, it is preferable that the average particle size is in the range of 0.1 μm to 10 μm. By setting the average particle diameter of the metal hydroxide particles in this range, the dispersibility and resin fluidity can be improved, and the reinforcing effect of the resin can also be expected.

本発明の回路部材接続用接着剤は、１８０℃で２０秒間加熱した後の示差走査熱量測定での反応率が、７５％以上であることが好ましい。示差走査熱量測定での反応率を上記の値とすることで、安定した低接続抵抗が得られ、熱圧着樹脂として優れるようになる。   The adhesive for connecting circuit members of the present invention preferably has a reaction rate of 75% or more in differential scanning calorimetry after heating at 180 ° C. for 20 seconds. By setting the reaction rate in the differential scanning calorimetry to the above value, a stable low connection resistance can be obtained, and it becomes excellent as a thermocompression bonding resin.

本発明の回路部材接続用接着剤は、４０℃〜１００℃の線膨張係数が７０×１０−６／℃以下であることが好ましい。このような特性の回路部材接続用接着剤を用いて半導体チップと回路基板を接続すると、接続後の温度変化や加熱吸湿による膨張などが抑制され、高接続信頼性が得られる。The adhesive for circuit member connection of the present invention preferably has a linear expansion coefficient of 40 ° C. to 100 ° C. of 70 × 10 −6 / ° C. or less. When the semiconductor chip and the circuit board are connected using the circuit member connecting adhesive having such characteristics, the temperature change after the connection and the expansion due to heating and moisture absorption are suppressed, and high connection reliability is obtained.

本発明はまた、上記回路部材接続用接着剤で接合された回路基板を有する半導体装置を提供する。   The present invention also provides a semiconductor device having a circuit board bonded with the circuit member connecting adhesive.

本発明により、半導体チップと基板との接続信頼性に優れると共に、半導体チップと基板の位置合わせに用いられるアライメントマークの認識性を実用上十分なレベルまで向上させた回路部材接続用接着剤が提供される。また、この回路部材接続用接着剤を用いた半導体装置が提供される。   According to the present invention, there is provided an adhesive for connecting a circuit member which has excellent connection reliability between a semiconductor chip and a substrate, and has improved the recognition of an alignment mark used for alignment of the semiconductor chip and the substrate to a practically sufficient level. Is done. In addition, a semiconductor device using the adhesive for connecting circuit members is provided.

本発明の回路部材接続用接着剤を用いることで、狭ピッチ化及び狭ギャップ化に対応可能なウェハ先置き型のアンダーフィル工法として、ダイシング時の汚染が無く、さらにダイシング後に簡便に接着剤付半導体付チップを得ることができ、さらにウェハへの高密着化によるダイシング時の剥がれ抑制、フィルムの高弾性化によるダイシング後のひげ、バリ、クラックの抑制、チップ実装時に低温かつ短時間で硬化することができようになる。また、本発明の回路部材接続用接着剤を用いたウェハ先置き型のアンダーフィル方法により、ウェハへの密着性とダイシングテープへの密着性の最適化によるダイシング時の剥がれ抑制とダイシング後の簡便なはく離性の両立が可能となり、ひげバリ、クラック等の発生を抑制させてダイシングするための未硬化時のフィルムの高弾性化を実現し、チップ実装時に低温かつ短時間で硬化できるようになる。   By using the adhesive for connecting circuit members of the present invention, the wafer-filled underfill method that can cope with narrowing of pitch and narrowing is free of contamination during dicing, and with adhesive easily after dicing. Chips with semiconductors can be obtained. Further, peeling at the time of dicing due to high adhesion to the wafer, suppression of whiskers, burrs and cracks after dicing due to high elasticity of the film, curing at a low temperature in a short time when mounting the chip I will be able to. In addition, the wafer-first underfill method using the adhesive for connecting circuit members of the present invention suppresses peeling during dicing by optimizing the adhesion to the wafer and the adhesion to the dicing tape, and simple after dicing. It is possible to achieve both peelability and high elasticity of the uncured film for dicing by suppressing the occurrence of whisker burrs, cracks, etc., and it can be cured at low temperature and in a short time when mounting chips. .

本発明における回路部材接続用接着剤について説明する。   The adhesive for connecting circuit members in the present invention will be described.

本発明の回路部材接続用接着剤は、相対向する回路基板を接続するための回路部材接続用接着剤である。相対向する回路基板としては特に限定する組み合わせはないが、例えば（Ｉ）突出した接続端子を有する半導体チップと（ＩＩ）配線パターンが形成された回路基板が挙げられる。   The adhesive for connecting circuit members of the present invention is an adhesive for connecting circuit members for connecting opposing circuit boards. There are no particular limitations on the circuit boards facing each other, and examples thereof include (I) a semiconductor chip having protruding connection terminals and (II) a circuit board on which a wiring pattern is formed.

（Ｉ）突出した接続端子を有する半導体チップにおいて、半導体チップの突出した接続端子は、金ワイヤを用いて形成される金スタッドバンプ、金属ボールを半導体チップの電極に熱圧着や超音波併用熱圧着機によって固定したもの、及びめっきや蒸着によって形成されたものでもよい。突出した接続端子は単一の金属で構成されている必要はなく、金、銀、銅、ニッケル、インジウム、パラジウム、スズ、ビスマス等複数の金属成分を含んでいてもよく、これらの金属層が積層された形をしていてもよい。また、突出した接続端子を有する半導体チップは、突出した接続端子を有する半導体ウェハの状態でもよい。半導体チップの突出した接続端子と配線パターンの形成された基板とを相対向して配置するために、通常、半導体チップは、突出した接続端子と同一面にアライメントマークを有する。この場合、半導体チップの突出した接続端子を有する面に回路部材接続用接着剤を貼付けた状態で、フリップチップボンダーが回路部材接続用接着剤を透過してチップの回路面に形成されたアライメントマークを認識することが可能であることが好ましい。   (I) In a semiconductor chip having a protruding connection terminal, the protruding connection terminal of the semiconductor chip is a gold stud bump formed using a gold wire, a metal ball is thermocompression bonded to the electrode of the semiconductor chip, or a thermocompression bonding using ultrasonic waves. It may be fixed by a machine or formed by plating or vapor deposition. The protruding connection terminal does not need to be made of a single metal, and may contain a plurality of metal components such as gold, silver, copper, nickel, indium, palladium, tin, and bismuth. It may have a laminated shape. Further, the semiconductor chip having the protruding connection terminal may be in the state of a semiconductor wafer having the protruding connection terminal. In order to dispose the protruding connection terminal of the semiconductor chip and the substrate on which the wiring pattern is formed, the semiconductor chip usually has an alignment mark on the same surface as the protruding connection terminal. In this case, the alignment mark formed on the circuit surface of the chip by passing the adhesive for connecting the circuit member through the flip chip bonder in a state where the adhesive for connecting the circuit member is attached to the surface of the semiconductor chip having the protruding connection terminal Is preferably recognizable.

（ＩＩ）配線パターンの形成された回路基板は通常の回路基板でもよく、また半導体チップでもよい。回路基板の場合、配線パターンは、エポキシ樹脂やベンゾトリアジン骨格を有する樹脂をガラスクロスや不織布に含浸して形成した基板、ビルドアップ層を有する基板、又はポリイミド、ガラス、セラミックスなどの絶縁基板表面に形成された銅などの金属層の不要な部分をエッチング除去して形成することができるほか、絶縁基板表面にめっきによって形成することもでき、又は蒸着などによって形成することもできる。また、配線パターンは単一の金属で形成されている必要はなく、金、銀、銅、ニッケル、インジウム、パラジウム、スズ、ビスマス等複数の金属成分を含んでいてもよく、これらの金属層が積層された形をしていてもよい。また、基板が半導体チップの場合、配線パターンは通常アルミニウムで構成されているが、その表面に、金、銀、銅、ニッケル、インジウム、パラジウム、スズ、ビスマスなどの金属層を形成してもよい。   (II) The circuit board on which the wiring pattern is formed may be a normal circuit board or a semiconductor chip. In the case of a circuit board, the wiring pattern is formed on the surface of an insulating substrate such as a substrate formed by impregnating a glass cloth or nonwoven fabric with an epoxy resin or a resin having a benzotriazine skeleton, a substrate having a build-up layer, or polyimide, glass, ceramics, etc. An unnecessary portion of the formed metal layer such as copper can be removed by etching, or can be formed on the surface of the insulating substrate by plating, or can be formed by vapor deposition. The wiring pattern does not need to be formed of a single metal, and may contain a plurality of metal components such as gold, silver, copper, nickel, indium, palladium, tin, and bismuth. It may have a laminated shape. When the substrate is a semiconductor chip, the wiring pattern is usually made of aluminum, but a metal layer such as gold, silver, copper, nickel, indium, palladium, tin, or bismuth may be formed on the surface thereof. .

例えば、回路部材接続用接着剤が付いた半導体チップは、（１）チップ化する前の突出した接続端子を有する半導体ウェハの突出した接続端子面に、半導体ウェハと同等の面積の回路部材接続用接着剤をラミネート等によって貼り付け、（２）前記半導体ウェハの裏面あるいは前記回路部材接続用接着剤上にダイシングテープを積層する工程によって得られた積層体をダイシングによって個片に切断し、（３）ダイシングテープから個片化した回路部材接続用接着剤が付いた半導体チップをはく離することによって得ることができる。ここで用いるダイシングテープは、基材テープ上に粘着材が塗布された市販のダイシングテープを適用することができる。ダイシングテープとしては、感圧型と放射線反応型に大別されるが、ＵＶ照射による硬化によって粘着力が減少し、粘着面に積層された被着体のはく離を容易とするような放射線反応型のダイシングテープがより好ましい。   For example, a semiconductor chip with an adhesive for connecting a circuit member is (1) for connecting a circuit member having an area equivalent to that of a semiconductor wafer on a protruding connection terminal surface of a semiconductor wafer having a protruding connection terminal before being formed into a chip. (2) The laminate obtained by the step of laminating the dicing tape on the back surface of the semiconductor wafer or the circuit member connecting adhesive is cut into individual pieces by dicing. ) It can be obtained by peeling the semiconductor chip with the circuit member connecting adhesive separated from the dicing tape. As the dicing tape used here, a commercially available dicing tape in which an adhesive material is applied on a base tape can be applied. Dicing tapes are roughly classified into pressure-sensitive and radiation-reactive types. However, radiation-sensitive types that reduce adhesion by UV irradiation and make it easier to peel off the adherend laminated on the adhesive surface. A dicing tape is more preferable.

本発明の回路部材接続用接着剤は、半導体チップの突出した接続端子を有する面に貼付けた状態で回路部材接続用接着剤を透過してチップの回路面に形成されたアライメントマークを認識できることが好ましい。アライメントマークは通常のフリップチップボンダーに搭載されたチップ認識用の装置で認識することができる。この認識装置は通常、ハロゲンランプを有するハロゲン光源、ライトガイド、照射装置、及びＣＣＤカメラから構成される。ＣＣＤカメラで取り込んだ画像は画像処理装置によってあらかじめ登録された位置合わせ用の画像パターンとの整合性が判断され、位置合わせ作業が行われる。本発明で言うところのアライメントマークを認識することが可能であることとは、フリップチップボンダーのチップ認識用装置を用いて取り込まれたアライメントマークの画像と、登録されているアライメントマークの画像との整合性が良好であり、位置合わせ作業が問題なく行われることを指す。例えば、アスリートＦＡ株式会社製フリップチップボンダーＣＢ−１０５０を使用した場合、回路部材接続用接着剤が突出した接続端子を有する面に貼付いた積層体の接続端子面とは反対の面でフリップチップボンダーの吸着ノズルに積層体を吸引する。その後、装置内のチップ認識用装置で接着剤層を透過して半導体チップ表面に形成されたアライメントマークを撮影し、あらかじめ画像処理装置に取り込んだ半導体チップのアライメントマークとの整合性がとれて位置合わせ作業ができる接着剤を認識できる回路部材接続用接着剤として、位置合わせできなかった場合を認識できない回路部材接続用接着剤として判別することができる。   The adhesive for connecting a circuit member of the present invention can recognize the alignment mark formed on the circuit surface of the chip through the adhesive for connecting the circuit member in a state where the adhesive is attached to the surface having the protruding connection terminal of the semiconductor chip. preferable. The alignment mark can be recognized by a chip recognition device mounted on a normal flip chip bonder. This recognition device is usually composed of a halogen light source having a halogen lamp, a light guide, an irradiation device, and a CCD camera. The image captured by the CCD camera is checked for consistency with an image pattern for registration registered in advance by the image processing apparatus, and the alignment operation is performed. Being able to recognize the alignment mark in the present invention means that the alignment mark image captured using the chip recognition device of the flip chip bonder and the registered alignment mark image. It means that the alignment is good and the alignment work is performed without any problems. For example, when the flip chip bonder CB-1050 manufactured by Athlete FA Co., Ltd. is used, the flip chip bonder is on the surface opposite to the connection terminal surface of the laminated body attached to the surface having the connection terminal from which the adhesive for connecting the circuit members protrudes. The laminate is sucked into the suction nozzle. After that, the alignment mark formed on the surface of the semiconductor chip through the adhesive layer is photographed by the chip recognition apparatus in the apparatus, and the alignment mark of the semiconductor chip previously taken in the image processing apparatus is taken and positioned. As an adhesive for connecting a circuit member capable of recognizing an adhesive that can be combined, it can be determined as an adhesive for connecting a circuit member that cannot be recognized when alignment is not possible.

本発明の回路部材接続用接着剤は、未硬化時の可視光並行透過率が１５〜１００％であることが好ましく、可視光並行透過率が１８〜１００％であることがより好ましく、可視光並行透過率が２５〜１００％であることが更に好ましい。可視光並行透過率が１５％より小さい場合は、フリップチップボンダーでのアライメントマークの認識が行えなくなって位置合わせ作業が困難になる場合がある。   The adhesive for connecting circuit members of the present invention preferably has a visible light parallel transmittance of 15 to 100% when uncured, more preferably a visible light parallel transmittance of 18 to 100%, and visible light. More preferably, the parallel transmittance is 25 to 100%. When the visible light parallel transmittance is less than 15%, the alignment mark may not be recognized by the flip chip bonder, which may make alignment work difficult.

可視光並行透過率は日本電色株式会社製濁度計ＮＤＨ２０００を用い、積分球式光電光度法で測定することができる。例えば、膜厚５０μｍの帝人デュポン製ＰＥＴフィルム（ピューレックス、全光線透過率９０．４５、ヘイズ４．４７）を基準物質として校正した後、ＰＥＴ基材に２５μｍ厚で回路接続用接着剤を塗工し、これを測定する。測定結果からは濁度、全光線透過率、拡散透過率及び並行透過率を求めることができる。   The visible light parallel transmittance can be measured by an integrating sphere photoelectric photometry method using a turbidimeter NDH2000 manufactured by Nippon Denshoku Co., Ltd. For example, a Teijin DuPont PET film with a film thickness of 50 μm (Purex, total light transmittance 90.45, haze 4.47) was calibrated as a reference material, and then a PET substrate was coated with an adhesive for circuit connection with a thickness of 25 μm. And measure it. From the measurement results, turbidity, total light transmittance, diffuse transmittance, and parallel transmittance can be obtained.

さらに、可視光並行透過率または可視光透過率は、日立製Ｕ−３３１０形分光光度計で測定することができる。例えば、膜厚５０μｍの帝人デュポン製ＰＥＴフィルム（ピューレックス、５５５ｎｍ透過率８６．０３％）を基準物質としてベースライン補正測定を行った後、ＰＥＴ基材に２５μｍ厚で回路部材接続用接着剤を塗工し、４００ｎｍ〜８００ｎｍの可視光領域の透過率を測定することができる。フリップチップボンダーで使用されるハロゲン光源とライトガイドの波長相対強度において５５０ｎｍ〜６００ｎｍが最も強度が高いことから、本発明においては５５５ｎｍの透過率をもって透過率の比較を行うことができる。   Furthermore, visible light parallel transmittance or visible light transmittance can be measured with a Hitachi U-3310 type spectrophotometer. For example, after a baseline correction measurement was performed using a Teijin DuPont PET film with a film thickness of 50 μm (Purex, 555 nm transmittance: 86.03%) as a reference material, an adhesive for connecting circuit members with a thickness of 25 μm was applied to the PET substrate. It can apply and can measure the transmittance | permeability of 400 nm-800 nm visible region. In the present invention, the transmittance can be compared with a transmittance of 555 nm because the wavelength relative intensity of the halogen light source and light guide used in the flip chip bonder is highest at 550 nm to 600 nm.

本発明の回路部材接続用接着剤をダイシングテープと組合せる場合、回路部材接続用接着剤のＵＶ照射後のダイシングテープに対する接着力が１０Ｎ／ｍ以下で、かつ半導体ウェハへの接着力が７０Ｎ／ｍ以上であることが好ましい。ＵＶ照射後のダイシングテープへの接着力が１０Ｎ／ｍ以上である場合、ダイシング後の個片化した回路部材接続用接着剤付き半導体チップをダイシングテープからはく離する作業において、チップ破壊の発生や接着剤層の変形が発生する場合がある。一方、半導体ウェハへの接着力が７０Ｎ／ｍ以下である場合、ダイシング時のブレードの回転切削による衝撃と水圧の影響でチップと接着剤界面ではく離が発生する傾向にある。   When the adhesive for connecting circuit members of the present invention is combined with a dicing tape, the adhesive force of the adhesive for connecting circuit members to the dicing tape after UV irradiation is 10 N / m or less, and the adhesive force to the semiconductor wafer is 70 N / m It is preferable that it is m or more. When the adhesive force to the dicing tape after UV irradiation is 10 N / m or more, chip breakage or adhesion occurs when the separated semiconductor chip with the circuit member connecting adhesive after dicing is peeled off from the dicing tape. Deformation of the agent layer may occur. On the other hand, when the adhesive force to the semiconductor wafer is 70 N / m or less, there is a tendency that separation occurs at the interface between the chip and the adhesive due to the impact of the rotary cutting of the blade during dicing and the influence of water pressure.

回路部材接続用接着剤とＵＶ照射後のダイシングテープの接着力は以下のようにして測定することができる。すなわち、回路部材接続用接着剤を加熱温度８０℃に設定したラミネータによってウェハにラミネートした後、ダイシングテープの粘着面を回路部材接続用接着剤として４０℃でラミネートを行った後、ダイシングテープ側に１５ｍＷで３００ｍＪ程度のＵＶ照射を行う。ＵＶ照射後のダイシングテープに１０ｍｍ幅の切込みを入れて引張り測定用の短冊を準備する。ウェハをステージに押さえつけ、短冊にしたダイシングテープの一端を引張り測定機の引張り治具に固定して９０°ピール試験を行い、回路部材接続用接着剤とＵＶ照射後のダイシングテープを引き剥がす。この測定によって回路部材接続用接着剤とＵＶ照射後のダイシングテープの接着力が測定できる。   The adhesive force between the circuit member connecting adhesive and the dicing tape after UV irradiation can be measured as follows. That is, after laminating the circuit member connecting adhesive on the wafer with a laminator set at a heating temperature of 80 ° C., laminating the adhesive surface of the dicing tape as the circuit member connecting adhesive at 40 ° C. UV irradiation of about 300 mJ is performed at 15 mW. Cut a 10 mm width into the dicing tape after UV irradiation to prepare a strip for tensile measurement. The wafer is pressed against the stage, one end of the dicing tape made into a strip is fixed to a pulling jig of a tensile measuring machine, a 90 ° peel test is performed, and the circuit member connecting adhesive and the dicing tape after UV irradiation are peeled off. By this measurement, the adhesive force between the circuit member connecting adhesive and the dicing tape after UV irradiation can be measured.

回路部材接続用接着剤と半導体ウェハの接着力は回路部材接続用接着剤を加熱温度８０℃に設定したラミネータによってウェハにラミネートした後、回路部材接続用接着剤に粘着面を向けてカプトンテープ（日東電工製、１０ｍｍ幅、２５μｍ厚）を貼付けて十分に密着させた後、カプトンテープ外形の回路部材接続用接着剤に１０ｍｍ幅に切込みを入れる。出来上がった回路部材接続用接着剤とカプトンテープの積層体の一端をウェハから引き剥がし、引張り測定機の引張り治具に固定する。ウェハをステージに押さえつけ、短冊を引き上げて９０°ピール試験を行い、回路部材接続用接着剤をウェハから引き剥がす。この測定によって回路部材接続用接着剤と半導体ウェハの接着力が測定できる。   The adhesive force between the circuit member connection adhesive and the semiconductor wafer is determined by laminating the circuit member connection adhesive on the wafer with a laminator set at a heating temperature of 80 ° C., and then facing the adhesive surface to the circuit member connection adhesive with the Kapton tape ( Nitto Denko's 10 mm width, 25 μm thickness) is applied and sufficiently adhered, and then a 10 mm width cut is made in the adhesive for circuit member connection in the shape of Kapton tape. One end of the finished laminate of circuit member connection adhesive and Kapton tape is peeled off from the wafer and fixed to a tension jig of a tension measuring machine. The wafer is pressed against the stage, the strip is pulled up, a 90 ° peel test is performed, and the adhesive for connecting the circuit members is peeled off from the wafer. By this measurement, the adhesive force between the circuit member connecting adhesive and the semiconductor wafer can be measured.

回路部材接続用接着剤は、半導体チップと回路基板を接続した後の温度変化や、加熱吸湿による膨張等を抑制して高接続信頼性を達成するため、硬化後の４０℃〜１００℃の線膨張係数が７０×１０−６／℃以下であることが好ましく、６０×１０−６／℃以下であるとより好ましく、５０×１０−６／℃以下であると更に好ましい。硬化後の線膨張係数が７０×１０−６／℃より大きい場合、実装後の温度変化や加熱吸湿による膨張によって半導体チップの接続端子と回路基板の配線間での電気的接続が保持できなくなる場合がある。The adhesive for connecting circuit members is a line of 40 ° C. to 100 ° C. after curing in order to achieve high connection reliability by suppressing temperature change after connecting the semiconductor chip and the circuit board and expansion due to heat absorption. The expansion coefficient is preferably 70 × 10 −6 / ° C. or less, more preferably 60 × 10 −6 / ° C. or less, and further preferably 50 × 10 −6 / ° C. or less. When the linear expansion coefficient after curing is greater than 70 × 10 −6 / ° C., the electrical connection between the connection terminal of the semiconductor chip and the wiring of the circuit board cannot be maintained due to temperature change after mounting or expansion due to heat absorption. There is.

本発明の回路部材接続用接着剤は、熱可塑性樹脂、熱硬化性樹脂及び硬化剤を含む樹脂組成物（以下、単に「樹脂組成物」という場合がある。）と金属水酸化物粒子を含むものであり、樹脂組成物は、可視光並行透過率が１５％以上のものが好ましく、５０％以上のものであるとより好ましく、８０％以上のものであると更に好ましい。可視光並行透過率が８０％以上ある場合は金属水酸化物粒子を高充填した場合であっても所定の透過率を満足することができるため好ましい。樹脂組成物の並行透過率が１５％より低い場合、金属水酸化物粒子を添加しない状態であってもフリップチップボンダーでのアライメントマークの認識が困難であり、位置合わせ作業に支障が生じる場合がある。   The adhesive for connecting circuit members of the present invention includes a resin composition containing a thermoplastic resin, a thermosetting resin, and a curing agent (hereinafter sometimes simply referred to as “resin composition”) and metal hydroxide particles. The resin composition preferably has a visible light parallel transmittance of 15% or more, more preferably 50% or more, and still more preferably 80% or more. When the visible light parallel transmittance is 80% or more, it is preferable because the predetermined transmittance can be satisfied even when the metal hydroxide particles are highly filled. When the parallel transmittance of the resin composition is lower than 15%, it is difficult to recognize the alignment mark on the flip chip bonder even when the metal hydroxide particles are not added, which may cause a problem in alignment work. is there.

以下に詳述するように、樹脂組成物中に含まれる熱硬化性樹脂としては、耐熱性樹脂として使用されるエポキシ樹脂が採用される場合が多く、その場合、硬化触媒としてイミダゾール化合物やアミン系の硬化剤が好適なものとして採用される。このような硬化剤は分子内に窒素原子を含む化合物であり、高屈折率化することが知られているため、回路部材接続用接着剤は、未硬化状態で屈折率が１．５以上となることが一般的である。   As will be described in detail below, as the thermosetting resin contained in the resin composition, an epoxy resin used as a heat-resistant resin is often employed. The curing agent is preferably used. Since such a curing agent is a compound containing a nitrogen atom in the molecule and is known to have a high refractive index, the adhesive for connecting circuit members has a refractive index of 1.5 or more in an uncured state. It is common to become.

また、本発明において樹脂組成物中には熱可塑性樹脂が含まれるが、熱可塑性樹脂の含有により、回路部材接続用接着剤のフィルム状への形成が容易になるという効果が奏される。この場合、高分子量の熱可塑性樹脂を採用すると好ましく、このような高分子量の熱可塑性樹脂としてはフェノキシ樹脂やアクリル樹脂（アクリル共重合体等）などが好適に用いられる。このような熱可塑性樹脂を採用した場合、回路部材接続用接着剤は、未硬化状態で屈折率が１．７以下となることが一般的である。よって、回路部材接続用接着剤は、未硬化状態で屈折率が１．５〜１．７とすることが好ましく、この場合、１．６が中心値となる。   Further, in the present invention, the resin composition contains a thermoplastic resin, but the inclusion of the thermoplastic resin has an effect of facilitating formation of the circuit member connecting adhesive into a film. In this case, it is preferable to employ a high molecular weight thermoplastic resin, and as such a high molecular weight thermoplastic resin, a phenoxy resin, an acrylic resin (such as an acrylic copolymer), or the like is preferably used. When such a thermoplastic resin is employed, the adhesive for connecting circuit members generally has a refractive index of 1.7 or less in an uncured state. Therefore, it is preferable that the adhesive for circuit member connection has an uncured state and a refractive index of 1.5 to 1.7. In this case, 1.6 is the center value.

本発明に用いられる金属水酸化物粒子は屈折率が１．５〜１．７のものを好適に使用することができる。屈折率が１．５を下回る場合は樹脂との屈折率差が大きくなるため、粒子分散後の未硬化状態のフィルムに光散乱が発生し、十分な透過性を得ることが出来ない。一方、屈折率が１．７よりも大きい場合も、同様に樹脂組成物との屈折率差が発生するため、十分な透過性を得ることが困難である。なお、樹脂の屈折率はアッベ屈折計を用い、ナトリウムＤ線（５８９ｎｍ）を光源として測定することができる。また、フィラーの屈折率はベッケ法によって顕微鏡下で測定することができる。   As the metal hydroxide particles used in the present invention, those having a refractive index of 1.5 to 1.7 can be suitably used. When the refractive index is less than 1.5, the difference in refractive index from the resin becomes large, so that light scattering occurs in the uncured film after dispersion of the particles, and sufficient transparency cannot be obtained. On the other hand, even when the refractive index is greater than 1.7, a difference in refractive index from the resin composition is similarly generated, so that it is difficult to obtain sufficient transparency. The refractive index of the resin can be measured using an Abbe refractometer with sodium D line (589 nm) as a light source. The refractive index of the filler can be measured under a microscope by the Becke method.

本発明に用いられる金属水酸化物粒子は平均粒径が０．１μｍ〜１０μｍであることが好ましい。平均粒径が０．１μｍを下回る場合、粒子の比表面積が大きく、表面エネルギーも大きくなるため、粒子同士の相互作用が大きくなり、凝集体が発生し、分散性を損なう場合がある。凝集体の分散が良好であったとしても、比表面積が大きいことによって、樹脂に分散した際の増粘挙動が大きくなり、成形性を損なうことがある。一方、平均粒径が１０μｍより大きい場合、粒径が小さい場合とは逆に比表面積が小さくなるため、樹脂の流動性が大きくなり、成型時のボイド発生が起きやすくなる。また、粒子分散の目的の一つである、樹脂の補強効果については、粒径が大きくなるため、同一添加量で粒子を分散させたとしても粒子数自体が少なくなり、補強効果が少なくなる。従って、分散性が良好であって、補強効果も期待できる粒子として平均粒径は０．１〜１０μｍが望ましい。また、粒子径が大きい場合の不具合として、チップのバンプと回路基板の電極間への金属水酸化物粒子のかみこみによる電気的特性の阻害発生も大粒径粒子混入が好ましくない理由である。特に低圧で実装する場合やバンプの材質がニッケル等の硬質である場合には金属水酸化物粒子が端子に埋め込まれず、直接接触におけるバンプと基板電極の接触の妨げや、導電粒子を添加した系においても導電粒子扁平の妨げとなり、電気的接続を阻害する場合がある。また、最大粒径が４０μｍ以上の場合はチップと基板のギャップよりも大きくなる可能性が発生し、実装時の加圧でチップの回路又は基板の回路を傷つける原因となる。   The metal hydroxide particles used in the present invention preferably have an average particle size of 0.1 μm to 10 μm. When the average particle size is less than 0.1 μm, the specific surface area of the particles is large and the surface energy is also large, so that the interaction between the particles becomes large, aggregates are generated, and the dispersibility may be impaired. Even if the agglomerates are well dispersed, the large specific surface area increases the thickening behavior when dispersed in the resin, which may impair the moldability. On the other hand, when the average particle size is larger than 10 μm, the specific surface area is small, contrary to the case where the particle size is small, the flowability of the resin is increased, and voids are easily generated during molding. In addition, with respect to the reinforcing effect of the resin, which is one of the purposes of particle dispersion, the particle size increases, so even if the particles are dispersed with the same addition amount, the number of particles itself is reduced, and the reinforcing effect is reduced. Accordingly, it is desirable that the average particle size is 0.1 to 10 μm as particles that have good dispersibility and can be expected to have a reinforcing effect. In addition, as a problem when the particle diameter is large, the occurrence of inhibition of electrical characteristics due to the inclusion of metal hydroxide particles between the bumps of the chip and the electrodes of the circuit board is also the reason why mixing of the large particle diameter is not preferable. In particular, when mounting at low pressure or when the bump material is hard, such as nickel, the metal hydroxide particles are not embedded in the terminals, preventing contact between the bumps and substrate electrodes in direct contact, or systems with conductive particles added In this case, the flatness of the conductive particles may be hindered, and the electrical connection may be hindered. Further, when the maximum particle size is 40 μm or more, there is a possibility that the gap is larger than the gap between the chip and the substrate, and the chip circuit or the substrate circuit may be damaged by the pressurization during mounting.

また、本発明に用いる金属水酸化物粒子は比重が５以下のものが好ましく、比重２〜５のものがより好ましく、比重２〜３．２のものが更に好ましい。比重が５より大きい場合は接着樹脂組成物のワニスに添加した場合、比重差が大きいことによってワニス中での沈降が発生する原因となり、金属水酸化物粒子が均一に分散した回路部材接続用接着剤を得ることが困難になる場合がある。   The metal hydroxide particles used in the present invention preferably have a specific gravity of 5 or less, more preferably have a specific gravity of 2 to 5, and still more preferably have a specific gravity of 2 to 3.2. When the specific gravity is greater than 5, when added to the varnish of the adhesive resin composition, the difference in specific gravity causes sedimentation in the varnish, and the metal hydroxide particles are uniformly dispersed. It may be difficult to obtain an agent.

また、本発明に用いる金属水酸化物粒子は、屈折率が１．５〜１．７であるとともに、樹脂組成物（接着樹脂組成物）との屈折率差が±０．１以内であることが好ましく、屈折率差が±０．０５以内であることがより好ましい。屈折率差が±０．１を超えると樹脂組成物（接着樹脂組成物）に添加することによって透過率が減少し、特に厚膜の場合に、半導体チップの突出した接続端子を有する面に貼付けた状態で回路部材接続用接着剤を透過してチップの回路面に形成されたアライメントマークを認識することが困難になる場合がある。   Further, the metal hydroxide particles used in the present invention have a refractive index of 1.5 to 1.7, and a refractive index difference from the resin composition (adhesive resin composition) is within ± 0.1. Is preferable, and the difference in refractive index is more preferably within ± 0.05. When the difference in refractive index exceeds ± 0.1, the transmittance is reduced by adding to the resin composition (adhesive resin composition). In this state, it may be difficult to recognize the alignment mark formed on the circuit surface of the chip through the circuit member connecting adhesive.

このような金属水酸化物としては屈折率が１．５〜１．７であり、平均粒子径が０．１μｍ〜１０μｍものであれば特に制限なく公知の金属水酸化物を用いることができるが、安定性及び入手の簡便さから、水酸化マグネシウム、水酸化カルシウム、水酸化バリウム、水酸化アルミニウムがより好ましい。金属水酸化物粒子の線膨張係数は０℃から７００℃以下の温度範囲で７×１０−６／℃以下であることが好ましく、３×１０−６／℃以下であるとより好ましい。熱膨張係数が大きい場合は回路部材接続用接着剤の熱膨張係数を下げるために金属水酸化物粒子を多量に添加する必要が発生する。As such a metal hydroxide, a known metal hydroxide can be used without particular limitation as long as it has a refractive index of 1.5 to 1.7 and an average particle diameter of 0.1 μm to 10 μm. From the viewpoint of stability and availability, magnesium hydroxide, calcium hydroxide, barium hydroxide, and aluminum hydroxide are more preferable. The coefficient of linear expansion of the metal hydroxide particles is preferably 7 × 10 −6 / ° C. or less, more preferably 3 × 10 −6 / ° C. or less, in the temperature range of 0 ° C. to 700 ° C. or less. When the thermal expansion coefficient is large, it is necessary to add a large amount of metal hydroxide particles in order to lower the thermal expansion coefficient of the adhesive for connecting circuit members.

回路部材接続用接着剤において、樹脂組成物１００重量部に対し、金属水酸化物粒子は２０〜１５０重量部であることが好ましく、２５重量部〜１００重量部であるとより好ましく、５０〜１００重量部であると更に好ましい。金属水酸化物粒子が２０重量部より少ない場合は回路部材接続用接着剤の線膨張係数の増大と、弾性率の低下とを招くため、圧着後の半導体チップと基板の接続信頼性が低下する場合がある。一方、配合量が１５０重量部より多い場合は、回路部材接続用接着剤の溶融粘度が増加するため、半導体の突出電極と基板の回路とが十分に接することが出来なくなる場合がある。   In the adhesive for connecting circuit members, the metal hydroxide particles are preferably 20 to 150 parts by weight, more preferably 25 to 100 parts by weight, and more preferably 50 to 100 parts per 100 parts by weight of the resin composition. More preferably, it is parts by weight. When the amount of the metal hydroxide particles is less than 20 parts by weight, the linear expansion coefficient of the circuit member connecting adhesive and the elastic modulus are reduced, so that the connection reliability between the semiconductor chip and the substrate after press bonding is lowered. There is a case. On the other hand, when the blending amount is more than 150 parts by weight, the melt viscosity of the circuit member connecting adhesive increases, so that there are cases where the semiconductor protruding electrode and the circuit of the substrate cannot be sufficiently in contact.

本発明の回路部材接続用接着剤の樹脂組成物（接着樹脂組成物）は、（ａ）熱可塑性樹脂、（ｂ）熱硬化性樹脂、及び（ｃ）硬化剤を成分とするものである。   The resin composition (adhesive resin composition) of the adhesive for connecting circuit members of the present invention comprises (a) a thermoplastic resin, (b) a thermosetting resin, and (c) a curing agent as components.

（ａ）熱可塑性樹脂としては、ポリエステル、ポリウレタン、ポリビニルブチラール、ポリアリレート、ポリメチルメタクリレート、アクリルゴム、ポリスチレン、フェノキシ樹脂、ＮＢＲ、ＳＢＲ、ポリイミドやシリコーン変性樹脂（アクリルシリコーン、エポキシシリコーン、ポリイミドシリコーン）等が挙げられる。また、（ｂ）熱硬化性樹脂としては、エポキシ樹脂、ビスマレイミド樹脂、トリアジン樹脂、ポリイミド樹脂、ポリアミド樹脂、シアノアクリレート樹脂、フェノール樹脂、不飽和ポリエステル樹脂、メラミン樹脂、尿素樹脂、ポリウレタン樹脂、ポリイソシアネート樹脂、フラン樹脂、レゾルシノール樹脂、キシレン樹脂、ベンゾグアナミン樹脂、ジアリルフタレート樹脂、シリコーン樹脂、ポリビニルブチラール樹脂、シロキサン変性エポキシ樹脂、シロキサン変性ポリアミドイミド樹脂、アクリレート樹脂があり、これらを単独もしくは２種以上の混合物として使用することができる。   (A) As a thermoplastic resin, polyester, polyurethane, polyvinyl butyral, polyarylate, polymethyl methacrylate, acrylic rubber, polystyrene, phenoxy resin, NBR, SBR, polyimide or silicone-modified resin (acryl silicone, epoxy silicone, polyimide silicone) Etc. (B) Thermosetting resins include epoxy resins, bismaleimide resins, triazine resins, polyimide resins, polyamide resins, cyanoacrylate resins, phenol resins, unsaturated polyester resins, melamine resins, urea resins, polyurethane resins, poly There are isocyanate resins, furan resins, resorcinol resins, xylene resins, benzoguanamine resins, diallyl phthalate resins, silicone resins, polyvinyl butyral resins, siloxane-modified epoxy resins, siloxane-modified polyamideimide resins, and acrylate resins. It can be used as a mixture.

前記熱硬化性樹脂の中でも、耐熱性、接着性の観点からエポキシ樹脂が好ましく、特に、透過性向上と高Ｔｇ化（Ｔｇ：ガラス転移温度）、低線膨張係数化が望めることから、ナフトールノボラック型固形エポキシ樹脂、フルオレン骨格含有の液状エポキシ樹脂、または固形エポキシ樹脂が好ましい。また、本発明における（ｃ）硬化剤（熱硬化性樹脂の硬化剤をいう。）としては、前記熱硬化性樹脂と反応する成分としてフェノール系、イミダゾール系、ヒドラジド系、チオール系、ベンゾオキサジン、三フッ化ホウ素−アミン錯体、スルホニウム塩、アミンイミド、ポリアミンの塩、ジシアンジアミド、有機過酸化物系の硬化剤が挙げられる。また、これらの硬化剤の可視時間を長くするために、ポリウレタン系、ポリエステル系の高分子物質等で被覆してマイクロカプセル化してもよい。   Among the thermosetting resins, epoxy resins are preferable from the viewpoints of heat resistance and adhesiveness. In particular, naphthol novolak can be expected because of improved permeability, high Tg (Tg: glass transition temperature), and low linear expansion coefficient. Type epoxy resin, fluorene skeleton-containing liquid epoxy resin, or solid epoxy resin is preferable. In the present invention, (c) the curing agent (refers to a curing agent for a thermosetting resin) includes phenol, imidazole, hydrazide, thiol, benzoxazine, a component that reacts with the thermosetting resin. Examples thereof include boron trifluoride-amine complexes, sulfonium salts, amine imides, polyamine salts, dicyandiamide, and organic peroxide curing agents. In order to increase the visible time of these curing agents, they may be microencapsulated by coating with a polyurethane-based or polyester-based polymer substance or the like.

また接着強度を増大するためにカップリング剤を含んでも良く、フィルム形成性を補助するためにポリエステル、ポリウレタン、ポリビニルブチラール、ポリアリレート、ポリメチルメタクリレート、アクリルゴム、ポリスチレン、フェノキシ樹脂、ＮＢＲ、ＳＢＲ、ポリイミドやシリコーン変性樹脂（アクリルシリコーン、エポキシシリコーン、ポリイミドシリコーン）等の熱可塑性樹脂を含んでも良く、また金属水酸化物粒子の表面改質の目的でシリコーンオイル、ポリシロキサン、シリコーンオリゴマー、カップリング剤を含んでも良い。   A coupling agent may be included to increase the adhesive strength, and polyester, polyurethane, polyvinyl butyral, polyarylate, polymethyl methacrylate, acrylic rubber, polystyrene, phenoxy resin, NBR, SBR, Thermoplastic resins such as polyimide and silicone-modified resins (acrylic silicone, epoxy silicone, polyimide silicone) may be included, and silicone oil, polysiloxane, silicone oligomer, coupling agent for the purpose of surface modification of metal hydroxide particles May be included.

本発明の回路部材接続用接着剤は、有機高分子化合物で被覆された粒径３〜５μｍの導電粒子及び／または金属の導電粒子を添加して異方導電接着剤とすることもできる。有機高分子化合物で被覆する前の導電粒子としては、Ａｕ、Ａｇ、Ｎｉ、Ｃｕ、はんだ等の金属粒子やカーボン等であり、十分なポットライフを得るためには、表層は遷移金属の中でもＮｉ、Ｃｕ等よりはＡｕ、Ａｇ又は白金族の貴金属類が好ましく、Ａｕがより好ましい。また、Ｎｉ、Ｃｕ等の金属の表面をＡｕ等の貴金属類で被覆したものでもよい。また、導電粒子として非導電性のガラス、セラミック、プラスチック等に前記導通層（導通材料から形成される層）を被覆等により形成し最外層を貴金属類としたものを使用した場合又は熱溶融金属粒子を使用した場合、導電粒子が加熱加圧による変形性を有するため電極の高さばらつきを吸収し、接続時に電極との接触面積が増加して接続信頼性が向上するので好ましい。良好な接続抵抗を得るためには、貴金属類の被覆層の厚みは１００オングストローム以上であることが好ましい。しかし、被覆時に生じる貴金属類層の欠損や導電粒子の混合分散時に生じる貴金属類層の欠損等が原因となって起こる酸化還元作用によって遊離ラジカルが発生すると、保存性低下を引き起こすため、Ｎｉ、Ｃｕ等の金属の上に貴金属類の層をもうける場合では、被覆層の厚みは３００オングストローム以上にすることが好ましい。そして、厚くなりすぎるとそれらの効果が飽和してくるので最大１μｍにするのが望ましいが、このことは被覆層の厚みを制限するものではない。   The adhesive for connecting circuit members of the present invention can be made into an anisotropic conductive adhesive by adding conductive particles having a particle diameter of 3 to 5 μm and / or metal conductive particles coated with an organic polymer compound. The conductive particles before coating with the organic polymer compound are metal particles such as Au, Ag, Ni, Cu, and solder, carbon, and the like. To obtain a sufficient pot life, the surface layer is Ni among transition metals. Au, Ag or platinum group noble metals are preferred over Au, Cu, etc., and Au is more preferred. Moreover, what coated the surface of metals, such as Ni and Cu, with noble metals, such as Au, may be used. In addition, when the conductive particles (nonconductive glass, ceramic, plastic, etc.) are formed by coating the conductive layer (layer formed from a conductive material) and the outermost layer is a noble metal, or hot-melt metal When particles are used, the conductive particles are deformable by heating and pressurization, so that variations in the height of the electrodes are absorbed, and the contact area with the electrodes increases during connection, thereby improving connection reliability. In order to obtain good connection resistance, the thickness of the coating layer of noble metals is preferably 100 angstroms or more. However, when free radicals are generated due to redox action caused by defects in the noble metal layer generated at the time of coating or defects in the noble metal layer generated at the time of mixing and dispersing the conductive particles, the storage stability is lowered. In the case where a noble metal layer is formed on such a metal, the thickness of the coating layer is preferably 300 angstroms or more. And if it becomes too thick, those effects are saturated, so it is desirable to make it 1 μm at maximum, but this does not limit the thickness of the coating layer.

通常、これらの導電粒子の表面を有機高分子化合物で被覆する。有機高分子化合物は水溶性であると被覆作業性が良好で好ましい。水溶性高分子として、アルギン酸、ペクチン酸、カルボキシメチルセルロース、寒天、カードラン及びプルラン等の多糖類；ポリアスパラギン酸、ポリグルタミン酸、ポリリシン、ポリリンゴ酸、ポリメタクリル酸、ポリメタクリル酸アンモニウム塩、ポリメタクリル酸ナトリウム塩、ポリアミド酸、ポリマレイン酸、ポリイタコン酸、ポリフマル酸、ポリ（ｐ−スチレンカルボン酸）、ポリアクリル酸、ポリアクリルアミド、ポリアクリル酸メチル、ポリアクリル酸エチル、ポリアクリル酸アンモニウム塩、ポリアクリル酸ナトリウム塩、ポリアミド酸、ポリアミド酸アンモニウム塩、ポリアミド酸ナトリウム塩及びポリグリオキシル酸等のポリカルボン酸、ポリカルボン酸エステル及びその塩、ポリビニルアルコール、ポリビニルピロリドン及びポリアクロレイン等のビニル系モノマー等が挙げられる。これらは単一の化合物を用いてもよく、２種以上の化合物を併用してもよい。被覆層の厚みは、１μｍ以下が好ましく、この被覆層を排除して導電粒子が接続端子と接続端子を電気的に接続するので、加熱、加圧時には接続端子と接触する部分の被覆層が排除されることが必要である。通常、導電性粒子は、樹脂組成物（接着剤樹脂）成分１００体積部に対して０．１〜３０体積部の範囲で用途により使い分ける。過剰な導電性粒子による隣接回路の短絡等を防止するためには０．１〜１０体積部とするのがより好ましい。   Usually, the surface of these conductive particles is coated with an organic polymer compound. It is preferable that the organic polymer compound is water-soluble because the coating workability is good. As water-soluble polymers, polysaccharides such as alginic acid, pectinic acid, carboxymethylcellulose, agar, curdlan and pullulan; polyaspartic acid, polyglutamic acid, polylysine, polymalic acid, polymethacrylic acid, polymethacrylic acid ammonium salt, polymethacrylic acid Sodium salt, polyamic acid, polymaleic acid, polyitaconic acid, polyfumaric acid, poly (p-styrenecarboxylic acid), polyacrylic acid, polyacrylamide, polymethyl acrylate, ethyl polyacrylate, ammonium polyacrylate, polyacrylic acid Polycarboxylic acids such as sodium salt, polyamic acid, polyamic acid ammonium salt, polyamic acid sodium salt and polyglyoxylic acid, polycarboxylic acid esters and salts thereof, polyvinyl alcohol, polyvinyl pyrrole Vinyl monomers such as emissions and polyacrolein, and the like. These may use a single compound or may use two or more compounds in combination. The thickness of the coating layer is preferably 1 μm or less. Since the conductive particles electrically connect the connection terminal and the connection terminal by excluding this coating layer, the coating layer in contact with the connection terminal during heating and pressurization is excluded. It is necessary to be done. Usually, electroconductive particle is properly used by the use in the range of 0.1-30 volume parts with respect to 100 volume parts of resin composition (adhesive resin) components. In order to prevent a short circuit of an adjacent circuit due to excessive conductive particles, the content is more preferably 0.1 to 10 parts by volume.

本発明は、以上説明した回路部材接続用接着剤で接合された回路基板を有する半導体装置を提供する。なお、回路基板は、回路部材接続用接着剤の硬化により接合されたものであることが好ましい。本発明の回路部材接続用接着剤で接合された回路基板を有する半導体装置の例としては、半導体メモリ、半導体メモリ用の封止樹脂パッケージ、ロジックコントローラ用の封止樹脂パッケージ等が挙げられる。   The present invention provides a semiconductor device having a circuit board bonded with the circuit member connecting adhesive described above. In addition, it is preferable that a circuit board is joined by hardening of the adhesive agent for circuit member connection. Examples of the semiconductor device having a circuit board bonded with the circuit member connecting adhesive of the present invention include a semiconductor memory, a sealing resin package for a semiconductor memory, a sealing resin package for a logic controller, and the like.

以下、実施例及び比較例に基づき本発明をさらに具体的に説明するが、本発明は以下の実施例に何ら限定されるものではない。   EXAMPLES Hereinafter, although this invention is demonstrated more concretely based on an Example and a comparative example, this invention is not limited to a following example at all.

（実施例１）
三次元架橋性樹脂としてエポキシ樹脂ＥＰ−１０３２−Ｈ６０（ジャパンエポキシレジン株式会社製、製品名）２０重量部、エポキシ樹脂ＹＬ９８０（ジャパンエポキシレジン株式会社製、製品名）１５重量部、フェノキシ樹脂ＹＰ５０Ｓ（東都化成株式会社、製品名）２５重量部、マイクロカプセル型硬化剤としてＨＸ−３９４１ＨＰ（旭化成株式会社製、製品名）４０重量部、及びシランカップリング剤ＳＨ６０４０（東レダウコーニングシリコーン製、製品名）１重量部を、トルエンと酢酸エチルの混合溶媒中に溶解し、接着樹脂組成物（樹脂組成物）のワニスを得た。このワニスの一部をセパレータフィルム（ＰＥＴフィルム）上にロールコータを用いて塗布した後、７０℃のオーブンで１０分間乾燥させることによって、セパレータ上に厚み２５μｍの接着剤樹脂組成物の膜を得た。Example 1
As a three-dimensional crosslinkable resin, 20 parts by weight of epoxy resin EP-1032-H60 (manufactured by Japan Epoxy Resin Co., Ltd., product name), 15 parts by weight of epoxy resin YL980 (manufactured by Japan Epoxy Resin Co., Ltd., product name), phenoxy resin YP50S ( Toto Kasei Co., Ltd., product name) 25 parts by weight, HX-3941HP (manufactured by Asahi Kasei Co., Ltd., product name) as a microcapsule type curing agent, and silane coupling agent SH6040 (manufactured by Toray Dow Corning Silicone, product name) 1 part by weight was dissolved in a mixed solvent of toluene and ethyl acetate to obtain a varnish of an adhesive resin composition (resin composition). A part of this varnish was applied on a separator film (PET film) using a roll coater and then dried in an oven at 70 ° C. for 10 minutes to obtain a film of an adhesive resin composition having a thickness of 25 μm on the separator. It was.

この膜をアッベ屈折計（ナトリウムＤ線）の試料台に設置し、セパレータを剥がしてこれにマッチングオイルを１滴垂らし、屈折率１．７４のテストピースを載せて屈折率を測定した。この結果、接着剤樹脂組成物の屈折率は１．６０（２５℃）であった。一方、ワニスを計量した後、これに平均粒径０．４９μｍの水酸化マグネシウムＭＨ−３０（岩谷化学工業株式会社製、製品名）を５９重量部加え、撹拌してワニス中に分散させた。このワニスをセパレータフィルム（ＰＥＴフィルム）上にロールコータを用いて塗布した後、７０℃のオーブンで１０分間乾燥させることによって、セパレータ上に厚み２５μｍの透過性確認用フィルムを得た。得られた透過性確認用フィルムのＵＶ−ＶＩＳ分光光度計で測定した５５５ｎｍの透過率は６５％であった。次に、はじめのワニスを別途計量した後、これに平均粒径０．４９μｍの水酸化マグネシウムを５９重量部加え、撹拌してワニス中に分散させた。このワニスをセパレータフィルム（ＰＥＴフィルム）上にロールコータを用いて塗布した後、７０℃のオーブンで１０分間乾燥させることによって、セパレータ上に厚み５０μｍの回路部材接続用接着剤を得た。   This film was placed on a sample stage of an Abbe refractometer (sodium D line), the separator was peeled off, one drop of matching oil was dropped on this, a test piece having a refractive index of 1.74 was placed, and the refractive index was measured. As a result, the refractive index of the adhesive resin composition was 1.60 (25 ° C.). On the other hand, after the varnish was weighed, 59 parts by weight of magnesium hydroxide MH-30 (product name, manufactured by Iwatani Chemical Industry Co., Ltd.) having an average particle size of 0.49 μm was added thereto, and the mixture was stirred and dispersed in the varnish. After applying this varnish on a separator film (PET film) using a roll coater, the varnish was dried in an oven at 70 ° C. for 10 minutes to obtain a film for confirming permeability having a thickness of 25 μm on the separator. The transmittance | permeability of 555 nm measured with the UV-VIS spectrophotometer of the obtained film for transparency confirmation was 65%. Next, after the first varnish was separately weighed, 59 parts by weight of magnesium hydroxide having an average particle size of 0.49 μm was added thereto and stirred to disperse in the varnish. After applying this varnish on a separator film (PET film) using a roll coater, the varnish was dried in an oven at 70 ° C. for 10 minutes to obtain an adhesive for connecting a circuit member having a thickness of 50 μm on the separator.

（実施例２）
実施例１の水酸化マグネシウム粒子に代えて平均粒径１．３μｍの水酸化アルミＢＦ０１３（日本軽金属株式会社製、製品名）６０．５重量部を加えたこと以外は実施例１と同様にして回路部材接続用接着剤を得た。(Example 2)
It replaced with the magnesium hydroxide particle of Example 1, and carried out similarly to Example 1 except having added 60.5 weight part of aluminum hydroxide BF013 (Nippon Light Metal Co., Ltd. product name) with an average particle diameter of 1.3 micrometers. An adhesive for connecting circuit members was obtained.

（比較例１）
実施例１の水酸化マグネシウム粒子に代えて平均粒径０．５μｍのシリカ粒子ＳＥ２０５０（アドマテックス社製、製品名）５５．２５重量部を加えたこと以外は実施例１と同様にして回路接続用接着剤を得た。(Comparative Example 1)
Circuit connection was performed in the same manner as in Example 1 except that 55.25 parts by weight of silica particles SE2050 (product name, manufactured by Admatechs Co., Ltd.) having an average particle size of 0.5 μm were added instead of the magnesium hydroxide particles of Example 1. An adhesive was obtained.

（比較例２）
実施例１の水酸化マグネシウム粒子に代えて平均粒径０．３μｍのシリカ粒子Ｆ−２１（株式会社龍森製、製品名）５５．２５重量部を加えたこと以外は実施例１と同様にして回路接続用接着剤を得た。

Figure 0005088376
Figure 0005088376
 (Comparative Example 2)
The same procedure as in Example 1 was performed except that 55.25 parts by weight of silica particles F-21 (manufactured by Tatsumori Co., Ltd., product name) having an average particle size of 0.3 μm were added instead of the magnesium hydroxide particles of Example 1. Thus, an adhesive for circuit connection was obtained.
Figure 0005088376
Figure 0005088376

（半導体装置の作製、特性確認）
実施例１〜２及び比較例１〜２で得た回路接続用接着剤で接続した半導体装置をそれぞれ作製し、特性確認を実施した。(Fabrication of semiconductor devices and confirmation of characteristics)
The semiconductor device connected with the adhesive agent for circuit connection obtained in Examples 1-2 and Comparative Examples 1-2 was produced, respectively, and the characteristic confirmation was implemented.

（半導体ウェハ／回路部材接続用接着剤／ダイシングテープ積層体）
ジェイシーエム製のダイアタッチフィルムマウンターの吸着ステージを８０℃に加熱後、吸着ステージ上に金めっきバンプが形成された厚さ１５０μｍ、直径６インチの半導体ウェハをバンプ側を上に向けて搭載した。実施例１〜２及び比較例１〜２記載の回路部材接続用接着剤をセパレータごと２００ｍｍ×２００ｍｍに切断し、絶縁性接着剤層側を半導体ウェハのバンプ側に向け、エアを巻き込まないように半導体ウェハの端からダイアタッチマウンターの貼付ローラで押しつけてラミネートした。ラミネート後、ウェハの外形に沿って接着剤のはみ出し部分を切断した。切断後、セパレータをはく離した。次いでセパレータ剥離後のウェハと回路部材接続用接着剤の積層体を、接着剤の貼付いた面を下に向けてステージ温度を２５℃に設定したダイアタッチフィルムマウンターの吸着ステージに搭載し、さらに１２インチウェハ用のダイシングフレームをウェハ外周に設置した。ＵＶ硬化型ダイシングテープＵＣ−３３４ＥＰ−１１０（古川電工製、製品名）の粘着面を半導体ウェハ側に向け、エアを巻き込まないようにダイシングフレームの端からダイアタッチマウンターの貼付ローラで押しつけてラミネートした。ラミネート後、ダイシングフレームの外周と内周の中間付近でダイシングテープを切断し、ダイシングフレームに固定された回路部材接続用接着剤／半導体ウェハ／ダイシングテープ積層体を得た。(Semiconductor wafer / adhesive for connecting circuit members / dicing tape laminate)
After heating the suction stage of the die attach film mounter made by JCM to 80 ° C., a semiconductor wafer having a thickness of 150 μm and a diameter of 6 inches and having a gold plating bump formed on the suction stage was mounted with the bump side facing up. Cut the adhesive for connecting circuit members described in Examples 1 and 2 and Comparative Examples 1 and 2 to 200 mm × 200 mm together with the separator so that the insulating adhesive layer side faces the bump side of the semiconductor wafer so that air is not involved. The laminate was pressed from the edge of the semiconductor wafer with a die attach mounter application roller. After lamination, the protruding portion of the adhesive was cut along the outer shape of the wafer. After cutting, the separator was peeled off. Next, the laminate of the wafer after separating the separator and the adhesive for connecting the circuit members is mounted on a suction stage of a die attach film mounter in which the stage temperature is set to 25 ° C. with the surface to which the adhesive is applied facing down. A dicing frame for inch wafer was installed on the outer periphery of the wafer. The UV curable dicing tape UC-334EP-110 (manufactured by Furukawa Electric Co., Ltd., product name) is laminated with the adhesive surface facing the semiconductor wafer and pressed from the end of the dicing frame with a die attach mounter application roller so as not to entrain air. . After lamination, the dicing tape was cut in the vicinity of the middle between the outer periphery and inner periphery of the dicing frame to obtain a circuit member connecting adhesive / semiconductor wafer / dicing tape laminate fixed to the dicing frame.

（ダイシング）
ダイシングフレームに固定された回路部材接続用接着剤／半導体ウェハ／ダイシングテープ積層体を株式会社ディスコ製フルオートマチックダイシングソーＤＦＤ６３６１に搭載した。接着剤を透過してスクライブラインの位置合わせを行った。シングルカットでダイシングテープ内まで１０ｍｍ×１０ｍｍの間隔で切断する。切断後、洗浄し、エアー吹きつけで水分を飛ばした後、ダイシングテープ側からＵＶ照射を行った。この後、ダイシングテープ側から半導体ウェハ側に突き上げ、回路部材接続用接着剤がバンプ側に形成された１０ｍｍ×１０ｍｍの半導体チップを得た。(Dicing)
The circuit member connecting adhesive / semiconductor wafer / dicing tape laminate fixed to the dicing frame was mounted on a fully automatic dicing saw DFD6361 manufactured by DISCO Corporation. The scribe line was aligned through the adhesive. A single cut cuts into the dicing tape at intervals of 10 mm × 10 mm. After cutting, the substrate was washed, water was blown off by air blowing, and then UV irradiation was performed from the dicing tape side. Then, it pushed up from the dicing tape side to the semiconductor wafer side, and obtained the 10 mm x 10 mm semiconductor chip in which the adhesive for circuit member connection was formed in the bump side.

（圧着）
回路部材接続用接着剤付き半導体チップの接着剤面をチップトレー底面に向けた状態でチップトレーに収納し、これをパナソニック製フリップチップボンダーＦＣＢ３のチップトレー収納場所に設置した。次いでＡｕ／ＮｉめっきＣｕ回路プリント基板を基板搭載ステージに設置した。半導体チップ回路面に形成されたアルミ製のアライメントマークを回路部材接続用接着剤側から認識し、基板と位置あわせを行ったのち、２００℃１０秒１．８６ＭＰａの条件で加熱加圧を行い、半導体装置を得た。得られた半導体装置の１７６バンプ連結デージーチェーンでの接続抵抗は８．６Ωであり、良好な接続状態であることを確認した。さらに、半導体装置を３０℃、相対湿度６０％の槽内に１９２時間放置した後、ＩＲリフロー処理（２６５℃最大）３回行った結果、チップのはく離や導通不良の発生はなかった。さらに、ＩＲリフロー後の半導体装置を高温高湿試験機（８５℃／８５％ＲＨ）に２００ｈ放置し、放置後の接続抵抗に導通不良が発生しないことを確認した。また、ＩＲリフロー後の半導体装置を温度サイクル試験機（−５５℃３０分、室温５分、１２５℃３０分）内に放置し、槽内での接続抵抗測定を行い、２００サイクル経過後の導通不良が発生しない事を確認した。(Crimping)
The semiconductor chip with the adhesive for connecting circuit members was stored in the chip tray with the adhesive surface facing the bottom surface of the chip tray, and this was installed in the chip tray storage place of the flip chip bonder FCB3 manufactured by Panasonic. Next, the Au / Ni plated Cu circuit printed circuit board was placed on the substrate mounting stage. The aluminum alignment mark formed on the circuit surface of the semiconductor chip is recognized from the circuit member connecting adhesive side, aligned with the substrate, and then heated and pressurized under the conditions of 200 ° C. for 10 seconds and 1.86 MPa, A semiconductor device was obtained. The connection resistance of the obtained semiconductor device in the 176 bump connection daisy chain was 8.6Ω, and it was confirmed that the connection state was good. Further, after leaving the semiconductor device in a bath at 30 ° C. and a relative humidity of 60% for 192 hours and performing IR reflow treatment (265 ° C. maximum) three times, no chip peeling or poor conduction occurred. Further, the semiconductor device after the IR reflow was left in a high-temperature and high-humidity tester (85 ° C./85% RH) for 200 hours, and it was confirmed that no conduction failure occurred in the connection resistance after being left. In addition, the semiconductor device after IR reflow is left in a temperature cycle tester (−55 ° C. for 30 minutes, room temperature for 5 minutes, 125 ° C. for 30 minutes), and the connection resistance is measured in the bath. It was confirmed that no defects occurred.

実施例１〜２及び比較例１〜２で得た回路部材接続用接着剤について、下記の測定で特性確認を行った。   About the adhesive for circuit member connection obtained in Examples 1-2 and Comparative Examples 1-2, the characteristic check was performed by the following measurement.

（線膨張係数測定）
実施例及び比較例で得た回路部材接続用接着剤をセパレータごと１８０℃に設定したオーブンに３時間放置し、加熱硬化処理を行った。加熱硬化後のフィルムをセパレータからはく離し、３０ｍｍ×２ｍｍの大きさに切断した。セイコーインスツルメンツ社製ＴＭＡ／ＳＳ６１００（製品名）を用い、チャック間２０ｍｍに設定後、測定温度範囲２０℃〜３００℃、昇温速度５℃／ｍｉｎ、断面積に対し０．５ＭＰａ圧力となる荷重条件で引張り試験モードにて熱機械分析を行い、線膨張係数を求めた。(Measurement of linear expansion coefficient)
The circuit member connecting adhesives obtained in Examples and Comparative Examples were left in an oven set at 180 ° C. together with the separator for 3 hours to perform heat curing treatment. The film after heat curing was peeled off from the separator and cut into a size of 30 mm × 2 mm. Using TMA / SS6100 (product name) manufactured by Seiko Instruments Inc. and setting the chuck to 20 mm, the measurement temperature range is 20 ° C. to 300 ° C., the heating rate is 5 ° C./min, and the load condition is 0.5 MPa pressure with respect to the cross-sectional area. Was subjected to thermomechanical analysis in the tensile test mode to determine the linear expansion coefficient.

（反応率測定）
実施例及び比較例で得た回路部材接続用接着剤をアルミ製測定容器に２〜１０ｍｇ計量した後、パーキンエルマー社製の示差走査熱量測定装置ＤＳＣ（Ｄｉｆｆｅｒｅｎｔｉａｌ Ｓｃａｎｉｎｇ Ｃａｌｏｒｉｍｅｔｅｒ）Ｐｙｌｉｓ１（製品名）で３０〜３００℃まで２０℃／ｍｉｎの昇温速度で発熱量測定を行い、これを初期発熱量とした。次いで、熱圧着装置の加熱ヘッドをセパレータに挟んだ熱電対で温度確認を行って２０秒後に１８０℃に達する温度に設定した。この加熱ヘッド設定で、セパレータに挟んだ回路部材接続用接着剤を２０秒間加熱し、熱圧着時と同等の加熱処理が施された状態のフィルムを得た。加熱処理後のフィルムを２〜１０ｍｇ計量してアルミ製測定容器にいれ、ＤＳＣで３０〜３００℃まで２０℃／ｍｉｎの昇温速度で発熱量測定を行い、これを加熱後発熱量とした。得られた発熱量から次の式で反応率（％）を算出した。
式；（初期発熱量−加熱後発熱量）／（初期発熱量）×１００(Reaction rate measurement)
After weighing 2 to 10 mg of the adhesive for connecting circuit members obtained in Examples and Comparative Examples into an aluminum measurement container, the differential scanning calorimeter DSC (Differential Scanning Calorimeter) Pylis1 (product name) manufactured by PerkinElmer is used as 30. The calorific value was measured at a temperature increase rate of 20 ° C./min up to ˜300 ° C., and this was defined as the initial calorific value. Next, the temperature was confirmed with a thermocouple that sandwiched the heating head of the thermocompression bonding apparatus, and the temperature reached 180 ° C. after 20 seconds. With this heating head setting, the adhesive for connecting circuit members sandwiched between the separators was heated for 20 seconds to obtain a film that had been subjected to the same heat treatment as in thermocompression bonding. 2 to 10 mg of the heat-treated film was weighed and placed in an aluminum measurement container, and the calorific value was measured at a heating rate of 20 ° C./min from 30 to 300 ° C. with DSC. The reaction rate (%) was calculated from the obtained calorific value by the following formula.
Formula: (initial calorific value-calorific value after heating) / (initial calorific value) x 100

回路部材接続用接着剤の特性として、並行透過率、硬化後の線膨張係数、フリップチッ
プボンダーでのアライメントマーク認識の可否、反応率、さらに圧着後の接続抵抗値及び
信頼性試験後の接続抵抗値を実施例及び比較例ごとに表３に示した。

Figure 0005088376
The characteristics of the adhesive for connecting circuit members are: parallel transmittance, linear expansion coefficient after curing, alignment mark recognition by flip chip bonder, reaction rate, connection resistance value after crimping and connection resistance after reliability test The values are shown in Table 3 for each example and comparative example.
Figure 0005088376

実施例に示すとおり、屈折率が１．５７〜１．６０の金属水酸化物粒子を添加した回路部材接続用接着剤は、１）並行透過率が３０％以上であるためフリップチップボンダーの認識システムを用いて接着剤を透過してチップ回路面のアライメントマークを認識することが可能であること、２）硬化後の線膨張係数が７０×１０−６／℃以下に低減されており、接続信頼性試験において導通不良が発生しないこと、３）熱圧着時の加熱条件で７５％以上の反応率に達しているため、安定した低接続抵抗を示し、ガラス基板を対象とした異方導電性接着剤としても、またガラエポ基板を対象とした接触型の熱圧着樹脂としても優れていること、が確認できた。一方、比較例１、２では、屈折率が１．４６のシリカを添加したことによって樹脂組成物との屈折率差が大きくなり、光散乱が発生し、並行透過率が小さかった。この場合、フリップチップボンダーでのアライメントマークの認識作業が行えず、位置合わせが出来ないため、半導体装置の初期導通を確保することが出来なかった。As shown in the examples, the adhesive for connecting a circuit member to which metal hydroxide particles having a refractive index of 1.57 to 1.60 are added is 1) recognition of a flip chip bonder because the parallel transmittance is 30% or more. It is possible to recognize the alignment mark on the chip circuit surface through the adhesive by using the system. 2) The linear expansion coefficient after curing is reduced to 70 × 10 −6 / ° C. or less, and the connection In the reliability test, no conduction failure occurs. 3) Since the reaction rate reaches 75% or more under the heating conditions during thermocompression bonding, it exhibits stable low connection resistance and anisotropic conductivity for glass substrates. It was confirmed that it was excellent as an adhesive and as a contact-type thermocompression bonding resin for glass epoxy substrates. On the other hand, in Comparative Examples 1 and 2, the addition of silica having a refractive index of 1.46 increased the refractive index difference from the resin composition, caused light scattering, and the parallel transmittance was small. In this case, since the alignment mark cannot be recognized by the flip chip bonder and cannot be aligned, the initial conduction of the semiconductor device cannot be ensured.

本発明の回路部材接続用接着剤は、狭ピッチ化及び狭ギャップ化に対応可能な先置きのアンダーフィルム工法として使用できる。接着剤付半導体チップは、ダイシング時の汚染が無く、ダイシング後に簡便にダイシングテープからはく離させることにより得ることができる。さらに、本発明の回路部材接続用接着剤は、接着剤付チップと回路基板との高精度な位置合わせを実現する透明性と、低熱膨張係数化による高接続信頼性とを両立することが可能な、速硬化性のウェハ貼付対応の接着剤として利用できる。   The adhesive for connecting circuit members of the present invention can be used as a pre-installed under film method that can cope with narrow pitch and narrow gap. The adhesive-attached semiconductor chip is free from contamination during dicing, and can be obtained by simply peeling off the dicing tape after dicing. Furthermore, the adhesive for connecting circuit members according to the present invention can achieve both transparency for realizing high-precision alignment between the chip with adhesive and the circuit board, and high connection reliability due to a low thermal expansion coefficient. In addition, it can be used as a fast-curing adhesive for wafer sticking.

Claims (7)

相対向する回路基板を接続するための回路部材接続用接着剤であって、
熱可塑性樹脂、熱硬化性樹脂及び硬化剤を含む樹脂組成物と、該組成物中に分散された金属水酸化物粒子とからなり、
前記熱可塑性樹脂がフェノキシ樹脂又はアクリル樹脂であり、
前記熱硬化性樹脂がエポキシ樹脂であり、
前記硬化剤がイミダゾール系又はアミン系の硬化剤であり、
前記金属水酸化物が水酸化マグネシウム、水酸化カルシウム、水酸化バリウム又は水酸化アルミニウムであり、
前記金属水酸化物粒子の配合量が、前記樹脂組成物１００重量部に対して５０〜１００重量部である、回路部材接続用接着剤。A circuit member connecting adhesive for connecting opposite circuit boards,
A resin composition comprising a thermoplastic resin, thermosetting resin and curing agent, Ri Do and a dispersed metal hydroxide particles in the composition,
The thermoplastic resin is a phenoxy resin or an acrylic resin;
The thermosetting resin is an epoxy resin;
The curing agent is an imidazole-based or amine-based curing agent;
The metal hydroxide is magnesium hydroxide, calcium hydroxide, barium hydroxide or aluminum hydroxide;
The adhesive for circuit member connection whose compounding quantity of the said metal hydroxide particle is 50-100 weight part with respect to 100 weight part of said resin compositions . 未硬化時の可視光並行透過率が１５〜１００％である、請求項１記載の回路部材接続用接着剤。  The adhesive for circuit member connection according to claim 1, wherein the visible light parallel transmittance when uncured is 15 to 100%. 前記金属水酸化物粒子は、屈折率が１．５〜１．７である、請求項１又は２に記載の回路部材接続用接着剤。  The adhesive for connecting circuit members according to claim 1 or 2, wherein the metal hydroxide particles have a refractive index of 1.5 to 1.7. 前記金属水酸化物粒子は、平均粒径が０．１μｍ〜１０μｍである、請求項１〜３のいずれか一項に記載の回路部材接続用接着剤。  The said metal hydroxide particle | grain is an adhesive for circuit member connection as described in any one of Claims 1-3 whose average particle diameter is 0.1 micrometer-10 micrometers. １８０℃で２０秒間加熱した後の示差走査熱量測定に基づく反応率が、７５％以上である、請求項１〜４のいずれか一項に記載の回路部材接続用接着剤。  The adhesive for circuit member connection according to any one of claims 1 to 4, wherein a reaction rate based on differential scanning calorimetry after heating at 180 ° C for 20 seconds is 75% or more. ４０℃〜１００℃の線膨張係数が、７０×１０−６／℃以下である、請求項１〜５のいずれか一項に記載の回路部材接続用接着剤。The adhesive for circuit member connection as described in any one of Claims 1-5 whose linear expansion coefficient of 40 to 100 degreeC is 70x10 < -6 > / degrees C or less. 請求項１〜６のいずれか一項に記載の回路部材接続用接着剤で接合された回路基板を有する半導体装置。  The semiconductor device which has a circuit board joined with the adhesive for circuit member connection as described in any one of Claims 1-6.
JP2009543887A 2007-11-29 2008-11-28 Circuit member connecting adhesive and semiconductor device Expired - Fee Related JP5088376B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009543887A JP5088376B2 (en) 2007-11-29 2008-11-28 Circuit member connecting adhesive and semiconductor device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007308668 2007-11-29
JP2007308668 2007-11-29
PCT/JP2008/071727 WO2009069783A1 (en) 2007-11-29 2008-11-28 Circuit member connecting adhesive and semiconductor device
JP2009543887A JP5088376B2 (en) 2007-11-29 2008-11-28 Circuit member connecting adhesive and semiconductor device

Publications (2)

Publication Number Publication Date
JPWO2009069783A1 JPWO2009069783A1 (en) 2011-04-21
JP5088376B2 true JP5088376B2 (en) 2012-12-05

Family

ID=40678672

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009543887A Expired - Fee Related JP5088376B2 (en) 2007-11-29 2008-11-28 Circuit member connecting adhesive and semiconductor device

Country Status (5)

Country Link
JP (1) JP5088376B2 (en)
KR (1) KR101302933B1 (en)
CN (2) CN101835866B (en)
TW (1) TWI419954B (en)
WO (1) WO2009069783A1 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5372665B2 (en) * 2009-08-31 2013-12-18 株式会社日立メディアエレクトロニクス Photo-curing adhesive, optical pickup device and manufacturing method thereof
JP5445187B2 (en) * 2010-02-05 2014-03-19 日立化成株式会社 Circuit member connecting adhesive and semiconductor device using the same
JP5415334B2 (en) * 2010-03-26 2014-02-12 ナミックス株式会社 Pre-feed type liquid semiconductor encapsulating resin composition
JP6043939B2 (en) * 2012-08-24 2016-12-14 ボンドテック株式会社 Method and apparatus for positioning an object on a substrate
JP6157890B2 (en) * 2013-03-26 2017-07-05 日東電工株式会社 Underfill material, sealing sheet, and method for manufacturing semiconductor device
JP2014203971A (en) * 2013-04-04 2014-10-27 日東電工株式会社 Underfill film, sealing sheet, method for manufacturing semiconductor device, and semiconductor device
JP2014074181A (en) * 2013-12-25 2014-04-24 Hitachi Chemical Co Ltd Manufacturing method of semiconductor device and semiconductor device manufactured thereby
CN104312471A (en) * 2014-11-10 2015-01-28 深圳市飞世尔实业有限公司 Anisotropic conductive film containing benzoxazine and preparation method of anisotropic conductive film
CN115360101A (en) * 2016-11-29 2022-11-18 Pep创新私人有限公司 Chip packaging method and packaging structure

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60117572A (en) * 1983-11-28 1985-06-25 日立化成工業株式会社 Method of connecting circuit
WO1997029490A1 (en) * 1996-02-08 1997-08-14 Asahi Kasei Kogyo Kabushiki Kaisha Anisotropic conductive composition
JP2004269626A (en) * 2003-03-06 2004-09-30 Sony Chem Corp Adhesive, method for producing adhesive and electric apparatus
JP2006199778A (en) * 2005-01-19 2006-08-03 Hitachi Chem Co Ltd Adhesive composition, adhesive for use in circuit connection, method for connecting circuits using the same, and connected body
JP2007016088A (en) * 2005-07-06 2007-01-25 Asahi Kasei Electronics Co Ltd Anisotropically electrically conductive adhesive sheet and fine-connected structure
JP2007091959A (en) * 2005-09-30 2007-04-12 Sumitomo Electric Ind Ltd Anisotropically conductive adhesive
WO2008084811A1 (en) * 2007-01-10 2008-07-17 Hitachi Chemical Company, Ltd. Adhesive for connection of circuit member and semiconductor device using the same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2698528B2 (en) * 1993-03-26 1998-01-19 日本碍子株式会社 Electrical insulator used for non-ceramic insulator housing
JP2002371263A (en) * 2001-06-14 2002-12-26 Nitto Denko Corp Adhesive composition for multilayer flexible printed circuit board and multilayer flexible printed circuit board obtained by using the same
KR20030001231A (en) * 2001-06-25 2003-01-06 텔레포스 주식회사 Anisotropic conductive adhesives having enhanced viscosity, bonding methods using the same and integrated cirduit pakages
JP2003073641A (en) * 2001-08-31 2003-03-12 Hitachi Chem Co Ltd Flame-retardant adhesive film, wiring board for mounting semiconductor, semiconductor and method for manufacturing the semiconductor device
JP2003206452A (en) * 2002-01-10 2003-07-22 Toray Ind Inc Adhesive composition for semiconductor device, adhesive sheet for semiconductor device using the same, substrates for connecting semiconductors and semiconductor device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60117572A (en) * 1983-11-28 1985-06-25 日立化成工業株式会社 Method of connecting circuit
WO1997029490A1 (en) * 1996-02-08 1997-08-14 Asahi Kasei Kogyo Kabushiki Kaisha Anisotropic conductive composition
JP2004269626A (en) * 2003-03-06 2004-09-30 Sony Chem Corp Adhesive, method for producing adhesive and electric apparatus
JP2006199778A (en) * 2005-01-19 2006-08-03 Hitachi Chem Co Ltd Adhesive composition, adhesive for use in circuit connection, method for connecting circuits using the same, and connected body
JP2007016088A (en) * 2005-07-06 2007-01-25 Asahi Kasei Electronics Co Ltd Anisotropically electrically conductive adhesive sheet and fine-connected structure
JP2007091959A (en) * 2005-09-30 2007-04-12 Sumitomo Electric Ind Ltd Anisotropically conductive adhesive
WO2008084811A1 (en) * 2007-01-10 2008-07-17 Hitachi Chemical Company, Ltd. Adhesive for connection of circuit member and semiconductor device using the same

Also Published As

Publication number Publication date
CN102977809A (en) 2013-03-20
TWI419954B (en) 2013-12-21
KR101302933B1 (en) 2013-09-06
WO2009069783A1 (en) 2009-06-04
JPWO2009069783A1 (en) 2011-04-21
TW200934851A (en) 2009-08-16
KR20100074312A (en) 2010-07-01
CN101835866A (en) 2010-09-15
CN101835866B (en) 2013-01-02

Similar Documents

Publication Publication Date Title
JP5487619B2 (en) Circuit member connecting adhesive and semiconductor device using the same
JP5088376B2 (en) Circuit member connecting adhesive and semiconductor device
JP5257499B2 (en) Adhesive film
JP5557526B2 (en) Circuit member connecting adhesive and semiconductor device
JP5569126B2 (en) Adhesive composition, adhesive sheet, and method for manufacturing semiconductor device
JP5224111B2 (en) Adhesive film for semiconductor wafer processing
JP5569121B2 (en) Adhesive composition, circuit member connecting adhesive sheet, and method for manufacturing semiconductor device
JP2005264109A (en) Film-shaped adhesive and manufacturing method of semiconductor device using the same
JP2012067302A (en) Film adhesive and method of manufacturing semiconductor device using the same
TWI425066B (en) Preparation method of adhesive composition, circuit board for connecting circuit member, and manufacturing method of semiconductor device
JP5263158B2 (en) Circuit member connecting adhesive and semiconductor device
JP5375351B2 (en) Manufacturing method of semiconductor circuit member
JP5445187B2 (en) Circuit member connecting adhesive and semiconductor device using the same

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20111004

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111205

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120814

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120827

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150921

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150921

Year of fee payment: 3

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150921

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees