JP4699707B2 - Fire alarm system - Google Patents

Description

  The present invention connects a plurality of fire detectors to a sensor line drawn from a receiver, and receives a common fire signal or a fire display signal from the fire sensor for each line, and issues a P-type fire alarm. About the system.

  Conventionally, in a fire alarm system known as a P type, as shown in FIG. 20, a plurality of fire detectors 104 are connected to a sensor line 102 drawn from a receiver 100, and fire detectors are connected in units of lines. The fire alarm is received by receiving the alarm signal from.

  A termination resistor 106 is connected to the end of the sensor line 104 and the receiver 100 monitors the disconnection. In the disconnection monitoring by the receiver 100, if the sensor line 102 is not disconnected, a predetermined current flows through the termination resistor 106 and a predetermined line voltage is obtained. When the current stops flowing, the line voltage increases with respect to the specified voltage, and an increase in the line voltage is detected to determine that the line is disconnected, and a failure alarm indicating the disconnection is issued.

  Furthermore, in the conventional P-type fire alarm system, the alarm search unit is provided in the receiver, and when a fire alarm is detected, a fire is generated by sending a search downlink signal to the alarm line. A search response unit is provided for searching for a sensor and determining and returning a downstream signal from the receiver to the fire sensor.

  FIG. 21 is a timing chart of the response operation of the fire detector according to the downstream signal from the receiver in the conventional P-type fire alarm system, and shows a case where the detector response is performed by the reading operation of the EEPROM provided in the fire detector. .

First, as a L-C voltage to sensor lines from the receiver, the monitoring level 11 volts, although higher signal level 18 volts and a read control signal including the read code and the address in the downlink signal varying ternary 2 4 volts Is converted and sent. In the sensor side, from the change in the 11 volt and 18 volt of the downlink signal received, as shown in FIG. 21 (B), the detected clock signal, the change of 18 volts and 2 4 volts voltage signal, As shown in FIG. 21C, a data signal including a dummy clock, a start bit, a read operation code, an address bit, and a data bit for serial bit output is detected.

Here, of the 32 bits, the EEPROM read address stores data in which only the data bit D2 has the bit value 1 and all the remaining bits have the bit value 0. Therefore, the bit value 1 is output at the output timing of the data bit D2. Corresponding to this, as shown in FIG. 21D, a sensor response current is passed through the sensor line, and an upstream signal for response is sent to the receiver. The reason why three values are used as the downlink signal is to detect the clock simultaneously with the data.

FIG. 21 shows an example of the call operation from the receiver at the time of monitoring. In the event of a fire, the fire detector that has detected a fire sends an alarm current to the sensor line, so the voltage of the sensor line is, for example, 4 Decrease to bolt. For this reason, from the receiver during the fire alarm, the read control signal including the read opcode and the address is converted into a down signal that changes in three values of an alarm level of 4 volts and a higher signal level of 7 volts and 10 volts, The sensor response can be made in the same way, although the voltage is different.
JP-A-5-108975 Japanese Patent Laid-Open No. 7-200957 JP 2001-184571 A

However, in such a conventional P-type fire alarm system, the downlink signal transmitted from the receiver to the fire detector, for example, 11 volts during the monitoring, 18 volts, using a 3 value as of 2 4 volts Therefore, the transmitter circuit on the receiver side and the receiver circuit on the sensor side are complicated, and the monitoring level is lowered to ensure a ternary signal level. Gives constraints.

  In a fire alarm system, various control signals such as monitoring and testing may be sent from a receiver to a terminal such as a fire detector. However, in a conventional system, the circuit becomes very complicated.

  The present invention has been made to solve such a problem, and the circuit configuration is simplified by the transmission of binary downstream signals that enable simultaneous detection of data and clock, and the design constraints of the sensor are reduced. An object is to provide a P-type fire alarm system.

  Another object of the present invention is to provide a fire alarm system that simplifies the circuit configuration for transmitting and receiving various control signals from the receiver to each terminal.

  In order to achieve this object, the present invention is configured as follows.

The present invention relates to a fire alarm system in which a plurality of fire detectors are connected to a sensor line drawn out from a receiver, and a warning signal is received from the fire sensor for each line to alert the receiver. provided, every constant period a downlink signal of a predetermined sensor lines, different between the two signal levels at varying alternately, 2 and in the constant period by the length between the time of two signal levels in the predetermined period One of the two values, a transmission circuit unit that converts a desired binary signal into a downstream signal and transmits it, and a fire detector, and the two signals from the downstream signal received from the sensor line the length between time either one of the levels is characterized by providing a reception circuit section that outputs to determine a binary signal.

Here, the transmission circuit unit of the receiver converts the binary signal for read control of a nonvolatile memory such as an EEPROM provided in the fire detector into the downstream signal and transmits it, and the reception circuit unit of the fire detector The down signal is received from the sensor line, and the read operation code of the nonvolatile memory, the read control signal including the address, the clock signal, and the chip select signal are detected .

Further , the transmission circuit unit of the receiver alternately changes the downstream signal voltage of the sensor line between a predetermined monitoring level and a predetermined signal level lower than the predetermined monitoring level, and either the monitoring level or the signal level. The binary signal is converted into a downstream signal and transmitted according to the length of the level time, and the fire detector receiving circuit unit determines whether the level time of either the monitoring level or the signal level from the received downstream signal of the sensor line. To determine and output the binary signal .

Fire detector, the number only one bit at a specific position at a predetermined address in the nonvolatile memory stores a unique number data as a distinguishing bit with another bit, designated a predetermined address from the receiver A unique response uplink signal is transmitted at the output timing of a specific bit by the data read operation.

  In the fire alarm system of the present invention, the transmission circuit unit of the receiver transmits a downlink signal having a time length that differs depending on a predetermined control type for one of the two signal levels, The reception circuit unit of the fire detector receives a downstream signal from the sensor line, detects the time of one of the signal levels, and executes a control process of a predetermined type corresponding to the detection time. And

  In this case, the transmission circuit unit of the receiver differs in the level time of either a predetermined monitoring level or a lower predetermined signal level corresponding to each of the sensor response control, the fire monitoring control, and the fire test control. The time signal length is set to transmit a downstream signal corresponding to each control, and the fire detector receiving circuit unit receives the downstream signal from the sensor line and receives either the monitoring level or the signal level. And the control process of any one of the sensor response control, the fire monitoring control, and the fire test control is executed in accordance with the detection time.

  The fire alarm system of the present invention changes the downstream signal alternately between two different signal levels as a downstream signal from the receiver to the fire detector, and the desired level of the downstream signal level depends on the length of the level time. By transmitting a binary signal converted to a downstream signal voltage and transmitting a downstream signal that enables simultaneous detection of data and clock on the detector side even if the signal level of the binary signal changes. The transmission circuit portion and the reception circuit portion can be simplified, and the cost can be reduced.

  In addition, since the lower one of the binary signal levels is set as the monitoring level, the monitoring level voltage can be secured at a sufficiently high level compared to the ternary downstream signal, and the fire detector in the monitoring state. The power supply voltage that can be supplied to the battery becomes higher, and accordingly, the restrictions on designing the fire detector can be reduced, and the degree of design freedom can be increased.

  FIG. 1 is an explanatory diagram of a fire alarm system according to the present invention. In FIG. 1, detector lines 18-1 to 18-m are drawn from the receiver 1, and fire detectors 4-11 to 4-mn each having a response function to a call by a downstream signal from the receiver 1 are respectively provided. Is connected. The number of detectors connected to each of the sensor lines 18-1 to 18-m is n as an example.

  As fire detectors 4-11 to 4-mn, various types of fire detectors such as photoelectric smoke detectors, semiconductor heat detectors, differential heat detectors, and constant temperature heat detectors can be connected. When a fire is detected, the sensor lines 18-1 to 18-m are short-circuited and a fire signal is sent to the receiver 1.

  In addition to the fire detection unit, the fire detectors 4-11 to 4-mn include a unique signal response unit that responds to the downlink signal periodically transmitted from the receiver 1 during monitoring as an uplink signal. For example, disconnection monitoring in the receiver 1 is performed by the response of the upstream signal.

The unique signal response unit of the fire detectors 4-11 to 4-mn includes a nonvolatile memory such as an EEPROM. Unique number data in which only one bit at a specific position has a bit value 1 is stored in a predetermined address of the nonvolatile memory. The upstream signal is transmitted at the output timing of bit value 1 by reading the number data based on the confirmation signal from the receiver 1.

  The receiver 1 is provided with an MPU 6. An operation unit 8, an alarm display unit 9, a district display unit 10, a transfer output unit 11, and a memory 12 are provided for the MPU 6.

  Further, monitoring circuit units 7-1 to 7-m are provided on the sensor line side of the MPU 6 for each line. Sensor lines 18-1 to 18-m are drawn from the monitoring circuit units 7-1 to 7-m, and fire detectors 4-11 to 4-mn are connected thereto.

  As represented by the monitoring circuit unit 7-1, the monitoring circuit units 7-1 to 7-m include a voltage control circuit 15, an output buffer circuit 16, and a current detection circuit 17. Among them, the voltage control circuit 15 and the output buffer circuit 16 constitute a downstream signal transmission circuit part, and the current detection circuit 17 constitutes an upstream signal reception circuit part from the sensor side.

  The downstream signal transmission circuit unit comprising the voltage control circuit 15 and the output buffer circuit 16 of the present invention alternately changes the downstream signal voltage of the sensor line 18-1 between two different signal levels, and Depending on the level time of either one of the downstream signal levels, the data required on the sensor side and the binary signal necessary for clock detection are converted into a downstream signal voltage and transmitted.

Specifically, the voltage control circuit 15 alternately changes the downstream signal voltage between the monitoring level of 18 volts and the higher 24 volts, and the bit value 0 is determined by the length of the 18 volt level period that becomes the monitoring level. , 1 is converted into a downstream signal voltage and output to the sensor line 18-1.

In response to the monitoring circuit portion 7-1 to 7-m, the function of pressurizing example monitoring control unit 14 in function of the receiving control section 13 is provided in the MPU 6. The reception control unit 13 detects an alarm signal for each line and performs alarm display, that is, fire representative display and district display (report line display) . Monitoring control unit 14 transmits a downlink signal to the sensor lines unit, by the response of the upstream signal from the fire detector connected to the respective line, the fire detector is judged to be normal if there is a response, no response In this case, it is judged that the fire detector is faulty and the fault is displayed.

  For example, among the fire detectors 4-11 to 4-1n connected to the sensor line 18-1, all the responses of the fire detectors after the specific fire detector are obtained as viewed from the receiver 1. If there is not, it can be determined that a disconnection of the sensor line has occurred at that position, and a failure display indicating the disconnection result can be performed. In order to quickly detect the disconnection state, it is desirable to periodically send the confirmation signal at intervals of 1 minute or less.

Downlink signals from the monitoring control unit 14 to the fire detectors 4-11 to 4-mn are read operation signals corresponding to predetermined addresses of the EEPROM provided in the unique signal response units of the fire detectors 4-11 to 4-mn. In the read address of the EEPROM, unique number data corresponding to the sensor line in which only 1 bit at a specific position is 1 and all others are 0 is written in advance.

Therefore, sensor lines 18-1 to 18-m for each output timing of the bit value of 1 by the read unique number data specifying the predetermined address of the EEPROM by the downlink signal from the receiver 1 (output period of the bit value 1 ) And responds by sending an upstream signal to the sensor line. The number data unique to the read address of the EEPROM may have a bit value 0 only at a specific position and a bit value 1 at another position.

  FIG. 2 is a circuit block diagram showing an embodiment of the fire detector 4 of FIG. The fire detector 4 is provided with a rectification / noise absorption circuit 21, an alarm circuit 22, a power supply circuit 24, a signal processing circuit 25, and a detection circuit 26 following the connection terminals L and C of the sensor line.

  The detection circuit 26 outputs a detection signal corresponding to smoke or heat from the fire to the signal processing circuit 25. The signal processing circuit 25 outputs, for example, a fire signal E2 to the alarm circuit 22 when the detection signal from the detection circuit 26 exceeds a predetermined fire determination threshold value, and is an EX-OR circuit that will be clarified in later explanation. By switching the transistor 23 by the output of 32, the alarm current Ic determined by the resistance R is caused to flow through the sensor line, thereby sending a fire signal to the receiver side.

The signal processing circuit 25, in the case of the light scattering type smoke detector detecting circuit 26 for detecting the light scattered by the smoke example intermittent light emission of the light emitting element, originating in two counts obtained that detection signal in intermittent light emission operating the multi-address circuit 22 Ru by sending a fire signal. In heat detection using a semiconductor element, the alarm circuit 22 is operated to output a fire signal when a comparator exceeds a fire determination threshold.

  In addition to such a basic circuit of the fire detector 4, in the present invention, the unique signal response unit 27 is provided corresponding to the monitoring control function on the receiver 1 side. The unique signal response unit 27 includes a clock detection circuit 28, a data detection circuit 29, a chip select detection circuit 30, an EEPROM 31 as a nonvolatile memory, an EX-OR circuit (exclusive OR circuit) 32, and a notification detection circuit 33. Is done.

Clock detection circuit 28, a downlink signal varying binary monitoring level 18 volts and this higher signal level 24 volts between sensor lines based on the downlink signal from the monitoring control unit 14 provided in MPU6 of FIG Is detected, and a clock pulse synchronized with the binary change of the downstream signal is detected and output to the EEPROM 31.

The data detection circuit 29 receives a binary downstream signal from the receiver, detects data values 0 and 1 by determining the time length (pulse width) of the monitoring level 18 volts in the downstream signal, and performs the read operation of the EEPROM 31. Output a data value indicating the operation code, address, and data output timing.

  The chip select detection circuit 30 inputs a binary down signal between the sensor lines, outputs a chip select detection signal over the time when the down signal is obtained, and performs a chip select for the reading operation of the EEPROM 31. .

Furthermore, when the fire signal is sent out by another fire detector in the same sensor line, the alarm detection circuit 33 detects the alarm state of the other fire detector from the voltage of the sensor line at this time. abrogated the operation of the signal processing circuit 25, so as to inhibit reading operation of the EEPROM31 as the response to the search signal from且one receiver device 1.

  As a result, among the multiple fire detectors connected to the same detector line, only the fire detector that is triggered by detecting the fire first outputs the fire signal and the fire response to the search from the receiver 1 It is possible to forbid the output of the fire alarm signal and the response to the search in the fire detector that detects the second and subsequent fires.

FIG. 3 is a time chart of detection operations of the data detection circuit 29 and the chip select detection circuit 30 of FIG. 2 for the downstream signal from the receiver 1 of FIG. FIG. 3A is a downstream signal from the receiver 1 by the sensor line received as a voltage between L and C in the fire detector. In this embodiment, 18 V, which is a monitoring level, by changing the signal voltage alternates between two signal levels of 24 volts to be higher signal levels, for example, it sends a binary signal data "10011".

Here, although the downstream signal has a repetition period T, pulse width modulation is performed to change the time of the monitoring level of 18 volts, that is, the time of the latter L level section in terms of pulses, according to the data values 1 and 0. Is going. For example, for the data value 1, the time of the L level section of the pulse signal having the period T that is the latter monitoring level of 18 volts is T ₁ hour, while the data value 0 is the L that is the latter monitoring level of 18 volts. The time of the level section is set to a shorter T ₀ time.

Therefore, in the data detection circuit 29 in FIG. 2, the L level time at which the monitoring level is 18 volts is monitored for each pulse of the received downstream signal, and if it is T ₁ time, the data value 1 is set at the next pulse period. The data is output as shown in FIG. 3C, and a data value 0 is output in the next cycle if it is T ₀ time.

On the other hand, in the chip select detection circuit 30 of FIG. 2, by detecting the first to the downlink signal is increased to a high signal level 24 volts than the monitoring level 18 volts as shown in FIG. 3 (A), the FIG. As shown in 3 (B), the chip select detection signal is turned on to H level.

Thereafter, when the time during which the voltage of the downstream signal is 18 volts, which is the monitoring level , continues for T ₂ hours longer than T ₁ time used for the determination of the data value 1, as shown in FIG. The chip select detection signal is turned off from the H level to the L level. As a result, while the downstream signal is obtained from the receiver, the chip select detection signal is turned on to the H level, and the chip select operation of the EEPROM 31 is performed.

  FIG. 4 is a circuit diagram showing an embodiment of the data detection circuit 29 and the chip select detection circuit 30 of FIG.

  4, the data detection circuit 29 is provided with an inverting amplifier 34, a time constant circuit 35, a comparator 36, an AND gate 37, an RS-FF 38, a time constant circuit 39, and a comparator 40. The chip select detection circuit 30 is provided with a comparator 41, a time constant circuit 42, a comparator 43, and an RS-FF 44.

  The inverting amplifier 34 of the data detection circuit 29 inverts the downstream signal as shown in FIG. 3A and inputs it to the time constant circuits 35 and 39. The output of the inverting amplifier 34 is simultaneously input to the time constant circuit 42 of the chip select detection circuit 30.

The time constant circuit 35 includes a diode D1, a resistor R1, a capacitor C1, and a switch S1, and the time constant according to the values of the resistor R1 and the capacitor C1 is a monitoring level of 18 volts T ₁ time corresponding to the data value 1 in FIG. The value corresponds to. Thus, the downlink signal inverted by the inverting amplifier 34, a diode D1, is the capacitor C1 through the resistor R1 charging, the charging voltage of the capacitor C1 reaches the reference voltage Vr of the comparator 36 when a lapse of ₁ hour T As a result, the output of the comparator 36 rises from 0 to 1.

On the other hand, the time constant circuit 39 is composed of a diode D2, a resistor R2, a capacitor C2, and a switch S2. As a time constant determined by the values of the resistor R2 and the capacitor C2, a monitoring level of 18 volts in the down signal of FIG. The time T ₀ corresponding to the data value 0 is set.

For this reason, the capacitor C2 is charged through the diode D2 and the resistor R2 by the down signal inverted by the inverting amplifier 34, and the charging voltage of the capacitor C2 reaches the reference voltage Vr of the comparator 40 after T ₀ time, and the output of the comparator 40 Rises from 0 to 1. The switches S1 and S2 connected in parallel to the capacitors C1 and C2 provided in the time constant circuits 35 and 39 are switched on in synchronization with the rising edge of the clock detection signal CK, and the capacitors C1 and C2 are discharged and reset.

  The outputs of the comparators 36 and 40 are input to the AND gate 37, and the output of the AND gate 37 is connected to the set input terminal S of the RS-FF 38.

Here, when the time monitoring level 18 volt downlink signal was T ₁ times corresponding to the data value 1, the charging voltage of the capacitor C2 of the time constant circuit 39 during the first T ₀ hours elapsed reaches the reference voltage Vr, the comparator The output of 40 rises from 0 to 1. Thereafter, the charging voltage of the capacitor C1 of the time constant circuit 35 when it reaches the time T ₁ reaches the reference voltage Vr, the output of the comparator 36 rises from 0 to 1, the output is 0 at this time the AND gates 37 1 and Become. The RS-FF 38 operates at the rising edge of the clock detection signal CK. Since the output of the AND gate 37 is 1 at that time, the set operation is performed, and the output Q is changed from 0 to 1, which becomes the data detection signal. .

  Further, the analog switches S1 and S2 are turned on at the timing of the setting operation of the clock detection signal CK of the RS-FF 38, and the discharge reset of the capacitors C1 and C2 is performed to prepare for the time detection of the next downstream signal.

When the time of the monitoring level of the downstream signal of 18 volts is T ₀ time corresponding to the data bit 0, the capacitor C2 of the time constant circuit 39 reaches the reference voltage Vr after T ₀ time, and the output of the comparator 40 is 0. However, the charging voltage of the capacitor C1 of the time constant circuit 35 does not reach Vr, and the output of the comparator 36 remains zero.

  Therefore, the RS-FF 38 reads the output 0 of the AND gate 37 at the timing of the clock detection signal CK and outputs a data detection signal that becomes 0 as the Q output. As a result, a data detection signal as shown in FIG. 3C can be detected from a downstream signal that changes in two values, that is, a monitoring level of 18 volts and a signal level of 24 volts as shown in FIG.

  As shown in FIG. 3A, the chip select detection circuit 30 first detects that the downstream signal has increased from the monitoring level 18 volts to the signal level 24 volts, and performs the setting operation of the RS-FF 44. As shown in FIG. 3B, the chip select detection signal is set to the high level.

Then is the time of the monitoring level 18 volts above the inverting amplifier 34 is input is ₁ hour or T ₀ h T, hours constant circuit 42 corresponds to the long T ₂ hours than ₁ hour T corresponding to the data value 1 Te, which determines the time constant of the resistor R3 and the capacitor C3, thus the charging voltage of the capacitor C3 is the input of T ₁ times of the monitoring level 18 volts and T ₀ hours without reaching the reference voltage Vr, the comparator 43 The output holds 1.

Thereafter, the time of the monitoring level 18 volts down signal is interrupted is Continuing T ₂ hours, the charging voltage of the capacitor C3 of the time constant circuit 42 reaches the reference voltage Vr, the output of the comparator 43 rises from 0 to 1. For this reason, the reset operation of the RS-FF 44 is performed, and the chip select detection signal falls from the previous high level to the low level.

  Further, the chip select detection signal is given to the reset terminal R of the RS-FF 38 of the data detection circuit 29, and the forced reset operation of the RS-FF 38 is performed.

Next, the EEPROM 31 provided in the unique signal response unit 27 in FIG. 2 will be described. EEPROM31 is capable of storing a 32-bit data for each that address. In the EEPROM 31 of the present invention, number data for responding an upstream signal to a downstream signal from the receiver 1 is stored at a specific address, for example, address “38” .

FIG. 5 shows the EEPROM 31-11 to 31-mn provided in the fire detectors 4-11 to 4-mn of the sensor lines 18-1 to 18-m of FIG. 1, and stores the number data at the address "38" . Indicates the state. For example, taking the sensor line 18-1 as an example, the EEPROM 31-11 to 311-1n of each fire detector has data bits D0 from the receiver 1 side to the terminal end side among the 32-bit data of the address “38”. , D1,..., D31 are stored with unique number data having a bit value of 1 and all others having a bit value of 0. The number data at the address “38” of the sensor line 18-1 is the same for the other sensor lines 18-2 to 18-m.

For the fire detectors connected to each of the sensor lines 18-1 to 18-m in this way, the number data obtained by sequentially shifting the storage bit position of the bit value 1 in the EEPROM of the fire sensor of the same sensor line is stored. Thus, based on the downstream signal designating the readout operation of the address “38” from the receiver 1, the readout operation of the EEPROM of all the connection sensors is simultaneously performed for each sensor line unit, and the upstream signals are responded in order. Can be made.

Unique number data to be set to the terminating fire detector of each sensor line, is set common termination data bit position, for example, the data bit D31 in the address "38" in the EEPROM31 of each fire detector 4 In the disconnection monitoring of the sensor line by sending the downstream signal from the receiver, if no upstream signal is received at the specific bit timing for termination (data bit D31), it is automatically determined as a disconnection failure. May be.

  FIG. 6 shows a list of outputs to the inputs of the response signal E1 and the fire signal E2 by the EX-OR circuit 32 of FIG. 2 and upstream signals by the alarm circuit 22 based on the output of the EX-OR circuit 32. In FIG. 6, first, in a state where no downstream signal is output from the receiver 1 at the time of monitoring, both the response signal E1 and the fire signal E2 are at L level, and the output of the EX-OR circuit 32 is also at L level. The current as an upstream signal is zero.

When a down signal is received from the receiver 1 during monitoring and the EEPROM 31 sets the response signal E1 to the H level by reading out the specific data bit 1 at the address "38" , the fire signal E2 is at the L level at this time. The output of the EX-OR circuit 32 becomes H level. When the output of the EX-OR circuit 32 becomes H level, the transistor 23 of the alarm circuit 22 is switched, and the alarm current Ic determined by the resistance R is caused to flow between the sensor lines L-C. Is sent to the receiver 1 as an upstream signal.

  On the other hand, in the event of a fire, when the fire signal E2 is H level and the response signal E1 is L level, the output of the EX-OR circuit 32 is H level, and the transistor 23 of the alarm circuit 22 is switched. The alarm current Ic determined by the resistance R is caused to flow between the sensor lines L-C, and a fire signal is sent to the receiver 1.

  When an upstream signal is transmitted from the receiver 1 during the fire alarm, the response signal E1 output from the EEPROM 31 becomes H level at the read timing of the data bit 1, and therefore the output of the EX-OR circuit 32 is the response signal. During the period in which E1 is output, it becomes L level, the transistor 23 of the alarm circuit 22 is restored to OFF, and the fire alarm signal is set to 0 in which the alarm current is temporarily set to zero.

  For this reason, on the receiver 1 side, even when the fire alarm signal is being received, the fire signal is temporarily interrupted during that time, so that the upstream signal for the downstream signal from the fire detector 4 Recognizing that it is a response, it is possible to identify the fire detector that detected the fire.

  FIG. 7 is a timing chart showing the response operation of the upstream signal to the downstream signal from the receiver 1 of FIG. 1 with respect to the fire detector 4 of FIG. In FIG. 7, for the sake of simplicity of explanation, a case where a downstream signal is sent only to the sensor line 18-1 drawn from the monitoring circuit unit 7-1 of the receiver 1 is taken as an example. Yes.

FIG. 7 (A) based on an instruction from the monitoring control unit 14 that are provided on MPU6 the receiver 1 of FIG. 1, the binary output to the sensor lines 18-1 from the monitoring circuit 7-1 This is a downstream signal, which is changed between a monitoring level of 18 volts and a signal level of 24 volts. Further, the downstream signal has a monitoring level of 18 for the data value 1 as shown in FIG. The pulse width modulation is performed by setting the L level time to be volt to T ₁ hour, and the data value 0 to set the L level time to be the monitoring level 18 volt to T ₀ time shorter than that, and the downstream signal is transmitted.

  Such a downstream signal of the sensor line 18-1 is input to the clock detection circuit 28 of the fire detector 4 of FIG. 2, and a clock signal synchronized with the downstream signal as shown in FIG. Is supplied as a clock.

  Here, the clock signal in FIG. 7B has the same pulse width as the pulse width-modulated downstream signal, but the clock signal operates with its rising timing valid, so that the pulse width differs. Is not a problem.

Further, as shown in FIG. 7D, the first half of the data by the down signal is a dummy clock, a start bit, a read operation code, and an address bit. Therefore, pulse width modulation corresponding to data values 0 and 1 representing this is performed. However, since only the clock timing is given to the data bit used for the serial read output of the 32-bit data of the EEPROM 31 in the latter half, the downstream signal has a normal clock with a duty of 50%. In synchronization with this, the clock in FIG. 7B also detects a clock pulse with a duty of 50%. The duty is 50%, but operation is possible even in other cases (there is no restriction on the duty).

Further, as shown in FIG. 7C, the chip select detection circuit 30 detects a voltage increase from the first monitoring level 18 volts to the signal level 24 volts of the downstream signal in FIG. turned to H level, the chip select detection signals downstream signal is interrupted, the time to return to 18 volts, the monitoring is turned off to the L level is reached T ₂ hours of FIG.

FIG. 7D shows data detected by the data detection circuit 29. From the top, a dummy clock “00”, a start bit “1”, a read opcode “10”, an address bit “100110” (address “38” ), Further, the read timing corresponding to the 32-bit data bits D31 to D0 is output.

Of the 32 data bits D31-D0, taking as an example a fire detector 4-1n in FIG. 1, as shown in EEPROM31-1n 5, previously stores bit value 1 to the data bits D31 The remaining data bits D30 to D0 store the bit value 0, and the read bit output of the data bit D31 storing the bit value 1 becomes the response signal E1 output from the EEPROM 31-1.

Therefore, at the time of monitoring, as shown in FIG. 7E, the read bit output of the first data bit D31 storing the bit value 1 is input to the EX-OR circuit 32 with the response signal E1 as H level. The output is set to H level, the transistor 23 of the alarm circuit 22 is switched, and the alarm current Ic determined by the resistor R is caused to flow to the sensor line as a response current at the time of monitoring as shown in FIG. As a result, the fire detector 4-1n responds to the upstream signal with respect to the downstream signal from the receiver 1.

  Subsequently, an upstream signal response is made to the same sensor line in the order of the data bits D30 to D0 of the fire detectors 4-1, n-1 to 4-11, and the receiver 1 has a fire detector failure or not. Can be monitored.

  The receiver 1 stores the unique data bit position of each connected fire detector 4, and determines that the detector is normal if it receives upstream signals from all of the connected fire detectors. If no upstream signal is received at the stored data bit position, it is determined that the fire detector 4 corresponding to the data bit position is faulty, and an abnormal display is performed.

  In the receiver, the number of fire detectors 4 connected to the sensor line 18 is stored, the number of bits of the upstream signal is counted, and the number of connected sensor connections is compared. Then, it may be determined whether all the fire detectors are normal or abnormal.

  Further, if there is no response from a plurality of fire detectors, if the connection order of the fire detectors is known in advance, it can be determined where the sensor line 18 is disconnected, and a more detailed abnormality display. It can be performed.

  On the other hand, when a fire is detected by the fire detector 4-1n itself, the fire signal E2 output from the signal processing circuit 25 when the fire is detected becomes H level, and at this time, the response signal E1 is L level. The output of the EX-OR circuit 32 becomes H level, the transistor 23 of the alarm circuit 22 is switched, and the alarm current Ic determined by the resistor R is continuously detected from the time of the fire as shown in FIG. A fire signal is sent to the receiver through the line 18-1.

  When a down signal is output from the receiver 1 in order to search for a sensor that has detected a fire during such a fire alarm, a response signal is output at the bit output timing of the data bit D31 in FIG. Since E1 becomes H level and the fire signal E2 is also H level at this time, the output of the EX-OR circuit 32 becomes L level during the reading period of the data bit D31, and the transistor 23 is turned off. As shown in F), the alarm current is temporarily cut off, so that the receiver 1 can recognize the response timing of the upstream signal from the terminating fire sensor 3 to the downstream signal.

  Here, the voltage of the downstream signal is lowered, but the voltage is kept higher than the voltage at which the circuit inside the fire detector can operate normally.

On the other hand, in the fire detectors other than the fire detector 4-1n that does not detect the fire in the sensor line 18-1, an attempt is made to read the EEPROM address "38". The alarm detection circuit 33 provided in the specific signal response unit 27 detects the alarm of the fire detector 4-1n, the reading operation of the EEPROM is suppressed, and a fire is detected in response to the downstream signal for search accompanying the alarm alarm. No response is made from a fire detector that has not detected

Incidentally, FIG. 3, in the embodiment of FIG. 7, the downlink signal transmitted from the receiver sends a data value of 1 or 0 with varying L level time corresponding to the monitored level of 18 volts per phase one allows constant However, the present invention is not limited to this. For example, as shown in FIG. 8, the L level time of the monitoring level of 18 volts is not common, but the time of the H level of the signal level of 24 volts follows. Data values 1 and 0 may be output to the sensor line by pulse width modulation with different values .

  FIG. 9 is a circuit diagram showing an embodiment of the data detection circuit 29 and chip select detection circuit 30 of FIG. 2 for performing chip select detection and data detection when the signal level time of 24 volts in the downstream signal of FIG. 8 is changed. is there.

  In FIG. 9, the data detection circuit 29 is provided with inverters 50 and 51, a diode D1, a resistor R4, and a capacitor C4, and the chip select detection circuit 30 is provided with an inverter 52, a diode D2, a resistor R5, and a capacitor C5. .

  The inverter 50 receives a voltage pulse signal as shown in FIG. 10 (A), inverts it, and outputs the clock detection signal shown in FIG. 10 (B). The data detection circuit 29 rapidly charges the capacitor C4 through the diode D1 when the clock detection signal in FIG. 10B inverted by the inverter 50 is at the H level, and when the clock detection signal becomes L level, the data detection circuit 29 starts from the capacitor C4 through the resistor R4. It discharges along the path leading to the 50 L level output, and changes like a signal at point a in FIG.

The inverter 51 has a predetermined threshold value TH. During a discharge period with a short pulse width corresponding to the bit value 0, the point-a signal does not drop to the threshold value TH, and the data detection signal output from the inverter 51 maintains the L level. . The L level data detection signal is read as a data value 0 at the rising edge of the clock detection signal. When the clock detection signal rises to H level, the capacitor C4 is charged again.

With a long pulse width corresponding to the next bit value 1, the point-a signal falls below the threshold value TH during the discharge period in which the clock detection signal is at the L level, and from the inverter 51 when the threshold value TH falls. The data detection signal becomes H level. This H level data detection signal is read as data value 1 at the rising edge of the clock detection signal. When the clock detection signal rises to H level, the capacitor C4 is charged again.

When the clock detection signal in FIG. 10B inverted by the inverter 50 falls from the H level to the L level corresponding to the bit value 0, the chip select signal detection circuit 30 also receives the input of the inverter 52 via the diode D2. 10B, the chip select detection signal in FIG. 10F output from the inverter 52 rises to the H level.

  Subsequently, when the clock detection signal rises from the L level to the H level, charging of the capacitor C5 is started via the resistor R5. For this reason, the input of the inverter 52 increases like the signal b in FIG. 10E, but before the threshold value TH of the inverter 52 is reached, the clock detection signal becomes L level, and the chip select detection signal maintains H level. To do.

Even during the L level period of the clock detection signal corresponding to the next bit value 1, the chip select detection signal from the inverter 52 maintains the H level. When the clock detection signal rises from the L level to the H level, charging of the capacitor C5 starts again. When the voltage pulse signal ends and the H level state of the clock detection signal is maintained, the charging of the capacitor C5 is performed during that time. The point b signal reaches the threshold value TH of the inverter 52, and the chip select detection signal returns to the L level. The time until the point b signal rises to the threshold value TH from the start of charging of the capacitor is set by the capacitor C5 or the like so as to be T2.

In addition, as for the stored data of the address “38” in the EEPROM of FIG. 5, the number of fire detectors provided in each line corresponding to the data size of 32 bits is taken as an example, This is the case where the maximum number of fire detectors that can be connected to one line is set to the maximum configuration. If the number is other than the maximum configuration, the necessary number of fire detectors can be provided for each detector line. The fire detector located at the end of the line may be the end fire detector.

  FIG. 11 is a time chart of the downstream signal according to the present invention in which the control type for the fire detector side is set according to the length of the signal level time for the downstream signal that changes with the binary value of the monitoring level of 18 volts and the signal level of 24 volts. is there.

In FIG. 11, three controls of (1) response control, (2) fire monitoring control, and (3) fire test control are taken as an example of control for the fire detector.

FIG. 11A shows response control. In this example, the time of a signal level of 24 volts is set to T ₀ for the control code portion of the start bit, control code, and address bit as control data. . The FIG. 11 (B) is a downlink signal of a fire monitoring control, and a 24 volt signal levels of time corresponding to the control code is set to T ₁ times. Further, FIG. 11 (C) is a fire test control has set a 24 volt signal level time T _2.

11 detects the length of the three types of 24 volt signal levels in FIG. 11 on the fire detector side, executes response control if the detection time is T ₀ , and executes fire monitoring control if the time is T ₁ time. In addition, if it is T ₂ hours, fire test control is executed.

  FIG. 12 is a block diagram of the fire detector 4 used in the present invention having the control functions of FIG.

In FIG. 12, the fire detector 4 is provided with a rectification / noise absorption circuit 21, an alarm circuit 22, a power supply circuit 24, a signal processing circuit 25, a detection circuit 26, a specific signal response unit 27, and a test circuit 46.

  The unique signal response unit 27 includes a clock detection circuit 28, a data detection circuit 29, a chip select detection circuit 30, an EEPROM 31, an EX-OR circuit 32, and a notification detection circuit 33 as in the embodiment of FIG. In addition, a function switching circuit 45 and a fall detection circuit 47 are provided for fire test control. Further, a recovery transistor 48 is connected to the alarm circuit 22 in series with the transistor 23.

Here, the data detection circuit 29 is configured to perform the response control T ₀ time of FIG. 11A, the fire monitoring T ₁ time of FIG. 11B, and the 11 C of the downlink signal transmitted from the receiver. It has a T ₂ hour detection function for fire test control, and for response control and fire monitoring control detection, the output to the function switching circuit 45 is stopped and the output of the EEPROM 31 is supplied to the EX-OR circuit 32. When the test control is detected, the function switching circuit 45 is switched, and the output of the EEPROM 31 is output to the test circuit 46 and the fall detection circuit 47.

Therefore, the data of the bit value 1 at the specific bit position read from the EEPROM 31 based on the detection of the clock, data, and chip select signals by the down signal for the fire test control is transferred from the function switching circuit 45 to the test circuit 46. The test circuit 46 forcibly activates the detection element of the detection circuit 26 to generate a test report.

  In response to the output of the detection circuit 26 by this test report, the signal processing circuit 25 outputs a fire signal E2 to the EX-OR circuit 32, and since the response signal E1 from the EEPROM 31 is 0, the EX-OR circuit 32 Becomes the high level, and the transistor 23 is turned on.

On the other hand, the fall detection circuit 47 always turns on the recovery transistor 48, but detects the fall timing of the output of the bit value 1 from the EEPROM 31, and turns off the transistor 48. Therefore, in the fire test control, after the transistor 23 is turned on by the test notification of the detection circuit 26, the transistor 48 is turned off at the timing when the output of the bit value 1 from the EEPROM 31 is cut off. As a result, the bit of the EEPROM 31 is turned off. The test alert signal by the fire test control is returned to the receiver 1 over the output period of value 1.

  On the other hand, regarding the operation at the time of monitoring or fire alarm, since the function switching circuit 45 connects the output of the EEPROM 31 to the EX-OR circuit 32, the test control function is disconnected, as shown in FIG. The response operation corresponding to the downstream signal from the receiver 1 as in the case of the fire detector 4 or the response operation corresponding to the downstream signal for searching during the fire alarm can be performed.

FIG. 13 is a timing chart of the control operation for the fire detector having the fire test control function of FIG. FIG. 13A shows a downlink signal. In correspondence with FIG. 11C, a downlink signal section corresponding to the control code is transmitted as a downlink signal with a time of a signal level of 24 volts being T ₂ hours. Yes.

Downlink signal of the T ₂ hours is determined by the data detection circuit 29 as a fire test control signals, 13 a control code indicating the example fire test control as the control code data (D) "11" is decoded. Based on this, the function switching circuit 45 switches the output of the EEPROM 31 to the test circuit 46 and the fall detection circuit 47, and in the read operation of the address “38” by the address bit following the control code, for example, as shown in FIG. When the data bit D31 has a bit value of 1 and all other bits have a bit value of 0, a test report current by fire test control can be sent to the receiver at the output timing of the bit value 1 of the data bit D31.

  The setting of the control type depending on the length of one of the two signal levels of the downlink signal from the receiver is shown in FIG. 3 in addition to the setting of the signal level of 24 volts in the downlink signal in FIG. Of course, it may be set by the length of the monitoring level of 18 volts.

In FIG. 11, the control time is determined by setting the level time as the control code for the read control of the EEPROM 31 provided in the fire detector, but different time lengths such as T ₀ , T ₁ , T _2. It is also possible to send a downstream signal directly to the fire detector, determine the control type from the time length on the fire detector side, and directly execute the control process.

  FIG. 14 is a circuit block diagram showing another embodiment of the fire detector 4 of FIG. 1, which is characterized by excluding the alarm detection circuit 33 provided in the embodiment of FIG. The operation is the same as in the embodiment of FIG.

In the embodiment of FIG. 14, since all the fire detectors connected to the same line for the downstream signal from the receiver 1 output response signals at a specific timing, the response current at the time of fire is As shown in FIG. 15 (F), following the interruption of the fire response current at the read timing of the data bit D31, which is the confirmation response of the fire detector that issued the fire, the data bits D31 to D0 of all the remaining fire detectors so that the current of the acknowledgment signal to the fire Wazawai応 answer current is superimposed read timing.

FIG. 16 is a circuit block diagram of an embodiment of the fire detector 4 according to the present invention in which fire test control is performed with a signal level time of 24 volts in a downstream signal that changes in binary. Further, in the embodiment , the control is performed by changing the pulse width of the data bit transmitted from the receiver. In the embodiment of FIG. 16, a T3 timer 60 is provided in the embodiment of FIG. 14, and the fire test is performed by adding the output of the T3 timer circuit 60 to the detection circuit 26 as a fire test control signal E3.

Figure 17 is a fire test control in the embodiment of FIG. 16, the bit value of data bit D30 in the 32-bit data in EEPROM31 address "38" 1 and to which fire detectors, i.e. detectors address "30" This shows the case where the fire detector is used.

First, as shown in the down signal of FIG. 17A, the signal level time of 24 volts of the down signal corresponding to the sensor address “30” is added to the predetermined time T3 and the fire test reporting time Tt is added ( T3 + Tt).

On the other hand, for the fire detectors whose data bits D31 and D29 to D0 are not subjected to the fire test control and whose bit value is 1 , that is, the fire detectors having the detector addresses “31” and “29” to “0” , The signal level time of the volt is a predetermined T0 time.

In response to such a downstream signal from the receiver 1, in the fire detector having the sensor address “30” , the response signal E1 by reading the data bit D30 is (T3 + Tt) as shown in FIG. Since the data is output from the EEPROM 31, the T3 timer circuit 60 outputs the fire test control signal E3 to the detection circuit 26 for the time Tt as shown in FIG. .

  At this time, if the detection circuit 26 and the signal processing circuit 25 are normal, the fire detection circuit 26 issues a test report, and a fire signal E2 is output from the signal processing circuit 25. As shown in FIG. The response current output to the receiver 1 is cut off based on the response signal E1 from the reading of.

In this case, the receiver 1 detects the rise of the response current for T3 time and the recovery of the subsequent Tt time, and determines that the fire detector at the sensor address “30” is normal.

On the other hand, if the detection circuit 26 and the signal processing circuit 25 are abnormal, the fire signal E2 is not output, and the response current is not recovered after T3 time and is output for (T3 + Tt) time as shown in FIG. Is done. For this reason, the receiver 1 determines that the fire detector with the sensor address “30” is abnormal because the response current does not recover after T3 time.

Furthermore, if there is no fire detector with sensor address “30” or if it is completely faulty, the response current does not flow at the start of the fire test control in the downstream signal that reads data bit D30, so this is received. The machine 1 judges that it is abnormal. As described above, as shown in FIGS. 16 and 17, in the embodiment in which the pulse width of the data bit is changed, various kinds of control designating a specific terminal can be performed.

  FIG. 18 is a circuit block diagram of another embodiment of the fire detector 4 according to the present invention in which fire test control is performed based on a signal level time of 24 volts in a downstream signal that changes in binary.

  In the embodiment of FIG. 18, an AND circuit 62 is provided instead of the T3 timer 60 of the embodiment of FIG. 16, and the response signal E1 from the EEPROM 31 and the data detection signal from the data detection circuit 29 are input to the AND circuit 62. The fire test is performed by adding the output of the AND circuit 62 to the detection circuit 26 as a fire test control signal E3.

Figure 19 is a fire test control in the embodiment of FIG. 18, the data bit D30 in the 32-bit data in the address 30 of the EEPROM31 as bit value 1 with which the fire detector, i.e. detectors fire of address "30" This shows the case where the container is used.

First, as shown in the down signal of FIG. 19A, the signal level time of 24 volts of the down signal from the receiver corresponding to the sensor address “30” is detected by the detection circuit 26 and the signal processing circuit by the fire test control signal. It is a time (Td + Tt) obtained by adding a fire test reporting time Tt to 25 response delay times Td.

On the other hand, for the fire detectors whose data bits D31 and D29 to D0 are not subjected to the fire test control and whose bit value is 1 , that is, the fire detectors having the detector addresses “31” and “29” to “0” , The signal level time of the volt is a predetermined T0 time. In order to perform fire test control of all the fire detectors, the signal level time of 24 volts for each downstream signal used for reading data bits D31 to D0 may be (Td + Tt) time.

In response to such a downstream signal from the receiver 1, in the fire detector having the sensor address “30” , the response signal E1 by reading the data bit D30 is time (Td + Tt) as shown in FIG. The data detection signal is also output from the data detection circuit 29 for (Td + Tt) time, and the AND circuit 62 outputs the fire test control signal E3 to the detection circuit 26 to perform the fire test operation. Make it.

If the detection circuit 26 and the signal processing circuit 25 are normal at this time, the fire signal E2 is output from the signal processing circuit 25 after the internal delay time Td, and a response signal by reading the data bit D30 as shown in FIG. The response current output to the receiver 1 based on E1 is cut off. In this case, the receiver 1 detects the rise of the response current Td time and the recovery of the subsequent Tt time, and determines that the fire detector at the sensor address “30” is normal.

On the other hand, if the detection circuit 26 and the signal processing circuit 25 are abnormal, the fire signal E2 is not output, and the response current is not recovered after Td time and is output for (Td + Tt) time as shown in FIG. The For this reason, the receiver 1 determines that the fire detector with the sensor address “30” is abnormal because the response current does not recover after the time Td.

Furthermore, if there is no fire detector with sensor address “30” or if it is completely faulty, the response current does not flow at the start of the fire test control in the downstream signal that reads data bit D30, so this is received. The machine 1 judges that it is abnormal.

  In this embodiment, the disconnection of the sensor line is determined based on the presence / absence of a return signal from the fire detector for termination. However, as shown in FIG. Monitoring by resistance may be performed to determine whether the detector is normal and to specify or control the fire alarm terminal with the configuration of the fire detector of FIG.

  In the fire detector of the present embodiment, the reading of the EEPROM address bits is used to monitor the detector function, identify the fire detector that detected the fire, or control the detector. Not limited to this, a CPU may be provided in the fire detector to perform the same operation.

  For example, for the downstream signal for confirmation from the receiver during normal monitoring, the sensor line is temporarily short-circuited at a timing specific to each sensor, and the sensor line is continued when a fire is detected. The same operation can be performed such as temporarily releasing the short circuit of the short-circuited sensor line when the sensor is specified at the time of fire alarm.

  Furthermore, it is also possible to receive a control signal with a variable pulse width of the downstream signal, detect the time of one of the signal levels, and execute a control process of a predetermined type corresponding to the detection time. In this case, it can also be achieved by eliminating the EX-OR circuit, the EEPROM and the like.

Explanatory drawing of the fire alarm system of the present invention Block diagram of the fire detector of FIG. Time chart of data detection processing by downstream signal and data detection circuit of FIG. 2 in the present invention 2 is a circuit diagram showing an embodiment of the data detection circuit and chip select detection circuit of FIG. Explanatory drawing of EEPROM address and stored data in fire detector of FIG. Explanatory drawing of the logical table of specific signal response and fire alarm by EX-OR circuit of FIG. Timing chart of specific signal response operation by EEPROM reading in fire detector of FIG. Time chart of other data detection processing by the data detection circuit of FIG. 2 when the EEPROM read clocks are uneven. FIG. 2 is a circuit diagram showing an embodiment of the data detection circuit and chip select detection circuit of FIG. Time chart showing signal waveforms of each part in FIG. Downstream signal time chart of the present invention in which the control type is set according to the length of time Block diagram of a fire detector used in the present invention with a fire test function Timing chart of response operation when fire test control of fire detector of FIG. 10 is performed using the down signal of FIG. The circuit block diagram which showed other embodiment of the fire detector of FIG. Timing chart of specific signal response operation by reading EEPROM in fire detector of FIG. A circuit block diagram of an embodiment of a fire detector according to the present invention that performs fire test control according to a 24 volt signal level time of a downstream signal Timing chart of fire test control in fire detector of FIG. Circuit block diagram of another embodiment of a fire detector according to the present invention that performs fire test control according to a 24 volt signal level time of a downstream signal Timing chart of fire test control in fire detector of FIG. Illustration of a conventional P-type fire alarm system Timing chart of sensor response operation in a conventional P-type fire alarm system in which the downstream signal is a ternary voltage level

1: Receiver 4: Fire detector 6: MPU
7-1 to 7-m: monitoring circuit unit 8: operation unit 9: alarm display unit 10: district display unit 11: transfer output unit 12: memory 13: reception control unit 14: monitoring control unit 15: voltage control circuit 16 : Output buffer circuit 17: Current detection circuit 18-1 to 18-m: Sensor line 21: Rectification / noise absorption circuit 22: Alarm circuit 23, 48: Transistor 24: Power supply circuit 25: Signal processing circuit 26: Detection circuit 27: Unique signal response unit 28: Clock detection circuit 29: Data detection circuit 30: Chip select detection circuit 31: EEPROM (nonvolatile memory)
32: EX-OR circuit 33: Alarm detection circuit 34: Inverting amplifier 35, 39, 42: Time constant circuit 36, 40, 41, 43: Comparator 37: AND gate 38, 44: RS-FF
45: Function switching circuit 46: Test circuit 47: Falling detection circuit 60: T3 timer 62: AND circuit

Claims (5)

In a fire alarm system that connects a plurality of fire detectors to a sensor line drawn out from a receiver, receives a warning signal from the fire detector for each sensor line, and warns.
Provided in the receiver, the sensor downstream signals of the line at every predetermined constant period, different between the two signal levels at varying alternately, and wherein the two times of the length of the signal level of the certain period A transmission circuit unit that represents any one of the binary values at a constant period, converts a desired binary signal into a downlink signal, and transmits the downlink signal;
A receiving circuit unit provided in the fire detector, which discriminates and outputs the binary signal from the downstream signal received from the sensor line based on the length of either one of the two signal levels within the fixed period. When,
Provided ,
The transmission circuit unit of the receiver converts a binary signal for reading control of a nonvolatile memory such as an EEPROM provided in the fire detector into the downlink signal and transmits the signal,
The reception circuit unit of the fire detector receives a downstream signal from the sensor line and detects a read control signal including a read code and an address of the nonvolatile memory, a clock signal, and a chip select signal. Fire alarm system.
In the fire alarm system according to claim 1,
The transmission circuit unit of the receiver alternately changes the downstream signal voltage of the sensor line between a predetermined monitoring level and a predetermined signal level lower than the predetermined monitoring level, and increases or decreases the time of the monitoring level and the signal level. To convert the binary signal into a downstream signal and transmit it,
The receiving circuit unit of the fire detector discriminates and outputs the binary signal based on the length of either the monitoring level or the signal level from the downstream signal received by the sensor line. Fire alarm system.
2. The fire alarm system according to claim 1 , wherein the fire detector has unique number data in which a bit at a specific position is distinguished from other bits at a predetermined address of the nonvolatile memory. A fire characterized by transmitting a unique response uplink signal at a 1-bit output timing of the specific position in response to an operation of reading the number data designating the predetermined address from the receiver Notification system.
In the fire alarm system according to claim 1,
The transmission circuit unit of the receiver transmits a downlink signal that is distinguished from the binary signal in which the time of either one of the two signal levels is different for each predetermined control type,
The reception circuit unit of the fire detector receives a downstream signal from the sensor line, detects a time of one of the signal levels distinguished from the binary signal, and determines in advance corresponding to the detection time A fire alarm system characterized by executing various types of control processing.
In the fire alarm system according to claim 4 ,
The transmission circuit unit of the receiver has a predetermined monitoring level or a predetermined signal level lower than the predetermined monitoring level corresponding to each of the sensor response control, the fire monitoring control, and the fire test control. Set and send a downlink signal according to each control,
The reception circuit unit of the fire sensor receives a downstream signal from the sensor line, detects either the monitoring level or the signal level, and controls the sensor response control in response to the detection time. A fire alarm system that performs control processing of either monitoring control or fire test control.

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