JP4547084B2

JP4547084B2 - Mobile communication device and transceiver

Info

Publication number: JP4547084B2
Application number: JP2000352553A
Authority: JP
Inventors: 聡田中; 一雄渡辺; 正生堀田; 豊彦本郷; 大造山脇; 真澄笠原; 久美子瀧川
Original assignee: Renesas Electronics Corp
Current assignee: Renesas Electronics Corp
Priority date: 1999-11-15
Filing date: 2000-11-15
Publication date: 2010-09-22
Anticipated expiration: 2020-11-15
Also published as: JP2001211098A

Description

【０００１】
【発明の属する技術分野】
本発明は、部品点数を低減できる移動体通信機に係り、特に大規模集積化に適したダイレクトコンバージョン方式を適用した送受信機に関するものである。
【０００２】
【従来の技術】
移動体通信機の爆発的な普及につれ、小型、低コスト化への要求が強まっている。そのため、ＶＣＯ（電圧制御形発振器）や、フィルタ数を低減し、集積度を上げた集積回路の適用が望まれている。送受信機の従来例としては瀧川等によりアイ、イー、イー、イー、１９９９年、第２５回、欧州集積回路会議予稿集２７８頁から２８１頁に発表された「ＧＳＭ、ＤＣＳ１８００向けデュアルバンドトランシーバＩＣ高周波技術」(K. Takikawa et. al. RF Circuits Technique of Dual-Band Transceiver IC for GSM and DCS1800 applications, IEEE 25^th European Solid-State Circuits Conference pp. 278-281, 1999)狽ェ挙げられる。構成図を図１０（ａ）に示す。（１０１６）が集積回路で、他の構成部品（１００１〜１０１５）は外付けとなる。本従来例は９００ＭＨｚ帯と１．８ＧＨｚ帯の２つの周波数帯に対応するものである。また、受信機としてスーパーヘテロダイン方式を適用し、送信機にはオフセットＰＬＬ方式を採用している。スーパーヘテロダイン受信機では、帯域外妨害波を抑圧するＲＦ（高周波）フィルタ（１００１，１００２）２個と、周波数変換に伴うイメージ周波数帯の妨害波を取り除くイメージ除去フィルタ（１００３，１００４）２個と、受信チャネル近傍の妨害波を除去するＩＦ（中間周波）フィルタ（１００５）が必要になる。また９００ＭＨｚ帯と１．８ＧＨｚ帯の２つの周波数帯に対応するため局部発振器（１００６，１００７）が２個必要となる。
【０００３】
外付け部品点数を削減できる受信方式に、ダイレクトコンバージョン方式がある。ダイレクトコンバージョン受信機の従来例としてはアイ、イー、イー、イー、１９９７年、ＶＬＳＩ回路シンポジウム予稿集１１３頁から１１４頁に発表された「９００ＭＨｚダイレクトコンバージョン受信機」（Behzad Razavi, "A 900-MHz CMOS Direct Conversion Receiver," IEEE Symposium on VLSI Circuits,pp. 113-114, 1997）が挙げられる。構成図を図１０（ｂ）に示す。原理的にイメージ応答が存在しないので、ダイレクトコンバージョン方式にはイメージ除去フィルタが不要である。また、ＩＦフィルタはＩＣに集積化されたフィルタで代用できるため不要となる。本従来例では、ＶＣＯ（１０２５）は受信機の入力周波数の２倍の周波数で発振し、その周波数は１８５０〜１９２０ＭＨｚである。この受信機をＧＳＭ，ＤＣＳ１８００のデュアルバンド受信機に適用する場合、ＶＣＯ（１０２５）は１８５０〜１９２０ＭＨｚ（ＧＳＭ）と３６１０〜３７６０ＭＨｚ（ＤＣＳ１８００）で発振する必要がある。しかし、これらの周波数帯を１つのＶＣＯでカバーするのは困難でありＶＣＯは２個必要となる。
【０００４】
ダイレクトコンバージョン受信機の広く知られた欠点は、直流オフセット電圧である。これは、ミキサ（１０１９，１０２０）の入力信号と局発発振信号の周波数が等しいために生じる。例えば、局発発振信号が入力信号の入力端子にリークすると局発発振信号同士の掛け算が生じて直流オフセット電圧が発生する。直流オフセット電圧を校正する方式の従来例としてはアイ、イー、イー、イー、１９９５年、半導体素子回路ジャーナル１３９９頁から１４１０頁に発表された「デジタル通信向けダイレクトコンバージョントランシーバ」（Asad A. Abidi et. al., "Direct-Conversion Radio Transceivers for Digital Communications," IEEE Journal of Solid-State Circuits, pp. 1399-1410, vol. 30, no. 12,Dec.,1995）が挙げられる。構成図を図１１に示す。可変利得増幅器（１１０２，１１０４）と低域通過フィルタ（１１０１，１１０３，１１０５）からなる可変利得増幅器の出力直流オフセット電圧は、ＤＳＰ（１１０６）で検知される。その情報に基づいてＤＳＰ（１１０６）は、低域通過フィルタ（１１０１）の入力に直流オフセット電圧校正信号を出力する。
【０００５】
【発明が解決しようとする課題】
上記の様に、ダイレクトコンバージョン受信機は外付けフィルタ数を削減することができる。しかし、図１０（ａ）のＧＳＭ，ＤＣＳ１８００デュアルバンド送受信機でスーパーへテロダイン受信機の代わりにダイレクトコンバージョン受信機を使用すると、局発発信器の数が増加してしまう問題がある。なぜなら、局発発振周波数として送信機では１１５０〜１１８５ＭＨｚ（ＧＳＭ），１５７５〜１６５０ＭＨｚ（ＤＣＳ１８００）が、受信機では１８５０〜１９２０ＭＨｚ（ＧＳＭ）,３６１０〜３７６０ＭＨｚ（ＤＣＳ１８００）が必要で、１つのＶＣＯで複数の帯域をカバーするのは困難だからである。さらなるコスト削減のため、ＶＣＯ数を削減することが第１の課題となる。
【０００６】
また、ＧＳＭシステムで高速データ通信を実現するＧＰＲＳ（ＧｅｎｅｒａｌＰａｃｋｅｔＲａｄｉｏＳｅｒｖｉｃｅ）では受信または送信に複数のスロットが割り当てられる。そのため高速な直流オフセット電圧校正が要求される。また、直流オフセット電圧校正は動作フレーム毎に行う必要がある。まず高速なオフセット校正の必要性から図４を用いて説明する。ＧＳＭの１フレームは８スロットから構成され、１スロットの時間は５７７μｓｅｃである。直流オフセット電圧校正にとって厳しい条件、すなわち受信（ＲＸ）に４スロット、送信（ＴＸ）に１スロット割り当てられた場合を想定する。送信スロットＴＸ１’はスロット７に割り当てられるが、基地局への伝播遅延を考慮してスロット７から２３７μｓｅｃ前のＴＸ１のタイミングで送信される。また、送受信以外に約５００μｓｅｃのモニタ期間とＰＬＬの同期期間が必要である。ＰＬＬ同期期間に１５０μｓｅｃ程度かかるとすると、送受信回路が動作せず直流オフセット電圧校正を行える時間は、１１５４−５００−２３７−１５０*２＝１１７μｓｅｃとなり、高速なＤＣオフセット校正が要求される。
【０００７】
次に、フレーム毎にオフセット校正を行う必要性について図５を用いて説明する。図５に、ミキサの出力直流オフセット電圧の受信周波数依存性を測るための測定回路とその測定結果を示す。測定結果から、出力直流オフセット電圧には周波数依存性があることが分かる。したがって、ＧＳＭ,ＤＣＳ１８００の様に通話中の受信周波数が固定でなく、受信帯域内で周波数ホッピングするシステムでは、前もって直流オフセット電圧を予見することは困難である。したがって、動作フレーム毎に直流オフセット電圧を校正する必要がある。
【０００８】
従来例（図１１）の方式はオフセット校正用の帰還ループ内にフィルタが介在するため高速なオフセット校正が困難で高速データ通信に不向きである。したがって、高速データ通信に適した高速なオフセット校正方式の実現が第２の課題である。
【０００９】
【課題を解決するための手段】
上記第１の課題を実現するために、本発明では１つのＶＣＯから分周器を利用して受信機と送信機にＲＦ帯の局部発振信号を供給する。受信機用の局部発振信号生成には分周比固定の分周器を用い、送信機用の局部発振信号生成には分周比の切り替えが可能な分周器を用いる。
【００１０】
上記第２の課題を実現するために、本発明ではベースバンド信号用の可変利得増幅器に直流オフセット電圧検出手段と、直流オフセット校正手段を設け、オフセット校正用の帰還ループ内にフィルタを介在させないことで高速に直流オフセットを校正する。
【００１１】
【発明の実施の形態】
本発明の第１の実施形態を図１を用いて説明する。ここではアプリケーションとして欧州セルラ電話ＧＳＭ（９００ＭＨｚ帯）、ＤＣＳ１８００（１８００ＭＨｚ帯）に対応する例を用いる。
【００１２】
受信機にはＲＦ信号を直接ベースバンド信号に変換するダイレクトコンバージョン方式を適用し、送信機には従来例ですでに示したオフセットＰＬＬ方式を採用している。受信機は低雑音増幅器（１０１，１０２）、ミキサ（１０３，１０４）、可変利得低域通過フィルタ（１３９）から構成される。ミキサでは信号周波数をＲＦ帯からベースバンド帯へ変換するとともに、sin成分とcos成分に分離する復調も同時に行う。このためミキサ（１０３，１０４）に９０°位相の異なる局部発振信号を加える必要があり、分周器（１０５,１１５）を用いて生成する。局部発振信号は、ＶＣＯ（１１１）とＰＬＬ（１１２）でＰＬＬループを組むことで発生させる。ＶＣＯ（１１１）として３６００ＭＨｚ帯発振のものを用いれば、分周器（１１５）の出力は１８００ＭＨｚ帯となりＤＣＳ１８００用の局部発振信号を得る。また、分周器（１１６）を分周器（１０５）の前段に配置することで、分周器（１０５）の出力周波数は９００ＭＨｚ帯となり、ＧＳＭ用局部発振信号を得る。ミキサ（１０３,１０４）の出力ベースバンド信号は可変利得低域通過フィルタ（１３９）に入力され、レベル調整と妨害波除去が行われる。可変利得低域通過フィルタ（１３９）は、低域通過フィルタ（１０６,１０７,１３７,１３８）と可変利得増幅器（１０８,１０９）から構成される。また、可変利得低域通過フィルタ（１３９）出力での直流オフセット電圧を抑圧するため、直流オフセット電圧検出手段と直流オフセット校正手段をもった直流オフセット電圧校正回路（１１０）を設ける。
【００１３】
外付け構成部品を減らすため、送信機でも受信機と同じＶＣＯ（１１１）を用いる。送信機で用いるＩＦ周波数（ｆＩＦ）の決め方を以下に説明する。アンテナ（１３６）で受信する受信周波数をｆｒ_G（ＧＳＭ）とｆｒ_D（ＤＣＳ１８００）、送信する送信周波数をｆｔ_G（ＧＳＭ）とｆｔ_D（ＤＣＳ１８００）とする。
前述の様に、ＶＣＯ（１１１）の発振周波数はＧＳＭ受信周波数の４倍、ＤＣＳ１８００受信周波数の２倍だから、ＶＣＯ（１１１）の発振周波数は、４・ｆｒ_G＝２・ｆｒ_Dと表すことができる。この発振周波数をｍ分周（ＧＳＭ）、ｎ分周（ＤＣＳ１８００）した信号をオフセットＰＬＬのミキサ（１２６）の局部発振信号として用いると、ＧＳＭ時のＩＦ周波数ｆＩＦ_Gは数式１の様に表せる。
【００１４】
【数１】

【００１５】
同様にＤＣＳ１８００時のＩＦ周波数ｆＩＦ_Dは数式２の様に表せる。
【００１６】
【数２】

【００１７】
ここで、ｆｒ_Ｇ＝９２５ＭＨｚ，ｆｔ_Ｇ＝８８０ＭＨｚ，ｆｒ_Ｄ＝１８０５ＭＨｚ，ｆｔ_Ｄ＝１７１０ＭＨｚとする。ｍに対してｆＩＦ_Ｇを計算したものを図１２に、ｎに対してｆＩＦ_Ｄを計算したものを図１３に示す。分周には２分周器を用いるので、ｍ，ｎとして２のｉ乗（ｉは正の整数）を用いた。ＩＦ周波数生成のためのＶＣＯを１個にするにはｍ，ｎは自由に選ぶことはできず、ｆＩＦ_ＧとｆＩＦ_Ｄはほぼ等しい必要がある。または、２分周器を使用した場合は、ｆＩＦ_ＧとｆＩＦ_Ｄの比が２のｊ乗（ｊは正の整数）にほぼ等しければよい。ここで、ほぼ等しいとは、２つの周波数が正確に一致しなくてもそれら２つがＶＣＯの発振周波数範囲に含まれていればよいという意味である。図１２、図１３において、上記条件を満たすｍとｎの組み合わせは、例えば、（ｍ，ｎ）＝（２，１）や（４，２）である。このｍ，ｎの組み合わせから、消費電力や不要スプリアス信号発生の有無等を考慮に入れて最終的にｆＩＦを決定する。本実施例では（ｍ，ｎ）＝（４，２）としてある。分周器（１１７，１１８）と切り替えスイッチ（１２１）をＶＣＯ（１１１）後段に設け、ＧＳＭ時にはＶＣＯ（１１１）出力周波数を４分周、ＤＣＳ１８００時には２分周する様に制御する。次に、ＶＣＯ（１１４）の発振周波数は、消費電力やＩＣに内蔵する受動素子の規模等によって決定される。本実施例では発振周波数を３００ＭＨｚ帯とし、ＶＣＯ（１１４）後段に分周器（１１９，１２０）と切り替えスイッチ（１２２）を設けることで、ＧＳＭ時には８分周、ＤＣＳ１８００時には４分周してｆＩＦ_Ｇ＝４５ＭＨｚ、ｆＩＦ_Ｄ＝９５ＭＨｚが生成される。
【００１８】
スプリアスの問題を更に具体的に説明する。図１７，１８にＩＦ周波数を固定し、局部発振周波数を変化させた場合のスプリアスを示す。図１７，１８はＧＳＭ、ＤＣＳ１８００に対応し、送信信号を送信用発振器（１２８、１２９）から発生させた場合に、ＩＦ周波数の整数倍（ｍ倍）と、局部発振周波数の差によって生じるスプリアスを示したものである。ここでｆＩＦはＩＦ周波数、ｆＶＣＯは送信周波数を示す。各欄に記入した数値はスプリアス信号と送信周波数の差をＭＨｚの単位で示したものである。ハッチをかけた部分は１０ＭＨｚ以内の近傍にスプリアスが発生する場合で、送信機のループフィルタ（１２７）で除去するのが困難なものである。図１７，１８より判るようにＩＦ周波数を１つに固定すると、送信帯域内でスプリアスが送信周波数の近傍に現れる領域を避けることが困難であり、ＩＦ周波数を送信周波数に応じて変化させることの有効性が理解される。例えば図１７に示すＧＳＭの例では、８８０ＭＨｚから８８８ＭＨｚまで４５ＭＨｚのＩＦ周波数を選び、８８８ＭＨｚから９１４ＭＨｚまで４６ＭＨｚのＩＦ周波数を選ぶとスプリアスを回避できる。
【００１９】
本実施例では送信機のミキサ回路（１２６）に印加される局部発振信号が受信帯域内に存在する。図１６に本実施例の送信部を拡大して示す。（２３０９）で示す経路を通じて受信帯域内に有る局部発振信号は漏洩し、後段の増幅器により増幅され放射される。ＧＳＭのスプリアスのほうしゃに関する規格を図１９にまとめる。受信帯域のスプリアスは、５点に限り-36 dBm以下のスプリアスが許容されるが、原則として-79dBm/100kHzに抑圧することが望まれる。図２０にこれまでの実施例で説明したＶＣＯの発振周波数をまとめる。ＤＣＳ1800の受信用帯域（２７０１）と送信用帯域（２７０３）は一致しており、ＧＳＭの受信用帯域（２７０２）と送信用帯域（２７０４）も同様に一致している。これをずらせる為図２１のような周波数配置を考える。ＤＣＳ1800の受信用帯域（２７０１）とずらせた送信用帯域（２７０５）は重なることなく、送信時に受信帯域内の周波数を持つ局部発振漏洩は回避できる。ＧＳＭについても同様である。
【００２０】
次に、本発明に係る受信機の第２の実施形態について図２を用いて説明する。
【００２１】
受信機は、低雑音増幅器（１０２）、ミキサ（１０４）、分周器（１０５）、低域通過フィルタ（１０６,１３７）、可変利得増幅器（１０８,２０１）、直流オフセット電圧校正回路（１１０，１１０ｂ）及びデコーダ（２０５）から構成される。また、低雑音増幅器は負荷抵抗（２０７）、トランジスタ（２０８）及び容量（２０９）から構成され、直流オフセット電圧校正回路（１１０）はデジタルアナログ変換器ＤＡＣ（２０２）、アナログデジタル変換器ＡＤＣ（２０３）及び制御回路（２０４）から構成される。ミキサ（１０４）は、ミキサ（２１０，２０６）から構成される。
【００２２】
可変利得増幅器（１０８）の出力直流電圧はＡＤＣ（２０３）でデジタル信号に変換され制御回路（２０４）へ入力される。制御回路（２０４）で、可変利得増幅器（１０８）出力での直流オフセット電圧が計測され、直流オフセット電圧を校正するための校正信号が出力される。該校正信号はＤＡＣ（２０２）でデジタル信号からアナログ信号に変換され、ＤＡＣ（２０２）出力信号により可変利得増幅器（１０８）の直流オフセット電圧が校正される。また、直流オフセット電圧校正回路（１１０）はデコーダ（２０５）により選択され、選択された回路だけが動作を行う。この様に、可変利得増幅器と直流オフセット電圧校正回路からなる帰還ループ内にフィルタが介在しないためフィルタでの遅延がなくなり高速なオフセット校正が実現できる。ここでＡＤＣのビット数は１ビットつまり単純な比較器を適用することも可能である。
【００２３】
本発明に係る可変利得増幅器と直流オフセット電圧校正回路の第３の実施形態について図３を用いて説明する。
【００２４】
可変利得増幅器は、抵抗（３０７，３０８,３１２）とトランジスタ（３０９，３１０，３１１）から構成される。トランジスタ（３０９，３１０）のベースに入力電圧が入力され、コレクタから出力電圧が出力される。利得は、例えば、トランジスタ（３１１）のベース電圧により制御することができる。ＤＡＣ（３１３）は、トランジスタ（３０１，３０２，３０３）と抵抗（３０４，３０５，３０６）から構成される。制御回路（２０４）の出力をトランジスタ（３０１，３０２，３０３）のベースに接続しているので、制御回路（２０４）でトランジスタ（３０１，３０２，３０３）のコレクタ直流電流を制御することができる。
該コレクタ直流電流はトランジスタ（３０９）のコレクタ電流と足し合わされ抵抗（３０７）で電圧に変換される。今、直流オフセット電圧ΔＶ（＝Ｖ₂−Ｖ₁）があるとする。抵抗（３０７，３０８）の抵抗値がＲ_L、ＤＡＣ（３１３）の出力直流電流をＩ_DAC1、ＤＡＣ（３１４）の出力直流電流をＩ_DAC2で表すことにする。この時、数式３の関係が成り立つ様に制御回路（２０４）はＤＡＣ（３１３，３１４）を制御する。
【００２５】
【数３】

【００２６】
本発明に係る可変利得増幅器の第４の実施形態について図６を用いて説明する。図６（ａ）に直流オフセット電圧のない理想的な可変利得増幅器（６０３）と可変利得増幅器（６０３）の入力換算直流オフセット電圧源（６０６）を示す。この場合、オフセット電圧を抑圧する手段がないので出力端子（６０４,６０５）の間にはオフセット電圧源（６０６）の出力電圧が可変利得増幅器（６０３）の利得倍されたオフセットが発生する。次に、本発明に係る第４の実施例である、切り替えスイッチ（６０７,６０８）を可変利得増幅器（６０３）の入出力に接続した構成を図６（ｂ,ｃ）に示す。切り替えスイッチ（６０７,６０８）の接続関係が図６（ｂ）と（ｃ）で逆になっているため、入出力端子間の接続関係は維持しつつオフセット電圧源（６０６）出力電圧の伝わる出力端子は逆になる。したがって、上記に示した切り替えスイッチ（６０７，６０８）の切り替えを周期的に行えば、オフセット電圧源（６０６）の出力電圧は出力端子（６０４）と（６０５）に同じ時間発生することになり、出力端子間のオフセット電圧は０になる。
【００２７】
本発明に係る受信機の第５の実施形態について図７を用いて説明する。本実施例は、第２の実施例において、可変利得増幅器（２０１）と直流オフセット電圧校正回路（１１０ｂ）の代わりに第４の実施例で示した可変利得増幅器（６０９）を用い、可変利得増幅器（６０９）後段に低域通過フィルタ（７０２）とバッファアンプ（７０１）を接続したことを特徴とする受信機である。
【００２８】
本発明に係る受信機の第６の実施形態について図８を用いて説明する。本実施例は、第２の実施例において、低域通過フィルタ（１４０）と可変利得増幅器（２０１）の間にスイッチ（８０１）を接続したことを特徴とする受信機である。
直流オフセット電圧校正時には、スイッチ（８０１）をオンにして可変利得増幅器（２０１）の入力を短絡し、校正時以外にはスイッチ（８０１）をオフにする。校正時にスイッチ（８０１）をオンにすることで、可変利得増幅器（２０１）は前段からの直流オフセット電圧の影響を受けずに校正を行うことができる。
【００２９】
本発明に係る移動体通信機の第７の実施形態について図９を用いて説明する。本実施例は、第１の実施例にベースバンド回路（９０１）を追加したことを特徴とする移動体通信機である。（９０７）には、第１の実施例においてアンテナ（１３６）とＩＣに内蔵される回路（１４３）以外のすべての回路が含まれる。ベースバンド回路（９０１）では、受信ベースバンド信号（９０２，９０３）から音声信号への変換や、音声信号から送信ベースバンド信号（９０５，９０６）への変換等の信号処理を行う。さらに、ベースバンド回路（９０１）は、回路（１４３）での直流オフセット電圧の校正を開始するタイミングを決めるＤＣオフセットキャンセル開始信号（９０４）を出力し、回路（１４３）に入力する。この開始信号は受信機が信号を受信開始する前に送られ、信号を受信する前に（１４３）の回路で発生する直流オフセットを除去する。
【００３０】
本発明に係る移動体通信機の第８の実施形態について図１４を用いて説明する。フィルタ（１４０）の容量（１４０３）と抵抗（１４０４，１４０５）の間にスイッチ（１４０１，１４０２）を挿入し、直流オフセット校正時の時定数を小さくする。これによりフィルタ（１４０）での伝搬遅延を短縮できるので図８に示す入力短絡用スイッチ（８０１）を使うことなく高速で直流オフセット校正が出来る。また、各増幅器（１０８，２０１）が図３に示すようにバイポーラトランジスタで構成された場合は、フィルタ抵抗（１４０４，１４０５）を介してベースバイアスが行われる。このため、ベース電流ばらつき、フィルタ抵抗ばらつきによるバイアスオフセットも含めて直流オフセット電圧を校正できる。これに対して、短絡用スイッチ（８０１）を用いる第６の実施例では該バイアスオフセットを校正できない。また、直流オフセットを前段から順に除去すると、残留誤差は後段の直流オフセット校正機能が除去するため、より高精度の直流オフセット除去が達成できる。
【００３１】
本発明に係る移動体通信機の第９の実施形態について図１５を用いて説明する。第８の実施例の様にフィルタの伝搬遅延を低減した場合は、直流オフセット電圧校正のための帰還ループ内にフィルタを介在できる。そのため、第８の実施例に比べてＡＤＣの数を削減でき回路規模を低減出来る。
【００３２】
【発明の効果】
本発明により従来のスーパーヘテロダイン形受信機を適用した場合に比べ、外付けフィルタ３個、外付けＶＣＯ１個削減することができる。さらにダイレクトコンバージョン受信機で問題となる直流オフセット電圧を高速で除去する方式をとることで、部品点数を削減しつつ、高速パケット伝送モードにも対応できる移動体通信機を実現できる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態を示す移動体通信機構成図。
【図２】本発明の移動体通信機の受信機部分構成図。
【図３】本発明の受信機の直流オフセットを除去する回路の詳細図。
【図４】ＧＳＭ規格における動作タイミング図。
【図５】ミキサ回路の発生する直流オフセット電圧測定方法と測定結果を示す図。
【図６】本発明に適用できるチョッパ形増幅器動作原理図。
【図７】本発明の受信機部分にチョッパ形増幅器を適用した場合の実施形態。
【図８】本発明の受信機に係る前段回路の影響なしに可変利得増幅器の直オフセット電圧校正を行う回路の構成図。
【図９】直流オフセット除去のためのタイミング信号がベースバンド回路から与えられることを示す図面。
【図１０】（ａ）従来のスーパーヘテロダイン方式を適用した移動体通信機構成図。（ｂ）従来のダイレクトコンバージョン受信機構成図。
【図１１】従来の直流オフセット電圧校正手法。
【図１２】ＧＳＭ動作時の送信機ＩＦ周波数を示す図。
【図１３】ＤＣＳ１８００動作時の送信機ＩＦ周波数を示す図。
【図１４】フィルタ容量を切り離し直流オフセット除去動作を加速する方法を示す図。
【図１５】フィルタ容量を切り離し直流オフセット除去回路を簡略化する方法を示す図。
【図１６】ＧＳＭ／ＤＣＳ１８００デュアルバンド送信回路を示す図。
【図１７】ＧＳＭ送信時スプリアス一覧を示す図。
【図１８】ＤＣＳ１８００送信時スプリアス一覧を示す図。
【図１９】ＧＳＭスプリアス規格を示す図。
【図２０】送信、受信の局部発振周波数帯が一致したＶＣＯ発振周波数配置を示す図。
【図２１】送信、受信の局部発振周波数帯が重ならないＶＣＯ発振周波数配置を示す図。
【符号の説明】
１０１、１０２低雑音増幅器
１０３、１０４、１２３、１２６、２０６、２１０、１０１９、１０２０ミキサ
１０５、１１５、１１６、１１７、１１８、１１９、１２０、１３９分周器
１０６、１０７、１２７、１３１、１３２、１３７、１３８、７０２、１０１２、１０１３, １０２１、１０２２、１１０１、１１０３、１１０５低域通過フィルタ
１０８、１０９、２０１、６０３、１１０２、１１０４可変利得増幅器
１１０直流オフセット電圧校正回路
１１１、１１４、１２８、１２９、１００６、１００７、１００８、１００９ＶＣＯ
１１２、１１３ＰＬＬ
１２１、１２２切り替えスイッチ
１２７位相比較器
１３０、１０１０、１０１１電力増幅器
１３３、１３４、１００１、１００２、１００３、１００４、１００５帯域通過フィルタ
１３５、１０１４アンテナスイッチ
１３６、１０１５アンテナ
１３９可変利得低域通過フィルタ
１４０、１０１６ IC内蔵回路
２０２ＤＡＣ
２０３ＡＤＣ
２０５デコーダ
７０１バッファアンプ
８０１、１４０１、１４０２、スイッチ
９０１ベースバンド回路
１４０３容量
１４０４、１４０５抵抗
２３０１、２３０２、２３０５、２３０６リミッタ増幅器
２３０３、２３０４、２３０７、２３０８低域通過フィルタ
２３０９送信用局部発振信号漏洩経路
２７０１、２７０２受信時ＶＣＯ発振周波数帯
２７０３、２７０４、２７０５、２７０６送信時ＶＣＯ発振周波数。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a mobile communication device capable of reducing the number of parts, and more particularly to a transceiver using a direct conversion method suitable for large-scale integration.
[0002]
[Prior art]
With the explosive spread of mobile communication devices, there is an increasing demand for miniaturization and cost reduction. Therefore, it is desired to apply a VCO (Voltage Controlled Oscillator) or an integrated circuit with a reduced number of filters and an increased degree of integration. As a conventional example of a transceiver, I. E., E. E., 1999, 25th, European Integrated Circuits Conference Proceedings, 278-281, “Dual Band Transceiver IC High Frequency for GSM, DCS1800” Technology '' (K. Takikawa et.al.RF Circuits Technique of Dual-Band Transceiver IC for GSM and DCS1800 applications, IEEE 25 ^th European Solid-State Circuits Conference pp. 278-281, 1999). A block diagram is shown in FIG. (1016) is an integrated circuit, and other components (1001 to 1015) are externally attached. This conventional example corresponds to two frequency bands of 900 MHz band and 1.8 GHz band. Further, a superheterodyne system is applied as a receiver, and an offset PLL system is employed as a transmitter. In the superheterodyne receiver, there are two RF (high frequency) filters (1001, 1002) for suppressing out-of-band jamming waves, and two image removal filters (1003, 1004) for removing jamming waves in the image frequency band accompanying frequency conversion In addition, an IF (intermediate frequency) filter (1005) for removing interference waves in the vicinity of the reception channel is required. Also, two local oscillators (1006, 1007) are required to support two frequency bands of 900 MHz band and 1.8 GHz band.
[0003]
There is a direct conversion method as a receiving method that can reduce the number of external parts. Conventional examples of direct conversion receivers include “900 MHz direct conversion receiver” (Behzad Razavi, “A 900-MHz”) published on pages 113 to 114 of the VLSI Circuit Symposium Proceedings in 1997. CMOS Direct Conversion Receiver, "IEEE Symposium on VLSI Circuits, pp. 113-114, 1997). A block diagram is shown in FIG. Since there is no image response in principle, the direct conversion method does not require an image removal filter. Further, the IF filter is unnecessary because it can be replaced by a filter integrated in the IC. Book Conventional In the example, the VCO (1025) oscillates at twice the receiver input frequency, which is between 1850 and 1920 MHz. When this receiver is applied to a dual band receiver of GSM and DCS1800, the VCO (1025) needs to oscillate at 1850 to 1920 MHz (GSM) and 3610 to 3760 MHz (DCS1800). However, it is difficult to cover these frequency bands with one VCO, and two VCOs are required.
[0004]
A widely known drawback of direct conversion receivers is the DC offset voltage. This occurs because the frequency of the input signal of the mixer (1019, 1020) is equal to the frequency of the local oscillation signal. For example, when the local oscillation signal leaks to the input terminal of the input signal, the local oscillation signals are multiplied together to generate a DC offset voltage. As a conventional example of a method for calibrating a DC offset voltage, “Direct Conversion Transceiver for Digital Communication” (Asad A. Abidi et al.) Published on pages 1399 to 1410 of Semiconductor Device Circuit Journal, I, E, E, E, 1995. al., “Direct-Conversion Radio Transceivers for Digital Communications,” IEEE Journal of Solid-State Circuits, pp. 1399-1410, vol. 30, no. 12, Dec., 1995). A block diagram is shown in FIG. Variable gain amplifier ( 1102, 1104 ) And low-pass filter ( 1101, 1103, 1105 ) Is detected by the DSP (1106). Based on the information, the DSP (1106) outputs a DC offset voltage calibration signal to the input of the low-pass filter (1101).
[0005]
[Problems to be solved by the invention]
As described above, the direct conversion receiver can reduce the number of external filters. However, if a direct conversion receiver is used instead of a superheterodyne receiver in the GSM / DCS1800 dual-band transceiver shown in FIG. 10A, there is a problem that the number of local oscillators increases. This is because the transmitter oscillation frequency requires 1150 to 1185 MHz (GSM) and 1575 to 1650 MHz (DCS1800), and the receiver requires 1850 to 1920 MHz (GSM) and 3610 to 3760 MHz (DCS1800). This is because it is difficult to cover this bandwidth. In order to further reduce the cost, the first problem is to reduce the number of VCOs.
[0006]
In GPRS (General Packet Radio Service) that realizes high-speed data communication in the GSM system, a plurality of slots are assigned to reception or transmission. Therefore, high-speed DC offset voltage calibration is required. Further, the DC offset voltage calibration needs to be performed for each operation frame. First, the necessity of high-speed offset calibration will be described with reference to FIG. One frame of GSM is composed of 8 slots, and the time of 1 slot is 577 μsec. Assume a strict condition for DC offset voltage calibration, that is, 4 slots for reception (RX) and 1 slot for transmission (TX). The transmission slot TX1 ′ is assigned to the slot 7, but is transmitted at the timing of TX1 237 μsec before the slot 7 in consideration of the propagation delay to the base station. In addition to transmission / reception, a monitor period of about 500 μsec and a PLL synchronization period are required. Assuming that the PLL synchronization period takes about 150 μsec, the time required for DC offset voltage calibration without operating the transmission / reception circuit is 1154-500-237-150 * 2 = 117 μsec, and high-speed DC offset calibration is required.
[0007]
Next, the necessity of performing offset calibration for each frame will be described with reference to FIG. FIG. 5 shows a measurement circuit for measuring the reception frequency dependence of the output DC offset voltage of the mixer and the measurement result. From the measurement results, it can be seen that the output DC offset voltage has frequency dependence. Therefore, it is difficult to predict the DC offset voltage in advance in a system in which the reception frequency during a call is not fixed, such as GSM and DCS1800, and frequency hopping is performed within the reception band. Therefore, it is necessary to calibrate the DC offset voltage for each operation frame.
[0008]
Conventional The method of FIG. 11 (FIG. 11) is not suitable for high-speed data communication because high-speed offset calibration is difficult because a filter is interposed in the feedback loop for offset calibration. Therefore, the realization of a high-speed offset calibration method suitable for high-speed data communication is a second problem.
[0009]
[Means for Solving the Problems]
In order to realize the first problem, in the present invention, a local oscillation signal in the RF band is supplied from one VCO to a receiver and a transmitter using a frequency divider. A frequency divider with a fixed division ratio is used for generating a local oscillation signal for a receiver, and a frequency divider capable of switching the frequency division ratio is used for generating a local oscillation signal for a transmitter.
[0010]
In order to realize the second problem, in the present invention, a variable gain amplifier for baseband signals is provided with DC offset voltage detection means and DC offset calibration means, and no filter is interposed in the feedback loop for offset calibration. To calibrate the DC offset at high speed.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
A first embodiment of the present invention will be described with reference to FIG. Here, examples corresponding to European cellular telephone GSM (900 MHz band) and DCS1800 (1800 MHz band) are used as applications.
[0012]
A direct conversion method for directly converting an RF signal into a baseband signal is applied to the receiver, and the offset PLL method already shown in the conventional example is adopted for the transmitter. The receiver includes a low noise amplifier (101, 102), a mixer (103, 104), and a variable gain low pass filter (139). In the mixer, the signal frequency is converted from the RF band to the baseband band, and at the same time, the demodulation for separating into the sin component and the cos component is simultaneously performed. For this reason, it is necessary to add local oscillation signals having a phase difference of 90 ° to the mixers (103, 104), which are generated using the frequency dividers (105, 115). The local oscillation signal is generated by forming a PLL loop with the VCO (111) and the PLL (112). If a VCO (111) having a 3600 MHz band oscillation is used, the output of the frequency divider (115) becomes the 1800 MHz band, and a local oscillation signal for DCS 1800 is obtained. Further, by arranging the frequency divider (116) in the preceding stage of the frequency divider (105), the output frequency of the frequency divider (105) becomes the 900 MHz band, and a GSM local oscillation signal is obtained. The output baseband signal of the mixer (103, 104) is input to the variable gain low-pass filter (139), where level adjustment and interference wave removal are performed. The variable gain low-pass filter (139) includes a low-pass filter (106, 107, 137, 138) and a variable gain amplifier (108, 109). Further, in order to suppress the DC offset voltage at the output of the variable gain low-pass filter (139), a DC offset voltage calibration circuit (110) having a DC offset voltage detection means and a DC offset calibration means is provided.
[0013]
In order to reduce external components, the transmitter uses the same VCO (111) as the receiver. A method for determining the IF frequency (fIF) used in the transmitter will be described below. The reception frequency received by the antenna (136) is fr. _G (GSM) and fr _D (DCS1800), the transmission frequency to be transmitted is ft _G (GSM) and ft _D (DCS1800).
As described above, since the oscillation frequency of the VCO (111) is four times the GSM reception frequency and twice the DCS1800 reception frequency, the oscillation frequency of the VCO (111) is 4 · fr. _G = 2 · fr _D It can be expressed as. When a signal obtained by dividing the oscillation frequency by m (GSM) and by n (DCS1800) is used as a local oscillation signal of the mixer (126) of the offset PLL, the IF frequency fIF at the time of GSM _G Can be expressed as Equation 1.
[0014]
[Expression 1]

[0015]
Similarly, IF frequency fIF at DCS1800 _D Can be expressed as Equation 2.
[0016]
[Expression 2]

[0017]
Where fr _G = 925 MHz, ft _G = 880 MHz, fr _D = 1805 MHz, ft _D = 1710 MHz. for m F IF _G FIG. 12 shows a calculation result of fIF with respect to n. _D FIG. 13 shows the result of calculating. Since a frequency divider is used for frequency division, 2 to the power of i (i is a positive integer) is used as m and n. To make one VCO for generating IF frequency, m and n cannot be selected freely. _G And fIF _D Must be approximately equal. Or, if a divide-by-2 is used, fIF _G And fIF _D It is sufficient that the ratio of is substantially equal to 2 to the power of j (j is a positive integer). Here, “substantially equal” means that the two frequencies need only be included in the oscillation frequency range of the VCO even if the two frequencies do not exactly match. 12 and 13, the combinations of m and n satisfying the above conditions are, for example, (m, n) = (2, 1) or (4, 2). From the combination of m and n, the final result is taken into account the power consumption and the presence / absence of unnecessary spurious signals. F Determine IF. In this embodiment, (m, n) = (4, 2). A frequency divider (117, 118) and a changeover switch (121) are provided in the subsequent stage of the VCO (111), and control is performed so that the VCO (111) output frequency is divided by 4 during GSM and by 2 during DCS1800. Next, the oscillation frequency of the VCO (114) is determined by the power consumption, the scale of passive elements built in the IC, and the like. In this embodiment, the oscillation frequency is set to a 300 MHz band, and by providing a frequency divider (119, 120) and a changeover switch (122) after the VCO (114), the frequency is divided by 8 at GSM and divided by 4 at DCS1800. _G = 45 MHz, fIF _D = 95 MHz is generated.
[0018]
The problem of spurious will be explained more specifically. 17 and 18 show the spurious when the IF frequency is fixed and the local oscillation frequency is changed. 17 and 18 correspond to GSM and DCS1800, and transmit signals are transmitted to transmission oscillators (128, 12). 9 ) Where In addition, the spurious generated by the difference between the integral multiple (m times) of the IF frequency and the local oscillation frequency is shown. Here, fIF represents the IF frequency, and fVCO represents the transmission frequency. The numerical values entered in each column indicate the difference between the spurious signal and the transmission frequency in units of MHz. The hatched part is a case where spurious is generated in the vicinity of 10 MHz, and it is difficult to remove by the loop filter (127) of the transmitter. 17 and 18, when the IF frequency is fixed to one, it is difficult to avoid a region where spurious appears in the vicinity of the transmission frequency in the transmission band, and the IF frequency can be changed according to the transmission frequency. Effectiveness is understood. For example, in the example of GSM shown in FIG. 17, spurious can be avoided by selecting an IF frequency of 45 MHz from 880 MHz to 888 MHz and selecting an IF frequency of 46 MHz from 888 MHz to 914 MHz.
[0019]
In this embodiment, the local oscillation signal applied to the mixer circuit (126) of the transmitter is present in the reception band. FIG. 16 shows an enlargement of the transmission unit of this embodiment. The local oscillation signal in the reception band leaks through the path indicated by (2309) and is amplified and radiated by the amplifier at the subsequent stage. FIG. 19 summarizes the standards related to GSM spurious brushes. As for the spurious of the reception band, spurious of −36 dBm or less is allowed only for 5 points, but in principle, it is desirable to suppress it to −79 dBm / 100 kHz. FIG. 20 summarizes the oscillation frequency of the VCO described in the embodiments so far. The DCS 1800 reception band (2701) and transmission band (2703) match, and the GSM reception band (2702) and transmission band (2704) also match. In order to shift this, a frequency arrangement as shown in FIG. 21 is considered. The transmission band (2705) shifted from the reception band (2701) of DCS 1800 does not overlap, and local oscillation leakage having a frequency within the reception band can be avoided during transmission. The same applies to GSM.
[0020]
Next, a second embodiment of the receiver according to the present invention Using FIG. explain.
[0021]
The receiver includes a low noise amplifier (102), a mixer (104), a frequency divider (105), a low pass filter (106, 137 ), Variable gain amplifier (108, 201), DC offset voltage calibration circuit (110, 201) 110b ) And a decoder (205). The low noise amplifier includes a load resistor (207), a transistor (208), and a capacitor (209). A DC offset voltage calibration circuit (110) includes a digital / analog converter DAC (202) and an analog / digital converter ADC (203). ) And a control circuit (204). The mixer (104) is composed of mixers (210, 206).
[0022]
The output DC voltage of the variable gain amplifier (108) is converted into a digital signal by the ADC (203) and input to the control circuit (204). The control circuit (204) measures the DC offset voltage at the output of the variable gain amplifier (108), and outputs a calibration signal for calibrating the DC offset voltage. The calibration signal is converted from a digital signal to an analog signal by the DAC (202), and the DC offset voltage of the variable gain amplifier (108) is calibrated by the DAC (202) output signal. The DC offset voltage calibration circuit (110) is selected by the decoder (205), and only the selected circuit operates. In this way, since no filter is interposed in the feedback loop composed of the variable gain amplifier and the DC offset voltage calibration circuit, there is no delay in the filter and high-speed offset calibration can be realized. Here, the number of bits of the ADC is 1 bit, that is, a simple comparator can be applied.
[0023]
A third embodiment of the variable gain amplifier and DC offset voltage calibration circuit according to the present invention will be described with reference to FIG.
[0024]
The variable gain amplifier includes resistors (307, 308, 312) and transistors (309, 310, 311). An input voltage is input to the bases of the transistors (309, 310), and an output voltage is output from the collector. The gain can be controlled by, for example, the base voltage of the transistor (311). The DAC (313) includes transistors (301, 302, 303) and resistors (304, 305, 306). Since the output of the control circuit (204) is connected to the base of the transistor (301, 302, 303), the collector DC current of the transistor (301, 302, 303) can be controlled by the control circuit (204).
The collector direct current is added to the collector current of the transistor (309) and converted into a voltage by the resistor (307). Now, the DC offset voltage ΔV (= V ₂ -V ₁ ). The resistance value of the resistor (307, 308) is R _L , The output DC current of the DAC (313) is I _DAC1 , The output DC current of the DAC (314) is I _DAC2 It will be expressed as At this time, the control circuit (204) controls the DAC (313, 314) so that the relationship of Formula 3 is satisfied.
[0025]
[Equation 3]

[0026]
A fourth embodiment of the variable gain amplifier according to the present invention will be described with reference to FIG. FIG. 6A shows an ideal variable gain amplifier (603) having no DC offset voltage and an input converted DC offset voltage source (606) of the variable gain amplifier (603). In this case, since there is no means for suppressing the offset voltage, an offset is generated between the output terminals (604, 605) by multiplying the output voltage of the offset voltage source (606) by the gain of the variable gain amplifier (603). Next, according to the present invention 4 A configuration in which the changeover switch (607, 608) is connected to the input / output of the variable gain amplifier (603) is shown in FIG. Since the connection relationship of the changeover switches (607, 608) is reversed in FIGS. 6B and 6C, the output from which the offset voltage source (606) output voltage is transmitted while maintaining the connection relationship between the input and output terminals. The terminals are reversed. Therefore, if the changeover switches (607, 608) described above are periodically switched, the output voltage of the offset voltage source (606) is generated at the output terminals (604) and (605) for the same time, The offset voltage between the output terminals becomes zero.
[0027]
A fifth embodiment of the receiver according to the present invention will be described with reference to FIG. This embodiment is different from the second embodiment in that the variable gain amplifier (201) and the DC offset voltage calibration circuit ( 110b ) 4 The receiver is characterized in that the variable gain amplifier (609) shown in the embodiment is used, and a low-pass filter (702) and a buffer amplifier (701) are connected to the subsequent stage of the variable gain amplifier (609).
[0028]
A sixth embodiment of the receiver according to the present invention will be described with reference to FIG. This embodiment is a receiver characterized in that a switch (801) is connected between a low-pass filter (140) and a variable gain amplifier (201) in the second embodiment.
At the time of DC offset voltage calibration, the switch (801) is turned on to short-circuit the input of the variable gain amplifier (201), and the switch (801) is turned off at times other than calibration. By turning on the switch (801) during calibration, the variable gain amplifier (201) can be calibrated without being affected by the DC offset voltage from the previous stage.
[0029]
A seventh embodiment of the mobile communication device according to the present invention will be described with reference to FIG. The present embodiment is a mobile communication device characterized in that a baseband circuit (901) is added to the first embodiment. (907) includes an antenna (13 in the first embodiment). 6 ) And a circuit (143) built in the IC. The baseband circuit (901) performs signal processing such as conversion from a reception baseband signal (902, 903) to an audio signal and conversion from an audio signal to a transmission baseband signal (905, 906). Further, the baseband circuit (901) outputs a DC offset cancel start signal (904) for determining the timing for starting calibration of the DC offset voltage in the circuit (143), and inputs it to the circuit (143). This start signal is sent before the receiver starts receiving the signal, and removes the DC offset generated in the circuit of (143) before receiving the signal.
[0030]
An eighth embodiment of a mobile communication device according to the present invention will be described with reference to FIG. Switches (1401, 1402) are inserted between the capacitor (1403) and the resistors (1404, 1405) of the filter (140) to reduce the time constant during DC offset calibration. As a result, the propagation delay in the filter (140) can be shortened, so that the DC offset calibration can be performed at high speed without using the input short-circuit switch (801) shown in FIG. Further, when each amplifier (108, 201) is composed of a bipolar transistor as shown in FIG. 3, a base bias is performed via a filter resistor (1404, 1405). Therefore, it is possible to calibrate the DC offset voltage including the bias offset due to the base current variation and the filter resistance variation. On the other hand, the bias offset cannot be calibrated in the sixth embodiment using the shorting switch (801). Further, when the DC offset is removed in order from the previous stage, the residual error is removed by the DC offset calibration function in the subsequent stage, so that more accurate DC offset removal can be achieved.
[0031]
A ninth embodiment of a mobile communication device according to the present invention will be described with reference to FIG. If the propagation delay of the filter is reduced as in the eighth embodiment, the filter can be interposed in the feedback loop for DC offset voltage calibration. The Therefore, the number of ADCs can be reduced and the circuit scale can be reduced as compared with the eighth embodiment.
[0032]
【The invention's effect】
According to the present invention, it is possible to reduce three external filters and one external VCO compared to the case where a conventional superheterodyne receiver is applied. Furthermore, by adopting a method for removing the DC offset voltage, which is a problem in the direct conversion receiver, at high speed, it is possible to realize a mobile communication device that can cope with the high-speed packet transmission mode while reducing the number of components.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a mobile communication device showing a first embodiment of the present invention.
FIG. 2 is a configuration diagram of a receiver part of the mobile communication device of the present invention.
FIG. 3 is a detailed diagram of a circuit for removing a DC offset of the receiver of the present invention.
FIG. 4 is an operation timing chart in the GSM standard.
FIG. 5 is a diagram illustrating a method for measuring a DC offset voltage generated by a mixer circuit and a measurement result.
FIG. 6 is an operation principle diagram of a chopper type amplifier applicable to the present invention.
FIG. 7 shows an embodiment in which a chopper amplifier is applied to the receiver portion of the present invention.
FIG. 8 is a configuration diagram of a circuit that performs direct offset voltage calibration of a variable gain amplifier without the influence of the preceding circuit according to the receiver of the present invention.
FIG. 9 is a diagram showing that a timing signal for removing a DC offset is supplied from a baseband circuit.
FIG. 10A is a configuration diagram of a mobile communication device to which a conventional superheterodyne method is applied. (B) Configuration diagram of a conventional direct conversion receiver.
FIG. 11 shows a conventional DC offset voltage calibration method.
FIG. 12 is a diagram showing a transmitter IF frequency during GSM operation.
FIG. 13 is a diagram showing a transmitter IF frequency during DCS1800 operation.
FIG. 14 is a diagram illustrating a method of accelerating a DC offset removal operation by disconnecting a filter capacitor.
FIG. 15 is a diagram illustrating a method for simplifying a DC offset removal circuit by cutting off a filter capacitor;
FIG. 16 is a diagram showing a GSM / DCS1800 dual-band transmission circuit.
FIG. 17 is a diagram showing a list of spurious during GSM transmission.
FIG. 18 is a diagram showing a list of spurious transmissions during DCS1800 transmission.
FIG. 19 is a diagram showing a GSM spurious standard.
FIG. 20 is a diagram showing a VCO oscillation frequency arrangement in which local oscillation frequency bands for transmission and reception match.
FIG. 21 is a diagram showing a VCO oscillation frequency arrangement in which local oscillation frequency bands for transmission and reception do not overlap.
[Explanation of symbols]
101, 102 Low noise amplifier
103, 104, 123, 126, 206, 210, 1019, 1020 Mixer
105, 115, 116, 117, 118, 119, 120, 139 Frequency divider
106, 107, 127, 131, 132, 137, 138, 702, 1012, 1013, 1021, 1022, 1101, 1103, 1105 Low-pass filter
108, 109, 201, 603, 1102, 1104 Variable gain amplifier
110 DC offset voltage calibration circuit
111, 114, 128, 129, 1006, 1007, 1008, 1009 VCO
112, 113 PLL
121, 122 selector switch
127 Phase comparator
130, 1010, 1011 Power amplifier
133, 134, 1001, 1002, 1003, 1004, 1005 Band pass filter
135, 1014 Antenna switch
136, 1015 antenna
139 Variable Gain Low-Pass Filter
140, 1016 IC built-in circuit
202 DAC
203 ADC
205 decoder
701 Buffer amplifier
801, 1401, 1402, switch
901 Baseband circuit
1403 capacity
1404, 1405 resistance
2301, 2302, 2305, 2306 Limiter amplifier
2303, 2304, 2307, 2308 Low-pass filter
2309 Local oscillation signal leakage path for transmission
2701, 2702 VCO oscillation frequency band at reception
2703, 2704, 2705, 2706 Transmission VCO oscillation frequency.

Claims

A first VCO; first and second frequency dividers connected to the output of the first VCO; an output signal of the first frequency divider and a first RF signal being input; A receiving circuit including a first mixer and a second mixer to which an output signal of the second frequency divider and a second RF signal are input;
A third divider having means for switching between a first divider ratio and a second divider ratio connected to the output of the first VCO; a second VCO; and an output of the second VCO A fourth frequency divider having means for switching between the third and fourth frequency division ratios, and a third mixer to which the output signal of the fourth frequency divider and the baseband signal are input. The output signal of the third frequency divider is the first input signal, the output signal of the third mixer is the second input signal, and the frequency using the frequencies of the first and second input signals is used. A transmitter including a frequency conversion circuit that uses the converted signal as an output signal ;
A transmitter / receiver characterized by comprising:

The transceiver according to claim 1,
2. A transceiver according to claim 1, wherein the first frequency divider has a frequency division ratio of 2, and the second frequency divider has a frequency division ratio of 4.

The transceiver according to claim 2,
When the frequency of the first RF signal is frf1, the frequency of the second RF signal is frf2, and the first and second output frequencies of the frequency conversion circuit are ftx1 and ftx2, respectively, the first frequency division The ratio m and the second division ratio n are obtained by switching the third mixer output frequency by switching the division ratio of the fourth divider within the frequency range in which the second VCO can oscillate. | (2 · frf1) / n -ftx1 | and | (4 · frf2) / m -ftx2 | to meet the condition of being able to, capable of oscillating frequency range of the VCO of the first, (2- A transmitter / receiver characterized by satisfying the condition that it can be frf1) or (4 · frf2) .

The transceiver according to claim 3,
The frequency conversion circuit includes a phase comparator, a first low-pass filter, third and fourth VCOs, and a fourth mixer.
The phase comparator outputs a signal proportional to the phase difference between the third mixer output signal and the fourth mixer output signal, and the first low-pass filter is connected to the output of the phase comparator; The third and fourth VCOs are connected to the output of the first low pass filter, and the fourth mixer receives the third or fourth VCO output signal and the third divider output signal. A transceiver comprising a frequency conversion circuit using a PLL for mixing.

A variable gain low-pass filter to which a baseband signal is input, and an offset voltage calibration circuit having means for calibrating a DC offset voltage of the low-pass filter;
The variable gain low-pass filter includes a plurality of variable gain amplifiers and a plurality of low-pass filters.
The offset voltage calibration circuit includes an ADC to which the variable gain amplifier output signal is input, and a control circuit that detects a DC offset voltage of the variable gain amplifier from the ADC output signal and outputs a signal for calibrating the DC offset voltage. A DAC that receives the control circuit output signal and outputs a signal to the variable gain amplifier,
The variable gain amplifier includes first and second transistors whose emitters are connected to each other, a first resistor connected to a collector and a power source of the first transistor, a collector of the second transistor, and a power source. A variable gain comprising a connected second resistor and a variable current source connected to the emitter, wherein a signal is input from the bases of the first and second transistors and a signal is output from the collector An amplifier,
The DAC includes a plurality of voltage-current conversion circuits including a third transistor and a third resistor connected to the emitter of the third transistor and a ground. The collector of the third transistor is the second transistor. A transceiver connected to the collector of one transistor and the base of the third transistor connected to the output of the control circuit.

A variable gain low-pass filter to which a baseband signal is input, and an offset voltage calibration circuit having means for calibrating a DC offset voltage of the low-pass filter;
The variable gain low-pass filter includes a plurality of variable gain amplifiers and a plurality of low-pass filters.
The offset voltage calibration circuit includes an ADC to which the variable gain amplifier output signal is input, and a control circuit that detects a DC offset voltage of the variable gain amplifier from the ADC output signal and outputs a signal for calibrating the DC offset voltage. A DAC that receives the control circuit output signal and outputs a signal to the variable gain amplifier,
The variable gain low-pass filter is constituted by a differential circuit,
At least one first low-pass filter of the low-pass filters includes second and third switches and a first capacitor, and the second switch is the second low-pass filter of the first low-pass filter. One signal line and the first capacitor, and the third switch is connected to the second signal line and the first capacitor of the first low-pass filter, and the second and third capacitors. The transmitter / receiver is in a short circuit state or an open state in synchronization with switch switching control.

The transceiver according to claim 6,
The control circuit for calibrating the DC offset voltage of the first variable gain amplifier connected to the previous stage of the first low-pass filter includes a first DAC and a first control circuit.
The transceiver is characterized in that the first control circuit is the same as a control circuit that calibrates a DC offset voltage of a second variable gain amplifier connected to a subsequent stage of the first low-pass filter.

A variable gain low-pass filter to which a baseband signal is input, and an offset voltage calibration circuit having means for calibrating a DC offset voltage of the low-pass filter;
The variable gain low-pass filter includes a plurality of variable gain amplifiers and a plurality of low-pass filters.
The variable gain low-pass filter is constituted by a differential circuit,
A transmitter / receiver characterized in that at least one of the variable gain amplifiers is replaced with a chopper type amplifier having third and fourth input terminals and first and second output terminals,
The chopper type amplifier includes a third variable gain amplifier having fifth and sixth input terminals, third and fourth output terminals, a fourth switch, and a fifth switch.
By the switching control of the fourth and fifth switches, the third input terminal and the fifth input terminal, the fourth input terminal and the sixth input terminal, the first output terminal and the first input terminal 3 output terminals, the first state in which the second output terminal and the fourth output terminal are connected, the third input terminal, the sixth input terminal, the fourth input terminal, and the fourth output terminal. 5 input terminals, the first output terminal and the fourth output terminal, the second state where the second output terminal and the third output terminal are connected can be switched,
A transmitter / receiver characterized in that the first and second states are periodically switched.

An antenna, an antenna switch connected to the antenna, a plurality of power amplifiers that output signals to the antenna switch, a plurality of bandpass filters connected to the antenna switch, the bandpass filter, and the power amplifier A mobile communication device having a transceiver connected to a baseband circuit,
The transceiver is the transceiver according to any one of claims 1 to 8,
A mobile communication device characterized in that a signal defining a timing for starting a DC offset voltage calibration operation is output from the baseband circuit to the transceiver.

The mobile communication device according to claim 9, wherein
A mobile communication device using a duplexer instead of the antenna switch.