JP4376798B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP4376798B2
JP4376798B2 JP2005008264A JP2005008264A JP4376798B2 JP 4376798 B2 JP4376798 B2 JP 4376798B2 JP 2005008264 A JP2005008264 A JP 2005008264A JP 2005008264 A JP2005008264 A JP 2005008264A JP 4376798 B2 JP4376798 B2 JP 4376798B2
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semiconductor device
semiconductor element
semiconductor
metal body
resin
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JP2005109526A (en
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尚彦 平野
孝紀 手嶋
真光　　邦明
賢次 八木
中瀬　　好美
康嗣 大倉
和仁 野村
豊 福田
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Denso Corp
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Denso Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

本発明は、発熱素子と、この発熱素子の両面に接合された一対の放熱板とを備えて成る半導体装置に関する。   The present invention relates to a semiconductor device including a heating element and a pair of heat sinks bonded to both surfaces of the heating element.

例えば高耐圧・大電流用の半導体チップ（発熱素子）は、使用時の発熱が大きいため、チップからの放熱性を向上させるための構成が必要になる。この構成の一例として、チップの両面に一対の放熱板を例えば半田層を介して接合する構成が、従来より、考えられており、この構成によれば、チップの両面から放熱できるので、放熱性が向上する。そして、上記した両面放熱型の半導体装置は、全体が樹脂でモールドされている。尚、一対の放熱板の各外面は、放熱性を良くするために、露出されるように構成されている。   For example, a semiconductor chip (heat generating element) for high withstand voltage and large current generates a large amount of heat during use, and thus requires a configuration for improving heat dissipation from the chip. As an example of this configuration, a configuration in which a pair of heat radiating plates is joined to both sides of a chip via, for example, a solder layer has been conventionally considered. According to this configuration, heat can be radiated from both sides of the chip. Will improve. The entire double-sided heat dissipation type semiconductor device is molded with resin. Each outer surface of the pair of heat radiating plates is configured to be exposed in order to improve heat dissipation.

上記構成の半導体装置においては、半導体チップ、ヒートシンク、樹脂の熱膨脹係数の差が大きいため、これら３つの部材の接触部にかなり大きな熱応力が作用し、この熱応力によって、半導体チップが破壊されてしまうことがある。この傾向は、半導体装置に加わる熱サイクルの温度差が大きいほど顕著である。   In the semiconductor device having the above configuration, since the difference in thermal expansion coefficient between the semiconductor chip, the heat sink, and the resin is large, a considerably large thermal stress acts on the contact portion of these three members, and the semiconductor chip is destroyed by this thermal stress. It may end up. This tendency becomes more prominent as the temperature difference of the thermal cycle applied to the semiconductor device is larger.

そこで、本発明の目的は、大きな熱応力が作用したとしても、素子破壊を防止することができ、半導体装置の長期的信頼性を向上させることができる半導体装置を提供することにある。   Accordingly, an object of the present invention is to provide a semiconductor device that can prevent element destruction even when a large thermal stress is applied and can improve the long-term reliability of the semiconductor device.

請求項１の発明では、半導体素子と金属体とを接合する接合層における歪み成分が１％以下となるように、前記半導体素子の厚さを２５０μｍ以下とすると共に、モールド樹脂により装置全体を拘束保持するように構成したので、耐冷熱サイクル性や耐クリープ性等の耐久性を向上させることができる。   According to the first aspect of the present invention, the thickness of the semiconductor element is set to 250 μm or less so that the strain component in the bonding layer for bonding the semiconductor element and the metal body is 1% or less, and the entire apparatus is restrained by the mold resin. Since it comprised so that it might hold | maintain, durability, such as cold-heat cycle resistance and creep resistance, can be improved.

また、請求項２の発明のように、半導体素子表面のせん断応力が３５ＭＰａ以下となるように、前記半導体素子の厚さを２５０μｍ以下とすると共に、前記モールド樹脂により装置全体を拘束保持するように構成することが好ましい。   Further, as in the invention of claim 2, the thickness of the semiconductor element is set to 250 μm or less so that the shear stress on the surface of the semiconductor element is 35 MPa or less, and the entire apparatus is restrained and held by the mold resin. It is preferable to configure.

また、請求項３の発明のように、３個の金属体のうちの少なくとも１つの金属体の厚みを１．０ｍｍ以上とすることも好ましい構成である。   Further, as in the invention of claim 3, it is also a preferable configuration that the thickness of at least one of the three metal bodies is 1.0 mm or more.

請求項４の発明によれば、接合層をＳｎ系はんだで構成したので、接合の強度が高くなると共に、接合層における歪み成分を低減できる。また、請求項５の発明のように、半導体素子のデバイス構造をトレンチゲートタイプとすることが好ましい。   According to invention of Claim 4, since the joining layer was comprised with Sn type solder, while the intensity | strength of joining becomes high, the distortion component in a joining layer can be reduced. Further, as in the invention of claim 5, it is preferable that the device structure of the semiconductor element is a trench gate type.

以下、本発明の第１の実施例について、図１ないし図４を参照しながら説明する。まず、図１は、本実施例の半導体装置の概略構成を示す断面図である。この図１に示すように、本実施例の半導体装置１は、半導体チップ（発熱素子、半導体素子）２と、下側ヒートシンク（放熱板、第１の金属体）３と、上側ヒートシンク（放熱板、第２の金属体）４と、ヒートシンクブロック５（第３の金属体）とを備えて構成されている。   A first embodiment of the present invention will be described below with reference to FIGS. First, FIG. 1 is a cross-sectional view showing a schematic configuration of the semiconductor device of this embodiment. As shown in FIG. 1, a semiconductor device 1 according to the present embodiment includes a semiconductor chip (heating element, semiconductor element) 2, a lower heat sink (heat sink, first metal body) 3, and an upper heat sink (heat sink). , Second metal body) 4 and a heat sink block 5 (third metal body).

この構成の場合、半導体チップ２の下面と下側ヒートシンク３の上面との間は、接合部材である例えば半田（接合層）６によって接合されている。そして、半導体チップ２の上面とヒートシンクブロック５の下面との間も、半田（接合層）６によって接合されている。更に、ヒートシンクブロック５の上面と上側ヒートシンク４の下面との間も、半田（接合層）６によって接合されている。これにより、上記構成においては、半導体チップ２の両面からヒートシンク３、４（即ち、一対の放熱板）を介して放熱される構成となっている。   In the case of this configuration, the lower surface of the semiconductor chip 2 and the upper surface of the lower heat sink 3 are joined by, for example, solder (joining layer) 6 which is a joining member. The upper surface of the semiconductor chip 2 and the lower surface of the heat sink block 5 are also bonded by solder (bonding layer) 6. Further, the upper surface of the heat sink block 5 and the lower surface of the upper heat sink 4 are also bonded by solder (bonding layer) 6. Thereby, in the said structure, it becomes the structure which is thermally radiated from both surfaces of the semiconductor chip 2 via the heat sinks 3 and 4 (namely, a pair of heat sink).

尚、上記半導体チップ２は、例えばＩＧＢＴやサイリスタ等のパワー半導体素子から構成されている。この場合、半導体チップ２のデバイス構造を、トレンチゲートタイプとすることが好ましい。もちろん、他のタイプのデバイス構造を用いるように構成しても良い。   The semiconductor chip 2 is composed of a power semiconductor element such as an IGBT or a thyristor. In this case, the device structure of the semiconductor chip 2 is preferably a trench gate type. Of course, other types of device structures may be used.

上記半導体チップ２の形状は、本実施例の場合、図２（ａ）に示すように、例えば矩形状の薄板状である。また、下側ヒートシンク３、上側ヒートシンク４及びヒートシンクブロック５は、例えばＣｕやＡｌ等の熱伝導性及び電気伝導性の良い金属で構成されている。この構成の場合、下側ヒートシンク３及び上側ヒートシンク４は、半導体チップ２の各主電極（例えばコレクタ電極やエミッタ電極等）に半田６を介して電気的にも接続されている。   In the case of this embodiment, the shape of the semiconductor chip 2 is, for example, a rectangular thin plate as shown in FIG. The lower heat sink 3, the upper heat sink 4 and the heat sink block 5 are made of a metal having good thermal conductivity and electrical conductivity, such as Cu and Al. In the case of this configuration, the lower heat sink 3 and the upper heat sink 4 are also electrically connected to each main electrode (for example, a collector electrode or an emitter electrode) of the semiconductor chip 2 via the solder 6.

また、下側ヒートシンク３は、図２（ａ）に示すように、全体として例えばほぼ長方形状の板材であり、端子部３ａが後方へ向けて延びるように突設されている。また、ヒートシンクブロック５は、図２（ａ）に示すように、半導体チップ２よりも１回り小さい程度の大きさの矩形状の板材である。更に、上側ヒートシンク４は、図２（ｄ）に示すように、全体として例えばほぼ長方形状の板材で構成されており、端子部４ａが後方へ向けて延びるように突設されている。尚、下側ヒートシンク３の端子部３ａと、上側ヒートシンク４の端子部４ａは、互いの位置がずれるように、即ち、対向しないように構成されている。   Further, as shown in FIG. 2A, the lower heat sink 3 is, for example, a substantially rectangular plate material as a whole, and protrudes so that the terminal portion 3a extends rearward. Further, the heat sink block 5 is a rectangular plate having a size that is slightly smaller than the semiconductor chip 2 as shown in FIG. Further, as shown in FIG. 2 (d), the upper heat sink 4 is formed of, for example, a substantially rectangular plate material as a whole, and protrudes so that the terminal portion 4a extends rearward. The terminal portion 3a of the lower heat sink 3 and the terminal portion 4a of the upper heat sink 4 are configured so that their positions are shifted, that is, not opposed to each other.

また、上記構成の場合、下側ヒートシンク３の上面と上側ヒートシンク４の下面との間の距離は、例えば１〜２ｍｍ程度になるように構成されている。図１及び図２においては、上記距離をかなり拡大して示している。   In the case of the above configuration, the distance between the upper surface of the lower heat sink 3 and the lower surface of the upper heat sink 4 is configured to be, for example, about 1 to 2 mm. In FIG. 1 and FIG. 2, the above distance is shown in a considerably enlarged manner.

更に、図１に示すように、一対のヒートシンク３、４の隙間、並びに、チップ２及びヒートシンクブロック５の周囲部分には、樹脂（例えばエポキシ樹脂）７が充填封止されている。この場合、ヒートシンク３、４等を樹脂７でモールドするに当たっては、上下型からなる成形型（図示しない）を使用している。尚、樹脂７とヒートシンク３、４との密着力、樹脂７と半導体チップ２との密着力、並びに、樹脂７とヒートシンクブロック５との密着力を強くするために、上記樹脂７をモールドする前に、コーティング樹脂である例えばポリアミド樹脂（図示しない）をヒートシンク３、４、ヒートシンクブロック５及びチップ２の表面に塗布しておくことが好ましい。   Further, as shown in FIG. 1, resin (for example, epoxy resin) 7 is filled and sealed in the gap between the pair of heat sinks 3 and 4 and the peripheral portions of the chip 2 and the heat sink block 5. In this case, when the heat sinks 3, 4 and the like are molded with the resin 7, a mold (not shown) composed of upper and lower molds is used. Before the resin 7 is molded in order to increase the adhesion between the resin 7 and the heat sinks 3 and 4, the adhesion between the resin 7 and the semiconductor chip 2, and the adhesion between the resin 7 and the heat sink block 5. In addition, for example, a polyamide resin (not shown) as a coating resin is preferably applied to the surfaces of the heat sinks 3 and 4, the heat sink block 5 and the chip 2.

次に、上記した構成の半導体装置１の製造方法（即ち、製造工程）について、図２を参照して簡単に説明する。まず、図２（ａ）及び（ｂ）に示すように、下側ヒートシンク３の上面に、半導体チップ２とヒートシンクブロック５を半田付けする工程を実行する。この場合、下側ヒートシンク３の上面に半田箔８を介してチップ２を積層すると共に、このチップ２の上に半田箔８を介してヒートシンクブロック５を積層する。この後、加熱装置（リフロー装置）によって上記半田箔８、８を溶融させてから、硬化させる。   Next, a manufacturing method (that is, a manufacturing process) of the semiconductor device 1 having the above configuration will be briefly described with reference to FIG. First, as shown in FIGS. 2A and 2B, a process of soldering the semiconductor chip 2 and the heat sink block 5 to the upper surface of the lower heat sink 3 is executed. In this case, the chip 2 is laminated on the upper surface of the lower heat sink 3 via the solder foil 8, and the heat sink block 5 is laminated on the chip 2 via the solder foil 8. Thereafter, the solder foils 8 and 8 are melted by a heating device (reflow device) and then cured.

続いて、図２（ｃ）に示すように、チップ２の制御電極（例えばゲートパッド等）とリードフレーム９ａ、９ｂとをワイヤーボンディングする工程を実行する。これにより、例えばＡｌやＡｕ等製のワイヤー１０によってチップ２の制御電極とリードフレーム９ａ、９ｂとが接続される。   Subsequently, as shown in FIG. 2C, a process of wire bonding the control electrode (eg, gate pad) of the chip 2 and the lead frames 9a and 9b is performed. Thereby, for example, the control electrode of the chip 2 and the lead frames 9a and 9b are connected by the wire 10 made of Al or Au.

次いで、図２（ｄ）及び（ｅ）に示すように、ヒートシンクブロック５の上に上側ヒートシンク４を半田付けする工程を実行する。この場合、図２（ｄ）に示すように、ヒートシンクブロック５の上に半田箔８を介して上側ヒートシンク４を載せる。そして、加熱装置によって上記半田箔８を溶融させてから、硬化させる。   Next, as shown in FIGS. 2D and 2E, a process of soldering the upper heat sink 4 on the heat sink block 5 is executed. In this case, the upper heat sink 4 is placed on the heat sink block 5 via the solder foil 8 as shown in FIG. Then, the solder foil 8 is melted by a heating device and then cured.

このとき、図２（ｅ）に示すように、上側ヒートシンク４の上に例えば重り１１を載置することにより、上側ヒートシンク４を下方へ向けて加圧するように構成されている。これと共に、上側ヒートシンク４と下側ヒートシンク３との間に、スペーサ治具（図示しない）を取り付けることにより、上側ヒートシンク４と下側ヒートシンク３との間の距離を設定距離に保持するように構成している。   At this time, as shown in FIG. 2 (e), for example, a weight 11 is placed on the upper heat sink 4 to pressurize the upper heat sink 4 downward. At the same time, a spacer jig (not shown) is attached between the upper heat sink 4 and the lower heat sink 3 so that the distance between the upper heat sink 4 and the lower heat sink 3 is maintained at a set distance. is doing.

この構成の場合、半田箔８が溶融する前の状態では、上側ヒートシンク４と下側ヒートシンク３との距離は、スペーサ治具の設定距離よりも大きくなるように構成されている。そして、半田箔８が溶融すると、重り１１の加圧力により、溶融した半田層の部分が薄くなり、上側ヒートシンク４と下側ヒートシンク３との距離がスペーサ治具の設定距離と等しくなる。このとき、半田層は、適度な薄さまで薄くなるように構成されている。そして、溶融した半田層が硬化すれば、チップ２とヒートシンク３、４とヒートシンクブロック５の接合及び電気的接続が完了する。   In the case of this configuration, before the solder foil 8 is melted, the distance between the upper heat sink 4 and the lower heat sink 3 is configured to be larger than the set distance of the spacer jig. When the solder foil 8 is melted, the portion of the melted solder layer is thinned by the pressure applied by the weight 11, and the distance between the upper heat sink 4 and the lower heat sink 3 becomes equal to the set distance of the spacer jig. At this time, the solder layer is configured to be thin to an appropriate thickness. When the molten solder layer is cured, the bonding and electrical connection between the chip 2, the heat sinks 3, 4 and the heat sink block 5 are completed.

この後、ポリアミド樹脂を、ヒートシンク３、４とヒートシンクブロック５とチップ２の表面等に塗布する工程を実行する。この場合、例えばディッピングにより塗布しても良いし、ポリアミド樹脂塗布用のディスペンサのノズルから滴下（または噴霧）することにより塗布しても良い。尚、ポリアミド樹脂は必要に応じて塗布すれば良く、ポリアミド樹脂の塗布を省略しても良い。   Then, the process of apply | coating polyamide resin to the heat sinks 3 and 4, the heat sink block 5, the surface of the chip | tip 2, etc. is performed. In this case, for example, it may be applied by dipping, or may be applied by dropping (or spraying) from a nozzle of a dispenser for applying polyamide resin. The polyamide resin may be applied as necessary, and the polyamide resin may be omitted.

そして、ポリアミド樹脂を塗布した後は、図示しない成形型を使用して、ヒートシンク３、４の隙間及び外周部に樹脂７を充填する工程（モールド工程）を実行する。これにより、図１に示すように、ヒートシンク３、４の隙間及び外周部等に、樹脂７が充填封止される。そして、樹脂７が硬化した後、成形型内から半導体装置１を取り出せば、半導体装置１が完成する。尚、上記構成の場合、下側ヒートシンク３の下面及び上側ヒートシンク４の上面が、それぞれ露出するように樹脂モールドされている。これにより、ヒートシンク３、４の放熱性を高めている。   And after apply | coating a polyamide resin, the process (mold process) of filling the resin 7 in the clearance gap and outer peripheral part of the heat sinks 3 and 4 using the shaping | molding die which is not shown in figure is performed. As a result, as shown in FIG. 1, the resin 7 is filled and sealed in the gaps and the outer periphery of the heat sinks 3 and 4. Then, after the resin 7 is cured, the semiconductor device 1 is completed by taking the semiconductor device 1 out of the mold. In the case of the above configuration, resin molding is performed so that the lower surface of the lower heat sink 3 and the upper surface of the upper heat sink 4 are exposed. Thereby, the heat dissipation of the heat sinks 3 and 4 is improved.

さて、上記構成の半導体装置１においては、半導体チップ２の厚さ寸法をｔ１とし、下側ヒートシンク３の厚さ寸法をｔ２としたときに、ｔ２／ｔ１≧５が成立するように構成した。尚、本実施例の場合、上側ヒートシンク４の厚さ寸法もｔ２としている。   The semiconductor device 1 having the above-described configuration is configured such that t2 / t1 ≧ 5 is established when the thickness dimension of the semiconductor chip 2 is t1 and the thickness dimension of the lower heat sink 3 is t2. In this embodiment, the thickness of the upper heat sink 4 is also t2.

ここで、厚さ寸法ｔ１、ｔ２の条件式、即ち、厚さ比率（ｔ２／ｔ１）を上記したように設定した理由について説明する。本発明者らは、試作や実験等を実行することにより、上記厚さ比率の条件式が成立する構成であれば、半導体チップ２を保持するための圧縮応力を大きくすることができると共に、半導体チップ２の表面のせん断応力を低減することができることを確認した。   Here, the reason why the conditional expression of the thickness dimensions t1 and t2, that is, the thickness ratio (t2 / t1) is set as described above will be described. The inventors of the present invention can increase the compressive stress for holding the semiconductor chip 2 as long as the conditional expression for the thickness ratio is satisfied by performing trial manufacture, experiments, and the like. It was confirmed that the shear stress on the surface of the chip 2 can be reduced.

具体的には、厚さ比率を変えた半導体装置１を試作し、各試作品の素子圧縮応力を測定し、図３に示すグラフを得た。この図３のグラフにおいて、横軸は厚さ比率を示し、縦軸は素子圧縮応力比を示し、プロットが実際に試作した半導体装置１を示している。ここで、素子圧縮応力比は、厚さ比率が３．７５の半導体装置１の素子圧縮応力を１．００と定義した場合の数値である。   Specifically, the semiconductor device 1 having a different thickness ratio was prototyped, the element compressive stress of each prototype was measured, and the graph shown in FIG. 3 was obtained. In the graph of FIG. 3, the horizontal axis indicates the thickness ratio, the vertical axis indicates the element compressive stress ratio, and the plot indicates the actually manufactured semiconductor device 1. Here, the element compressive stress ratio is a numerical value when the element compressive stress of the semiconductor device 1 having a thickness ratio of 3.75 is defined as 1.00.

この厚さ比率が３．７５（即ち、素子圧縮応力比が１．００）の半導体装置１に対して温度差の大きい熱サイクルを作用させると、半導体チップ２が割れてしまうことを確認している。そして、厚さ比率が２．５（即ち、素子圧縮応力比が０．９８）の半導体装置１に対して温度差の大きい熱サイクルを作用させたときも、半導体チップ２が割れてしまうことを確認している。   It was confirmed that when the thermal cycle having a large temperature difference is applied to the semiconductor device 1 having the thickness ratio of 3.75 (that is, the element compressive stress ratio is 1.00), the semiconductor chip 2 is cracked. Yes. Even when a thermal cycle having a large temperature difference is applied to the semiconductor device 1 having a thickness ratio of 2.5 (that is, the element compressive stress ratio is 0.98), the semiconductor chip 2 is cracked. I have confirmed.

これに対して、厚さ比率が７．００（即ち、素子圧縮応力比が１．０９）と厚さ比率が１５．００（即ち、素子圧縮応力比が１．１３）の半導体装置１に対して温度差の大きい熱サイクルを作用させた場合、両者の半導体チップ２が割れないことを確認している。即ち、厚さ比率ひいては素子圧縮応力比が大きいほど、半導体チップ２が割れ難くなることを確認している。   On the other hand, for the semiconductor device 1 having a thickness ratio of 7.00 (ie, the element compressive stress ratio is 1.09) and a thickness ratio of 15.00 (ie, the element compressive stress ratio is 1.13). When a thermal cycle with a large temperature difference is applied, it is confirmed that both semiconductor chips 2 are not broken. That is, it has been confirmed that the semiconductor chip 2 becomes harder to break as the thickness ratio and thus the element compressive stress ratio increases.

従って、図３のグラフから、厚さ比率（ｔ２／ｔ１）を５．００以上に設定すれば、素子圧縮応力を十分大きく保持することができ、その半導体装置１に対して大きな熱応力が作用しても、素子破壊の発生を防止できることがわかる。これによって、半導体装置１の長期的信頼性を向上させることができる。   Therefore, from the graph of FIG. 3, if the thickness ratio (t2 / t1) is set to 5.00 or more, the element compressive stress can be kept sufficiently large, and a large thermal stress acts on the semiconductor device 1. However, it can be understood that the occurrence of element breakdown can be prevented. Thereby, the long-term reliability of the semiconductor device 1 can be improved.

また、厚さ比率を変えた半導体装置１の各試作品の素子表面のせん断応力を、シミュレーションによって計算し、図４に示すグラフを得た。この図４のグラフにおいて、横軸は厚さ比率を示し、縦軸は素子表面のせん断応力比を示し、プロットが実際に試作した半導体装置１を示している。ここで、せん断応力比は、厚さ比率が３．７５の半導体装置１のせん断応力を１．００と定義した場合の数値である。   Further, the shear stress of the element surface of each prototype of the semiconductor device 1 with the thickness ratio changed was calculated by simulation, and the graph shown in FIG. 4 was obtained. In the graph of FIG. 4, the horizontal axis indicates the thickness ratio, the vertical axis indicates the shear stress ratio of the element surface, and the plot indicates the actually manufactured semiconductor device 1. Here, the shear stress ratio is a numerical value when the shear stress of the semiconductor device 1 having a thickness ratio of 3.75 is defined as 1.00.

この厚さ比率が３．７５（即ち、せん断応力比が１．００）の半導体装置１に対して温度差の大きい熱サイクルを作用させると、半導体チップ２の表面付近の樹脂が剥離してしまうことを確認している。そして、厚さ比率が２．５（即ち、せん断応力比が１．０２）の半導体装置１に対して温度差の大きい熱サイクルを作用させたときも、半導体チップ２の表面付近の樹脂が剥離してしまうことを確認している。   When a thermal cycle having a large temperature difference is applied to the semiconductor device 1 having the thickness ratio of 3.75 (that is, the shear stress ratio is 1.00), the resin near the surface of the semiconductor chip 2 is peeled off. I have confirmed that. Even when a thermal cycle having a large temperature difference is applied to the semiconductor device 1 having a thickness ratio of 2.5 (that is, the shear stress ratio is 1.02), the resin near the surface of the semiconductor chip 2 is peeled off. I have confirmed that it will.

これに対して、厚さ比率が７．００（即ち、せん断応力比が０．６）と厚さ比率が１５．００（即ち、せん断応力比が０．１５）の半導体装置１に対して温度差の大きい熱サイクルを作用させた場合、両者の半導体チップ２の表面付近の樹脂が剥離しないことを確認している。即ち、厚さ比率が大きいほど（即ち、せん断応力比が小さいほど）、半導体チップ２表面の樹脂が剥離し難くなることを確認している。   On the other hand, the temperature of the semiconductor device 1 having a thickness ratio of 7.00 (that is, the shear stress ratio is 0.6) and a thickness ratio of 15.00 (that is, the shear stress ratio is 0.15). It is confirmed that when a thermal cycle with a large difference is applied, the resin in the vicinity of the surfaces of the two semiconductor chips 2 does not peel off. That is, it has been confirmed that the resin on the surface of the semiconductor chip 2 becomes difficult to peel off as the thickness ratio increases (that is, as the shear stress ratio decreases).

従って、図４のグラフから、厚さ比率（ｔ２／ｔ１）を５．００以上に設定すれば、せん断応力を十分低減することができ、その半導体装置１に対して大きな熱応力が作用しても、素子表面の樹脂の剥離を防止できることがわかる。これによって、半導体装置１の長期的信頼性を向上させることができる。   Therefore, from the graph of FIG. 4, if the thickness ratio (t2 / t1) is set to 5.00 or more, the shear stress can be sufficiently reduced, and a large thermal stress acts on the semiconductor device 1. It can also be seen that the resin surface can be prevented from peeling off. Thereby, the long-term reliability of the semiconductor device 1 can be improved.

尚、上記実施例の場合、厚さ比率を大きくすれば、良い効果が得られることはわかっているが、厚さ比率をあまり大きくすることは困難である。というのは、厚さ比率を大きくする方法は、２つあり、１つの方法は半導体チップ２の厚み寸法ｔ１を薄くすることであり、他の１つの方法はヒートシンク３、４の厚み寸法ｔ２を厚くすることである。   In the case of the above embodiment, it is known that a good effect can be obtained by increasing the thickness ratio, but it is difficult to increase the thickness ratio too much. This is because there are two methods for increasing the thickness ratio, one method is to reduce the thickness dimension t1 of the semiconductor chip 2, and the other method is to reduce the thickness dimension t2 of the heat sinks 3 and 4. It is to make it thicker.

しかし、半導体チップ２の厚み寸法ｔ１を薄くする場合、０．１ｍｍ程度が加工限界であり、ヒートシンク３、４の厚み寸法ｔ２を１．０ｍｍ程度に固定すると、厚さ比率は１５が限界となる。一方、ヒートシンク３、４の厚み寸法ｔ２を厚くする場合には、半導体装置１の全体の厚み寸法が厚くなってしまうので、実用上（製品上）の制約がある。従って、厚さ比率は１５程度が限界であり、チップの加工のし易さ及び実用上の制約から見ると、ベストの厚さ比率は７〜８程度となる。   However, when the thickness dimension t1 of the semiconductor chip 2 is reduced, the processing limit is about 0.1 mm. When the thickness dimension t2 of the heat sinks 3 and 4 is fixed to about 1.0 mm, the thickness ratio is limited to 15. . On the other hand, when the thickness dimension t2 of the heat sinks 3 and 4 is increased, the overall thickness dimension of the semiconductor device 1 is increased, so there is a practical (product) limitation. Accordingly, the thickness ratio is limited to about 15, and the best thickness ratio is about 7 to 8 from the viewpoint of ease of chip processing and practical restrictions.

また、上記実施例においては、ヒートシンク３、４の材料として、ヤング率が常温で１００ＧＰａ以上の金属や合金等の材料を使用することが好ましい。上記１００ＧＰａ以上のヤング率の材料は、硬く、十分な剛性があることから、十分な大きさの圧縮応力を得ることが可能になるためである。尚、圧縮応力を大きくするためには、材料の剛性が大きいほど良い。   Moreover, in the said Example, it is preferable to use materials, such as a metal and an alloy whose Young's modulus is 100 GPa or more at normal temperature as a material of the heat sinks 3 and 4. FIG. This is because the material having a Young's modulus of 100 GPa or more is hard and has sufficient rigidity, so that a sufficiently large compressive stress can be obtained. In order to increase the compressive stress, the higher the rigidity of the material, the better.

そして、上記ヤング率の条件を満たすヒートシンク３、４の材料としては、例えばＣｕ、Ｃｕ系合金、Ａｌ、Ａｌ系合金等があり、これらの金属や合金を使用すれば良い。   And as a material of the heat sinks 3 and 4 which satisfy | fill the said Young's modulus, there exist Cu, Cu type alloy, Al, Al type alloy etc., for example, What is necessary is just to use these metals and alloys.

また、上記実施例において、半導体チップ２とヒートシンク３、４及びヒートシンクブロック５とを接合する半田６の具体的材料としては、例えばＳｎ−Ｐｂ系、Ｓｎ−Ａｇ系、Ｓｎ−Ｓｂ系、Ｓｎ−Ｃｕ系などの２元系、或いは、多元系組成から適宜選択すれば良い。更に、モールド用の樹脂７としては、エポキシ系などの適正な素材の中から適宜選択すれば良い。   Moreover, in the said Example, as a specific material of the solder 6 which joins the semiconductor chip 2, and the heat sinks 3 and 4 and the heat sink block 5, it is Sn-Pb type | system | group, Sn-Ag type | system | group, Sn-Sb type | system | group, Sn--, for example. What is necessary is just to select suitably from binary type | system | groups, such as Cu type | system | group, or a multi-component type | system | group composition. Furthermore, the molding resin 7 may be appropriately selected from appropriate materials such as epoxy.

尚、上記実施例においては、下側ヒートシンク３及び上側ヒートシンク４の両方の厚み寸法をｔ２としたが、これに限られるものではなく、下側ヒートシンク３の厚み寸法だけをｔ２とし、上側ヒートシンク４の厚み寸法をｔ２と異なる寸法にしても良いし、反対に、上側ヒートシンク４の厚み寸法だけをｔ２とし、下側ヒートシンク３の厚み寸法をｔ２と異なる寸法にしても良い。   In the above-described embodiment, the thickness dimension of both the lower heat sink 3 and the upper heat sink 4 is t2, but the present invention is not limited to this. Only the thickness dimension of the lower heat sink 3 is t2, and the upper heat sink 4 The thickness dimension of the lower heat sink 3 may be different from t2, while the thickness dimension of the lower heat sink 3 may be different from t2.

図５ないし図７は、本発明の第２の実施例を示す図である。この第２の実施例は、第１の実施例の半導体装置１において、ヒートシンク３、４の熱膨張係数をα１とし、樹脂７の熱膨張係数をα２としたときに、０．５α１≦α２≦１．５α１が成立するように構成したものである。   5 to 7 are views showing a second embodiment of the present invention. In the second embodiment, when the thermal expansion coefficient of the heat sinks 3 and 4 is α1 and the thermal expansion coefficient of the resin 7 is α2 in the semiconductor device 1 of the first embodiment, 0.5α1 ≦ α2 ≦ The configuration is such that 1.5α1 is established.

本発明者らは、試作や実験等を実行することにより、上記熱膨張係数の条件式が成立するように構成した半導体装置１であれば、半導体チップ（発熱素子）２の表面の端部に対する引張り応力及び半導体チップ２の表面のせん断応力を低減できることを確認した。以下、実験結果等に基づいて、上記熱膨張係数の条件式が有効であることを具体的に説明する。   If the semiconductor device 1 is configured such that the conditional expression of the thermal expansion coefficient is established by executing a trial manufacture, an experiment, or the like, the present inventors are directed to the end of the surface of the semiconductor chip (heating element) 2. It was confirmed that the tensile stress and the shear stress on the surface of the semiconductor chip 2 can be reduced. Hereinafter, it will be specifically described that the conditional expression for the thermal expansion coefficient is effective based on experimental results and the like.

まず、樹脂７の熱膨張係数α２を変えた半導体装置１の各試作品の半導体チップ２の表面の端部における引張り力、即ち、Ｚ方向の応力を、シミュレーションによって計算し、図５に示すグラフを得た。この図５のグラフにおいて、横軸は樹脂７の熱膨張係数α２を示し、縦軸はＺ方向の応力を示し、プロットが実際に試作した半導体装置１を示している。尚、Ｚ方向は、半導体チップ２に直交する方向、即ち、図１における上下方向である。また、半導体装置１の各試作品のヒートシンク３、４は例えばＣｕで形成されており、Ｃｕの熱膨張係数α１は１７ｐｐｍである。   First, the tensile force at the end of the surface of the semiconductor chip 2 of each prototype of the semiconductor device 1 in which the thermal expansion coefficient α2 of the resin 7 is changed, that is, the stress in the Z direction is calculated by simulation, and the graph shown in FIG. Got. In the graph of FIG. 5, the horizontal axis indicates the thermal expansion coefficient α2 of the resin 7, the vertical axis indicates the stress in the Z direction, and the plot indicates the actually manufactured semiconductor device 1. The Z direction is a direction orthogonal to the semiconductor chip 2, that is, the vertical direction in FIG. Further, the heat sinks 3 and 4 of each prototype of the semiconductor device 1 are made of Cu, for example, and the thermal expansion coefficient α1 of Cu is 17 ppm.

上記図５から、樹脂７の熱膨張係数α２が大きくなるほど、Ｚ方向の応力、即ち、半導体チップ２の表面の端部の引張り力が小さくなり、半導体チップ２を強固に保持できることがわかる。   From FIG. 5, it can be seen that as the thermal expansion coefficient α2 of the resin 7 increases, the stress in the Z direction, that is, the tensile force at the end of the surface of the semiconductor chip 2 decreases, and the semiconductor chip 2 can be held firmly.

次に、樹脂７の熱膨張係数α２を変えた半導体装置１の各試作品の半導体チップ２の表面におけるせん断応力を、シミュレーションによって計算し、図６に示すグラフを得た。この図６のグラフにおいて、横軸は樹脂７の熱膨張係数α２を示し、縦軸はせん断応力を示し、プロットが実際に試作した半導体装置１を示している。   Next, the shear stress on the surface of the semiconductor chip 2 of each prototype of the semiconductor device 1 in which the thermal expansion coefficient α2 of the resin 7 was changed was calculated by simulation, and the graph shown in FIG. 6 was obtained. In the graph of FIG. 6, the horizontal axis indicates the thermal expansion coefficient α2 of the resin 7, the vertical axis indicates the shear stress, and the plot indicates the actually manufactured semiconductor device 1.

この場合、せん断応力は、０に近いほど好ましく、その絶対値が大きくなると、良くないことがわかっている。そして、上記図６に示す５個の試作品については、大きな熱応力を作用させても、樹脂７の剥離等の発生は確認しておらず、熱膨張係数α２が２５ｐｐｍであっても、そのときのせん断応力が問題ないことを確認している。   In this case, the shear stress is preferably closer to 0, and it has been found that the absolute value of the shear stress is not good. For the five prototypes shown in FIG. 6, even if a large thermal stress is applied, the occurrence of peeling of the resin 7 has not been confirmed, and even if the thermal expansion coefficient α2 is 25 ppm, It is confirmed that there is no problem with the shear stress.

ここで、樹脂７の熱膨張係数α２をヒートシンク３、４の熱膨張係数α１で表現し、これを横軸とし、更に、縦軸を、Ｚ方向の応力（即ち、半田の降伏応力）と、せん断応力の絶対値として、図７に示す２つのグラフ（曲線）Ａ及びＢを得た。この場合、曲線ＡがＺ方向の応力と樹脂７の熱膨張係数との関係を示し、曲線Ｂがせん断応力と樹脂７の熱膨張係数との関係を示している。   Here, the thermal expansion coefficient α2 of the resin 7 is expressed by the thermal expansion coefficient α1 of the heat sinks 3 and 4, and this is the horizontal axis, and the vertical axis is the stress in the Z direction (that is, the yield stress of the solder), Two graphs (curves) A and B shown in FIG. 7 were obtained as absolute values of the shear stress. In this case, the curve A shows the relationship between the stress in the Z direction and the thermal expansion coefficient of the resin 7, and the curve B shows the relationship between the shear stress and the thermal expansion coefficient of the resin 7.

この図７において、Ｚ方向の応力の上限値は、３５〜４０ＭＰａ程度であり、Ｚ方向の応力は上記上限値よりも小さくしなければならない。従って、樹脂７の熱膨張係数α２を、０．５α１以上としなければならない。また、せん断応力の上限値は、５０ＭＰａ程度であり、せん断応力は上記上限値よりも小さくしなければならない。従って、樹脂７の熱膨張係数α２を、１．５α１以下としなければならない。   In FIG. 7, the upper limit value of the stress in the Z direction is about 35 to 40 MPa, and the stress in the Z direction must be smaller than the upper limit value. Therefore, the thermal expansion coefficient α2 of the resin 7 must be 0.5α1 or more. Moreover, the upper limit of the shear stress is about 50 MPa, and the shear stress must be smaller than the upper limit. Therefore, the thermal expansion coefficient α2 of the resin 7 must be 1.5α1 or less.

この結果、前記した熱膨張係数の条件式、即ち、０．５α１≦α２≦１．５α１が得られる。そして、この熱膨張係数の条件式が成立する構成の半導体装置１であれば、大きな熱応力が作用したとしても、半導体チップ２が割れるようなことはなく、長期的信頼性を向上させることができる。   As a result, the conditional expression for the thermal expansion coefficient, that is, 0.5α1 ≦ α2 ≦ 1.5α1 is obtained. And if it is the semiconductor device 1 of the structure with which the conditional expression of this thermal expansion coefficient is materialized, even if a big thermal stress acts, the semiconductor chip 2 will not be cracked and long-term reliability can be improved. it can.

尚、Ｚ方向の応力の上限値が３５〜４０ＭＰａ程度である理由は、半導体チップ２とヒートシンク３、４を接合する半田（例えばＳｎ−Ｐｂ系の半田）の引張り強度が３５〜４０ＭＰａ程度であり、これを越えると半田接合の耐久信頼性を確保することができないためである。このことは、文献（例えば高信頼度マイクロソルダリング技術、工業調査会）に記載されている。   The reason why the upper limit value of the stress in the Z direction is about 35 to 40 MPa is that the tensile strength of the solder (for example, Sn-Pb solder) that joins the semiconductor chip 2 and the heat sinks 3 and 4 is about 35 to 40 MPa. If this is exceeded, the durability reliability of the solder joint cannot be ensured. This is described in the literature (for example, high reliability micro soldering technology, industrial research committee).

また、せん断応力の上限値が５０ＭＰａ程度である理由は、Ｃｕのフレームと一般的なモールド樹脂との密着強度は、５０ＭＰａ程度であり、これを越えるようなせん断応力が加わった場合、樹脂の剥離が発生するためである。このことは、本出願人の実験によって確認した。   The reason why the upper limit of the shear stress is about 50 MPa is that the adhesion strength between the Cu frame and a general mold resin is about 50 MPa. When shear stress exceeding this is applied, the resin is peeled off. This is because of this. This was confirmed by the applicant's experiment.

尚、上記実施例において、ヒートシンク３、４を例えばＣｕやＣｕ系合金で形成した場合（この場合、ヒートシンク３、４の熱膨張係数α１は１７ｐｐｍ程度となる）には、樹脂７の熱膨張係数α２を１０ｐｐｍ以上に設定することが好ましいことを、本発明者らは実験等で確認している。   In the above embodiment, when the heat sinks 3 and 4 are made of, for example, Cu or a Cu-based alloy (in this case, the thermal expansion coefficient α1 of the heat sinks 3 and 4 is about 17 ppm), the thermal expansion coefficient of the resin 7 is used. The present inventors have confirmed through experiments and the like that α2 is preferably set to 10 ppm or more.

また、ヒートシンク３、４を例えばＣｕ系焼結合金やＣｕ系複合材で形成した場合（この場合、ヒートシンク３、４の熱膨張係数α１は８ｐｐｍ程度となる）には、樹脂７の熱膨張係数α２を６ｐｐｍ以上に設定することが好ましいことを、本発明者らは実験等で確認している。   When the heat sinks 3 and 4 are formed of, for example, a Cu-based sintered alloy or a Cu-based composite material (in this case, the thermal expansion coefficient α1 of the heat sinks 3 and 4 is about 8 ppm), the thermal expansion coefficient of the resin 7 The present inventors have confirmed through experiments and the like that α2 is preferably set to 6 ppm or more.

更に、上記実施例においては、樹脂７として、ヤング率が１０ＧＰａ以上のものを使用した。これは、全体の応力のバランスを考慮すると、半導体装置１のほぼ全体をモールドして保護する樹脂７のヤング率が１０ＧＰａ以上あることが好ましいためである。   Furthermore, in the said Example, the thing with a Young's modulus of 10 GPa or more was used as the resin 7. This is because the Young's modulus of the resin 7 that molds and protects almost the entire semiconductor device 1 is preferably 10 GPa or more in consideration of the balance of the overall stress.

尚、上記第２の実施例では、第１の実施例の半導体装置１において、ヒートシンク３、４の熱膨張係数をα１と、樹脂７の熱膨張係数をα２との間に前記条件式が成立するように構成したが、これに限られるものではなく、厚さ比率（ｔ２／ｔ１）が５未満の構成の半導体装置において、前記熱膨張係数の条件式が成立するように構成しても良く、この構成の場合も、ほぼ同じ作用効果を得ることができる。   In the second embodiment, in the semiconductor device 1 of the first embodiment, the conditional expression is established between the thermal expansion coefficient α1 of the heat sinks 3 and 4 and the thermal expansion coefficient α2 of the resin 7. However, the present invention is not limited to this, and a semiconductor device having a thickness ratio (t2 / t1) of less than 5 may be configured so that the conditional expression for the thermal expansion coefficient is satisfied. Even in this configuration, substantially the same operational effects can be obtained.

図８は、本発明の第３の実施例を示す図である。この第３の実施例は、第１の実施例または第２の実施例の半導体装置１において、半導体チップ２の裏面の面粗度をＲａとしたときに、Ｒａ≦５００ｎｍが成立するように構成したものである。   FIG. 8 is a diagram showing a third embodiment of the present invention. The third embodiment is configured so that Ra ≦ 500 nm is established when the surface roughness of the back surface of the semiconductor chip 2 is Ra in the semiconductor device 1 of the first embodiment or the second embodiment. It is a thing.

このように、半導体チップ２の裏面の面粗度Ｒａを設定すると、素子破壊に対する強度を向上させることができ、大きな熱応力が作用したときに、半導体チップ２が割れることを確実に防止できる。   Thus, when the surface roughness Ra of the back surface of the semiconductor chip 2 is set, the strength against element destruction can be improved, and the semiconductor chip 2 can be reliably prevented from cracking when a large thermal stress is applied.

ここで、本発明者らは、上記面粗度Ｒａを変えた半導体装置１の各試作品に、熱応力を作用させたときに、半導体チップ２に割れがどの程度の割合で発生したかを調べ、その結果を図８に示した。この図８において、横軸は、半導体チップ２の裏面の面粗度Ｒａを示し、縦軸は、半導体チップ２の割れ発生率を示している。   Here, the present inventors have determined how much cracking has occurred in the semiconductor chip 2 when thermal stress is applied to each prototype of the semiconductor device 1 with the surface roughness Ra changed. The results are shown in FIG. In FIG. 8, the horizontal axis indicates the surface roughness Ra of the back surface of the semiconductor chip 2, and the vertical axis indicates the crack occurrence rate of the semiconductor chip 2.

この図８から、面粗度Ｒａを５００ｎｍ以下に設定すると、半導体チップ２の強度が高くなり、半導体チップ２がほとんど割れないことがわかる。尚、面粗度Ｒａを２０００ｎｍに設定する場合は、一般的な小さいチップの場合である。   FIG. 8 shows that when the surface roughness Ra is set to 500 nm or less, the strength of the semiconductor chip 2 increases and the semiconductor chip 2 hardly breaks. The case where the surface roughness Ra is set to 2000 nm is a case of a general small chip.

尚、上記第３の実施例においては、第１の実施例または第２の実施例の半導体装置１において、半導体チップ２の裏面の面粗度Ｒａを５００ｎｍ以下としたが、これに限られるものではなく、第１の実施例の厚さ比率（ｔ２／ｔ１）が５未満の構成の半導体装置や、第２の実施例の熱膨張係数の条件式が成立しないような構成の半導体装置等において、半導体チップ２の裏面の面粗度Ｒａを５００ｎｍ以下とするように構成しても良い。このような構成の場合も、ほぼ同じ作用効果を得ることができる。   In the third embodiment, the surface roughness Ra of the back surface of the semiconductor chip 2 is set to 500 nm or less in the semiconductor device 1 of the first embodiment or the second embodiment. However, the present invention is not limited to this. Instead, in a semiconductor device having a thickness ratio (t2 / t1) of less than 5 in the first embodiment, a semiconductor device having a configuration in which the conditional expression for the thermal expansion coefficient in the second embodiment is not satisfied, or the like The surface roughness Ra of the back surface of the semiconductor chip 2 may be 500 nm or less. Even in such a configuration, substantially the same operational effects can be obtained.

図９及び図１０は、本発明の第４の実施例を示す図である。この第４の実施例は、第１の実施例の半導体装置１において、ヒートシンク３、４の厚み寸法（ｔ２）を例えば１．５ｍｍ程度に固定し、半導体チップ２の厚み寸法（ｔ１）を変化させるように構成したものである。そして、第２の実施例では、半導体チップ２の厚み寸法を薄く設定することにより、半導体チップ２の端部部分２ａ（図９参照）で樹脂７が剥離する事態を防止するようにしている。   9 and 10 are diagrams showing a fourth embodiment of the present invention. In the fourth embodiment, in the semiconductor device 1 of the first embodiment, the thickness dimension (t2) of the heat sinks 3 and 4 is fixed to about 1.5 mm, for example, and the thickness dimension (t1) of the semiconductor chip 2 is changed. It is comprised so that it may make it. In the second embodiment, the thickness of the semiconductor chip 2 is set to be thin, thereby preventing the resin 7 from being peeled off at the end portion 2a (see FIG. 9) of the semiconductor chip 2.

具体的には、第４の実施例の場合、半導体チップ２の厚み寸法を変えた半導体装置１の各試作品の素子表面のせん断応力を、シミュレーションによって計算し、図１０に示すグラフを得た。この図１０のグラフにおいて、横軸は半導体チップ２の厚み寸法を示し、縦軸は素子表面のせん断応力比を示し、プロットが実際に試作した半導体装置１を示している。ここで、せん断応力比は、半導体チップ２の厚み寸法が４００μｍ（第１の実施例の厚さ比率（ｔ２／ｔ２）に換算すると、３．７５）の半導体装置１のせん断応力を１．００と定義した場合の数値である。   Specifically, in the case of the fourth embodiment, the shear stress of the element surface of each prototype of the semiconductor device 1 in which the thickness dimension of the semiconductor chip 2 was changed was calculated by simulation, and the graph shown in FIG. 10 was obtained. . In the graph of FIG. 10, the horizontal axis indicates the thickness dimension of the semiconductor chip 2, the vertical axis indicates the shear stress ratio of the element surface, and the plot indicates the actually manufactured semiconductor device 1. Here, the shear stress ratio of the semiconductor device 1 in which the thickness dimension of the semiconductor chip 2 is 400 μm (3.75 when converted to the thickness ratio (t2 / t2) of the first embodiment) is 1.00. It is a numerical value when defined as

この半導体チップ２の厚み寸法が４００μｍ（即ち、せん断応力比が１．００）の半導体装置１に対して温度差の大きい熱サイクルを作用させると、半導体チップ２の表面端部部分２ａ付近の樹脂が剥離してしまうことを、本発明者らは確認している。   When a thermal cycle having a large temperature difference is applied to the semiconductor device 1 having a thickness dimension of 400 μm (that is, a shear stress ratio of 1.00), the resin in the vicinity of the surface end portion 2 a of the semiconductor chip 2. The present inventors have confirmed that is peeled off.

これに対して、半導体チップ２の厚み寸法が２００μｍ（厚さ比率が７．００で、せん断応力比が０．６）の半導体装置１になると、この半導体装置１に対して温度差の大きい熱サイクルを作用させた場合、樹脂剥離の寿命が１０倍以上延びることを、本発明者らは確認している。そして、半導体チップ２の厚み寸法が１００μｍ（厚さ比率が１５．００で、せん断応力比が０．１５）の半導体装置１に対して温度差の大きい熱サイクルを作用させた場合も、樹脂が剥離しないことを確認している。   On the other hand, when the semiconductor device 1 has a semiconductor chip 2 having a thickness dimension of 200 μm (thickness ratio is 7.00 and shear stress ratio is 0.6), heat having a large temperature difference with respect to the semiconductor device 1 is obtained. The present inventors have confirmed that when the cycle is applied, the life of the resin peeling is extended by 10 times or more. Even when a thermal cycle having a large temperature difference is applied to the semiconductor device 1 having the thickness dimension of the semiconductor chip 2 of 100 μm (the thickness ratio is 15.00 and the shear stress ratio is 0.15), the resin It is confirmed that it does not peel.

従って、半導体チップ２の厚み寸法が薄くなるほど（厚さ比率が大きいほど、即ち、せん断応力比が小さいほど）、半導体チップ２表面の樹脂が剥離し難くなることがわかる。   Therefore, it can be understood that the resin on the surface of the semiconductor chip 2 becomes harder to peel off as the thickness dimension of the semiconductor chip 2 becomes thinner (the thickness ratio is larger, that is, the shear stress ratio is smaller).

尚、上記各実施例では、ヒートシンク３、４と半導体チップ２とヒートシンクブロック５とを接合する接合部材として半田箔８を用いたが、これに代えて、半田ペースト等を用いるように構成しても良い。   In each of the above embodiments, the solder foil 8 is used as a joining member for joining the heat sinks 3 and 4, the semiconductor chip 2, and the heat sink block 5, but instead of this, a solder paste or the like is used. Also good.

更に、上記各実施例においては、ヒートシンク３、４間に半導体チップ（放熱素子）２を１個挟むように構成したが、これに限られるものではなく、２個以上のチップ（または２種類以上のチップ）を挟むように構成しても良い。   Further, in each of the embodiments described above, one semiconductor chip (heat dissipating element) 2 is sandwiched between the heat sinks 3 and 4. However, the present invention is not limited to this, and two or more chips (or two or more types) are used. The chip) may be sandwiched.

次に、本発明者らが、先の出願（特願２００１−２２５９６３）を行った後の研究結果について、図１１ないし図１６を参照して説明する。まず、上述した各実施例の半導体装置１の冷熱サイクル等に対する耐久性を向上させるためには、半導体チップ（半導体素子）２とヒートシンク（金属体）３、４、５との接合部における歪みを低減する、または、半導体チップ２の表面のせん断応力を低減すれば、よいことがわかった。   Next, the research results after the present inventors filed the previous application (Japanese Patent Application No. 2001-225963) will be described with reference to FIGS. First, in order to improve the durability of the semiconductor device 1 of each of the above-described embodiments with respect to the thermal cycle and the like, the distortion at the junction between the semiconductor chip (semiconductor element) 2 and the heat sinks (metal bodies) 3, 4, 5 is It has been found that it is better to reduce or to reduce the shear stress on the surface of the semiconductor chip 2.

そして、接合部の歪みを低減して素子破壊を防止する対策としては、（１）半導体チップ２に圧縮応力を加え、圧縮による変位を保持し、引張り応力を発生させないことと、（２）半導体チップ２の圧縮変位を容易にさせるために、半導体チップ２の剛性を低減させること等があることがわかった。以下、これらの条件を数値的に規定しながら、半導体装置１の耐久性が高くなることを具体的に説明する。   As measures for reducing the distortion of the joint portion and preventing element destruction, (1) applying compressive stress to the semiconductor chip 2 to maintain displacement due to compression, and not generating tensile stress, and (2) semiconductor It has been found that the rigidity of the semiconductor chip 2 may be reduced in order to facilitate the compressive displacement of the chip 2. Hereinafter, it will be specifically described that the durability of the semiconductor device 1 is enhanced while numerically defining these conditions.

本発明者らによれば、半導体装置１の耐久性を高くするのに必要な要件が、次の４つにまとめられることがわかった。   According to the present inventors, it has been found that the requirements necessary for increasing the durability of the semiconductor device 1 can be summarized into the following four.

（ａ）半導体素子（半導体チップ２）を構成するシリコンは、圧縮応力が６００ＭＰａ以上かかっても破壊しないが、引張り応力が１００ＭＰａ程度かかるだけで破壊してしまうことが知られているので、製造工程内においても、または、使用環境下においても、常に圧縮応力が半導体素子に加わるように構成することである。   (A) Silicon constituting the semiconductor element (semiconductor chip 2) does not break even when the compressive stress is 600 MPa or more, but it is known that the silicon element breaks only when the tensile stress is about 100 MPa. Even in the interior or in the environment of use, the semiconductor device is configured so that compressive stress is always applied.

（ｂ）半導体素子への圧縮応力の発生源は、金属体と半導体素子（シリコン）との熱膨張係数の差に起因する熱応力である。そして、半導体素子に圧縮応力を加えるためには、熱応力を半導体素子へ確実に伝達し、且つ、圧縮状態を保持するように構成することである。このため、金属体と半導体素子との接合材としては、圧縮応力の伝達の観点から、従来周知のＰｂ−Ｓｎ系はんだと比較して高強度であると共に、圧縮応力の保持の観点から、従来周知のＰｂ−Ｓｎ系はんだと比較して耐クリープ性に優れたはんだを用いる必要がある。   (B) The source of compressive stress applied to the semiconductor element is thermal stress resulting from the difference in thermal expansion coefficient between the metal body and the semiconductor element (silicon). In order to apply a compressive stress to the semiconductor element, the thermal stress is surely transmitted to the semiconductor element and the compressed state is maintained. For this reason, as a bonding material between the metal body and the semiconductor element, from the viewpoint of transmission of compressive stress, it has higher strength than the conventionally known Pb-Sn solder, and from the viewpoint of maintaining compressive stress, It is necessary to use a solder excellent in creep resistance as compared with a known Pb—Sn solder.

（ｃ）半導体素子の圧縮応力を高め、変位を容易にし、且つ、圧縮応力に対する半導体素子からの反発力を低減するためには、半導体素子の厚さを薄くする必要がある。   (C) In order to increase the compressive stress of the semiconductor element, facilitate displacement, and reduce the repulsive force from the semiconductor element against the compressive stress, it is necessary to reduce the thickness of the semiconductor element.

（ｄ）半導体素子へ効果的に圧縮応力を加え、圧縮応力を保持するための別の構成として、半導体素子と金属体を樹脂によりモールドする構成がある。この構成の場合、モールド用の樹脂の熱膨張係数を、金属体の熱膨張係数に対して、同等またはそれ以上とすることにより、圧縮応力状態を保持することができる。   (D) As another configuration for effectively applying compressive stress to the semiconductor element and maintaining the compressive stress, there is a configuration in which the semiconductor element and the metal body are molded with resin. In the case of this configuration, the compressive stress state can be maintained by setting the thermal expansion coefficient of the molding resin to be equal to or higher than the thermal expansion coefficient of the metal body.

以下、上記各要件の作用効果（及び実験データ等）について順に説明する。   Hereinafter, the operational effects (and experimental data, etc.) of the above requirements will be described in order.

まず、図１１は、半導体素子に圧縮応力が加わる過程を説明する図である。半導体素子の表面及び裏面と金属体を接合する場合、半導体素子、金属体及び接合材（はんだ）を所定の温度まで上昇させて、接合材を溶融、硬化させるリフロー行程が一般的に採用される。この場合、接合材が溶融後、冷却されると、接合が完了するが、この過程において、圧縮応力が発生する。   First, FIG. 11 is a diagram illustrating a process in which compressive stress is applied to a semiconductor element. When joining the front and back surfaces of a semiconductor element to a metal body, a reflow process is generally employed in which the semiconductor element, the metal body, and the bonding material (solder) are raised to a predetermined temperature to melt and harden the bonding material. . In this case, when the bonding material is melted and cooled, the bonding is completed. In this process, a compressive stress is generated.

例えば、半導体素子がシリコン、金属体がＣｕである場合、両者の熱膨張係数の差はかなり大きい。そして、一般的に熱膨張係数差が大きいほど、圧縮応力が高くなるが、接合材や金属体の降伏、塑性変形があるため、圧縮応力は線形には増加しない。尚、主な材料の熱膨張係数を下記の表１に示す。   For example, when the semiconductor element is silicon and the metal body is Cu, the difference in thermal expansion coefficient between them is quite large. In general, the larger the difference in thermal expansion coefficient, the higher the compressive stress. However, the compressive stress does not increase linearly because of the yielding and plastic deformation of the bonding material and metal body. The thermal expansion coefficients of main materials are shown in Table 1 below.

Figure 0004376798
そして、冷却後、放置を行うと、接合材のクリープにより圧縮応力が緩和していく。緩和が進展すると、最終的には半導体素子の内部応力はゼロになってしまう。この状態で、半導体素子の発熱や雰囲気温度の上昇が起こると、半導体素子に引張り応力が加わることになり、半導体素子の破壊を起こすおそれがある。
Figure 0004376798
 And if it is allowed to stand after cooling, the compressive stress is relaxed by the creep of the bonding material. As the relaxation progresses, the internal stress of the semiconductor element eventually becomes zero. If the semiconductor element generates heat or the ambient temperature rises in this state, tensile stress is applied to the semiconductor element, which may cause destruction of the semiconductor element.

上記圧縮応力の緩和の挙動は、主に接合材のクリープ特性に起因する。そこで、以下、接合材の強度と緩和について説明する。主な接合材の強度を、下記の表２に示す。   The behavior of relaxation of the compressive stress is mainly caused by the creep characteristics of the bonding material. Therefore, the strength and relaxation of the bonding material will be described below. The strength of main bonding materials is shown in Table 2 below.

Figure 0004376798
一般的に、ＳｎをベースとするＳｎ系はんだは、Ｐｂベースのはんだに比べて、機械的強度が高いことが知られている。このため、接合材としてＳｎ系はんだを使用することが好ましく、これにより、冷却過程で生ずる熱応力を半導体素子へ確実に加えることができ、素子に対して圧縮応力を生じさせることができる。尚、Ｓｎ系はんだは、種類が多く、さまざまな組成のものが提案されているが、２元系、３元系を問わず、Ｐｂ系はんだと比較して、破断強度や降伏応力等が高いはんだを選定すれば良い。
Figure 0004376798
 In general, it is known that Sn-based solder based on Sn has higher mechanical strength than Pb-based solder. For this reason, it is preferable to use Sn-based solder as the bonding material, whereby the thermal stress generated in the cooling process can be reliably applied to the semiconductor element, and a compressive stress can be generated on the element. In addition, Sn type solder has many kinds and the thing of various compositions is proposed, but a fracture strength, yield stress, etc. are high compared with Pb type solder regardless of binary system and ternary system. Select solder.

このようにして、半導体素子に圧縮応力を加えることができたとしても、緩和してしまうと、半導体素子の破壊につながってしまう。そこで、次に、半導体素子の圧縮状態を保持するための要件について考察する。材料に応力が加わると、材料は応力を緩和する方向に変位していく。この挙動がクリープと呼ばれ、Ｐｂでは顕著である。ここで、主な接合材の緩和速度を、下記の表３に示す。   Even if a compressive stress can be applied to the semiconductor element in this manner, if it is relaxed, the semiconductor element will be destroyed. Then, next, the requirements for maintaining the compressed state of the semiconductor element will be considered. When stress is applied to the material, the material is displaced in a direction to relax the stress. This behavior is called creep and is remarkable in Pb. Here, the relaxation rates of the main bonding materials are shown in Table 3 below.

Figure 0004376798
上記表から、Ｐｂはんだに比べて、Ｓｎはんだは、クリープによる歪み速度が遅く、素子の圧縮応力の保持に有効であることがわかる。
Figure 0004376798
 From the above table, it can be seen that Sn solder has a slower strain rate due to creep than Pb solder and is effective in maintaining the compressive stress of the device.

また、図１２は、Ｐｂ系はんだとＳｎ系はんだを使用した場合の半導体素子中央部の圧縮応力値の経時変化（接合後、常温にて放置した場合）を比較したグラフである。この図１２から、接合材をＳｎ系はんだとすることにより、圧縮応力を増加させると共に、その状態を維持することができることがわかる。   FIG. 12 is a graph comparing the change over time in the compressive stress value at the center of the semiconductor element when Pb-based solder and Sn-based solder are used (when left at room temperature after bonding). From FIG. 12, it can be seen that by using Sn solder as the bonding material, the compressive stress can be increased and the state can be maintained.

次に、上述した方法とは別の方法で、素子の圧縮応力を増加させると共に、緩和挙動を抑制することも可能であり、以下、この方法について述べる。素子への圧縮応力は、半導体素子と金属体との熱膨張係数差のような材料物性値以外では、各部の剛性によっても左右されることがわかった。   Next, it is possible to increase the compressive stress of the element and suppress the relaxation behavior by a method different from the method described above, and this method will be described below. It was found that the compressive stress on the element depends on the rigidity of each part except for the material property value such as the difference in thermal expansion coefficient between the semiconductor element and the metal body.

例えば、接合部が塑性や降伏をしないと仮定した場合、金属体に対して相対的に半導体素子の厚さを薄くしていくと、半導体素子はより変位しやすくなり、圧縮応力は増加していく。図１３は、半導体素子に加わる圧縮応力をシミュレーションにより計算した結果、即ち、応力分布を示す図であり、図１３（ａ）は半導体素子の厚さが０.４ｍｍの場合であり、図１３（ｂ）は半導体素子の厚さが０.２ｍｍの場合である。この図１３から、半導体素子の暑さを薄くすることにより、圧縮応力を増加させ得ることがわかる。   For example, if it is assumed that the joint is not plastic or yielded, the semiconductor element becomes more easily displaced and the compressive stress increases as the thickness of the semiconductor element is reduced relative to the metal body. Go. FIG. 13 is a diagram showing a result of calculation of compressive stress applied to a semiconductor element, that is, a stress distribution. FIG. 13A shows a case where the thickness of the semiconductor element is 0.4 mm, and FIG. b) is the case where the thickness of the semiconductor element is 0.2 mm. FIG. 13 shows that compressive stress can be increased by reducing the heat of the semiconductor element.

この結果は、半導体素子の厚さを薄くし、半導体素子の剛性を低減すれば、素子は金属体とともに変位する傾向がより強くなることを意味する。従って、半導体素子の厚さを薄くすると、半導体素子は金属体に「なじむ」ように振舞うため、半導体素子の表面及び裏面のせん断応力が低下し、且つ、半導体装置の耐久性に関わる接合部の歪み成分が縮小することを期待できる。   This result means that if the thickness of the semiconductor element is reduced and the rigidity of the semiconductor element is reduced, the element is more likely to be displaced with the metal body. Accordingly, when the thickness of the semiconductor element is reduced, the semiconductor element behaves so as to “adhere” to the metal body. Therefore, the shear stress on the front surface and the back surface of the semiconductor element is reduced, and the junction portion related to the durability of the semiconductor device is reduced. It can be expected that the distortion component is reduced.

図１４は、半導体素子の厚さとせん断塑性歪みとの関係を実測して得たグラフである。この図１４から、半導体素子の厚さを薄くすると、接合部のせん断歪みが低下することがわかり、特に、素子厚さを２５０μｍ以下とすると、せん断方向の塑性歪み値が１％以下となることがわかる。そして、この場合、冷熱衝撃試験に代表される耐久性能が向上することがわかる。   FIG. 14 is a graph obtained by actually measuring the relationship between the thickness of the semiconductor element and the shear plastic strain. From FIG. 14, it can be seen that when the thickness of the semiconductor element is reduced, the shear strain of the joint portion is reduced. In particular, when the element thickness is 250 μm or less, the plastic strain value in the shear direction is 1% or less. I understand. And in this case, it turns out that the durability performance represented by the thermal shock test improves.

次に、モールド樹脂と圧縮応力（耐久性能）との関係について説明する。基本的に、モールド樹脂は、金属体の熱膨張係数と同等の熱膨張係数を有することが好ましい。例えば、金属体としてＣｕを使用した場合、モールド樹脂の熱膨張係数が１１〜２０ｐｐｍ程度であれば、十分な耐久性能が得られることを実験等で確認している。   Next, the relationship between mold resin and compressive stress (durability) will be described. Basically, the mold resin preferably has a thermal expansion coefficient equivalent to that of the metal body. For example, when Cu is used as the metal body, it has been confirmed through experiments and the like that sufficient durability can be obtained if the thermal expansion coefficient of the mold resin is about 11 to 20 ppm.

図１５は、モールド樹脂の熱膨張係数と、半導体素子に対するＺ方向の応力との関係をシミュレーションにより評価した結果を示す特性図である。この図１５から、樹脂の熱膨張係数を大きくすれば、Ｚ方向も含め、圧縮応力を増加させ得ることがわかる。尚、樹脂の熱膨張係数を２５ｐｐｍ以上とすると、シミュレーション上では、Ｃｕとの界面におけるせん断応力が高くなり、樹脂と金属体との剥離を生じさせるおそれがあることがわかっている。ただし、樹脂の影響は、それほど大きくないため、副次的なパラメータであると推定される。   FIG. 15 is a characteristic diagram showing the result of evaluating the relationship between the thermal expansion coefficient of the mold resin and the stress in the Z direction on the semiconductor element by simulation. From FIG. 15, it can be seen that if the thermal expansion coefficient of the resin is increased, the compressive stress including the Z direction can be increased. In addition, when the thermal expansion coefficient of the resin is 25 ppm or more, it is known from the simulation that the shear stress at the interface with Cu is increased and the resin and the metal body may be separated. However, since the influence of the resin is not so great, it is estimated that it is a secondary parameter.

さて、以上説明した各要件に基づいて、半導体装置を試作し、耐久性評価を実施した結果を、図１６に示す。この図１６においては、縦方向に半導体素子の厚さをとり、横方向に金属体の厚さをとっている。また、「ばつ印」はすべての試作品の半導体素子が割れたものであり、「三角印」は一部の試作品の半導体素子が割れたものであり、「丸印」はすべての試作品の半導体素子が割れなかったものである。図１６上の直線は、前記した比（ｔ２／ｔ１）が５の場合を示している。従って、上記比（ｔ２／ｔ１）が５以下であれば、十分な耐久性が得られることがわかる。   Now, FIG. 16 shows the result of trial manufacture of a semiconductor device based on each requirement described above and the evaluation of durability. In FIG. 16, the thickness of the semiconductor element is taken in the vertical direction, and the thickness of the metal body is taken in the horizontal direction. Also, “Batsu-in” means that all the prototype semiconductor elements are broken, “Triangle” means that some of the prototype semiconductor elements are broken, and “Maru” means all prototypes. The semiconductor element was not broken. The straight line in FIG. 16 shows the case where the ratio (t2 / t1) is 5. Therefore, it can be seen that if the ratio (t2 / t1) is 5 or less, sufficient durability can be obtained.

尚、金属体の厚さに関しては、放熱性の観点からは、厚いほど優れていることが容易にわかるが、一般的なフレーム材として入手可能なものの厚さは、２．５ｍｍ程度までであり、実際には、１.０〜２.０ｍｍ程度のものが量産に適している。   In addition, regarding the thickness of the metal body, from the viewpoint of heat dissipation, it can be easily understood that the thickness is better, but the thickness of what is available as a general frame material is up to about 2.5 mm. Actually, a material of about 1.0 to 2.0 mm is suitable for mass production.

本発明の第１の実施例を示す半導体装置の縦断面図1 is a longitudinal sectional view of a semiconductor device showing a first embodiment of the present invention; 半導体装置の製造工程を示す図The figure which shows the manufacturing process of a semiconductor device 厚さ比率と圧縮応力比との関係を示す特性図Characteristic diagram showing the relationship between thickness ratio and compressive stress ratio 厚さ比率とせん断応力比との関係を示す特性図Characteristic diagram showing the relationship between thickness ratio and shear stress ratio 本発明の第２の実施例を示すものであり、樹脂の熱膨張係数とＺ方向の応力と の関係を示す特性図The characteristic diagram which shows the 2nd Example of this invention and shows the relationship between the thermal expansion coefficient of resin and the stress of a Z direction. 樹脂の熱膨張係数とせん断応力との関係を示す特性図Characteristic diagram showing the relationship between thermal expansion coefficient of resin and shear stress 熱膨張係数とＺ方向の応力及びせん断応力の絶対値との関係を示す特性図Characteristic diagram showing the relationship between the coefficient of thermal expansion and the absolute values of stress and shear stress in the Z direction 本発明の第３の実施例を示すものであり、半導体チップの裏面の面粗度と割れ発生率との関係を示す特性図The characteristic diagram which shows the 3rd Example of this invention and shows the relationship between the surface roughness of the back surface of a semiconductor chip, and a crack generation rate. 本発明の第４の実施例を示す半導体装置の部分縦断面図Partial vertical sectional view of a semiconductor device showing a fourth embodiment of the present invention. 半導体チップの厚み寸法とせん断応力比との関係を示す特性図Characteristic diagram showing the relationship between the thickness dimension of semiconductor chips and the shear stress ratio 半導体素子への圧縮応力発生過程と圧縮応力緩和過程を説明する図Diagram explaining compressive stress generation process and compressive stress relaxation process to semiconductor device 半導体素子にかかる圧縮応力の経時変化を示す特性図Characteristic diagram showing time-dependent change in compressive stress applied to semiconductor elements （ａ）は厚さ０．４ｍｍの半導体素子に加わる圧縮応力の分布を示す図、（ｂ）は厚さ０．２ｍｍの半導体素子に加わる圧縮応力の分布を示す図(A) is a diagram showing a distribution of compressive stress applied to a semiconductor element having a thickness of 0.4 mm, and (b) is a diagram showing a distribution of compressive stress applied to a semiconductor element having a thickness of 0.2 mm. 半導体素子の厚さと接合部のせん断塑性歪みとの関係を示す特性図Characteristic diagram showing the relationship between the thickness of the semiconductor element and the shear plastic strain at the joint 樹脂の熱膨張係数と半導体素子に加わるＺ方向の応力との関係を示す特性図Characteristic diagram showing the relationship between the thermal expansion coefficient of the resin and the stress in the Z direction applied to the semiconductor element 半導体素子の厚さと金属体の厚さと耐久評価結果との関係を示す図The figure which shows the relationship between the thickness of a semiconductor element, the thickness of a metal body, and the endurance evaluation result

符号の説明Explanation of symbols

１は半導体装置、２は半導体チップ（発熱素子、半導体素子）、３は下側ヒートシンク（放熱板、第１の金属体）、４は上側ヒートシンク（放熱板、第２の金属体）、５はヒートシンクブロック（第３の金属体）、６は半田（接合層）、７は樹脂を示す。   1 is a semiconductor device, 2 is a semiconductor chip (heating element, semiconductor element), 3 is a lower heat sink (heat sink, first metal body), 4 is an upper heat sink (heat sink, second metal body), 5 is A heat sink block (third metal body), 6 is solder (bonding layer), and 7 is resin.

Claims (9)

半導体素子と、この半導体素子の裏面に接合され電極と放熱を兼ねる第１の金属体と、前記半導体素子の表面側に接合され電極と放熱を兼ねる第２の金属体と、前記半導体素子の表面と前記第２の金属体との間に接合された第３の金属体とを備え、前記一対の放熱板の一面が露出するように装置のほぼ全体を樹脂でモールドした半導体装置において、
前記半導体素子と前記金属体とを接合する接合層における塑性歪み率が１％以下となるように、前記半導体素子の厚さを２５０μｍ以下とすると共に、
前記半導体素子の厚さ寸法をｔ１とし、前記第１の金属体及び前記第２の金属体の厚さ寸法をｔ２としたときに、
ｔ２／ｔ１≧５
が成立するように構成したものであって、
前記モールド樹脂により装置全体を拘束保持するように構成したことを特徴とする半導体装置。 A semiconductor element, a first metal body bonded to the back surface of the semiconductor element and serving as an electrode and heat dissipation, a second metal body bonded to the surface side of the semiconductor element and also serving as a heat sink, and a surface of the semiconductor element And a third metal body joined between the second metal body and a semiconductor device in which almost the entire device is molded with a resin so that one surface of the pair of heat sinks is exposed.
While the thickness of the semiconductor element is 250 μm or less so that the plastic strain rate in the bonding layer for bonding the semiconductor element and the metal body is 1% or less,
When the thickness dimension of the semiconductor element is t1, and the thickness dimension of the first metal body and the second metal body is t2,
t2 / t1 ≧ 5
Is configured to hold,
A semiconductor device characterized in that the entire device is restrained and held by the mold resin. 半導体素子と、この半導体素子の裏面に接合され電極と放熱を兼ねる第１の金属体と、前記半導体素子の表面側に接合され電極と放熱を兼ねる第２の金属体と、前記半導体素子の表面と前記第２の金属体との間に接合された第３の金属体とを備え、前記一対の放熱板の一面が露出するように装置のほぼ全体を樹脂でモールドした半導体装置において、
前記半導体素子表面のせん断応力が３５ＭＰａ以下となるように、前記半導体素子の厚さを２５０μｍ以下とすると共に、
前記半導体素子の厚さ寸法をｔ１とし、前記第１の金属体及び前記第２の金属体の厚さ寸法をｔ２としたときに、
ｔ２／ｔ１≧５
が成立するように構成したものであって、
前記モールド樹脂により装置全体を拘束保持するように構成したことを特徴とする半導体装置。 A semiconductor element, a first metal body bonded to the back surface of the semiconductor element and serving as an electrode and heat dissipation, a second metal body bonded to the surface side of the semiconductor element and also serving as a heat sink, and a surface of the semiconductor element And a third metal body joined between the second metal body and a semiconductor device in which almost the entire device is molded with a resin so that one surface of the pair of heat sinks is exposed.
The thickness of the semiconductor element is 250 μm or less so that the shear stress of the semiconductor element surface is 35 MPa or less,
When the thickness dimension of the semiconductor element is t1, and the thickness dimension of the first metal body and the second metal body is t2,
t2 / t1 ≧ 5
Is configured to hold,
A semiconductor device characterized in that the entire device is restrained and held by the mold resin. 前記３個の金属体のうちの少なくとも１つの金属体の厚みを１．０ｍｍ以上としたことを特徴とする請求項１または２記載の半導体装置。 3. The semiconductor device according to claim 1, wherein a thickness of at least one of the three metal bodies is 1.0 mm or more. 前記接合層をＳｎ系はんだで構成したことを特徴とする請求項１ないし３のいずれかに記載の半導体装置。 4. The semiconductor device according to claim 1, wherein the bonding layer is made of Sn-based solder. 前記半導体素子のデバイス構造を、トレンチゲートタイプとしたことを特徴とする請求項１ないし４のいずれかに記載の半導体装置。 5. The semiconductor device according to claim 1, wherein the device structure of the semiconductor element is a trench gate type. 前記金属体の熱膨張係数をα１とし、前記樹脂の熱膨張係数をα２としたときに、
０．５α１≦α２≦１．５α１
が成立するように構成したことを特徴とする請求項１または２に記載の半導体装置。 When the thermal expansion coefficient of the metal body is α1, and the thermal expansion coefficient of the resin is α2,
0.5α1 ≦ α2 ≦ 1.5α1
The semiconductor device according to claim 1, wherein the semiconductor device is configured so that 前記半導体素子の裏面の面粗度をＲａとしたときに、
Ｒａ≦５００ｎｍ
が成立するように構成したことを特徴とする請求項１または２に記載の半導体装置。 When the surface roughness of the back surface of the semiconductor element is Ra,
Ra ≦ 500nm
The semiconductor device according to claim 1, wherein the semiconductor device is configured so that 前記一対の放熱板は、その一面が前記樹脂から露出するようにモールドされていることを特徴とする請求項１ないし７のいずれかに記載の半導体装置。 It said pair of heat sink, the semiconductor device according to any one of claims 1 to 7, characterized in that one surface thereof is molded so as to be exposed from the resin. 前記半導体素子と前記第１の金属体とは、接合層により直接接合されていることを特徴とする請求項１ないし８のいずれかに記載の半導体装置。
Wherein the semiconductor element and the first metal body, a semiconductor device according to any one of claims 1, characterized in that it is directly bonded by a bonding layer 8.
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