JP4352082B2 - Frequency synchronization circuit, method, program, and receiver using the same - Google Patents

Description

  The present invention relates to a frequency synchronization circuit, a method, a program, and a receiving apparatus using these, which cancel a frequency offset of a received baseband signal.

  Generally, in wireless communication, frequency synchronization between transmission and reception is necessary. Non-Patent Document 1 discloses a frequency synchronization method in a wireless communication system using orthogonal frequency division multiplexing (OFDM) signals.

  More specifically, in Non-Patent Document 1, coarse frequency synchronization that estimates and corrects the amount of phase rotation using the correlation of guard intervals to which a cyclic prefix is applied, and subcarriers after fast Fourier transform (FFT) processing. Frequency synchronization is performed in two stages, ie, fine frequency synchronization for estimating and correcting the amount of phase rotation. In a wireless communication system in which a cyclic prefix is applied to the guard interval, the end of the symbol is copied to the beginning as the guard interval for each OFDM symbol, and the phase rotation amount can be estimated from the correlation due to the repetition of the guard interval.

On the other hand, paragraphs [0002] to [0004] of Patent Document 1 and FIG. 43 describe a method of estimating a frequency offset necessary for frequency synchronization after multiplying a received signal to remove a modulation component. .
JP-A-9-214293 802.11 high-speed wireless LAN textbook, ISBN 4-87280-490-2

  The technique described in Non-Patent Document 1 is based on a wireless communication system in which a cyclic prefix is applied to a guard interval when performing coarse frequency synchronization. Therefore, in a wireless communication system in which a unique word is applied to the guard interval or a transmission signal is a so-called burst signal with a short duration, the frequency offset is not effectively canceled.

  On the other hand, in the method using the multiplication process described in Patent Document 1, if the multiplication ratio is increased too much, the signal-to-noise ratio (SNR) of the multiplied signal is deteriorated, and the estimation accuracy of the frequency offset is lowered. Therefore, since the upper limit of the multiplication ratio is limited, the frequency offset that can be canceled is also limited.

  Accordingly, an object of the present invention is to provide a frequency synchronization circuit capable of canceling a frequency offset more effectively.

  A frequency synchronization circuit according to an aspect of the present invention includes: a first multiplication unit that multiplies a received baseband signal by a first multiplication ratio and outputs a first multiplied signal; and suppresses noise in the first multiplied signal. A filter that outputs a filter signal; a second multiplier that multiplies the filter signal by a second multiplication ratio and outputs a second multiplied signal; and a frequency of the received baseband signal from the second multiplied signal An estimator that estimates an offset and outputs an estimated value; and an offset remover that multiplies the received baseband signal by the estimated value to remove the frequency offset.

  The frequency synchronization circuit according to another aspect of the present invention includes: an offset removing unit that multiplies an input signal by a cumulative estimated value of a frequency offset to remove the frequency offset and output an offset removed signal; A first multiplier for multiplying by a multiplication ratio and outputting a first multiplied signal; a filter for suppressing a noise in the first multiplied signal and outputting a filter signal; and the filter signal at a second multiplication ratio A second multiplying unit that multiplies and outputs a second multiplied signal; an estimation unit that estimates the frequency offset from the second multiplied signal and outputs the accumulated estimated value and the residual estimated value; And a setting unit that sets the second multiplication ratio so as to be within an allowable range.

  According to the present invention, the frequency offset can be effectively canceled even if a unique word is used for the guard interval or the transmission signal is a burst signal.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
As shown in FIG. 1, the frequency synchronization circuit according to the first embodiment of the present invention includes a multiplication unit 100, a frequency offset estimation unit 140, and a mixer 150. The reception baseband signal 11 including the digitally modulated symbol that is an input of the frequency synchronization circuit is input to the multiplier 100 and the mixer 150.

The multiplier 100 multiplies the input received baseband signal 11 by a predetermined multiplication ratio, and passes the multiplied signal to the frequency offset estimator 140. The multiplied signal output from the multiplier 100 is input to the frequency offset estimator 140.

  The frequency offset estimator 140 estimates the frequency offset of the received baseband signal 11 from the multiplied signal. As will be described later, if the frequency offset is estimated after the reception baseband signal 11 is multiplied by the multiplication unit 100, the estimation accuracy can be improved. The estimated frequency offset value 15 is input to the offset removing unit 150.

  The offset removal unit 150 includes, for example, a mixer and a filter, and multiplies the input received baseband signal 11 by the estimated value 15 (estimated offset frequency) of the frequency offset by the mixer. When the reception baseband signal 11 is multiplied by the estimated value 15 of the frequency offset, the frequency components of the sum and difference of the frequency of the reception baseband signal 11 and the estimated value 15 are obtained. Therefore, the offset removing unit 150 further removes only the frequency component of the received baseband signal 11 from which the frequency offset has been removed by removing only the frequency component of the difference by removing the sum frequency component from the output of the mixer. Output.

  Next, the multiplication unit 100 will be described. As shown in FIG. 2, for example, the multiplication unit 100 includes a first multiplication unit 110, a filter 120, and a second multiplication unit 130, and performs multiplication processing in two stages.

  The first multiplication unit 110 multiplies the input signal to the multiplication unit 100 by a predetermined first multiplication ratio, and passes the first multiplication signal 12 to the filter 120. Here, the first multiplication ratio is preferably set to a value that can remove the modulation component of the received baseband signal 11. As an example, consider a case where a received signal is composed of a symbol sequence modulated by four-phase phase shift keying (QPSK). At this time, the signal point arrangement (constellation) of the symbols on the IQ plane is as follows. The symbol “00” is a point of phase π / 4 on the IQ plane, the symbol “01” is a point of phase 3π / 4 on the IQ plane, and the symbol “11” is a phase on phase IQ. At a point of 5π / 4, the symbol “10” is arranged at a point of phase 7π / 4 on the IQ plane.

  If the first multiplication ratio is “4”, the modulation component of each symbol included in the received baseband signal 11 is removed. That is, when the reception baseband signal 11 is multiplied by the multiplication ratio 4, the phase of the modulation component of the symbol “00” becomes π, the phase of the modulation component of the symbol “10” becomes 3π (= π), and the symbol “11 ”Is 5π (= π), and the phase of the modulation component of symbol“ 10 ”is 7π (= π), and the first multiplied signal 12 from which the symbol modulation component is removed is obtained. .

  The filter 120 detects the frequency offset multiplied by the first multiplication ratio from the first multiplication signal 12 output from the first multiplication unit 110. That is, the filter 120 passes the first band signal component in the vicinity of the multiplied frequency offset, suppresses the noise component existing in the other second band, and uses the first band signal component as the filter signal 13 as the second signal. To the multiplier 130. Although the specific configuration of the filter 120 is not particularly limited, for example, the filtering process is realized by a convolution operation of the first multiplied signal 12 and the filter function.

  The second multiplication unit 130 multiplies the filter signal 13 from the filter 120 by the second multiplication ratio and outputs the second multiplied signal 14. The second multiplication ratio will be described using the following table.

  As shown in Table 1, the second multiplication ratio is a value obtained by subtracting the first multiplication ratio from the final multiplication ratio P by the multiplication unit 100. The final multiplication ratio P is a multiplication ratio required to suppress an estimation error of a frequency offset, which will be described later, within an allowable range in a system in which the frequency synchronization circuit according to the present embodiment is used. The correspondence between the modulation scheme shown in Table 1 and the first multiplication ratio is merely an example, and the present invention is not limited to this. Therefore, the first multiplication ratio shown in Table 1 may be increased or decreased, and the second multiplication ratio may be decreased or increased accordingly.

Here, the technical significance of performing the multiplication processing of the frequency synchronization circuit according to this embodiment in two stages will be described.
For example, suppose that the multiplication unit 100 shown in FIG. 1 is replaced with a multiplication unit that simply P-multiplies a signal composed of a symbol sequence modulated by QPSK. At this time, the multiplied signal shown in FIG. 3A is obtained. In general, when a signal is multiplied by m, the signal-to-noise ratio (SNR) is degraded by ₁₀ log ₁₀ m (dB), and the noise component affects the signal component over a wide band. Therefore, if the SNR is deteriorated by multiplying the reception baseband signal 11 by a large multiplication ratio in the multiplication unit 100, the frequency offset estimation unit 140 becomes difficult to estimate the frequency offset.

  On the other hand, as shown in FIG. 2, the multiplication process is divided into two stages, the received baseband signal 11 is multiplied by the first multiplication unit 110 at the first multiplication ratio “4”, and the filter 120 outputs the first multiplied signal 12. When the filtering process is performed and the second multiplication unit multiplies by the second multiplication ratio “P-4”, the second multiplied signal 14 having a high SNR as shown in FIG. 3B is obtained.

  In other words, the first multiplication unit 110 performs only the multiplication processing necessary to suppress noise by the filter 120 and extract the frequency offset. Since the filter 120 suppresses noise existing in the second band excluding the first band in the vicinity of the frequency offset of the first multiplied signal 12, the SNR degradation can be minimized. Therefore, the second multiplied signal 14 obtained by multiplying the output signal of the filter 120 by the second multiplying unit 130 estimates the frequency offset as compared to the first multiplied signal 12 shown in FIG. 3A, as shown in FIG. 3B. It is an easy high SNR signal.

  The frequency offset estimation unit 140 estimates the frequency offset of the received baseband signal 11 from the multiplied signal (second multiplied signal 14) from the multiplication unit 100 and passes the estimated value 15 to the mixer 150. Specifically, the frequency offset estimation unit 140 estimates the frequency offset from the multiplied signal using, for example, a discriminator (frequency discriminator) or a fast Fourier transform.

  First, a method for estimating a frequency offset using a discriminator will be described. When a complex discrete time signal x (n) = I (n) + jQ (n) corresponding to an arbitrary sample number n is input, the output f (n) of the discriminator can be expressed as follows. .

Here, fs indicates a sampling frequency. The output f of this discriminator (n corresponds to the frequency offset. In this way, the frequency offset can be estimated by detecting f (n) in equation (1) using the discriminator.

  Next, a method for estimating a frequency offset using fast Fourier transform will be described. The frequency corresponding to the peak of the power spectrum obtained by fast Fourier transform of the complex discrete time signal x (n) corresponds to the frequency offset. That is, the frequency offset can be estimated by detecting the frequency that gives the peak of the power spectrum using the fast Fourier transform.

  Here, several methods for estimating the frequency offset with higher accuracy than the above-described peak detection will be exemplified.

  First, a method for estimating the frequency offset using the output of the discriminator will be described. If the output of the discriminator is f (k), the frequency offset fo is estimated by an average value of f (k), for example, and can be expressed by the following equation.

Here, fo represents a frequency offset, and K represents a signal size. The median value of the output f (k) of the discriminator may be used as the frequency offset.

  Next, a method for estimating a frequency offset using fast Fourier transform will be described. For example, as shown in FIG. 4, the frequency offset fo can be estimated by an arithmetic average of frequencies f1 and f2 at which a predetermined XdB level decrease is detected from the maximum peak of the power spectrum. Further, the weighted average of the power spectrum p (k) may be estimated as the frequency offset according to the following equation.

Here, fo represents the frequency offset, and K represents the size of the fast Fourier transform.

  Finally, a method for estimating the frequency offset from the interval between the zero cross points will be described. Assuming that the interval between the i-th zero-cross point and the (i + 1) -th zero-cross point is Tdi and the number of zero-cross points is L, the frequency offset can be estimated as follows.

  The frequency offset estimation unit 140 estimates the frequency offset as described above. However, in the method using the discriminator, the estimation accuracy is strongly influenced by the SNR when the frequency offset is low. Further, in the method using the fast Fourier transform, there is a limit to the estimation accuracy due to the frequency resolution Δf per bin (BIN). However, in this embodiment, the frequency offset estimation unit 140 estimates the frequency offset indirectly from the multiplied signal without directly estimating the frequency offset from the input signal. Can be improved.

Consider a case where the frequency offset is estimated from the peak of the power spectrum obtained by the fast Fourier transform. The BIN number corresponding to the peak of the power spectrum is k, and the frequency resolution is Δf. At this time, the frequency offset fo of the input signal is estimated to be k * Δf, but may actually exist in the range of (k−1) * Δf <fo <(k + 1) * Δf. That is, the estimated value k * Δf may include an estimation error of Δf at the maximum. On the other hand, the frequency offset fmo (= m * fo) of the multiplied signal obtained by multiplying the input signal by m is estimated as k * m * Δf, and (k * m−1) * Δf <fmo <(k * m + 1) * Δf Can exist in range. When the frequency offset fmo of the multiplied signal is divided by the multiplication ratio m, an estimated value k * Δf of the frequency offset fo of the input signal is obtained. The frequency offset fo at this time is (k−1 / m) * Δf <Fo <(k + 1 / m) * Δf, and the estimation error is Δf / m at most. That is, the estimation error can be reduced to the inverse of the multiplication ratio. Since the SNR deteriorates by ₁₀ log ₁₀ (m) by multiplying the input signal by m as described above, if the size of the fast Fourier transform is K, the influence on the final SNR is ₁₀ log ₁₀ (K / m ) Therefore, if the multiplication ratio is excessively increased, the SNR is deteriorated.

  5A, 5B, and 5C show frequency offset estimation errors when 8-, 16-, and 32-fold signals are input to the frequency offset estimation unit 140, respectively. 5A, 5B, and 5C, the horizontal axis represents SNR [dB] and the vertical axis represents the frequency offset estimation error [Hz], respectively, and plots both the case where the filter 120 is present and the case where the filter 120 is not present. 5A, 5B, and 5C, it can be seen that the filter 120 improves the frequency offset estimation error particularly when the SNR is low. It is also possible to confirm the aforementioned property that the frequency offset estimation error is improved as the multiplication ratio increases.

  The mixer 150 cancels the estimated value 15 given from the frequency offset estimator 140 from the received baseband signal 11 and outputs an offset removal signal 16.

Hereinafter, the frequency synchronization method according to the present embodiment will be described with reference to the flowchart shown in FIG.
First, the input signal is multiplied by the first multiplication ratio (step S701). Here, the first multiplication ratio is, for example, a number that suppresses the modulation component of the symbol included in the input signal. Next, filter processing for suppressing noise in the second band excluding the first band near the frequency offset from the first multiplied signal 12 obtained in step S701 is performed (step S702).

  Next, the filter signal 13 obtained in step S702 is multiplied by the second multiplication ratio (step S703). Here, the second multiplication ratio is, for example, the first multiplication ratio from the multiplication ratio necessary for suppressing the estimation error of the frequency offset within the allowable range in the system using the frequency synchronization method according to the present embodiment. Is the number obtained by subtracting.

  Next, the frequency offset is estimated from the second multiplied signal 14 obtained in step S703 (step S704). For example, the frequency offset is estimated by dividing the frequency corresponding to the peak of the power spectrum obtained by fast Fourier transform of the second multiplied signal 14 by the multiplication ratio.

  Next, the frequency offset obtained in step S705 is canceled from the input signal (step S706). For example, the frequency offset is canceled from the input signal by multiplying the input signal by the frequency offset and extracting only the low frequency component.

  As described above, in the present embodiment, the frequency offset estimation error is improved by dividing the multiplication process into two stages and inserting the filtering process therebetween. Therefore, according to the present embodiment, the frequency offset can be effectively canceled even for a system using a burst signal having a short duration, a unique word such as Chinese terrestrial digital broadcasting (DTMB) or 3GPP. .

(Second Embodiment)
As shown in FIG. 7, the frequency synchronization circuit according to the second embodiment of the present invention includes a multiplication unit 200, a frequency offset estimation unit 240, a mixer 150, and a multiplication ratio setting unit 260. 7, the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The mixer 150 outputs an offset removal signal 16 obtained by canceling the cumulative estimated value 15B of the frequency offset given in advance from the frequency offset estimating unit 240 from the received baseband signal 11 including the digitally modulated symbol. The offset removal signal 16 is also input to the multiplication unit 200.

  The multiplication unit 200 is basically the same as the multiplication unit 100 according to the first embodiment. However, when the final multiplication ratio is set by the multiplication ratio setting unit 260 described later, It is possible to change the multiplication ratio of. The multiplier 200 performs the same processing as the multiplier 100 on the input offset removal signal 16 and passes the multiplied signal to the frequency offset estimator 240.

  The frequency offset estimator 240 estimates the residual frequency offset from the multiplied signal, passes the residual estimated value 15A of the frequency offset to the multiplication ratio setting unit 260, and supplies the cumulative estimated value 15B obtained by accumulating the residual estimated value to the mixer 150. hand over. Here, as described above, when the frequency synchronization circuit according to the present embodiment is first operated, an initial value of the cumulative estimated value 15B of the frequency offset to be given to the mixer 150 is required. For example, 0 is used. . As described above, the frequency offset estimation unit 240 estimates the residual frequency offset after multiplying the offset removal signal 16 in which the cumulative estimated value 15B of the frequency offset is canceled by the mixer 150. For example, if the frequency offset estimation unit 240 estimates the frequency offset using fast Fourier transform, the BIN number corresponding to the peak of the power spectrum obtained from the amplitude spectrum of the multiplied signal is multiplied by the frequency resolution Δf. The remaining frequency offset is estimated by dividing the multiplication ratio in the multiplication unit 200 from the obtained value. If the i-th residual estimated value is foi, the p-th residual estimated value is fop, and the cumulative estimated value 15B of the offset frequency canceled by the mixer 150 is fo1 + fo2 +. Since the absolute value of the frequency offset residual estimation value foi monotonously decreases, the residual estimation value approaches 0 each time estimation is performed, and the frequency offset cumulative estimation value 15B canceled by the mixer 150 becomes a true value. Converge.

  The multiplication ratio setting unit 260 sets a multiplication ratio determined based on the residual frequency offset estimated value 15 </ b> A from the frequency offset estimation unit 240 in the multiplication unit 200. From the sampling theorem, the maximum multiplication ratio n that can be set in the multiplication unit 200 can be expressed as n = fs / | 2fo | using the sampling frequency fs and the residual frequency offset fo. As described above, the absolute value of the residual estimated value 15A output from the frequency offset estimation unit 240 monotonously decreases and converges to 0, so that the multiplication ratio that can be set by the multiplication ratio setting unit 260 is equivalently infinite. Therefore, ideally, the multiplying ratio setting unit 260 can increase the multiplying ratio that can be set in the multiplying unit 200 indefinitely, and therefore, the optimum multiplying factor according to the system in which the frequency synchronization circuit according to the present embodiment is used. The ratio can be set.

  As described above, in this embodiment, the residual estimated value of the frequency offset is accumulated, and the remaining frequency offset is estimated from the received baseband signal from which the accumulated estimated value is canceled. Therefore, according to the present embodiment, since the residual estimated value of the frequency offset gradually converges to 0, it is possible to effectively cancel the frequency offset by setting a desired multiplication ratio regardless of the sampling frequency.

(Third embodiment)
As shown in FIG. 8, the frequency synchronization circuit according to the third exemplary embodiment of the present invention includes a switch 370, a buffer 380, a mixer 150, a multiplication unit 200, a frequency offset estimation unit 240, a multiplication ratio setting unit 260, and a switching determination unit 390. Have 8, the same parts as those in FIG. 7 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The switch 370 switches the connection so that one of the received baseband signal 11 including the digitally modulated symbol or the offset removal signal 16 from the mixer 150 designated by the switching determination unit 390 is input to the buffer 380.

  The buffer 380 temporarily stores the signal input via the switch 370 and outputs the signal to the mixer 150. The signal stored in the buffer 380 is sequentially updated by the input signal.

  The mixer 150 cancels the cumulative estimated value 15B of the frequency offset given from the frequency offset estimation unit 240 from the output signal of the buffer 380, and passes the offset removal signal 16 to the multiplication unit 200. At this time, depending on the connection of the switch 370, the offset removal signal 16 is input to the buffer 380 via the switch 370 as described above.

  Similarly to the second embodiment, the frequency offset estimation unit 240 estimates the residual frequency offset based on the multiplied signal from the multiplication unit 200, and passes the residual estimated value 15A to the multiplication ratio setting unit 260 and the switching determination unit 390. The accumulated estimated value 15B is passed to the mixer 150.

  For example, the switching determination unit 390 compares the absolute value of the residual estimated value of the frequency offset given from the multiplication ratio setting unit 260 with a predetermined threshold value, and switches the switch 370 according to the comparison result. Specifically, if the absolute value is less than the threshold value, the received baseband signal 11 is input to the buffer 380. If the absolute value is equal to or greater than the threshold value, the offset removal signal 16 from the mixer 150 is buffered. The switch 370 is switched so as to be input to 380. Note that the switching determination conditions by the switching determination unit 390 are not limited to those described above. For example, the switching may be performed when the estimated accumulated value 15B of the frequency offset falls within a predetermined range. In the receiving apparatus using the frequency synchronization circuit according to the present embodiment, the switching determination unit 390 may perform switching when the bit error rate (BER) is lower than a predetermined value.

  As described above, in the present embodiment, the synchronization process is repeated until the frequency offset can be sufficiently canceled. Therefore, according to the present embodiment, the frequency offset can be effectively canceled even for a signal having a limited duration such as a burst signal. The present embodiment is also effective in a system that requires high-speed pull-in.

(Fourth embodiment)
The frequency synchronization circuit according to the fourth embodiment of the present invention is obtained by replacing the multiplication unit with the multiplication unit shown in FIG. 9 in any of the first to third embodiments described above. As shown in FIG. 9, the multiplication unit according to the present embodiment includes a first multiplication unit 410, a fast Fourier transformer (FFT) 411, a bandwidth estimation unit 412, a multiplication ratio setting unit 413, a filter 420, and a second multiplication unit. Part 430.

  The first multiplication unit 410 is basically the same as the first multiplication unit 110 according to the first embodiment, but the first multiplication ratio is set by a multiplication ratio setting unit 413 described later. That is, the first multiplication unit 410 multiplies the received signal including the digitally modulated symbol by the first multiplication ratio set by the multiplication ratio setting unit 413 and passes the first multiplied signal 12 to the filter 420. The first multiplied signal 12 is also output to the FFT 411.

  The FFT 411 passes the power spectrum obtained by fast Fourier transform of the first multiplied signal 12 to the bandwidth calculation unit 412.

  The bandwidth estimation unit 412 estimates the bandwidth of the first multiplied signal 12 from the power spectrum. The bandwidth estimation method is not particularly limited. As an example, the bandwidth estimation unit 412 calculates the bandwidth by the following method. First, the bandwidth estimation unit 412 detects the maximum peak of the power spectrum. A point where a level drop of X dB is observed from the maximum peak in both frequency directions (ie, high frequency side and low frequency side) from the frequency where the maximum peak is detected is detected, and the frequency width of both points is estimated bandwidth And The level drop XdB from the maximum peak is empirically obtained, and the specific numerical value is not particularly limited. The bandwidth calculation unit 412 detects a line spectrum for a plurality of peaks in the power spectrum. The line spectrum is a spectrum in which a significant level of attenuation is observed within about 1 BIN to several BINs. When the line spectrum does not exist, it can be determined that the multiplication by the first multiplication unit 410 described above is insufficient and the removal of the modulation component is incomplete. The bandwidth estimation unit 412 notifies the multiplication ratio setting unit 413 of the estimated bandwidth and the detection result of the line spectrum.

  The multiplication ratio setting unit 413 derives a new first multiplication ratio based on the detection result of the estimated bandwidth and the line spectrum notified from the bandwidth estimation unit 412 and sets it in the first multiplication unit 410. . Specifically, the multiplication ratio setting unit 413 sets the previous time when the estimated bandwidth notified from the bandwidth estimation unit 412 is wider than the estimated bandwidth notified last time and no line spectrum is detected. A first multiplication ratio larger than the first multiplication ratio is newly set. On the other hand, when the estimated bandwidth notified from the bandwidth estimation unit 412 is equal to or less than the estimated bandwidth notified last time or the line spectrum is detected, the first multiplication ratio set last time is maintained. The first multiplication ratio may be increased by a power of 2 such as 1, 2, 4,..., Or may be increased by 1 such as 1, 2, 3, 4,. However, it may be increased by other rules.

  As described above, in the present embodiment, the first multiplication ratio is adaptively set according to the bandwidth of the first multiplied signal 12 and the presence or absence of the line spectrum. Therefore, according to the present embodiment, the frequency offset can be canceled with high accuracy even in a system in which the symbol modulation scheme is changed to unknown or adaptive.

(Fifth embodiment)
The frequency synchronization circuit according to the fifth embodiment of the present invention is obtained by replacing the filter shown in FIG. 10 with any one of the first to fourth embodiments described above. As illustrated in FIG. 10, the filter according to the present embodiment includes an FFT 521, a frequency offset estimation unit 522, a noise suppression unit 523, and a fast inverse Fourier transformer (IFFT) 524.

  The FFT 521 performs fast Fourier transform on the first multiplied signal 12 from the first multiplying unit, and passes the amplitude spectrum to the frequency offset estimating unit 522 and the noise suppressing unit 523.

  The frequency offset estimation unit 522 detects, for example, a sharp power spectrum having a predetermined bandwidth or less from the power spectrum calculated from the amplitude spectrum, estimates the frequency offset from the BIN number indicating the maximum power spectrum among these, The noise suppression unit 523 is notified.

  The noise suppression unit 523 suppresses noise in the fast Fourier transform signal based on the estimated value of the frequency offset from the frequency offset estimation unit 522. Hereinafter, a specific example of noise suppression by the noise suppression unit 523 will be described. For example, the noise suppression unit 523 may pass the first interval of several BIN around the estimated value of the frequency offset and replace the signal values of the remaining second interval with 0. Further, the noise suppression unit 523 may multiply, for example, a window function having a bandwidth of ± several BIN around the estimated value of the frequency offset. Further, the noise suppression unit 523 may pass the signal in the first section until the signal level is lowered by several dB from the signal level in the estimated value of the frequency offset, for example, and replace the signal value in the remaining second section with 0.

  The IFFT 524 performs a fast inverse Fourier transform on the signal from the noise suppression unit 523 and passes the signal to the second multiplication unit as the filter signal 13.

  As described above, in the present embodiment, the first multiplied signal 12 is subjected to the fast Fourier transform, and the signal value in the second section excluding the first section in the vicinity of the frequency offset is replaced with 0. Therefore, according to the present embodiment, for example, noise can be effectively suppressed even for a single burst signal.

(Sixth embodiment)
As shown in FIG. 11, a receiving apparatus according to the sixth embodiment of the present invention includes an antenna 601, a receiving unit 602, an analog-digital converter (ADC) 603, a frequency synchronization circuit 604, a phase fluctuation suppressing unit 605, a resampler. 606, a symbol synchronization unit 607, and a demodulation / decoding unit 608.

  The antenna 601 receives a signal including a digitally modulated symbol transmitted from a master station (not shown). The receiving unit 602 down-converts the signal received by the antenna 601 and extracts the received baseband signal. The ADC 603 performs analog-to-digital conversion on the received baseband signal extracted by the receiving unit 602 and outputs it to the frequency synchronization circuit 604.

  The frequency synchronization circuit 604 is a frequency synchronization circuit according to any one of the first to fifth aspects, and cancels the frequency offset from the reception baseband signal output from the ADC 603 to obtain an offset removal signal.

  The phase fluctuation suppression unit 605 suppresses the gradual phase fluctuation of the synchronization signal from the frequency synchronization circuit 604 and passes it to the resampler 606. The resampler 606 suppresses the fluctuation in the sampling rate of the synchronization signal given from the phase fluctuation suppression unit 605 and passes it to the symbol synchronization unit 607.

  The symbol synchronization unit 607 performs timing detection for extracting symbols from the synchronization signal supplied from the resampler 606. The demodulation / decoding unit 608 demodulates and decodes the symbols according to the timing detected by the symbol synchronization unit 607.

  As described above, in the present embodiment, the frequency synchronization circuit according to any one of the first to fifth is used in the receiving apparatus. Therefore, according to this embodiment, the carrier frequency between transmission and reception can be appropriately synchronized even in a system in which a unique word is applied to the guard interval portion instead of the cyclic prefix.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. Further, for example, a configuration in which some components are deleted from all the components shown in the embodiment is also conceivable. Furthermore, you may combine suitably the component described in different embodiment.

1 is a block diagram showing a frequency synchronization circuit according to a first embodiment. The block diagram which shows the multiplication part shown in FIG. 1 in detail. The graph figure which shows the power spectrum of the multiplication signal at the time of performing the multiplication process with respect to a received signal collectively at once. The graph figure which shows the power spectrum of the multiplication signal at the time of dividing and performing the multiplication process with respect to a received signal in two steps. The graph figure which shows notionally the frequency offset estimated value estimated by the frequency offset estimation part shown in FIG. The graph which shows the estimation error of the frequency offset of an 8 times signal. The graph figure which shows the estimation error of the frequency offset of a 16 times multiplication signal. The graph figure which shows the estimation error of the frequency offset of a 32 times signal. FIG. 2 is a block diagram showing the operation of the frequency synchronization circuit shown in FIG. 1. The block diagram which shows the frequency synchronization circuit which concerns on 2nd Embodiment. The block diagram which shows the frequency synchronous circuit which concerns on 3rd Embodiment. The block diagram which shows concretely the multiplication part used for the frequency synchronous circuit which concerns on 4th Embodiment. The block diagram which shows concretely the filter used for the frequency synchronous circuit which concerns on 5th Embodiment. The block diagram which shows the receiver which concerns on 6th Embodiment.

Explanation of symbols

11... Received baseband signal 12... First multiplied signal 13... Filter signal 14 ... Second multiplied signal 15 ... Estimated value of frequency offset 15 A ... Frequency offset 15B ... Accumulated estimated value of frequency offset 16 .... Offset removal signal 100 ... Multiplier 110 ... First multiplier 120 ... Filter 130 ... Second multiplier Unit 140 ... frequency offset estimation unit 150 ... mixer 200 ... multiplication unit 240 ... frequency offset estimation unit 260 ... multiplication ratio setting unit 370 ... switch 380 ... buffer 390 ... Switching determination unit 410 ... first multiplication unit 411 ... FFT
412 ... Bandwidth estimation unit 413 ... Multiplication ratio setting unit 420 ... Filter 430 ... Second multiplication unit 521 ... FFT
522 ... Frequency offset estimation unit 523 ... Noise suppression unit 524 ... IFFT
601 ... Antenna 602 ... Receiver 603 ... ADC
604 ... AFC
605 ... CPE
606 ... Resampler 607 ... Symbol synchronization unit 608 ... Demodulation / decoding unit

Claims (13)

A first multiplier that multiplies the received baseband signal by a first multiplication ratio and outputs a first multiplied signal;
A filter that suppresses noise in the first multiplied signal and outputs a filter signal;
A second multiplier for multiplying the filter signal by a second multiplication ratio and outputting a second multiplied signal;
An estimation unit that estimates a frequency offset of the received baseband signal from the second multiplied signal and outputs an estimated value;
An offset remover that multiplies the received baseband signal by the estimated value to remove the frequency offset;
A frequency synchronization circuit comprising: The received baseband signal includes symbols modulated with a certain modulation scheme;
2. The frequency synchronization circuit according to claim 1, wherein the first multiplication ratio is set such that a modulation component of the received baseband signal is removed by the first multiplication unit.   2. The frequency synchronization circuit according to claim 1, wherein a sum of the first multiplication ratio and the second multiplication ratio is set so that an estimation error of the estimated value falls within an allowable range. A fast Fourier transformer for fast Fourier transforming the first multiplied signal and outputting an amplitude spectrum;
A bandwidth estimation unit for estimating a bandwidth of the first multiplied signal from a power spectrum obtained by squaring the amplitude spectrum;
If the bandwidth is equal to or greater than a predetermined threshold, a setting unit that sets the first multiplication ratio to be larger;
The frequency synchronization circuit according to claim 1, further comprising: The filter is
A fast Fourier transformer for fast Fourier transforming the first multiplied signal to output a first amplitude spectrum;
A multiplied frequency offset estimator for estimating a frequency offset of the first multiplied signal from a power spectrum obtained by squaring the first amplitude spectrum;
A suppression unit that suppresses noise of the first amplitude spectrum based on a frequency offset of the first multiplied signal and outputs a second amplitude spectrum;
The frequency synchronization circuit according to claim 1, further comprising: a fast inverse Fourier transformer that performs fast inverse Fourier transform on the second amplitude spectrum and outputs the filter signal. An offset removal unit that multiplies the input signal by a cumulative estimate of the frequency offset to remove the frequency offset and output an offset removal signal;
A first multiplier for multiplying the offset removal signal by a first multiplication ratio and outputting a first multiplied signal;
A filter that suppresses noise in the first multiplied signal and outputs a filter signal;
A second multiplier for multiplying the filter signal by a second multiplication ratio and outputting a second multiplied signal;
An estimation unit that estimates the frequency offset from the second multiplied signal and outputs the cumulative estimated value and the residual estimated value;
A setting unit that sets the second multiplication ratio so that the residual estimated value falls within an allowable range;
A frequency synchronization circuit comprising: The input signal includes symbols modulated by a certain modulation scheme;
The frequency synchronization circuit according to claim 6, wherein the first multiplication ratio is set such that a modulation component of the received baseband signal is removed by the first multiplication unit. A buffer that temporarily stores either the received baseband signal including the modulated symbol or the offset removal signal and outputs the buffer as the input signal;
If the absolute value of the residual estimated value is less than a threshold value, the received baseband signal is stored in the buffer, and if the absolute value of the estimated value is greater than or equal to the predetermined threshold value, the offset removal signal is stored in the buffer. The frequency synchronization circuit according to claim 6, further comprising a switching unit that switches the input of the buffer. A fast Fourier transformer for fast Fourier transforming the first multiplied signal and outputting an amplitude spectrum;
A bandwidth estimation unit for estimating a bandwidth of the first multiplied signal from a power spectrum obtained by squaring the amplitude spectrum;
If the bandwidth is equal to or greater than a predetermined threshold, a setting unit that sets the first multiplication ratio to be larger;
The frequency synchronization circuit according to claim 6, further comprising: The filter is
A fast Fourier transformer for fast Fourier transforming the first multiplied signal to output a first amplitude spectrum;
A multiplied frequency offset estimator for estimating a frequency offset of the first multiplied signal from a power spectrum obtained by squaring the first amplitude spectrum;
A suppression unit that suppresses noise of the first amplitude spectrum based on a frequency offset of the first multiplied signal and outputs a second amplitude spectrum;
The frequency synchronization circuit according to claim 6, further comprising: a fast inverse Fourier transformer that performs a fast inverse Fourier transform on the second amplitude spectrum and outputs the filter signal. A receiving unit that down-converts a received signal including a modulated symbol and outputs a received baseband signal;
The frequency synchronization circuit according to claim 1, wherein a frequency offset is removed from the received baseband signal to output an offset removal signal;
A symbol synchronizer for synchronizing the timing of the symbols;
And a demodulator that demodulates the symbols according to the timing. Multiply the received baseband signal by the first multiplication ratio and output the first multiplied signal,
Suppressing the noise in the first multiplied signal and outputting a filter signal;
A second multiplier for multiplying the filter signal by a second multiplication ratio and outputting a second multiplied signal;
Estimating the frequency offset of the received baseband signal from the second multiplied signal and outputting an estimated value;
The frequency synchronization method, wherein the received baseband signal is multiplied by the estimated value to remove the frequency offset. A first multiplication means for multiplying a received baseband signal by a first multiplication ratio and outputting a first multiplied signal;
Filter means for suppressing noise in the first multiplied signal and outputting a filter signal;
Second multiplication means for multiplying the filter signal by a second multiplication ratio and outputting a second multiplied signal;
Estimating means for estimating a frequency offset of the received baseband signal from the second multiplied signal and outputting an estimated value;
A frequency synchronization program for causing the received baseband signal to function as an offset removing means for removing the frequency offset by multiplying the estimated value.

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