JP4306654B2 - トランジスタアレイパネル - Google Patents
トランジスタアレイパネル Download PDFInfo
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- JP4306654B2 JP4306654B2 JP2005215717A JP2005215717A JP4306654B2 JP 4306654 B2 JP4306654 B2 JP 4306654B2 JP 2005215717 A JP2005215717 A JP 2005215717A JP 2005215717 A JP2005215717 A JP 2005215717A JP 4306654 B2 JP4306654 B2 JP 4306654B2
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- 239000010408 film Substances 0.000 claims description 86
- 239000010409 thin film Substances 0.000 claims description 76
- 230000001681 protective effect Effects 0.000 claims description 59
- 239000003990 capacitor Substances 0.000 claims description 41
- 230000002093 peripheral effect Effects 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 15
- 239000011159 matrix material Substances 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 76
- 229910021417 amorphous silicon Inorganic materials 0.000 description 28
- 229910052751 metal Inorganic materials 0.000 description 28
- 239000002184 metal Substances 0.000 description 28
- 239000004065 semiconductor Substances 0.000 description 18
- 239000004973 liquid crystal related substance Substances 0.000 description 15
- 239000004020 conductor Substances 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 11
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- 238000000034 method Methods 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 238000007740 vapor deposition Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 5
- 230000000149 penetrating effect Effects 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 239000007787 solid Substances 0.000 description 2
- 238000001894 space-charge-limited current method Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- BEQNOZDXPONEMR-UHFFFAOYSA-N cadmium;oxotin Chemical compound [Cd].[Sn]=O BEQNOZDXPONEMR-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/50—Protective arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Nonlinear Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
Description
ゲート電極11及びゲートライン2は絶縁性の透明基板51上にパターニングされ、窒化シリコン等からなるゲート絶縁膜52により被覆されている。
薄膜トランジスタ10及びデータライン3は、層間絶縁膜53により被覆されている。
図3は表示領域100の右側外周部(図1のA部)を示す透過平面図である。図3において、左側が表示領域100、右側が表示領域外であり、表示領域100の外周に沿って図3の上下方向に、保護ライン4及び補助容量の共通ライン7が設けられている。
接続配線55とゲートライン2との交差部分にはゲート絶縁膜52を貫通するコンタクトホール56が形成されており、コンタクトホール56には金属層55cと同じ導体56aが充填される。ゲートライン2と接続配線55とは導体56aを介して導通している。
補助容量の共通ライン7は薄膜トランジスタ20,30と対応する位置の層間絶縁膜53上に上下方向に形成される。補助容量の共通ライン7はキャパシタ層9と一体に形成され、オーバーコート絶縁膜54により被覆されている。
また、データライン3と保護ライン5との交差部分には、データライン3に生じた静電気を保護ライン5に逃がす保護素子として、薄膜トランジスタ40が設けられている。
補助容量の共通ライン7は薄膜トランジスタ40と対応する位置の層間絶縁膜53上に左右方向に形成される。補助容量の共通ライン7はキャパシタ層9と一体に形成され、オーバーコート絶縁膜54により被覆されている。
まず、気相成長法(スパッタリング法、CVD法、PVD法等)によって透明基板51にゲート膜をべた一面に成膜し、フォトリソグラフィー法及びエッチング法によってゲート膜をパターニングする。これにより、複数のゲートライン2、複数の薄膜トランジスタ10,20,30,40,50,60,70のゲート電極、保護ライン5、保護回路の共通ライン6を同時に形成する(図8(a))。
次に、気相成長法によってオーバーコート絶縁膜54をべた一面に成膜し、オーバーコート絶縁膜54によりキャパシタ層9、補助容量の共通ライン7を被覆する。
次に、層間絶縁膜53及びオーバーコート絶縁膜54のうち各薄膜トランジスタのソース電極に重なる部分にコンタクトホール8aを形成する(図9(c))。
2 ゲートライン
3 データライン
4,5 保護ライン
6 保護回路の共通ライン
7 補助容量の共通ライン
8 画素電極
9 キャパシタ層(導電膜パターン)
20,30,40 薄膜トランジスタ(保護素子)
52,53,54 絶縁膜
100 表示領域
Claims (2)
- 基板上の表示領域内において複数の画素電極がマトリクス状に配置されるとともに、複数のゲートラインと複数のデータラインとが互いに絶縁膜を挟んだ状態で直交するように配置され、
前記複数のゲートラインと前記複数のデータラインとの各交差部において薄膜トランジスタが配置され、
前記薄膜トランジスタのゲートが前記ゲートラインに接続され、前記薄膜トランジスタのドレインまたはソースの一方が前記データラインに接続され、他方が前記画素電極のいずれかと接続されたトランジスタアレイパネルにおいて、
前記表示領域の外周部には、前記ゲートライン及び前記データラインと絶縁された状態で直交するように保護ラインが配置され、前記ゲートラインまたは前記データラインと前記保護ラインとは保護素子を介して接続され、
前記表示領域内において、前記ゲートライン、前記データライン、前記画素電極と絶縁された導電膜パターンが形成され、
前記導電膜パターンは前記各画素電極の一部と重なるように形成されて補助容量を形成するとともに、前記表示領域の外周部において前記保護素子及び前記保護ラインと絶縁された補助容量の共通ラインと接続されており、
前記補助容量の共通ラインは前記保護素子または前記保護ラインと絶縁膜を介して重ねられていることを特徴とするトランジスタアレイパネル。 - 前記導電膜パターン及び前記補助容量の共通ラインは同一の導電膜をパターニングして形成されていることを特徴とする請求項1に記載のトランジスタアレイパネル。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005215717A JP4306654B2 (ja) | 2005-07-26 | 2005-07-26 | トランジスタアレイパネル |
US11/492,114 US7491971B2 (en) | 2005-07-26 | 2006-07-24 | Transistor array panel, liquid crystal display panel, and method of manufacturing liquid crystal display panel |
TW095127110A TWI339770B (en) | 2005-07-26 | 2006-07-25 | Transistor array panel, liquid crystal display panel, and method of manufacturing liquid crystal dispaly panel |
CNB2006101074826A CN100483234C (zh) | 2005-07-26 | 2006-07-26 | 晶体管阵列面板 |
KR1020060070167A KR100821794B1 (ko) | 2005-07-26 | 2006-07-26 | 트랜지스터 어레이 패널, 액정 디스플레이 패널, 및 액정 디스플레이 패널의 제조방법 |
US12/240,773 US7781769B2 (en) | 2005-07-26 | 2008-09-29 | Transistor array panel, liquid crystal display panel, and method of manufacturing liquid crystal display panel |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005215717A JP4306654B2 (ja) | 2005-07-26 | 2005-07-26 | トランジスタアレイパネル |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007033760A JP2007033760A (ja) | 2007-02-08 |
JP4306654B2 true JP4306654B2 (ja) | 2009-08-05 |
Family
ID=37673997
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005215717A Expired - Fee Related JP4306654B2 (ja) | 2005-07-26 | 2005-07-26 | トランジスタアレイパネル |
Country Status (5)
Country | Link |
---|---|
US (2) | US7491971B2 (ja) |
JP (1) | JP4306654B2 (ja) |
KR (1) | KR100821794B1 (ja) |
CN (1) | CN100483234C (ja) |
TW (1) | TWI339770B (ja) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4740203B2 (ja) * | 2006-08-04 | 2011-08-03 | 北京京東方光電科技有限公司 | 薄膜トランジスタlcd画素ユニットおよびその製造方法 |
US7825013B2 (en) * | 2006-11-20 | 2010-11-02 | Qimonda Ag | Integrated circuit comprising an amorphous region and method of manufacturing an integrated circuit |
KR101488925B1 (ko) * | 2008-06-09 | 2015-02-11 | 삼성디스플레이 주식회사 | 박막 트랜지스터 기판, 이의 제조 방법, 및 이를 갖는 표시장치 |
EP2172804B1 (en) * | 2008-10-03 | 2016-05-11 | Semiconductor Energy Laboratory Co, Ltd. | Display device |
KR102011614B1 (ko) * | 2009-07-10 | 2019-08-16 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 및 그 제조 방법 |
US10090374B2 (en) | 2012-06-18 | 2018-10-02 | Samsung Display Co., Ltd. | Organic light-emitting display device |
KR102051465B1 (ko) * | 2012-06-18 | 2019-12-05 | 삼성디스플레이 주식회사 | 유기발광 표시장치 |
KR101906248B1 (ko) * | 2012-12-13 | 2018-10-11 | 엘지디스플레이 주식회사 | 액정 디스플레이 장치 |
KR102113607B1 (ko) | 2013-08-30 | 2020-05-21 | 엘지디스플레이 주식회사 | 액정 표시 장치 및 그의 제조 방법 |
CN103531096B (zh) | 2013-10-17 | 2016-07-06 | 京东方科技集团股份有限公司 | 显示基板及其制作方法、显示面板和显示装置 |
KR102373536B1 (ko) * | 2015-01-27 | 2022-03-11 | 삼성디스플레이 주식회사 | 비사각형 디스플레이 |
KR102687853B1 (ko) * | 2016-12-09 | 2024-07-24 | 삼성디스플레이 주식회사 | 표시 장치 |
CN107121860B (zh) * | 2017-06-14 | 2020-05-26 | 厦门天马微电子有限公司 | 一种阵列基板、显示面板及显示装置 |
US11366366B2 (en) * | 2019-02-13 | 2022-06-21 | Sharp Kabushiki Kaisha | Active matrix substrate and photoelectric imaging panel with the same |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07230098A (ja) | 1994-02-18 | 1995-08-29 | Sanyo Electric Co Ltd | 液晶表示装置 |
JP3315829B2 (ja) | 1994-11-17 | 2002-08-19 | 株式会社東芝 | 半導体装置 |
JPH08179360A (ja) | 1994-12-20 | 1996-07-12 | Casio Comput Co Ltd | アクティブマトリックスパネル |
TW457690B (en) * | 1999-08-31 | 2001-10-01 | Fujitsu Ltd | Liquid crystal display |
KR100658526B1 (ko) | 2000-08-08 | 2006-12-15 | 엘지.필립스 엘시디 주식회사 | 액정 표시장치의 정전 손상 보호장치 |
JP3449361B2 (ja) | 2001-03-12 | 2003-09-22 | 松下電器産業株式会社 | 液晶表示装置の製造方法 |
JP3938112B2 (ja) * | 2002-11-29 | 2007-06-27 | セイコーエプソン株式会社 | 電気光学装置並びに電子機器 |
JP4385691B2 (ja) | 2003-09-12 | 2009-12-16 | カシオ計算機株式会社 | 表示パネルの静電気保護構造及び液晶表示パネル |
-
2005
- 2005-07-26 JP JP2005215717A patent/JP4306654B2/ja not_active Expired - Fee Related
-
2006
- 2006-07-24 US US11/492,114 patent/US7491971B2/en not_active Expired - Fee Related
- 2006-07-25 TW TW095127110A patent/TWI339770B/zh not_active IP Right Cessation
- 2006-07-26 KR KR1020060070167A patent/KR100821794B1/ko not_active IP Right Cessation
- 2006-07-26 CN CNB2006101074826A patent/CN100483234C/zh not_active Expired - Fee Related
-
2008
- 2008-09-29 US US12/240,773 patent/US7781769B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN100483234C (zh) | 2009-04-29 |
TW200720804A (en) | 2007-06-01 |
KR100821794B1 (ko) | 2008-04-11 |
KR20070014072A (ko) | 2007-01-31 |
US20090026456A1 (en) | 2009-01-29 |
TWI339770B (en) | 2011-04-01 |
US7781769B2 (en) | 2010-08-24 |
US20070023752A1 (en) | 2007-02-01 |
CN1904703A (zh) | 2007-01-31 |
JP2007033760A (ja) | 2007-02-08 |
US7491971B2 (en) | 2009-02-17 |
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