JP4153678B2 - Mask data generation method, exposure mask creation method, and pattern formation method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a mask data generation method, an exposure mask generation method, and a pattern formation method in the semiconductor field.
[0002]
[Prior art]
Recent progress in semiconductor manufacturing technology is very remarkable, and semiconductor devices having a minimum processing dimension of 0.18 μm are mass-produced. Such miniaturization of semiconductor elements has been realized by rapid progress of fine pattern formation techniques such as a mask process technique, an optical lithography technique, and an etching technique.
[0003]
When the pattern size is sufficiently large, the planar shape of the LSI pattern to be formed on the wafer is directly drawn as a design pattern, a mask pattern that is faithful to the design pattern is created, and the mask pattern is transferred onto the wafer by the projection optical system. Then, by etching the base, a pattern almost as designed can be formed on the wafer.
[0004]
However, as pattern miniaturization progresses, it has become difficult to faithfully form a pattern in each process, and a problem has arisen that the final finished dimension does not match the design pattern.
[0005]
In particular, in the lithography and etching processes that are most important for achieving microfabrication, other pattern layout environments arranged around the pattern to be formed greatly affect the dimensional accuracy of the pattern.
[0006]
Therefore, in order to reduce these effects, optical proximity correction (OPC) or process proximity effect correction that adds an auxiliary pattern to the design pattern in advance so that the dimension after processing is formed into a desired pattern. (PPC: Process proximity Correction) technology and the like are reported in Japanese Patent Laid-Open No. 09-319067.
[0007]
However, such OPC / PPC (hereinafter referred to as PPC) has the following problems. In order to perform highly accurate correction by PPC, it is necessary to add many fine auxiliary patterns to the design pattern. On the other hand, if there are many fine auxiliary patterns, an increase in the amount of design data and an increase in the mask creation time become problems. That is, the conventional technique has a problem that it is difficult to achieve both improvement in correction accuracy and reduction in correction time.
[0008]
The design data includes various patterns ranging from a fine pattern that is very difficult to form by a process to a relatively loose pattern. When correcting these patterns with high accuracy, it is important to accurately predict the finished dimensions of the pattern on the wafer. However, with the miniaturization, the calculation necessary for predicting the finished dimensions has become complicated, and as a result, the problem of increase in calculation time and further increase in correction time has become apparent. This is also the reason why it is difficult to achieve both improvement in correction accuracy and reduction in correction time.
[0009]
[Problems to be solved by the invention]
As described above, in the conventional technology, for example, a large number of auxiliary patterns are required when performing high-precision correction by PPC, and the mask creation time increases, so it is difficult to achieve both improvement in correction accuracy and reduction in correction time. There was a problem of being.
[0010]
The present invention has been made in consideration of the above circumstances, and the object of the present invention is to provide a mask data generation method, an exposure mask generation method, and a pattern that enable both improvement in correction accuracy and reduction in correction time. It is to provide a forming method.
[0011]
[Means for Solving the Problems]
Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows. That is, in order to achieve the above object, a mask data generation method according to the present invention includes a step of dividing design data related to an exposure mask into a plurality of data groups to be corrected, and a pattern after correction for each data group . Assigning correction parameters affecting the shape , wherein the correction parameters include a minimum correction grid used for correction , and each data group is corrected using the correction parameters assigned thereto, and a plurality of corrections are performed. possess a step of forming a pattern group, and a step of synthesizing the plurality of correction pattern groups, the step of dividing said plurality of data groups is carried out by classification based on the value of MEF, the plurality of correction pattern group the step of forming the can, and characterized in that performed by correction by the correction parameters including the minimum correction grid corresponding to the value of the MEF That.
[0012]
According to the present invention, the correction accuracy is not corrected by correcting a plurality of data groups defined by design data with one common correction parameter, but with correction parameters appropriate for each data group. It is possible to achieve both improvement of the correction and shortening of the correction time.
[0013]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.
[0015]
(First embodiment)
FIG. 1 is a diagram showing a flow of a manufacturing method of a semiconductor device according to the first embodiment of the present invention. Specifically, steps from mask data generation to a pattern formation method are shown.
[0016]
First, exposure mask design data is prepared (step S1). The design data is designed by a known method.
[0017]
Next, the plurality of patterns defined by the design data are distributed to a plurality of layers (data group) based on, for example, dimensions, layout, or shape (step S2). Specifically, the distribution is made according to the pattern line width in the design data, the space width (L / S) adjacent to the pattern, or the pattern shape. These layers may be those that have already been designed with different layers in advance in the design data in step S1, or extracted by extracting only the necessary pattern shapes using a design rule checker (DRC). Only the pattern may be changed to a different layer. Further, if the design data has a hierarchical structure, a plurality of layers may be distributed based on the cell name of the design data.
[0018]
Next, a plurality of distributed layers are defined and identified as layers 1, 2,... N, respectively (step S3).
[0019]
Next, appropriate correction parameters 1, 2,... N are assigned to the respective layers 1, 2,... N (step S4). In the present invention, the correction parameter means all parameters that may affect the shape after correction of the pattern.
[0020]
Specifically, the minimum grid used for correction (minimum dimension of the short side of the auxiliary pattern having a rectangular shape) and the height of the minimum correction step used for correction (the dimension of the long side of the auxiliary pattern having a rectangular shape) And an optical model used for correction value calculation and a process prediction model used for correction. In the case of a fine pattern that is very difficult to form by a process, for example, a process prediction model is used, and in the case of a relatively loose pattern, for example, a minimum grid is selected.
[0021]
Further, the appropriate correction parameter is an effective correction parameter for obtaining a finished pattern faithful to the design data, and when there are a plurality of such correction parameters , it does not take time to create them. In other words, it means that the amount of data after correction is reduced.
[0022]
Next, based on the correction parameters 1, 2,... N , each layer 1, 2,... N is corrected, and the correction layers 1, 2,.
[0023]
At this time, as described above, since the appropriate correction parameters 1, 2,... N are assigned to each layer 1, 2,... N, the correction layers 1, 2,. In addition, the amount of data is smaller than in the past. Since the amount of data is small, it does not take extra time to create it. This leads to shortening of the correction time.
[0024]
Next, the correction layers 1, 2,... N are combined to obtain mask data necessary for creating an exposure mask (step S6). Since the correction layers 1, 2,... N have a smaller amount of data than in the prior art, the amount of mask data is also smaller than in the prior art.
[0025]
Next, the mask data is converted into a data format that can be used by the exposure apparatus, and mask data (exposure mask data) that can be used by the exposure apparatus is acquired (step S7).
[0026]
Next, the exposure mask data is input to the exposure apparatus, the light shielding film of the mask substrate (glass substrate / light shielding film) is processed according to a known method, and an exposure mask is created (step S8). At this time, since the amount of the exposure mask data is smaller than the conventional one, the mask drawing time can be shorter than the conventional one. This leads to shortening of the correction time.
[0027]
Finally, a photoresist pattern is prepared using the exposure mask according to a known method (exposure process, development process), and the photoresist pattern base is etched using the photoresist pattern as a mask. A pattern is formed (step S9). The base is, for example, an insulating film, a metal film, a semiconductor film, at least two laminated films of these three films, or a semiconductor substrate.
[0028]
As described above, according to the present embodiment, by classifying different layers according to the shape of the pattern to be corrected, etc., and correcting each layer with appropriate correction parameters, the correction accuracy can be improved and corrected. It becomes possible to realize a mask data generation method, an exposure mask generation method, and a pattern formation method that can achieve a reduction in time. Specifically, it was confirmed that the necessary correction accuracy could be ensured with a conventional correction time of 1/10.
[0029]
(Second Embodiment)
Next, more specific embodiments of the present invention will be described. Here, a case will be described in which the L / S pattern 1 (layout with high pattern density) shown in FIG. 2A and the isolated pattern 2 (layout with low pattern density) shown in FIG. 2B are created. That is, description will be given of creation of a pattern in which another pattern layout environment (degree of pattern density) arranged around the pattern to be formed greatly affects the dimensional accuracy of the pattern.
[0030]
In the case of the present embodiment, it is divided into two layers: a layer corresponding to FIG. 2A and a layer corresponding to FIG. Accordingly, there are two correction parameters and two correction layers.
[0031]
If the minimum dimension unit of the auxiliary pattern added at the time of correction is 2.5 nm / edge (on-wafer dimension conversion), the edges of the patterns 1 and 2 are both corrected with a correction unit of 2.5 nm / edge.
[0032]
On the other hand, the finished dimension fluctuation amount (MEF: Mask Enhanced Factor) on the wafer when the mask dimension fluctuates by 1 nm / edge differs between the patterns 1 and 2.
[0033]
Although the above values vary depending on the exposure conditions, etc., under the normally used exposure conditions, the L / S pattern 1 is about 2, the isolated pattern 2 is about 1, and the L / S pattern 1 is about twice as large as the isolated pattern 2. Value.
[0034]
Therefore, when the exposure mask is prepared by correcting the pattern with a correction unit of minimum 2.5 nm / edge for both the patterns 1 and 2 (conventional method), the finished dimension on the wafer is 2.5 for the L / S pattern 1. In the case of × 2 = 5 nm / edge and the isolated pattern 2, it is impossible to correct more finely than 2.5 × 1 = 2.5 nm / edge.
[0035]
However, the L / S pattern 1 is a pattern that is used in places where strict dimensional control is required, such as a memory cell portion of a gate layer and a metal layer, and the finished dimension on the wafer is not corrected more finely than 5 nm / edge. In some cases, it may be difficult to achieve the required dimensional accuracy.
[0036]
Therefore, the L / S pattern 1 needs to be corrected with a finer correction grid. On the other hand, if a finer correction grid is used, the amount of data after correction becomes enormous and the mask drawing time may increase.
[0037]
Therefore, in this embodiment, first, the L / S pattern 1 having a large MEF and the isolated pattern 2 having a small MEF are classified into different layers by the design rule checker (DRC) (layer distribution).
[0038]
The layer corresponding to the L / S pattern 1 (first layer) corrects the correction grid with a minimum correction grid of 1.25 nm / edge smaller than 2.5 nm / edge, and creates a first correction layer, On the other hand, the layer corresponding to the isolated pattern 2 (second layer) was corrected with a normal minimum correction grid of 2.5 nm / edge to create a second layer.
[0039]
Thereafter, the first layer and the second layer were synthesized, exposure mask data was acquired, an exposure mask was created, and patterns 1 and 2 were formed on the wafer.
[0040]
As a result, an exposure mask having dimensional accuracy required for each of the L / S pattern 1 and the isolated pattern 2 can be obtained, and an increase in data amount and mask drawing time can be minimized. Further, when the finished dimensions on the wafer were measured, it was confirmed that the L / S pattern 1 and the isolated pattern 2 could be corrected with the required dimensional accuracy.
[0041]
Here, the correction of the two patterns of the L / S pattern 1 and the isolated pattern 2 has been described, but the L / S pattern 1 and the other MEF large pattern are corrected together in the same layer, and the isolated pattern 2 and Other small MEF patterns may be corrected together by using the same layer. This makes it possible to achieve both improvement in correction accuracy and reduction in correction time even when there are various patterns ranging from a very difficult pattern to be formed to a relatively loose pattern. It becomes like this.
[0042]
(Third embodiment)
Here, a case where a line pattern is created will be described. In the case of this embodiment, a layer corresponding to the end of the line pattern and a layer corresponding to a portion other than the end of the line pattern are allocated. Accordingly, there are two correction parameters and two correction layers.
[0043]
Normally, when the exposure amount is determined so that the line width of the line pattern is finished as desired using a certain exposure condition, as shown in FIG. 3, the end portion of the line pattern (actual line pattern) 3 formed on the wafer. The (line end) is shorter than the end of the line pattern (design line pattern) 4 corresponding to the design data. Hereinafter, such a final finished dimension being shorter than the design pattern is referred to as shortening.
[0044]
In order to correct the shortening in the actual line pattern 3, it is necessary to accurately predict the amount of shortening at the line end under the condition that the line width at a certain exposure amount is finished as desired.
[0045]
However, it is generally difficult to accurately predict the finished width of the line width and the finished dimension of the line end (shortening amount) with the same process prediction model in various patterns. Requires a very complex and time-consuming process prediction model. This leads to an increase in correction time.
[0046]
On the other hand, it is relatively easy to predict the line width and the finished size of the line end with separate process prediction models (process parameters), and the time required for calculation is also relatively short.
[0047]
Therefore, in the present embodiment, only the end of the line is extracted by DRC, the extracted part is set as the first layer, and the other part is set as the second layer. Then, a finished dimension is predicted for each of the first and second layers using different process prediction models, a correction value is calculated based on the predicted value, and the first value for the first layer is calculated using the correction value. A correction layer and a second correction layer for the second layer were created.
[0048]
Thereafter, the first layer and the second layer were synthesized, exposure mask data was acquired, an exposure mask was created, and an actual line pattern 3 was formed.
[0049]
As a result, it is possible to achieve the required dimensional accuracy at the line width and the line end on the wafer, and to minimize the increase in data amount and mask drawing time.
[0050]
The first to third embodiments of the present invention have been described above, but the present invention is not limited to these embodiments. For example, in the second embodiment, the correction minimum grid is selected as the correction parameter, and this is changed for each layer. Alternatively, the maximum line width to be corrected may be selected at the same time. That is, a plurality of types of correction parameters may be used.
[0051]
In the third embodiment, the process prediction model is changed for each layer. However, not only the process prediction model but also an optical image calculation method (for example, aerial image calculation, reflection from the ground for aerial image calculation). It is also possible to apply the calculation considering the light and the calculation including the development model only to the layer after the classification to further appropriately adjust the balance between the correction time and the correction accuracy.
[0052]
Furthermore, the exposure apparatus (exposure method) that can be used in the present invention is not limited to the exposure apparatus (exposure method) using light, and for example, an exposure apparatus (exposure method) using electron beam, X-ray exposure, or the like. Can also be used.
[0053]
Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, if the problem described in the column of the problem to be solved by the invention can be solved, the configuration in which this constituent requirement is deleted Can be extracted as an invention. In addition, various modifications can be made without departing from the scope of the present invention.
[0054]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to realize a mask data generation method, an exposure mask generation method, and a pattern formation method that can achieve both improvement in correction accuracy and reduction in correction time.
[Brief description of the drawings]
FIG. 1 is a diagram showing a flow of a semiconductor device manufacturing method according to a first embodiment of the present invention. FIG. 2 is a plan view showing L / S patterns and isolated patterns. FIG. 3 is a line pattern corresponding to design data. And plan view showing line pattern formed on wafer [description of symbols]
DESCRIPTION OF SYMBOLS 1 ... L / S pattern 2 ... Isolated pattern 3 ... Line pattern 4 formed on a wafer ... Line pattern corresponding to design data

Claims (3)

Dividing the design data related to the exposure mask into a plurality of data groups to be corrected ;
Assigning correction parameters that affect the shape after correction of the pattern to each data group , wherein the correction parameters include a minimum correction grid used for correction ;
Correcting each data group using a correction parameter assigned thereto, and forming a plurality of correction pattern groups;
Possess a step of synthesizing the plurality of correction pattern groups, the step of dividing said plurality of data groups is carried out by classification based on the value of the MEF, forming the plurality of correction pattern groups, the MEF A mask data generation method, which is performed by correction using a correction parameter including a minimum correction grid corresponding to the value of . Obtaining mask data of an exposure mask using the mask data generating method according to claim 1 ;
And a step of forming a pattern on a mask substrate based on the mask data. Forming a resist pattern using an exposure mask created using the exposure mask creating method according to claim 2 ;
And a step of etching the underlayer of the resist pattern using the resist pattern as a mask.

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