JP4147005B2 - Semiconductor integrated circuit, test method and manufacturing method thereof - Google Patents

Description

表１において、「ｎｏｐ」で示される命令は、プログラムカウンタ４１２の値をインクリメンタ４３１で「＋１」してプログラムカウンタ４１２へ戻すことを指示するノーオペレーション命令つまりプログラムカウンタの更新以外に何の操作を行なわずに次の命令に移ることを指令する命令である。
また、「ｊｉｎｄｅｘ１」〜「ｊｉｎｄｅｘ４」は、ジャンプによる命令のループを回すために用意された命令である。メモリのパターンテストにおいては、ジャンプ命令を用いて同じ命令を何回も繰り返して実行することで命令数、すなわち、プログラム長を減らすことができる場合（例えば、アドレスを最終番地までインクリメントすることで、全メモリセルに「１」を書き込んで読み出すような場合）がある。このループ（ジャンプ）の回数を設定できるようにするために、本実施例では、インデックスレジスタ４３３を設けている。しかも、複数種類の判定方式を実行できるようにするため、ジャンプ命令とインデックスレジスタ４３３およびワーキングレジスタ４３５をそれぞれ４つずつ設けている。
各ジャンプ命令は同じ制御内容であるので、以下「ｊｉｎｄｅｘ１」による制御動作を説明し、他のジャンプ命令「ｊｉｎｄｅｘ２」〜「ｊｉｎｄｅｘ４」の説明は省略される。オペコードフィールドＭＦｂからｊｉｎｄｅｘ１命令が読み出されると、それが最初のｊｉｎｄｅｘ１命令であるか判定されて、その判定結果がフラグ４３７に反映される。具体的には、最初のｊｉｎｄｅｘ１のときはフラグｊｆ１＝０とされ、２回目以降はｊｆ１＝１とされる。
フラグｊｆ１＝０のときにｊｉｎｄｅｘ１命令が読み出されると、そのマイクロ命令のアドレスフィールドＭＦａ内のジャンプ先アドレスとしてのＰＣアドレスがプログラムカウンタ４１２へ設定されるように、マルチプレクサ４３２が制御される。それによって、マイクロ命令の実行シーケンスはその番地にジャンプされるとともに、フラグｊｆ１は「１」にセットされる。これと同時に、オペランドフィールドＭＦｃ内で定義されるループ回数がインデックスレジスタ４３３のｉｄｘに読み込まれる。
フラグｊｆ１＝１のときにｊｉｎｄｅｘ１命令が読み出されると、そのマイクロ命令のアドレスフィールドＭＦａ内のＰＣアドレスがプログラムカウンタ４１２へ設定される。そして、インデックスレジスタ４３３のｉｄｘ１内のループ回数がマルチプレクサ４３８を介してデクリメンタ４３４に供給されデクリメント「−１」される。デクリメントされた値は、デマルチプレクサ４３９を介してワーキングレジスタ４３５のｉｄｘｗ１に格納される。そして、ワーキングレジスタ４３５のｉｄｘｗ１が「０」になると、マイクロ命令のアドレスフィールドＭＦａ内のＰＣアドレスをプログラムカウンタ４１２へ設定しないで代わりに、プログラムカウンタ４１２のアドレスをインクリメンタ４３１で「＋１」してプログラムカウンタ４１２へ戻すようにマルチプレクサ４３２が制御される。
従って、マイクロ命令のオペコードフィルードＭＦｂにｊｉｎｄｅｘ命令が定義乃至記述され、そのアドレスフィールドＭＦａ内に当該マイクロ命令のジャンプ先アドレスとしてのＰＣアドレスが定義乃至記述されていると、オペランドフィールドＭＦｃ内で指定されたループ回数だけ同一のｊｉｎｄｅｘ命令が繰り返し実行され、最後にプログラムカウンタ４１２がインクリメントされて、次のマイクロ命令へ進んでループから抜け出すような制御が行なわれる。
また、表１内の「ｊｘｄ」命令は、フラグ４３６内のｄｆｌｇを参照し、そのｄｆｌｇフラグの値によってプログラムカウンタの値を操作する命令とされる。「ｊｘｄ」命令は、フラグ４３６内のｄｆｌｇフラグが「０」のような第１の値のときは、オペランドをプログラムカウンタへ転送し、プログラムをオペランドの示す飛び先番地の命令へジャンプさせ、かつ、ｄｆｌｇフラグを「１」のような第２の値にセットする。一方、「ｊｘｄ」命令は、ｄｆｌｇフラグが「１」のような第２の値のときは、プログラムカウンタの値をインクリメントし、プログラムカウンタへ戻し、かつ、ｄｆｌｇフラグを「０」のような第１の値にリセットする。
「ｊｍｐ」命令は、オペランドをプログラムカウンタへ転送して、プログラムをオペランドの示す飛び先番地の命令へジャンプさせることを指令する命令である。
「ｓｔｏｐ」命令は、シーケンス制御を終了させる事を指示する停止命令である。
図１６には、上記アドレス演算回路４１４の構成例が示されている。
この実施例のアドレス演算回路４１４は、大きく分けてＸアドレスの生成を行なうＸアドレス演算部４４１と、Ｙアドレスの生成を行なうＹアドレス演算部４４２とにより構成されている。Ｘアドレス演算部４４１とＹアドレス演算部４４２は、ほぼ同一の構成であるので、以下、Ｘアドレス演算部４４１の構成を説明し、Ｙアドレス演算部４４２の構成の説明を省略する。また、必要に応じて不可的なＺアドレス演算部を設けることにより、部分的なパターンの生成（パーシャルパターン）を行なわせるようにできる。
Ｘアドレス演算部４４１は、Ｘアドレスの初期値を格納する初期値レジスタＸｈｏｌｄと、「０」を保持するゼロ設定手段４４３と、Ｘアドレスの初期値または「０」のいずれかを選択するマルチプレクサＭＵＸ１と、選択された初期値または「０」を保持するベースレジスタＸｂａｓｅと、レジスタＸｂａｓｅの値を加算する第１の演算器ＡＬＵ１と、演算器ＡＬＵ１の演算結果または「０」または帰還値のいずれかを選択する第２のマルチプレクサＭＵＸ２と、選択された値を保持するカレントレジスタＸｃｕｒｒｅｎｔと、レジスタＸｃｕｒｒｅｎｔの値を加算もしくは減算する第２の演算器ＡＬＵ２と、この第２演算器ＡＬＵ２または上記第１演算器ＡＬＵ１の出力のいずれかを選択する第３のマルチプレクサＭＵＸ３と、選択された出力を反転可能なインバータＩＮＶとから構成されている。
このインバータＩＮＶは、メモリのパターンテストにおいて、アドレス信号の切り換えノイズによる誤動作を試験する場合があり、その際にアドレス信号の反転信号を出力する必要があるため設けられる。このインバータＩＮＶを使用することで、上記試験におけるアドレス信号の反転信号を容易に形成することができる。
特に制限されないが、この実施例では、上記Ｘアドレス演算部４４１の演算器ＡＬＵ１，ＡＬＵ２で生成されたＸアドレスをＹアドレス側へ、また、Ｙアドレス演算部４４２で生成されたＹアドレスをＸアドレス側へ出力できるように、それぞれの第３マルチプレクサＭＵＸ３が構成されている。
これにより、複数の種類のメモリ、例えば、アドレスマルチプレックス方式のメモリおよびアドレスノンマルチプレックス方式のメモリのいずれのテスト回路としても使用できるように構成されている。つまり、命令メモリ４１１に格納されるマイクロ命令を書き換えるだけで、すべてのメモリに対してそれに必要なテストパターンの発生乃至検査を行なうことができる。
なお、上記Ｘアドレス演算部４４１とＹアドレス演算部４４２の異なる点は、Ｘアドレス演算部４４１の第１演算器ＡＬＵ１がオーバーフローしたときにＹアドレス演算部４４２の第１演算器ＡＬＵ１に対してはボロー信号ＢＲが供給されるようにされている点である。
表２には、上記マイクロ命令内の演算コードフィールドＭＦｅに記述乃至定義格納されるところの上記Ｙアドレス演算部４４２の第１演算器ＡＬＵ１でのＹアドレス演算（ベース演算）に用いられる演算コードの種類とその内容が示されている。
【表２】

表２において、Ｙｂａｓｅ←０は、ベースレジスタＹｂａｓｅの値を「０」にすることを指令する命令である。Ｙｂａｓｅ←Ｙｈｏｌｄは、初期値レジスタＹｈｏｌｄの内容をベースレジスタＹｂａｓｅに入れることを指令する命令である。Ｙｂａｓｅ←Ｙｂａｓｅ＋１は、ベースレジスタＹｂａｓｅの値をインクリメント（＋１）してレジスタＹｂａｓｅに戻すことを指令する命令である。Ｙｂａｓｅ←Ｙｂａｓｅ＋１（ＢＲ）は、ベースレジスタＸｂａｓｅの値が最大値でなければＹｂａｓｅの値をそのままにし、かつ、Ｘｂａｓｅの値が最大値であればＹｂａｓｅの値をインクリメントしてレジスタＹｂａｓｅに戻すことを指令する命令である。このとき、第１演算器ＡＬＵ１から第２演算器ＡＬＵ２へボロー信号ＢＲが供給される。
表３には、上記Ｘアドレス演算部４４１の第１演算器ＡＬＵ１でのアドレス演算に用いられる演算コードの種類とその内容が示されている。
表４には、上記Ｙアドレス演算部４４２の第２演算器ＡＬＵ２でのＹアドレス演算（カレント演算）に用いられる演算コードの種類とその内容が示されている。
表５には、上記Ｘアドレス演算部４４１の第２演算器ＡＬＵ２でのアドレス演算に用いられる演算コードの種類とその内容が示されている。
表４において、左側の欄はテスタ言語を用いて記述されたＡＬＰＧ記述で、右側の欄はそれに対応した機能動作レベル記述である。この記述をハードウェア記述言語（ＨＤＬ記述）のルールに従い記述して機能を表現できる。
【表３】

【表４】

【表５】

図１７には上記テストデータ生成回路４１５の構成例が示されている。
この実施例のテストデータ生成回路４１５は、ライトデータまたは期待値の初期値を格納する初期値レジスタＴｐｈｏｌｄと、当該初期値レジスタＴｐｈｏｌｄの値を反転可能なインバータＩＮＶＥＲＴ１と、出力すべきテストデータまたは期待値の基準データを保持するベースデータレジスタＴｐと、ビットシフト機能を有する演算器ＡＬＵと、演算器ＡＬＵの出力を反転可能なインバータＩＮＶＥＲＴ２とから構成されている。なお、上記実施例では、ビット幅を１８ビットとしているが、必要に応じてテストデータ回路を拡大して、所望のビット幅に構成できる。
表６には、上記マイクロ命令内のデータ生成コードフィールドＭＦｆに定義乃至は記述されるところの上記テストデータ生成回路４１５での動作制御に用いられる制御コードの種類とその内容が示されている。表６において、表３〜表５の命令と同一規則で表されている命令は、ほぼ同様の命令である。
Ｔｐ←Ｔｐ＊２は、レジスタＴｐと演算器ＡＬＵを制御してレジスタＴｐ内の１８ビットのデータを演算器ＡＬＵで処理してビット列をＭＳＢ側もしくはＬＳＢ側へ１ビットシフトさせてレジスタＴｐに戻す命令である。この命令によって、メモリ部が１ワードあるいは１バイトのような単位でデータのリード・ライトが行なわれるタイプのメモリであっても、メモリセルに対して１ビットずつデータ「１」を書き込むためのテストデータを比較的容易に生成することができる。
【表６】

表７には、メモリの試験方法の１つであるところのマーチング試験に関するマイクロ命令のリストの一例が示される。
マーチング試験は、次のように行われる。メモリアレイ１内のメモリセルの全ビットにおいて、その中の１ビットが順番に選択される。選択されたメモリセルには、「０」のデータが書き込まれる。その後、書き込まれた「０」のデータの読み出しが行なわれる。続いて、全ビットにおいて、その中の１ビットが順番に選択される。選択されたメモリセルには「１」のデータが書き込まれる。その後、書き込まれた「１」のデータが読み出されて、それぞれ期待値と比較して欠陥の有無が判定される。
一例として、Ｘアドレスが４ビット、Ｙアドレスが４ビットで、２５６ビットの記憶容量を有するメモリアレイを想定したマーチング試験が説明される。
【表７】

表７において、記号ＷおよびＲは、制御フィールドＭＦｄに記述乃至定義されるところのメモリに対するリード／ライトを指示する制御コードである。この制御コードは、Ｗに対応したビットとＲに対応したビット、つまり、２ビットで表すようにされている。「ＰＣアドレス」の欄に記載されている数字は、飛び先番地を示すもので、当該マイクロ命令実行後にＰＣの欄に記述されている番号のマイクロ命令に移行してループもしくはジャンプすることを意味している。また、「制御命令等」の欄に記載されている記号Ｘ←Ｘｂａｓｅ，Ｙ←Ｙｂａｓｅは、それぞれベースレジスタＸｂａｓｅ，Ｙｂａｓｅの値をＸアドレス，Ｙアドレスとして出力することを意味している。
図１８および図１９には、前記マイクロプログラム制御方式の制御部と演算部とからなるテスト回路（ＡＬＰＧ）によりＳＲＡＭ１４０のマーチング試験を行なう場合の表７のマイクロ命令リストに従った処理フローの一例を示す。このうち図１８はマイクロ命令内のオペコードとオペランドとによるシーケンス制御のフローを示す。また、図１９は、図１８に示されるシーケンス制御のフローと並行して実行されるところのアドレス演算コードとデータ生成コードによるテストアドレスおよびテストデータ（ライトデータ、期待値データ）の生成フローを示す。これらの処理は、前述の表１〜表６に記述されている命令コードを用いてシーケンス制御回路４１３およびアドレス演算回路４１４、データ生成回路４１５を動作させることにより実行することができる。
以下、図１８と図１９の各ステップを対応させながら、マーチング試験の手順を説明する。
外部からプログラムカウンタ４１２にスタートアドレスとして、表７のリストに示される最初の命令の番地がセットされると、図１８および図１９のフローが開始される。先ず、命令メモリ４１１から表７の最初のマイクロ命令が読み出されると、オペコードは「ｎｏｐ」であるため、シーケンス制御回路４１３は何もせずただプログラムカウンタ４１２を１つだけ進める（ステップＳ２０１）。一方、アドレス演算回路４１４およびデータ生成回路４１５は、初期値レジスタＸｈｏｌｄ，Ｙｈｏｌｄ，Ｔｈｏｌｄに入っている初期値「０」をベースレジスタＸｂａｓｅ，Ｙｂａｓｅ，Ｔｐにそれぞれ設定する（ステップＳ２２１）。
次に、上記ステップＳ２０１でプログラムカウンタ４１２がインクリメントされているため、表７の２番目のマイクロ命令が読み出される。第２のマイクロ命令のオペコードは「ｊｉｎｄｅｘ１」であるため、シーケンス制御回路４１３ではオペランドの繰り返し回数がインデックスレジスタｉｄｘ１にセットされる（ステップＳ２０２）。
インデックスレジスタｉｄｘ１の最初の設定値はメモリアレイ１の容量（バイト数もしくはワード数）に対応される。一方、アドレス演算回路４１４では、演算コードＸ←Ｘｂａｓｅ，Ｙ←ＹｂａｓｅによってベースレジスタＸｂａｓｅ，Ｙｂａｓｅの値をＸアドレス，Ｙアドレスとしてそれぞれ出力する。データ生成回路４１５からはレジスタＴｐの値「０」が出力される。そして、このとき、制御信号Ｗ（書き込み）が出力される。これによって、メモリアレイ１ではアドレス演算回路４１４から出力されたＸ，Ｙアドレスに対応したメモリセルが選択されてデータ「０」が書き込まれる（ステップＳ２２２）。
シーケンス制御回路４１３はオペコード「ｊｉｎｄｅｘ１」によってインデックスレジスタｉｄｘ１の値をデクリメントしてワーキングレジスタｉｄｘｗに入れ、それが「０」になるまで同一命令を繰り返す（ステップＳ２０３，Ｓ２０４）。
また、アドレス演算回路４１４では演算コードＸｂａｓｅ←Ｘｂａｓｅ＋１によってベースレジスタＸｂａｓｅの値すなわちＸアドレスをインクリメントし、Ｙｂａｓｅ←Ｙｂａｓｅ＋１（ＢＲ）によってベースレジスタＸｂａｓｅが最大値になるとＹアドレスをインクリメントする。上記インデックスレジスタｉｄｘ１の最初の設定値はメモリアレイ１の容量と同じであるので、上記動作の繰り返しによって、メモリアレイ１内のすべてのメモリセルに順番にデータ「０」が書き込まれる（ステップＳ２２３，Ｓ２２４）。
ワーキングレジスタｉｄｘｗの値が「０」になると、シーケンス制御回路４１３はプログラムカウンタ４１２の値をインクリメントして、表７の３番目のマイクロ命令を読み出す。そのオペコードは「ｎｏｐ」であるため、シーケンス制御回路４１３は何もせずプログラムカウンタ４１２を１つだけ進める（ステップＳ２０５）。
一方、アドレス演算回路４１４は、３番目のマイクロ命令の演算コードに従って、Ｘ，ＹアドレスをインクリメントしてからベースレジスタＸｂａｓｅ，Ｙｂａｓｅに入っている値をＸアドレス，Ｙアドレスとしてそれぞれ出力する。このときベースレジスタＸｂａｓｅ，Ｙｂａｓｅの値は「０」に戻っている。データ生成回路４１５はこのとき「０」を出力する。また、制御フィールドＭＦｄの制御コードに従って、制御信号Ｒ（読み出し）が出力される。これによって、当該アドレスのデータが読み出され、期待値データ「０」と比較される（ステップＳ２２５，Ｓ２２６）。
次に、上記ステップＳ２０５でプログラムカウンタ４１２がインクリメントされているため、表７の４番目のマイクロ命令が読み出される。第４のマイクロ命令のオペコードは「ｊｉｎｄｅｘ１」であるため、シーケンス制御回路４１３ではオペランドの繰り返し回数がインデックスレジスタｉｄｘ１にセットされる（ステップＳ２０６）。インデックスレジスタｉｄｘ１の最初の設定値はメモリアレイ１の容量（バイト数もしくはワード数）に対応される。ただし、第４命令のｊｉｎｄｅｘ１命令コードは第２命令のｊｉｎｄｅｘ１命令コードと異なるＰＣアドレス（飛び先番地）を有するため、実行後に第３の命令（オペコードが「ｎｏｐ」）に戻る。
一方、アドレス演算回路４１４では、演算コードＸ←Ｘｂａｓｅ，Ｙ←ＹｂａｓｅによってベースレジスタＸｂａｓｅ，Ｙｂａｓｅの値をＸアドレス，Ｙアドレスとしてそれぞれ出力する。また、データ生成コードＤｉｎｖｅｒｔによって、データ生成回路４１５からはレジスタＴｐの値「０」を反転したデータ「１」が出力される。そして、このとき、制御信号Ｗ（書き込み）が出力される。これによって、メモリアレイ１では出力されたＸ，Ｙアドレスのメモリセルにデータ「１」が書き込まれる（ステップＳ２２７）。
シーケンス制御回路４１３はオペコード「ｊｉｎｄｅｘ１」によってインデックスレジスタｉｄｘ１の値をデクリメントしてワーキングレジスタｉｄｘｗに入れ、それが「０」になるまで「ｎｏｐ」命令に戻って繰り返す（ステップＳ２０７，Ｓ２０８）。また、アドレス演算回路４１４では演算コードＸｂａｓｅ←Ｘｂａｓｅ＋１によってベースレジスタＸｂａｓｅの値すなわちＸアドレスをインクリメントし、Ｙｂａｓｅ←Ｙｂａｓｅ＋１（ＢＸ）によってベースレジスタＸｂａｓｅが最大値になるとＹアドレスをインクリメントする。上記インデックスレジスタｉｄｘ１の最初の設定値はメモリアレイ１の容量と同じであるので、上記手順によって、メモリアレイ１内のすべてのメモリセルに対して順番に読み出しが行なわれ期待値と比較されてから当該アドレスに「１」が書き込まれる動作を繰り返す（ステップＳ２２７，Ｓ２２８）。
次に、表７の５番目のマイクロ命令が読み出される。第５のマイクロ命令のオペコードは「ｊｉｎｄｅｘ１」であるため、シーケンス制御回路４１３ではオペランドの繰り返し回数がインデックスレジスタｉｄｘ１にセットされる（ステップＳ２０９）。インデックスレジスタｉｄｘ１の最初の設定値はメモリアレイ１の容量（バイト数もしくはワード数）に対応される。この第５のｊｉｎｄｅｘ１命令コードは第２のｊｉｎｄｅｘ１命令コードと同じＰＣアドレスを有し、同一命令を繰り返す命令とされる。一方、アドレス演算回路４１４では、演算コードＸ←Ｘｂａｓｅ，Ｙ←ＹｂａｓｅによってベースレジスタＸｂａｓｅ，Ｙｂａｓｅの値をＸアドレス，Ｙアドレスとしてそれぞれ出力する。また、データ生成コードＤｉｎｖｅｒｔによって、データ生成回路４１５からはレジスタＴｐの値「０」を反転したデータ「１」が出力される。そして、このとき、制御信号Ｒ（書き込み）が出力される。これによって、メモリアレイ１では出力されたＸ，Ｙアドレスによって指定されたメモリセルからデータの読み出しが行われる（ステップＳ２２９）。
シーケンス制御回路４１３はオペコード「ｊｉｎｄｅｘ１」によってインデックスレジスタｉｄｘ１の値をデクリメントしてワーキングレジスタｉｄｘｗに入れ、それが「０」になるまで「ｊｉｎｄｅｘ１」命令を繰り返す（ステップＳ２１０，Ｓ１１）。また、アドレス演算回路４１４では演算コードＸｂａｓｅ←Ｘｂａｓｅ＋１によってベースレジスタＸｂａｓｅの値すなわちＸアドレスをインクリメントし、Ｙｂａｓｅ←Ｙｂａｓｅ＋１（ＢＲ）によってベースレジスタＸｂａｓｅが最大値になるとＹアドレスをインクリメントする。上記インデックスレジスタｉｄｘ１の最初の設定値はメモリアレイ１の容量と同じであるので、上記動作の繰り返しによって、メモリアレイ１内のすべてのメモリセルが順番に読み出しが行なわれて期待値「１」と比較される（ステップＳ２３０，Ｓ２３１）。
次に、表７の６番目のマイクロ命令が読み出される。第６のマイクロ命令のオペコードは「ｊｘｄ」であるため、シーケンス制御回路４１３ではアドレスフィールドＭＦｃ内のＰＣアドレスの示す飛び先番地へジャンプする。この実施例では、表７の第２の命令「ｊｉｎｄｅｘ１」へ戻るようにされている。そして、再びｊｉｎｄｅｘ１命令が読み出されたときにフラグｄｆｌｇが「１」にセットされる。これにより、２巡目のシーケン処理においては、図１８のステップＳ２１２で「ＹＥＳ」と判定して、マーチング試験を終了する。
一方、２巡目のマイクロ命令リストの実行に際しては、図１９のステップＳ２２２〜Ｓ２３１において、データ生成回路４１４によりライトデータと期待値データを「１」として全ビットへ連続して書き込みを行なってから、書き込んだデータを１ビットずつ読み出してそこへ反転データ「０」を書き込み、その後、全ビットの連続した読み出しが行なわれるようにされている。図１９のフローでは、ステップＳ２３２で、ステップＳ２２２〜Ｓ２３１による上記のような１巡目とは逆のデータの書き込み読み出しが終了したか否かの判定（裏データ終了判定）が行なわれるようにされている。なお、上記裏データによる検査を行なうための裏データ生成は図１７のＴｈｏｌｄのＩＮＶＥＲＴとｄｆｌｇでコントロールして生成するようにされている。
上述したように、図１８および図１９のフローに従った制御は、表１〜表６に記述されている命令コードを用いて命令メモリ４１１内のマイクロ命令を次の表７の命令リストのように記述することで、僅か６つのマイクロ命令によりマーチング試験を実行することができる。
さらに、前記実施例のテスト回路（ＡＬＰＧ）においては、表１〜表６に記述されている命令コードを用いることにより上記マーチング試験の他に、すべてのメモリセルに「０」または「１」が書き込めるか検査するオール「０」判定試験またはオール「１」判定試験や、あるビットに「１」を書き込んでそれによって他のビットが誤書込みされていないかすべてのビットについて検査するいわゆるＮ^２乗パターン試験（もしくはギャロッピング試験）等も実行することができる。
表８に、Ｎ^２乗パターン試験のためのマイクロ命令リストを示す。なお、ｉｘｄは、初期値レジスタＴｐｈｏｌｄの下にあるフラグｄｆｌｇでコントロールされるインバータＩＮＶＥＲＴをコントロールして裏テストパターンを生成する命令である。フラグｄｆｌｇが０のときは初期値レジスタＴｐｈｏｌｄの値をそのままレジスタＴｐに格納し、フラグｄｆｌｇが１のときはその逆のパターンがレジスタＴｐに設定される。
【表８】

上記実施例においては、プログラムカウンタ４１２に最初に設定する値を、表７や表８に示される最初のマイクロ命令の命令番地に変更することで、マーチング試験やＮ^２乗パターン試験を開始させることができる。
次に、前記カスタム論理部１１０およびＣＰＵ１３０の検査の際にＦＰＧＡ１２０内に構築されるロジックテスタの詳細について説明する。
ロジックテスタは、メモリのテストパターンを生成する図１２に示されているＡＬＰＧと類似の構成を有し、例えば図２０に示されているように、所定のテストパターン生成アルゴリズムに従って記述された複数のマイクロ命令群からなるマイクロプログラムが格納された命令メモリ４１１と、該命令メモリ４１１から読み出すべきマイクロ命令を指定するプログラムカウンタ４１２、命令メモリ４１１から読み出されたマイクロ命令内の命令コードを解読して上記プログラムカウンタ４１２など制御部４００内の回路に対する制御信号を形成する命令解読制御回路４３０、基準クロックφ０に基づいてタイミング制御信号を形成するタイミング発生部４２０、マイクロ命令内のタイミング設定ビットＭＦｄ（ＴＳビット）に基づいてタイミング発生部４２０に対する制御データを出力するデータレジスタセット４１７、マイクロ命令内のタイミング設定ビットＭＦｄ（ＴＳビット）をデコードしてデータレジスタセット４１７から制御データを読み出すデコーダ４１８などを備えている。
また、テスト対象となる論理回路の内、その機能が特定されている回路（例えば、ＡＬＵ：Ａｒｉｔｈｍｅｔｉｃ Ｌｏｇｉｃ Ｕｎｉｔ）の場合には、すでに適切なテストパターン形成方式が確立されている場合が多いので、そのテストパターンの資産を利用することで、効率の良いテストパターンの生成が可能である。また、組合せ論理回路に関しては、故障仮定法および一つの回路には故障は一つであるという単一故障という考えに基づくＤアルゴリズムと呼ばれる効率の良いテストパターンの生成方法が知られている。この手法を利用することによって、テストパターン生成のためのマイクロプログラムを短くすることができ、命令メモリ４１１の容量の増大を実現可能な程度まで抑えることができる。
この実施例では、特に制限されないが、デコーダ４１８でデコードされるタイミング設定ビットＴＳは２ビットで構成され、データレジスタセット４１７には７個の制御データが格納されている。これらの制御データのうち一つはテスト・サイクルを規定するデータ“ＲＡＴＥ”、残りの６個の制御データは、テスタ専用バスの各信号線ごとにハイレベルもしくはロウレベルの信号の出力タイミングを与える２種類の制御データ“ＡＣＬＫ１”，“ＡＣＬＫ２”と、パルス信号の立上がりタイミングを与える２種類の制御データ“ＢＣＬＫ１”，“ＢＣＬＫ２”と、パルス信号の立下がりタイミングおよび期待値との比較出力タイミングを与える２種類の制御データ“ＣＣＬＫ１”，“ＣＣＬＫ２”である。
これらの各制御データが、タイミング発生部４２０に供給されると、制御データＲＡＴＥに関しては予め規定されたタイミングの信号ＲＡＴＥがプログラムカウンタ４１２に供給されて命令メモリ４１１からのマイクロ命令コードの取り込みが行なうわれる。また制御データとして“ＡＣＬＫ１”〜“ＣＣＬＫ２”がタイミング発生部４２０に供給されると、タイミングクロックＡＣＬＫ１〜ＣＣＬＫ２の中からその制御コードに対応するクロックが信号形成・比較部３００に出力される。各クロックの使用のための接続や選択は必要に応じて適宜実施される。
さらに、ロジックテスタには、上記プログラムカウンタ４１２の値を「＋１」にインクリメントするためのインクリメンタ４２１や、上記インクリメンタ４２１またはアドレスフィールドＭＦａ内の飛び先番地のいずれかを選択してプログラムカウンタ４１２へ供給するマルチプレクサ４２２、オペランドフィールドＭＦｃ内の繰り返し数を保持するインデックスレジスタ４２３、該インデックスレジスタ４２３の値を「−１」するためのデクリメンタ４２４、「−１」にディクリメントされた値を保持するワーキングレジスタ４２５、所定の命令で用いられるオペランドのプログラムカウンタ４１２への転送の有無を示すフラグ４２７、レジスタ４２３，４２５の値を選択的に上記デクリメンタ４２４に供給するマルチプレクサ４２８、デクリメンタ４２４の値をワーキングレジスタ４２５のいずれかのプレーンに分配するデマルチプレクサ４２９などが設けられている。
このロジックテスタでは、マイクロ命令コードに命令の繰り返し数を格納するオペランドフィールドＭＦｃを設けるとともに、その繰り返し数を保持するインデックスレジスタ４２３を設けているので、同一テスト信号を繰り返し生成するような場合に、必要なマイクロ命令数を減らしマイクロプログラムを短くすることができる。また、この実施例では、インデックスレジスタ４２３やワーキングレジスタ４２５、フラグ４２７が複数プレーン（図では４個）設けられていることにより、あるループ処理内におけるサブループ処理、さらにそのサブループ処理内におけるサブループ処理といったことを容易に実行することができ、マイクロプログラムを短くすることができる。
図２１には、上記信号形成・比較部３００の実施例が示されている。なお、図２１の回路は、テスタ専用バス２２０を構成する信号線のうちの１本に対応するドライバ／コンパレータ回路のみが代表的に示されているが、実際にはテスタ専用バス２２０を構成する信号線の数だけ図２１に示す回路が設けられる。
図２１に示すように、この実施例のドライバ／コンパレータ回路は、テスタ専用バスへ出力する信号を形成するドライバ回路（信号形成回路）３４０と、テスタ専用バス上の信号と期待値信号とを比較して一致／不一致を比較するコンパレータ回路（比較回路）３５０と、ドライバ回路３４０とコンパレータ回路３５０とを切り替える切替え回路３６０とから構成される。切替え回路３６０は、ドライバ回路３４０と入出力ノードＮｉｏとの間に設けられた伝送ゲートＴＧ１と、入出力ノードＮｉｏとコンパレータ回路５０と間に設けられた伝送ゲートＴＧ２とから構成され、上記制御部４００から供給される入出力制御ビットＩ／Ｏに応じていずれか一方が開かれ他方は遮断状態とされる。
ドライバ回路３４０は、タイミング発生部４２０から供給されるタイミングクロックＡＣＬＫｉによって入出力制御ビットＴＰを取り込んで保持するエッジトリガ型フリップフロップ３４１と、タイミング発生部４２０から供給されるタイミングクロックＢＣＬＫｉとＣＣＬＫｉとの論理和をとるＯＲゲート３４２と、このＯＲゲート３４２の出力と上記エッジトリガ型フリップフロップ３４１の出力を入力信号とするＪ／Ｋフリップフロップ３４３と、このＪ／Ｋフリップフロップ３４３の出力と制御部４００から供給される入出力制御ビットＣＯＮＴとを入力信号とするＡＮＤゲート３４４と、上記エッジトリガ型フリップフロップ３４１の出力と制御部４００から供給される入出力制御ビットＣＯＮＴとを入力信号とするＡＮＤゲート３４５と、これらのＡＮＤゲート３４４，３４５の出力によってテスタ専用バスを駆動するドライバ３４６とから構成されている。
一方、コンパレータ回路３５０は、タイミング発生部４２０から供給されるタイミングクロックＣＣＬＫｉと制御部４００から供給される入出力制御ビットＣＯＮＴとを入力信号とするＡＮＤゲート３５１と、上記Ｄ型フリップフロップ３４１の出力（期待値）と伝送ゲートＴＧ２を介して供給されるテスタ専用バス上の信号とを入力信号とするエクスクルーシブＯＲゲート３５２と、このエクスクルーシブＯＲゲート３５２と上記ＡＮＤゲート３５１との出力を入力信号とするＡＮＤゲート３５３と、このＡＮＤゲート３５３の出力をラッチするフリップフロップ３５４とから構成されており、すべてのコンパレータ回路３５０の出力の回路の論理和をとった信号がトータル・フェイル信号ＴＦＬとして出力される。上記入出力制御ビットＩ／Ｏ、ＴＰ、ＣＯＮＴは、上記制御信号に相当する。
図２０に示されているように、本実施例のテスト回路におけるマイクロ命令は、ジャンプ命令で使用する命令の飛び先番地を示すＰＣアドレスが格納されるアドレスフィールドＭＦａと、シーケンス制御コードが格納されるオペコードフィールドＭＦｂと、命令の繰り返し数などが格納されるオペランドフィールドＭＦｃと、上記データレジスタセット１４からタイミング発生部４２０に対する制御信号を読み出すためのタイミング設定ビットＴＳが格納されるタイミング設定フィールドＭＦｄと、上記信号形成・比較部３００の入出力制御ビットが格納される入出力制御フィールドＭＦｅとからなる。
上記タイミング設定フィールドＭＦｄに格納されるタイミング設定ビットＴＳは、前述したようにこの実施例では２ビットであるが、３ビット以上設けてもよい。また、上記入出力制御フィールドＭＦｅに格納される入出力制御ビットは、テスタ専用バス２２０のｎ本の信号線に対応して、ドライバ・ビットＴＰとＩ／Ｏビットとコントロール・ビットＣＯＮＴの３ビットを１セットとし、ｎセットだけ設けられている。これらのビットのうち、Ｉ／Ｏビットは入力か出力かを指定する制御ビットで“１”のときは伝送ゲートＴＧ１を開きかつＴＧ２を遮断してドライバの出力信号をテスタ専用バス２２０の対応する信号線上へ出力し、“０”のときは伝送ゲートＴＧ１を遮断しかつＴＧ２を開いてテスタ専用バス２２０の対応する信号線上の信号を比較用のゲート３５２へ入力させる。ドライバ・ビットＴＰおよびコントロール・ビットＣＯＮＴは、その組合せに応じてハイ出力またはロウ出力か、正パルスもしくは負パルスの出力か、入力無効状態か、出力ハイインピーダンス状態かを指定する。
表９には、上記入出力制御ビットＴＰ，Ｉ／Ｏ，ＣＯＮＴと信号形成・比較部３００の動作状態との関係が示されている。
【表９】

表９に示されているように、入出力制御ビットＴＰ，Ｉ／Ｏ，ＣＯＮＴが「１１１」のときはドライバ回路３４０がハイレベルの信号を出力し、「０１１」のときはドライバ回路３４０がロウレベルの信号を出力し、「１１０」のときはドライバ回路３４０が正のパルス信号を出力し、「１１０」のときはドライバ回路３４０が負のパルス信号を出力するように制御が行なわれる。また、入出力制御ビットＴＰ，Ｉ／Ｏ，ＣＯＮＴが「１０１」のときはコンパレータ回路３５０がハイレベルの入力信号を期待し、「００１」のときはコンパレータ回路３５０がロウレベルの入力信号を期待し、「１００」のときは入力信号を無効とするように制御が行なわれる。
なお、この実施例の信号形成・比較部３００では、制御ビットＴＰ，Ｉ／Ｏ，ＣＯＮＴが「０００」となる状態は何ら意味を持たないように構成されている。ただし、制御ビットＴＰ，Ｉ／Ｏ，ＣＯＮＴが「０００」のときは、例えば伝送ゲートＴＧ１を閉じてＴＧ２を開き、かつエクスクルーシブＯＲゲート３５２を上記ハイレベルとロウレベルの間にある２つのレベルで動作するシュミット回路としてその２つのレベル間にテスタ専用バス２２０に接続された入出力ノードＮｉｏの電位が存在する状態（ハイインピーダンス状態）を比較できるように信号形成・比較部３００を構成しておくことも可能である。
図２２には上記実施例におけるタイミング発生部４２０より供給されるタイミングクロックＡＣＬＫ１〜ＣＣＬＫ２と信号形成・比較部３００からテスタ専用バス２２０上に出力される信号の一例が示されている。図２２において、（ａ）は外部から供給される基準クロックφ０を、（ｂ）〜（ｇ）はタイミングクロックＡＣＬＫ１〜ＣＣＬＫ２の波形を、（ｈ）は表９の出力テスト信号として「１」が指定されかつクロックとしてＡＣＬＫ１が選択された端子の出力信号の波形を示す。また、（ｉ）は表９の出力テスト信号として「０」が指定されかつクロックとしてＡＣＬＫ２が選択された端子の出力信号の波形を示す。また、（ｊ）は表９の出力テスト信号として「Ｐ」が指定されかつクロックとしてＢＣＬＫ１，ＣＣＬＫ１が選択された端子の出力信号の波形を示す。さらに、（ｋ）は表９の出力テスト信号として「Ｎ」が指定されかつクロックとしてＢＣＬＫ２，ＣＣＬＫ２が選択された端子の出力信号の波形を示す。
図２２から分かるように、入出力制御ビットＴＰ，Ｉ／Ｏ，ＣＯＮＴが「１１１」に設定されクロックＡＣＬＫ１が指定された端子からはクロックＡＣＬＫ１に従い図２２（ｈ）のようなハイレベルの信号が出力され、ＴＰ，Ｉ／Ｏ，ＣＯＮＴが「０１１」に設定されクロックＡＣＬＫ２が指定された端子からはクロックＡＣＬＫ２に従い図２２（ｉ）のようなロウレベルの信号が出力され、ＴＰ，Ｉ／Ｏ，ＣＯＮＴが「１１０」に設定されクロックＡＣＬＫ１，ＢＣＬＫ１，ＣＣＬＫ１が指定された端子からはクロックＡＣＬＫ１でセットされたデータに従いＢＣＬＫ１，ＣＣＬＫ１をエッジとする図２２（ｊ）のような正パルスが出力され、ＴＰ，Ｉ／Ｏ，ＣＯＮＴが「０１０」に設定されクロックＡＣＬＫ２，ＢＣＬＫ２，ＣＣＬＫ２が指定された端子からはクロックＡＣＬＫ２でセットされたデータに従いＢＣＬＫ２，ＣＣＬＫ２をエッジとする図２２（ｋ）のような負パルスが出力される。
また、図示しないが、入出力制御ビットＴＰ，Ｉ／Ｏ，ＣＯＮＴが「１０１」に設定されクロックＣＣＬＫ１が指定された端子では期待値をハイレベルとして図２２（ｆ）のクロックＣＣＬＫ１をストローブ信号として比較が行なわれ、ＴＰ，Ｉ／Ｏ，ＣＯＮＴが「００１」に設定されクロックＣＣＬＫ２が指定された端子では期待値をロウレベルとし図２２（ｇ）のクロックＣＣＬＫ２をストローブ信号として比較が行なわれる。なお、クロックの選択は上記に限定されず任意の組合せとすることができる。
以上説明したように上記実施例においては、半導体チップ上に複数の基本論理セル（セル論理ブロック）からなり基本論理セルごとに回路が正常か異常かを示す信号を出力可能でかつ任意の論理を構成可能なＦＰＧＡ（Ｆｉｅｌｄ Ｐｒｏｇｒａｍｍａｂｌｅ Ｇａｔｅ Ａｒｒａｙ）のような可変論理回路を搭載するようにしたものである。これにより、外部テスタを使用することなく可変論理回路（ＦＰＧＡ）内に不良個所があることおよびその位置を知ることができる。また、不良個所を回避して論理を構成することにより歩留まりを向上させるとともに、この可変論理回路（ＦＰＧＡ）を用いてテスト回路を構築して他の内部回路をテストする場合にテスト回路自身の故障による誤ったテスト結果が出力されるのを回避することができるという効果がある。
また、本発明に係る半導体集積回路のテスト方法は、回路が正常か異常かを示す信号を出力可能でかつ任意の論理を構成可能な可変論理回路（ＦＰＧＡ）と読出し書込み可能なメモリ回路とを内蔵した半導体集積回路において、まず上記可変論理回路（ＦＰＧＡ）により自己テストを行なわせ、その結果得られた不良個所を示す情報を用いて不良個所を除いた基本論理セルのみで所定のアルゴリズムに従ってメモリ回路を検査するメモリテスト回路を構築して上記メモリ回路を検査するようにした。これによって、高機能の外部テスタを用いることなくＬＳＩ内部のメモリ回路のテストを行なうことができるという効果がある。
さらに、本発明に係る半導体集積回路の他のテスト方法は、半導体集積回路がメモリ回路と共にＣＰＵ（中央処理ユニット）やユーザが要求する論理機能を構成したユーザ論理回路のようなカスタム論理回路を含むような場合に、上記ＦＰＧＡに所定のアルゴリズムに従ってＣＰＵやカスタム論理回路のテスト信号および期待値信号を生成してテストを行なうテスト回路（ロジックテスタ）を構築するとともに、既に前記テストにより正常と判定されたメモリ回路を使用して、そのメモリ回路にテストパターンもしくはテストパターン生成プログラムを格納し、ＦＰＧＡに構築されたテスト回路を起動してＣＰＵやカスタム論理回路のテストを行なうようにした。これによって、高機能の外部テスタを用いることなくＬＳＩ内部のＣＰＵや論理回路のテストを行なうことができるという効果がある。
さらに、本発明に係る半導体集積回路の製造方法は、まず上記可変論理回路により自己テストを行なわせ、その結果得られた不良個所を示す情報を用いて該可変論理回路内に、不良個所を除いた基本論理セルのみで所定のアルゴリズムに従って第１のメモリ回路を検査するメモリテスト回路を構築して、上記第１のメモリ回路を検査し、
次に、上記可変論理回路内に、不良個所を除いた基本論理セルのみで所定のアルゴリズムに従ってカスタム論理回路または中央処理ユニットを検査するロジックテスト回路を構築するとともに上記第１のメモリ回路内にテストパターンもしくはテストパターン生成プログラムを格納して、上記カスタム論理回路または中央処理ユニットを検査し、
しかる後、上記可変論理回路内に、不良個所を除いた基本論理セルのみで所定のアルゴリズムに従って第２のメモリ回路を検査するメモリテスト回路を構築して、上記第２のメモリ回路を検査し、
その後、上記第２のメモリ回路の検査結果に基づいて上記第２のメモリ回路に付随する冗長回路を用いて第２のメモリ回路内の欠陥ビットを予備のビットと置き替えるビット救済処理を行なうようにしたので、メモリ回路のビット救済を自動的に行なうことができ、半導体集積回路の歩留まりおよび生産性を向上させることができるという効果がある。
また、本発明に係る半導体集積回路の製造方法は、上記第２のメモリ回路のビット救済処理後に、上記可変論理回路内に所望の論理を構成するようにしたので、テスト終了後にＬＳＩチップ内には無駄な回路が残らないので、テスト回路をＬＳＩ内部に設けることに伴うハードウェアのオーバーヘッドを減らすことができるという効果がある。
さらに、本発明に係る半導体集積回路の製造方法は、上記第２のメモリ回路の検査の際に欠陥ビットの位置を示す情報を上記第１のメモリ回路内に記憶するようにしたので、上記第１のメモリ回路内に記憶されている情報を読み出すことにより不良解析を容易に行なうことができるという効果がある。
以上本発明者によってなされた発明を実施例に基づき具体的に説明したが、本発明は上記実施例に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。例えば上記実施例においては、セル論理ブロックＣＬＢ内の回路が正常か否か検出して出力する排他的論理和ゲート回路ＬＧ２の出力状態をクロスポイントスイッチ回路ＣＳＷ内のメモリセルＳＭＣに記憶させるようにしているが、ＬＳＩチップの外部へ出力させるように構成してもよい。
また、上記実施例においては、ＤＲＡＭ１５０〜１８０のテストの際に欠陥ビットの位置を記憶するフェールメモリをＳＲＡＭ１４０内に構成するようにしているが、外部のテスタ内にフェールメモリを設けるようにしてもよい。さらに、上記実施例ではテスト用のインタフェース回路としてＩＥＥＥで規定されているＴＡＰを利用しているが、それに限定されるものでなく、本実施例に適した専用のインタフェース回路を別途設計して設けるようにしても良い。
産業上の利用可能性
以上の説明では主として本発明者によってなされた発明をその背景となった利用分野であるＣＰＵとＳＲＡＭ、ＤＲＡＭおよびカスタム論理回路を備えたシステムＬＳＩにおける自己検証方法を例にとって説明したが、この発明はそれに限定されず、ＣＰＵとＳＲＡＭおよびカスタム論理回路を備えた論理ＬＳＩ、ＣＰＵとＤＲＡＭおよびカスタム論理回路を備えた論理ＬＳＩ、ＣＰＵとカスタム論理回路を備えた論理ＬＳＩ、ＳＲＡＭとＤＲＡＭおよびカスタム論理回路を備えた論理ＬＳＩさらには上記のようなディジタル回路の他にアナログ回路が搭載された半導体集積回路にも利用することができる。
【図面の簡単な説明】
図１は、本発明を適用した論理ＬＳＩの一実施例の全体構成を示すブロック図である。
図２は、本発明を適用した論理ＬＳＩ内に設けられる可変論理回路（ＦＰＧＡ）の一実施例を示す回路構成図である。
図３は、ＦＰＧＡを構成するクロスポイントスイッチの具体例を示すブロック図である。
図４は、ＦＰＧＡを構成するセル論理ブロックの具体例を示す論理回路図および概念図である。
図５は、ＦＰＧＡを構成するセル論理ブロックの他の例を示す論理回路図である。
図６は、本発明を適用した論理ＬＳＩ内に設けられるテスト用インタフェース回路の一構成例を示すブロック図である。
図７は、本発明を適用した論理ＬＳＩにおける内部回路の検査手順の一例を示すフローチャート図である。
図８は、図７のフローチャートのステップＳ１〜Ｓ３におけるＦＰＧＡ部の検査手順の具体的内容を示すフローチャートである。
図９は、図７のフローチャートのステップＳ４〜Ｓ５におけるＳＲＡＭ部の検査手順の具体的内容を示すフローチャートである。
図１０は、図７のフローチャートのステップＳ６〜Ｓ８におけるカスタム論理回路およびＣＰＵ部の検査手順の具体的内容を示すフローチャートである。
図１１は、図７のフローチャートのステップＳ９〜Ｓ１２におけるＤＲＡＭ部の検査手順の具体的内容を示すフローチャートである。
図１２は、ＦＰＧＡ内に構築されるＡＬＰＧの構成を示すブロック図である。
図１３は、ＡＬＰＧを使用してメモリ回路をテストする際のバスの構成例を示すブロック図である。
図１４は、ＡＬＰＧの命令メモリに格納されるマイクロ命令の命令フォーマットの構成例を示す説明図である。
図１５は、ＡＬＰＧのシーケンス制御部の構成例を示すブロック図である。
図１６は、ＡＬＰＧのアドレス演算部の構成例を示すブロック図である。
図１７は、ＡＬＰＧのテストデータ生成演算部の構成例を示すブロック図である。
図１８は、ＡＬＰＧによりメモリ回路の検査を行なう場合のマイクロ命令のオペコードおよびオペランドを用いたシーケンス制御手順の一例を示すフローチャートである。
図１９は、ＡＬＰＧによりメモリ回路の検査を行なう場合のマイクロ命令の演算コードおよびデータ生成コードを用いたテストアドレスおよびデータの生成、出力手順の一例を示すフローチャートである。
図２０は、ＦＰＧＡ内に構築されるロジックテスタの構成例を示すブロック図である。
図２１は、ロジックテスタ内の信号形成・比較手段の具体例を示す論理回路図である。
図２２は、ロジックテスタにより形成されるテスト用信号波形の一例を示す波形図である。Technical field
The present invention relates to a semiconductor integrated circuit (IC: Integrated Circuit) and a test technique and a manufacturing technique thereof, and provides, for example, a logic LSI (Large Scale Integration) capable of configuring a logic by detecting a fault and avoiding a fault location. is there.
Background art
As a test method for a logic IC, a method in which test pattern data is generated by a test device called a tester, input to the IC, and an output data signal is compared with an expected value to detect it. However, as the logic scale of the logic IC increases, the number of test pattern steps becomes longer, and the time required for test pattern creation and test using the test pattern becomes very long.
Therefore, as a method for facilitating the test by the tester, a shift register can be configured by cascading sequential circuits such as flip-flops constituting the original function of the IC so that the shift register can be configured during the test. The test pattern is serially input (scanned in) to be captured (set), the test data captured in the shift register is input to a desired combinational logic circuit, and then the output data signal of the logic circuit is captured in the shift register. A testability design technology called a so-called scan path method that can be shifted out (scanned out) has been developed and put into practical use.
In the method of inputting a test pattern from the outside, if a logic circuit includes a sequential circuit, the output differs depending on the internal state. Therefore, in order to inspect a certain logic circuit, the state of the sequential circuit contained therein is first tested. However, the test pattern becomes very long because it has to be set in step 1. However, the test pattern can be significantly reduced by inputting (scanning in) the test pattern with a flip-flop as a shift register configuration.
However, the scan path method has a smaller amount of test patterns than the previous test methods, but it is difficult to generate test patterns, and it is difficult to increase the defect detection rate, and the test pattern can be input (transferred) serially. Since the test is repeated, there is a problem when the test time becomes long. In addition, a newly developed logic LSI includes a memory circuit such as a RAM (Random Access Memory) and a ROM (Read Only Memory) and a large cell such as a CPU (Macro Cell or IP Core: Intelligent Property Core). In order to test these cells, it is necessary to create and input an enormous amount of test patterns, so that there is a problem that the test cannot be performed in practice.
On the other hand, a BIST (Built in self test) type test technique in which a pattern generation circuit for generating a random test pattern such as a pseudo random number generation circuit is built in a logic integrated circuit has been proposed.
However, the test circuit of the BIST system is not guaranteed that the generated test pattern is a test pattern sufficient to detect a defect. For this reason, there is a problem that it is necessary to separately verify whether or not a sufficient defect detection rate can be obtained with the test pattern of the test circuit.
Further, any LSI on which a conventional test circuit is mounted does not take any measures against its own failure or defect. In other words, when the test circuit itself fails, there is a drawback that a failure is determined even if the original circuit of the chip is normal. And as a countermeasure, there is no choice but to minimize the scale of the test circuit and suppress the occurrence of failures and defects, but this leads to a result that contradicts the objective of improving the sufficiency of the test, that is, the defect detection rate. .
An object of the present invention is to provide a test technique capable of testing a circuit inside an LSI without using a high-function external tester.
Another object of the present invention is to provide a high-yield LSI capable of detecting a fault location by itself and repairing itself.
Another object of the present invention is to provide an LSI having a self-test function with less hardware overhead.
Another object of the present invention is to provide an LSI that can be easily analyzed for defects.
Still another object of the present invention is to provide a manufacturing technique suitable for application to a so-called system LSI having a control circuit such as a central processing unit, a memory circuit, a custom logic circuit, etc. on one chip. is there.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
Disclosure of the invention
Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
In other words, the semiconductor integrated circuit according to the present invention comprises a plurality of basic logic cells (cell logic blocks) on a chip and can output a signal indicating whether the circuit is normal or abnormal for each basic logic cell and constitutes arbitrary logic. A variable logic circuit such as a possible FPGA (Field Programmable Gate Array) is mounted. Thereby, it is possible to know that there is a defective part and its position in the variable logic circuit (FPGA) without using an external tester. In addition to improving the yield by avoiding defective parts and configuring the logic, a failure of the test circuit itself occurs when a test circuit is built using this variable logic circuit (FPGA) to test other internal circuits. It is possible to avoid outputting an erroneous test result by.
As a basic logic cell capable of outputting a signal indicating whether the circuit is normal or abnormal, for example, determination means for comparing the output with a two-line line logic (logical product gate circuit) having a complementary output and determining the presence or absence of abnormality ( And an exclusive OR gate). By configuring the basic logic cell in this way, a variable logic circuit (FPGA) capable of outputting a signal indicating whether the circuit is normal or abnormal and capable of configuring any logic with a relatively small circuit is realized. can do.
The semiconductor integrated circuit test method according to the present invention comprises at least a plurality of basic logic cells (cell logic blocks), and can output a signal indicating whether the circuit is normal or abnormal for each basic logic cell, In a semiconductor integrated circuit incorporating a configurable variable logic circuit (FPGA) and a readable / writable memory circuit, first, a self-test is performed by the variable logic circuit (FPGA), and information indicating a defective portion obtained as a result is obtained. Is used to generate a predetermined test signal and an expected value signal in accordance with a predetermined algorithm using only basic logic cells excluding defective portions, and supply the test signal to the memory circuit. As a result, an output signal (output) obtained from the memory circuit Data) and the expected value signal (expected value data) are compared, and if they do not match, a signal indicating a defect is formed to the outside of the chip It is obtained so as to build a memory test circuit for force.
Such a memory test circuit can be configured as a test pattern generator called an ALPG (Algoromic Memory Pattern Generator) that generates a test pattern of a memory according to a predetermined algorithm. Further, the ALPG includes a control unit of a known microprogram control system that decodes an instruction code to control an arithmetic unit and the like, and an arithmetic unit that generates a test pattern by calculation. Then, the test pattern generation program instruction code is sequentially supplied to the ALPG constructed in the FPGA as described above to generate a test pattern, and the test pattern is supplied to the memory circuit which is the circuit under test. Can be inspected.
Further, the test pattern generation program is described using an existing tester language or a test language, and a test pattern (address and data) is generated according to the predetermined algorithm defined by the instruction code. The tester language is regarded as an effective instruction language for efficiently generating a test pattern including an address and data. The tester language is a language used in the tester industry. For example, a language compatible with the tester language of Advantest is used. This is because the program data of the existing test pattern can be used. The language for describing the predetermined algorithm is not limited to the tester language, and may be any instruction language that can generate a test pattern including an address and data.
Another test method for a semiconductor integrated circuit according to the present invention is such that the semiconductor integrated circuit includes a custom logic circuit such as a CPU (Central Processing Unit) and a user logic circuit that constitutes a logic function requested by a user together with a memory circuit. In this case, a test circuit (logic tester) for generating a test signal and an expected value signal for the CPU and custom logic circuit according to a predetermined algorithm in the FPGA is constructed, and a memory that has already been determined to be normal by the test. A test pattern or test pattern generation program is stored in the memory circuit using the circuit, the test circuit built in the FPGA is activated, and the CPU or custom logic circuit is read while reading the test pattern or test pattern generation program from the memory circuit. Is to test
As a result, the logic circuit inside the LSI can be tested without using a high-function external tester.
A test circuit that generates a test signal and an expected value signal for a CPU or a custom logic circuit according to a predetermined algorithm and performs a test includes: a microinstruction type control unit that decodes an instruction code to form a control signal; A test signal and an expected value signal for the CPU or custom logic circuit are generated based on the output control signal, and a failure is indicated when the signal output from the CPU or custom logic circuit does not match the expected value signal. This is realized by constructing signal forming / comparing means for forming a signal in the FPGA. In this case, a timing generation circuit that forms a plurality of clock signals having different phases and duties based on the reference clock signal can be built in the FPGA, and the timing can be set for each test signal in accordance with the control signal from the control unit. It is good to do so.
As described above, the test circuit outputs a control signal for generating a test signal and an expected value signal for the CPU and the custom logic circuit according to a predetermined algorithm, and a control unit of a microprogram control system, which is output from the control unit. A signal generator that generates a test signal and an expected value signal of the internal logic circuit based on the control signal, and forms a signal indicating a failure when the signal output from the internal logic circuit and the expected value signal do not match Since it is constituted by the comparison means, it is not necessary to store all the test patterns in the internal memory, and the data of the instruction code itself can be compressed by the configuration of the control unit, and can be sufficiently constructed in the FPGA. belongs to.
BEST MODE FOR CARRYING OUT THE INVENTION
Preferred embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram of an embodiment of a system LSI to which the present invention is applied. The system LSI is configured on a single semiconductor chip 100 such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.
In FIG. 1, reference numerals 110 to 180 are internal circuits configured on the semiconductor chip 100, 190 is an interface circuit for inputting and outputting signals between these internal circuits and external devices, and 200 is the internal circuits 110 to 180. This is an internal bus that connects between each other and the interface circuit 190. Among the internal circuits 110 to 180, 110 and 120 are custom logic circuits such as a user logic circuit that constitutes a logic function requested by the user. Among these, 120 is configured by an FPGA that can arbitrarily configure logic. ing. This custom logic circuit may be left as it is without configuring the user logic.
Reference numeral 130 denotes a CPU (central processing unit) that decodes program instructions and executes corresponding processes and operations, 140 is a static RAM (random access memory), and 150 to 180 are dynamic RAMs. Further, the system LSI of this embodiment is not particularly limited. However, in order to input / output signals to / from the external tester 500 when testing the internal circuit, the TAP defined in the IEEE1149.1 standard is used. (Test Access Port) 210 is provided as an interface circuit. The tester 500 is not a high-functional one such as a conventional logic LSI or memory tester, but can perform data writing and reading and simple data processing, and a personal computer can also be used.
The CPU 130 may be configured as a microprocessor including a so-called microcomputer peripheral circuit such as a program ROM, a working RAM, a serial communication interface, a timer circuit, and a digital / analog conversion circuit in addition to the CPU in a narrow sense.
The static RAM 140 and the dynamic RAMs 150 to 180 include a memory peripheral circuit such as an address decoder that selects a corresponding memory cell when an address signal is applied via the internal bus 200. Further, the dynamic RAMs 150 to 180 include a refresh control circuit that periodically performs pseudo-selection so that the information charges of the memory cells are not lost even if the non-access time is increased. Although not particularly limited, in this embodiment, when there is a defective bit in the memory array, the dynamic RAMs 150 to 180 include a memory row or memory column including the defective bit as a spare memory row or spare memory. So-called redundant circuits are provided to replace the memory columns.
FIG. 2 shows a specific example of an FPGA constituting the custom logic circuit 120 among the internal circuits 110 to 180 shown in FIG.
The FPGA of this embodiment includes a plurality of cell logic blocks CLB arranged in a matrix, wiring groups 121 and 122 provided between the cell logic blocks CLB for connecting cells, and wiring between the outside. The cross point switch CSW is capable of changing the connection state. As shown in FIG. 3, the cross point switch CSW is applied to, for example, a switch MOSFET Qsw having a drain and a drain connected to the horizontal wiring Lx and the vertical wiring Ly, and the gate of the switch MOSFET Qsw. The wiring connection information storage memory cell SMC stores control information. The wiring groups 121 and 122 are preferably formed in a state of being insulated from each other by different wiring layers using a multilayer wiring technique. In FIG. 2, two wires are shown between each cell logic block, but more wires are actually formed. The number of wires is increased in proportion to the number of cell logic blocks.
Although not particularly limited, an X decoder circuit, a Y decoder circuit, a write circuit, or the like for selecting the wiring connection information storage memory cell SMC and writing data is provided around the FPGA block. May be. The wiring connection information storage memory cell SMC can be provided as an SRAM memory array around the FPGA block instead of being provided one-to-one with the switch MOSFET Qsw.
For example, as shown in FIG. 4A, the cell logic block CLB includes an AND gate circuit (two-line line logic) LG1 having complementary outputs such as AND logic and NAND logic, and an exclusive input having the complementary output as an input. And a logical OR gate circuit (comparison means) LG2. This gate circuit LG2 outputs a low level output signal when the two input signals have the same logic level, and outputs a high level output signal when the two input signals have different logic levels. When the LG1 is defective and the output to be complementary is the in-phase output, the output of the gate circuit LG2 becomes low level to notify that the gate circuit LG1 is defective.
Although the output signal of the gate circuit LG2 may be output to the outside of the FPGA block as it is, in this embodiment, the memory cell for storing the wiring connection information constituting the crosspoint switch CSW shown in FIG. It is configured so that it can be input and stored in the node N2 of the SMC.
Therefore, the power supply voltage is applied to each cell logic block CLB, and the output state of the gate circuit LG2 at that time is stored in the wiring connection information storage memory cell SMC, and then the storage information of the wiring connection information storage memory cell SMC is stored in the external It is possible to know whether or not the cell logic block CLB operates normally. It is also possible to detect whether or not a memory cell has failed by sequentially writing and reading data from outside the chip to each wiring connection information storing memory cell SMC. Further, by writing data into the wiring connection information storage memory cell SMC, turning on the desired switch MOSFET Qsw and using the wiring groups 121 and 122 to input and check signals from the outside, the switch MOSFET Qsw breaks down. It can also be detected.
Note that by devising the gate structure of the MOSFET Q1 or the memory cell circuit constituting the memory cell SMC for wiring connection information storage to which the output state of the gate circuit LG2 is inputted, when the output of the gate circuit LG2 is at a low level, the external circuit The MOSFET Q1 may be configured not to be inverted, that is, turned off by the data input. Thereby, it is possible to efficiently detect whether or not there is a failure in the cell logic block CLB.
As a specific method for realizing such a function, the MOSFET Q1 constituting the memory cell SMC has a structure having a control gate and a floating gate as shown in FIG. 4B, for example, and the output (low level) of the gate circuit LG2 Is inverted by the inverter INV and a high level voltage Vp is applied to the control gate CG of the MOSFET Q1 to inject charges into the floating gate FG so that the state of the memory cell does not change depending on external data input. Can be considered.
Further, as the AND gate circuit LG1 having complementary outputs such as AND logic and NAND logic shown in FIG. 4A, for example, a circuit as shown in FIG. 4C can be considered. In other words, the AND gate circuit LG1 includes a first MOSFET string composed of MOSFETs Q11 to Q13 connected in series between the power supply voltage terminal Vcc and the ground point, and a second MOSFET string composed of MOSFETs Q21 to Q23 in series. When the first input signal X is supplied to the gates of Q12 and Q21, the logical product output Z (= X · Y) of the input signals X and Y is output from the output node N12 of the second MOSFET array. It operates so as to output the inverted output / Z (= / X · Y) of the logical product output Z of the input signals X and Y from the output node N11 of the 1MOSFET series. The MOSFETs Q11 and Q23 shown in the drawing act as loads when the gate and drain are coupled or a predetermined potential is applied to the gate.
FIG. 5A shows another configuration example of the cell logic block CLB.
The cell logic block CLB of this embodiment is a BIST (Built in self test) built-in type logic block, which latches two input signals X and Y, respectively, and signals X, / X of the positive phase and the negative phase, respectively. Flip-flops FF1 and FF2 for outputting Y, / Y, a logical unit ALU capable of performing a plurality of logical operations such as logical sum, logical product, exclusive logical sum using these four output signals as input signals, A flip-flop FF3 that latches the output Z and outputs signals Z and / Z in the positive and negative phases, a read / writeable memory MEM that stores control information that specifies the logical operation of the logical unit, and a test pattern Consists of a well-known LFSR (Linear Feedback Shift Register) generated in the form of random numbers and a comparator CMP It has been.
The memory MEM for storing the logical unit control information is configured to be able to write control information from the outside. The LFSR is configured to be connectable to the input signals X and Y, the logic unit control information, and the transmission signal lines of the output signals Z and / Z of the FF 3 via the switch MOSFETs G1 to G7, and operates in synchronization with the clock CLK. To do.
When the cell logic block CLB of this embodiment is subjected to a self-inspection operation, the control signal CHK is inputted to the gates of the switch MOSFETs G1 to G7 to be turned on. Then, a random pattern is formed by the LFSR and supplied to the flip-flops FF1 and FF2 and the logic unit ALU, and the generated pattern and the output of the flip-flop FF3 are logically synthesized and compressed to form a comparator pattern CMP as a signature pattern. Is output.
For example, as shown in FIG. 5B, the comparator CMP is a latch timing signal from a read-only memory ROM storing an expected signature pattern, an exclusive OR gate EOR, an output latch OLT, and a clock CLK. The timing generation circuit TMG etc. which generate | occur | produce. When the signature pattern is input from the LFSR, the comparator CMP compares the expected signature pattern stored in the read-only memory ROM with the output pattern of the LFSR by the exclusive OR gate EOR. And a low level signal, and if they do not match, a high level signal is output. This output is latched by the latch OLT and output as a signal ERR indicating good / bad.
Note that the operation principle of the LFSR is already known and described in various documents and the like, and detailed description thereof is omitted. However, optimization according to the logic circuit to be inspected can be performed according to the principle. In general logic LSIs incorporating a BIST to which LFSR is applied, optimization of LFSR is required for each logic circuit, which is troublesome in design, but the FPGA of this embodiment uses the same cell logic block CLB. Therefore, the optimization can be performed uniformly and the design burden is reduced. In addition, since a conventional LSI having a built-in BIST is a global BIST in which one BIST inspects all the LSI internal circuits, test sufficiency is not guaranteed with the generated test pattern. Since it is a local BIST provided in the cell logic block CLB, test sufficiency is also guaranteed.
FIG. 6 shows a specific example of the interface circuit 210 using the TAP shown in FIG.
As described above, the TAP is an interface and control circuit for the scan test and BIST circuit defined in the IEEE1149.1 standard, and is used to shift the test data from the input port to the output port. A data register 212 used for transmitting a specific signal to the circuit, a device ID register 213 for setting a chip-specific manufacturing identification number, and an instruction register 214 used for selecting a data register and controlling an internal test method , And a controller 215 for controlling the entire TAP circuit.
The data register 212 is an optional register. In addition, as the instructions set in the instruction register 214, four essential instructions and three optional instructions are prepared. The controller 215 receives a test mode select signal TMS, a test clock TCK, and a reset signal TRST for designating a test mode from three dedicated external terminals, and the registers 211 to 214 are based on these signals. And control signals for the selector circuits 216 to 218 are formed.
Further, the TAP is provided with an input terminal for test data TDI and an output terminal for test result data TDO. The input test data TDI is sent to the registers 211 to 214 or the internal scan path Iscan via the selector circuit 216. , Bscan. The contents of the registers 211 to 214 and the scan-out data from the internal circuit are output to the outside of the chip via the selector circuits 217 and 218. Further, a signal indicating the test result output from the BIST circuit is sent to the TAP via the selector circuits 217 and 218 according to the contents of the data register 212 and the instruction register 214. So that it can be output to the outside of the chip.
In the system LSI of the embodiment of FIG. 1, the self-test circuit built on the custom logic circuit (FPGA) 120 or the CPU 130 is regarded as a BIST circuit as will be described in detail later, and is used for the BIST circuit of the TAP. Using the signal input / output function, setting signals and data for self-test to the custom logic circuit (FPGA) 120 and the CPU 130 are input, and test results and data stored in the memory cells and the SRAM 140 in the FPGA 120 are input. It is configured to output. The function for the scan test of the TAP is not used in the system LSI of the embodiment of FIG.
In FIG. 6, “Iscan” means a test path for diagnosing the internal logic circuit using a shift register in which flip-flops constituting the internal logic circuit are connected in a chain as a scan path for test data. To do. “Bscan” uses a shift register in which a flip-flop provided in the signal input / output unit (interface circuit 190 in FIG. 1) is connected in a chain shape as a scan path, and is connected to other semiconductor integrated circuits. This means a test path for performing a connection state diagnosis (boundary scan test).
Next, an example of a test procedure when the test method according to the present invention is applied to the system LSI shown in FIG. 1 will be described with reference to FIGS. FIG. 7 shows an outline of the test procedure for the entire LSI, and FIGS. 8 to 11 show specific examples of the test procedure for each block constituting the LSI.
According to the test method of the present invention, as shown in FIG. 7, first, the FPGA 120 is inspected using the function of the cell logic block described above, and it is determined whether there is a defect. Is avoided (steps S1 to S3). Next, a test circuit (ALPG) for testing the SRAM 140 is constructed in a portion of the FPGA 120 excluding the defective portion, and the test of the SRAM 140 is executed (steps S4 and S5).
If no defective part is found in the SRAM 140, a test circuit (logic tester) for testing the custom logic circuit 110 and the CPU 130 is constructed in a portion of the FPGA 120 excluding the defective part, and the custom logic circuit 110 and A test of the CPU 130 is executed (steps S6 to S8). At this time, a test pattern or a test pattern generation program is stored using an SRAM that has already been inspected.
If no defect is found, a test circuit (ALPG) for testing the DRAMs 150 to 180 is constructed in the portion of the FPGA 120 excluding the defective part, and the tests of the DRAMs 150 to 180 are sequentially executed (steps). S9, S10). If a defective part is found, a repair program for repairing the defective bit using the redundancy circuit provided in the DRAMs 150 to 180 after being stored in the SRAM 140 or the external storage device. The program is read by the CPU 130 and the program is executed by the CPU 130 to perform bit relief (steps S11 and S12).
Thereafter, a part of the custom logic such as the user logic is formed in the part of the FPGA 120 excluding the defective part, and the system LSI is completed (step S13). In this step S13, first, the TAP 210 is set to the access mode of the connection information storage memory cell SMC in the FPGA 120, and then the defective portion is avoided by using the information indicating the defective portion obtained in step S1. The desired logic is configured by writing the data configuring the user logic into the memory cell SMC of the normal crosspoint switch in the FPGA 120.
FIG. 8 shows a more detailed procedure for self-verification of the custom logic circuit (FPGA) 120 in steps S1 to S3 in the flowchart of FIG.
When the power supply voltage is applied to the device (system LSI) of this embodiment, the logic gate circuits LG1 and LG2 of the cell logic block CLB constituting the FPGA 120 are activated, and if there is a defect, the output of the logic gate circuit LG1. Becomes low level, and its output state is stored in the connection information storing memory cell SMC (step S111).
Next, a test mode select signal TMS and a code to be set in the instruction register 214 are input to the TAP 210 as a test interface circuit using the tester 500, and the access mode of the connection information storage memory cell SMC in the FPGA 120 is input to the TAP 210. (Step S112). Subsequently, data indicating normality (a logic level opposite to a logic level indicating a defect state by self-verification of the cell logic block CLB) is written to the memory cell SMC (step S113). Next, the data in the memory cell SMC is read (step S114).
Then, it is determined which cell logic block CLB is defective by comparing the read data and the write data (step S115). Further, for example, by writing and reading data opposite to the write data, it is possible to detect a cross point switch CSW having a defect in the memory cell SMC itself.
Next, the tester 500 creates a map of the normal crosspoint switch CSW and the cell logic block CLB based on the determination result (step S116). The created map, that is, information indicating normality / abnormality of the crosspoint switch CSW and the cell logic block CLB is stored in a storage device or the like in the tester 500. Then, the HDL description of the SRAM tester (ALPG) constructed on the FPGA 120 is read from the database or the like and logic synthesis is performed by the tester 500 to avoid the defective crosspoint switch CSW and the cell logic block CLB based on the map. Then, data for constructing ALPG (Algorithmic Memory Pattern Generator) is generated (step S117). Then, the generated data is stored in a storage device or the like in the tester 500 (step S118). This data is data for selectively turning on the switch MOSFET Qsw of the normal crosspoint switch CSW according to the logic to be configured.
FIG. 9 shows a more detailed procedure of the inspection of the SRAM unit 140 in steps S4 to S5 in the flowchart of FIG.
In the inspection of the SRAM unit 140, first, a control signal is supplied from the tester 500 to the TAP 210, and the memory cell SMC for storing the cross point switch control information in the FPGA 120 is set to a selected state (step S121). Then, the data for constructing the ALPG stored in the storage device in step S118 is transferred to the selected memory cell SMC (step S122). As a result, a test circuit including an ALPG capable of generating a test pattern for inspecting the SRAM in the FPGA 120 is constructed. The structure of the ALPG constructed in the FPGA 120 and a specific method for constructing the ALPG will be described in detail later.
Next, a program for operating the ALPG to generate a test pattern is written into the memory circuit in the FPGA 120 by the tester 500 via the TAP 210 (step S123). This memory circuit is configured by the cell logic block CLB and the crosspoint switch CSW that constitute the FPGA 120 when the ALPG is constructed in step S122.
Subsequently, a control signal is supplied from the tester 500 to the TAP 210 to place the SRAM unit 140 in a selected state (step S124). Then, the ALPG in the FPGA 120 is activated, the test pattern generation program written in step S123 is executed to generate a test pattern, and the generated test pattern is transferred to the selected SRAM unit 140 via the bus 200 or the like. The supplied test is performed, and the test result is output to the outside (tester 500) via the TAP 210 (steps S125 and S126).
Then, the tester 500 determines whether or not there is a defect in the SRAM unit 140 from the output test result, and selects a non-defective product and a defective product (step S127). Note that the write data formed by the ALPG built in the FPGA 120 is output to the outside as an expected value, and the data read from the SRAM is also output to the outside, so that the expected value and the read data are output by an external tester. It is also possible to configure so as to determine whether or not there is a defect by comparing the two. Further, instead of storing the test pattern generation program in the memory circuit configured in the FPGA, an instruction code configuring the test pattern generation program may be sequentially input from the outside via the TAP.
FIG. 10 shows a more detailed procedure for checking the logic unit, that is, the custom logic unit 110 and the CPU unit 130 in steps S6 to S8 in the flowchart of FIG.
In the inspection of the logic units 110 and 130, first, the tester 500 creates data for constructing a logic tester in the FPGA 120 (step S131). At this time, there is data for building a logic tester by avoiding a faulty circuit using the map of the normal cell logic block CLB and the crosspoint switch CSW generated in step S116 of the FPGA self-verification flow of FIG. Created.
Next, a control signal is supplied from the tester 500 to the TAP 210 to select the memory cell SMC that stores the cross point switch control information in the FPGA 120 (step S132). Then, data for constructing the logic tester stored in the storage device in step S131 is transferred to the selected memory cell SMC (step S133). As a result, a test circuit capable of generating a test pattern for inspecting the logic unit in the FPGA 120 is constructed. At this time, a program for configuring the program memory in the FPGA and operating the logic tester may be transferred to the configured memory. The structure of the logic tester built in the FPGA 120 and the specific procedure for building the logic tester will be described in detail later.
Next, a control signal is supplied from the tester 500 to the TAP 210, and the SRAM unit 140 for which the flow inspection of FIG. 9 has been completed is selected (step S134). Then, a program for generating a test pattern for inspecting the custom logic unit 110 prepared in advance in the tester 500 is written in the SRAM 140 via the TAP 210 by the tester 500 (step S135). As in the case of a program for generating an SRAM test pattern, the logic circuit test pattern is generally longer than the memory test pattern when it is stored in the SRMA that has been inspected without being stored in the memory circuit in the FPGA. This is because a larger memory area is required.
Subsequently, the logic tester in the FPGA 120 is activated, and the test pattern generation program written in the SRAM 140 in step S135 is read and supplied to the custom logic unit 110 while generating a test pattern (step S136). Then, the output signal from the custom logic unit 110 is compared with the expected value, and the test result is output to the outside (tester 500) via the TAP 210 (step S137).
Then, the tester 500 determines whether there is a defect in the custom logic unit 140 from the output test result, and selects a non-defective product and a defective product (step S138).
Next, a test pattern generation program for inspecting the CPU 130 prepared in advance in the tester 500 is transferred to the SRAM 140 (step S139). Subsequently, the logic tester in the FPGA 120 is activated, and the test pattern generation program written in the SRAM 140 in step S135 is read and supplied to the CPU 130 while generating a test pattern (step S140). Then, the output signal from the CPU 130 is compared with the expected value, and the test result is output to the outside (tester 500) via the TAP 210 (step S141).
Then, the tester 500 determines whether or not there is a defect in the CPU 130 from the output test result, and selects a non-defective product and a defective product (step S142).
FIG. 11 shows a more detailed procedure of the inspection of the DRAM units 150 to 180 in steps S9 to S12 in the flowchart of FIG.
In the inspection of the DRAM units 150 to 180, first, the tester 500 creates data for constructing an ALPG (Algoromic Memory Pattern Generator) capable of generating a test pattern for inspecting the DRAM in the FPGA 120 (step S151). At this time, data that constructs an ALPG by avoiding a faulty circuit using the map of the normal cell logic block CLB and the crosspoint switch CSW generated in step S116 of the FPGA self-verification flow of FIG. 8 is created. Is done. Note that the ALPG for inspecting the DRAM is almost the same as the ALPG for inspecting the SRAM, except that a process for determining whether the refresh operation is normal or abnormal is added.
Next, a control signal is supplied from the tester 500 to the TAP 210 to select the memory cell SMC that stores the cross point switch control information in the FPGA 120 (step S152). Then, the data for constructing the ALPG created in step S151 is transferred to the selected memory cell SMC (step S153). As a result, a test circuit including an ALPG for inspecting the DRAM in the FPGA 120 is constructed. The structure of the ALPG constructed in the FPGA 120 and the specific method for constructing the ALPG are almost the same as the ALPG for inspecting the SRAM described in detail later.
Next, a program for operating the ALPG to generate a test pattern is written by the tester 500 to the memory circuit in the FPGA 120 via the TAP 210 (step S154). This memory circuit is configured by the cell logic block CLB and the crosspoint switch CSW that constitute the FPGA 120 when the ALPG is constructed in step S153. The test pattern generation program may be stored in the SRAM 140, or instruction codes may be sequentially input from the outside to the ALPG in the FPGA at the time of DRAM inspection.
Subsequently, a control signal is supplied from the tester 500 to the TAP 210 to place the SRAM unit 140 in a selected state (step S155), and the position of a defective bit detected in a DRAM test (step S159) described later is stored in the SRAM. The fail memory is configured (step S156). Next, a control signal is supplied from the tester 500 to the TAP 210 to set the CPU unit 130 in a selected state (step S157), and a repair program for repairing defective bits in the DRAM is transferred to the memory in the CPU 130 (step S158). . This relief program may be stored in the SRAM 140.
This relief program sets a replacement address in an address conversion circuit in a redundant circuit provided in association with the DRAM 150 according to a predetermined replacement algorithm, and sets a memory row or a memory column including a defective bit as a spare row or a spare row. It can be replaced with a line. Based on the test results, the redundant replacement algorithm itself, which selects the most appropriate spare memory row or spare memory column and replaces it with a defective bit, is known per se. Does not require a replacement algorithm.
Then, the control signal is supplied to the TAP 210 by the tester 500 to activate the DRAM 150 in the FPGA 120, and the test pattern generation program written in step S154 is executed to generate a test pattern. The test pattern is supplied to the selected DRAM unit 150 for testing, and the result, that is, the position of the defective bit is stored in the fail memory configured in the SRAM 140 (step S159). In the DRAM test in step S159, in addition to the read / write test similar to the SRAM test, a test is performed to determine whether a normal refresh operation is performed.
Next, a bit that replaces a memory row or memory column including a defective bit with a spare row or spare column based on the information of the defective bit stored in the fail memory (SRAM 140) by activating the CPU 130 to execute the relief program. Relief processing is performed (step S160). Thereafter, a test of whether or not relief has been normally performed is performed as a series of operations of the relief program (step S161). Then, the test result is output to the tester 500 outside the chip.
Then, the tester 500 determines whether or not there is a defect in the DRAM unit 150 from the output test result, and selects a non-defective product and a defective product (step S162). When the test of the DRAM unit 150 and the bit repair are completed, the process returns to step S159 again, and the test, bit repair, and determination of the test result are similarly performed for the other DRAM units 160, 170, and 180.
Next, the details of the ALPG built in the FPGA 120 when the SRAM 140 is inspected will be described. For example, as shown in FIG. 12, the ALPG is read from the instruction memory 411 in which a microprogram composed of a plurality of microinstruction groups described according to a predetermined test pattern generation algorithm is stored. A program counter 412 for designating the instruction address of the microinstruction, and an instruction code in the microinstruction read from the instruction memory 411 are decoded to control signals for the memory circuit unit and an internal circuit in the test circuit such as the program counter 412 A sequence control circuit 413 for generating a control signal, an address arithmetic circuit 414 for generating a test address according to a microinstruction read from the instruction memory 411, and a test data for generating test data and expected value data according to the read microinstruction The data generation circuit 415 compares the data read from the SRAM unit 140 by the test address with the expected value data generated by the test data generation circuit 415 and determines whether normal writing has been performed. The circuit 416 is configured.
The determination result in the comparison / determination circuit 416 is configured to be output to the outside of the chip via the TAP 210 as a determination signal F indicating data match / mismatch. Test pattern generation algorithms themselves are known, and applying them does not require a new algorithm especially for this embodiment.
The plurality of microinstructions stored in the instruction memory 411 can be described using an existing tester language or test language. A test pattern (address and data) is generated according to the predetermined algorithm defined by the plurality of instructions. The tester language is regarded as an effective instruction language for efficiently generating a test pattern including an address and data. The tester language is a language used in the tester industry. For example, a language compatible with the tester language of Advantest Corporation is used. This is because existing test pattern program data can be used. The language for describing the predetermined algorithm is not limited to the tester language, and may be any instruction language that can generate a test pattern including an address and data.
When the instruction memory 411 is composed of SRAM memory cells, it is necessary to load a program into the instruction memory prior to performing the test. When the FPGA 120 includes a non-volatile memory, the program is stored in a part of the address area of the non-volatile memory, and in response to the transition to the SRAM test mode, the address is stored from the address area in which the program is stored. It is preferable to load the program into the instruction memory 411. Instead of providing the instruction memory 411, continuous instruction codes may be sequentially input from an external tester to the ALPG sequence control unit 414 built in the FPGA 120 to generate an SRMA test pattern.
If the CPU 130 and the custom logic circuit 110 are provided in addition to the memory as in the system LSI of FIG. 1 to which this embodiment is applied, the memory circuit 140 (150 to 180) is provided as shown in FIG. Further, a variable bus configuration in which a signal switching circuit 230 including a dedicated bus 220 and change-over switches SW1 to SWn may be provided between the CPU 130 and the custom logic circuit 110 and the FPGA 120 on which the test circuit is constructed.
The signal CS for controlling the change-over switches SW1 to SWn in the signal change-over circuit 230 may be generated by an instruction in the ALPG and given to the switches SW1 to SWn when testing the memory circuit. Further, the switching control signal CS may be formed based on a test mode designation signal supplied from the outside.
The change-over switches SW1 to SWn are not only used for switching the connection between the memory circuit 140 and the CPU 130 and the custom logic circuit 110, or between the memory circuit 140 and the FPGA 120 on which the ALPG is constructed, but also the CPU 130 and the custom logic circuit. 110 and the FPGA 120 are preferably connected to each other.
FIG. 14 shows a configuration example of the instruction format of the microinstruction stored in the instruction memory 411. As described above, the format of this microinstruction is based on the tester language.
The microinstruction of this embodiment stores an address field MFa for storing a PC address indicating a jump address of an instruction used in the jump instruction, an operation code field MFb for storing a sequence control code, and the number of instruction repetitions. Operand field MFc, control field MFd for storing a control code for instructing output and reading / writing of an address and data, an address operation code field MFe for storing an address operation instruction code, and a data generation instruction code It consists of a data generation code field MFf and the like to be stored. The address field MFa is regarded as a field that defines the address of the instruction to be executed next.
A feature of the microinstruction as the tester language used in this embodiment is that two instructions are executed in parallel by specifying a test address operation and a data operation by one instruction.
FIG. 15 shows a configuration example of the sequence control circuit 413. The sequence control circuit 413 of this embodiment includes an instruction decoding control unit 430 including a decoder that decodes the control code of the operation code field MFb to form a control signal, and an incrementer for “+1” the value of the program counter 412 431, a multiplexer 432 that selects either the incrementer 431 or the jump address in the address field MFa and supplies it to the program counter 412, a plurality of index registers 433 that hold the number of repetitions in the operand field MFc, A decrementer 434 for decrementing the value of the index register 433, a working register 435 composed of a plurality of planes or ways holding the decremented value, and a jxd instruction described later (see Table 1). Data used in A flag 436 indicating the presence / absence of a transfer, a plurality of flags 437 indicating the presence / absence of transfer of operands used in the jindex instruction to the program counter 412, and a plurality of multiplexers selectively supplying the values of the registers 433 and 435 to the decrementer 434 438 and a demultiplexer 439 that distributes the value of the decrementer 434 to any plane of the working register 435.
Table 1 shows the types and contents of the opcodes used for the sequence control defined or described in the opcode field MFb in the microinstruction.
[Table 1]

In Table 1, the instruction indicated by “nop” is a no-operation instruction instructing to return the value of the program counter 412 to “+1” by the incrementer 431 and returning to the program counter 412, that is, any operation other than updating the program counter. It is an instruction for instructing to move to the next instruction without performing.
In addition, “jindex1” to “jindex4” are instructions prepared for turning a loop of instructions by jump. In the memory pattern test, the number of instructions, that is, the program length can be reduced by repeatedly executing the same instruction using the jump instruction (for example, by incrementing the address to the final address, There is a case where “1” is written to and read from all memory cells. In this embodiment, an index register 433 is provided so that the number of loops (jumps) can be set. In addition, four jump instructions, four index registers 433, and four working registers 435 are provided so that a plurality of types of determination methods can be executed.
Since each jump instruction has the same control content, the control operation by “jindex1” will be described below, and description of the other jump instructions “jindex2” to “jindex4” will be omitted. When the jindex1 instruction is read from the opcode field MFb, it is determined whether it is the first jindex1 instruction, and the determination result is reflected in the flag 437. Specifically, the flag jf1 = 0 is set for the first jindex1, and jf1 = 1 is set for the second and subsequent times.
When the jindex1 instruction is read when the flag jf1 = 0, the multiplexer 432 is controlled so that the PC address as the jump destination address in the address field MFa of the microinstruction is set in the program counter 412. Thereby, the execution sequence of the microinstruction is jumped to the address, and the flag jf1 is set to “1”. At the same time, the loop count defined in the operand field MFc is read into idx of the index register 433.
When the jindex1 instruction is read when the flag jf1 = 1, the PC address in the address field MFa of the microinstruction is set in the program counter 412. The number of loops in idx1 of the index register 433 is supplied to the decrementer 434 via the multiplexer 438 and decremented by “−1”. The decremented value is stored in idxw1 of the working register 435 via the demultiplexer 439. When idxw1 of the working register 435 becomes “0”, instead of setting the PC address in the address field MFa of the microinstruction to the program counter 412, the address of the program counter 412 is “+1” by the incrementer 431. Multiplexer 432 is controlled to return to program counter 412.
Therefore, if the jindex instruction is defined or described in the opcode field MFb of the microinstruction and the PC address as the jump destination address of the microinstruction is defined or described in the address field MFa, it is specified in the operand field MFc. The same index instruction is repeatedly executed as many times as the number of loops. Finally, the program counter 412 is incremented, and control is performed so as to proceed to the next microinstruction and exit from the loop.
The “jxd” instruction in Table 1 refers to the dflg in the flag 436, and is an instruction for manipulating the value of the program counter according to the value of the dflg flag. When the dflg flag in the flag 436 is a first value such as “0”, the “jxd” instruction transfers the operand to the program counter, causes the program to jump to the instruction at the jump address indicated by the operand, and , The dflg flag is set to a second value such as “1”. On the other hand, when the dflg flag is a second value such as “1”, the “jxd” instruction increments the value of the program counter, returns it to the program counter, and sets the dflg flag to “0”. Reset to a value of 1.
The “jmp” instruction is an instruction that transfers an operand to the program counter and instructs the program to jump to the instruction at the jump address indicated by the operand.
The “stop” instruction is a stop instruction for instructing to end the sequence control.
FIG. 16 shows a configuration example of the address calculation circuit 414.
The address calculation circuit 414 of this embodiment is roughly composed of an X address calculation unit 441 that generates an X address and a Y address calculation unit 442 that generates a Y address. Since the X address calculation unit 441 and the Y address calculation unit 442 have substantially the same configuration, the configuration of the X address calculation unit 441 will be described below, and the description of the configuration of the Y address calculation unit 442 will be omitted. In addition, by providing an impossible Z address calculation unit as necessary, partial pattern generation (partial pattern) can be performed.
The X address calculation unit 441 includes an initial value register Xhold that stores the initial value of the X address, zero setting means 443 that holds “0”, and a multiplexer MUX1 that selects either the initial value of the X address or “0”. And the base register Xbase that holds the selected initial value or “0”, the first arithmetic unit ALU1 that adds the value of the register Xbase, the operation result of the arithmetic unit ALU1, or “0” or a feedback value A second multiplexer MUX2 that selects the current value, a current register Xcurrent that holds the selected value, a second arithmetic unit ALU2 that adds or subtracts the value of the register Xcurrent, and the second arithmetic unit ALU2 or the first operation A third multiplexer MUX3 that selects one of the outputs of the ALU1 It is composed of a reversible inverter INV output.
The inverter INV is provided because a malfunction due to address signal switching noise may be tested in a memory pattern test, and an inverted signal of the address signal needs to be output at that time. By using this inverter INV, an inverted signal of the address signal in the test can be easily formed.
Although not particularly limited, in this embodiment, the X address generated by the arithmetic units ALU1 and ALU2 of the X address arithmetic unit 441 is directed to the Y address side, and the Y address generated by the Y address arithmetic unit 442 is the X address. Each of the third multiplexers MUX3 is configured so that it can output to the side.
Thereby, it can be used as a test circuit for any of a plurality of types of memories, for example, an address multiplex type memory and an address non-multiplex type memory. That is, by simply rewriting the microinstruction stored in the instruction memory 411, it is possible to generate or inspect a test pattern necessary for all the memories.
The difference between the X address computing unit 441 and the Y address computing unit 442 is that the first computing unit ALU1 of the Y address computing unit 442 is different from the first computing unit ALU1 of the Y address computing unit 442 when the first computing unit ALU1 of the X address computing unit 441 overflows. The borrow signal BR is supplied.
Table 2 shows the operation codes used for the Y address operation (base operation) in the first operation unit ALU1 of the Y address operation unit 442 described or defined in the operation code field MFe in the microinstruction. Types and their contents are shown.
[Table 2]

In Table 2, Ybase ← 0 is an instruction for instructing the value of the base register Ybase to be “0”. Ybase ← Yhold is an instruction for instructing to put the contents of the initial value register Yhold into the base register Ybase. Ybase ← Ybase + 1 is an instruction for instructing to increment (+1) the value of the base register Ybase and return to the register Ybase. Ybase ← Ybase + 1 (BR) means that if the value of the base register Xbase is not the maximum value, the value of Ybase is left as it is, and if the value of Xbase is the maximum value, the value of Ybase is incremented and returned to the register Ybase. It is a command to command. At this time, the borrow signal BR is supplied from the first arithmetic unit ALU1 to the second arithmetic unit ALU2.
Table 3 shows types of operation codes used for address calculation in the first arithmetic unit ALU1 of the X address calculation unit 441 and their contents.
Table 4 shows types of operation codes used for Y address calculation (current calculation) in the second arithmetic unit ALU2 of the Y address calculation unit 442 and the contents thereof.
Table 5 shows types of operation codes used for address calculation in the second arithmetic unit ALU2 of the X address calculation unit 441 and their contents.
In Table 4, the left column is an ALPG description written using a tester language, and the right column is a functional operation level description corresponding to the ALPG description. Functions can be expressed by describing this description according to the rules of the hardware description language (HDL description).
[Table 3]

[Table 4]

[Table 5]

FIG. 17 shows a configuration example of the test data generation circuit 415.
The test data generation circuit 415 of this embodiment includes an initial value register Thold that stores the initial value of write data or an expected value, an inverter INVERT1 that can invert the value of the initial value register Thold, and test data or expectation to be output. A base data register Tp that holds reference data of values, an arithmetic unit ALU having a bit shift function, and an inverter INVERT2 capable of inverting the output of the arithmetic unit ALU. In the above embodiment, the bit width is 18 bits. However, the test data circuit can be expanded as necessary to configure a desired bit width.
Table 6 shows the types and contents of control codes used for operation control in the test data generation circuit 415 defined or described in the data generation code field MFf in the microinstruction. In Table 6, the instructions represented by the same rules as the instructions in Tables 3 to 5 are almost the same instructions.
Tp ← Tp * 2 controls the register Tp and the arithmetic unit ALU, processes the 18-bit data in the register Tp by the arithmetic unit ALU, shifts the bit string by one bit to the MSB side or the LSB side, and returns it to the register Tp. It is an instruction. A test for writing data “1” to a memory cell bit by bit even if the memory unit is a type of memory in which data is read / written in units of 1 word or 1 byte by this instruction. Data can be generated relatively easily.
[Table 6]

Table 7 shows an example of a list of microinstructions related to a marching test, which is one of memory testing methods.
The marching test is performed as follows. Among all the bits of the memory cells in the memory array 1, one bit among them is selected in order. Data “0” is written in the selected memory cell. Thereafter, the written data “0” is read. Subsequently, among all the bits, one bit among them is selected in order. Data of “1” is written into the selected memory cell. Thereafter, the written data “1” is read out and compared with the expected value to determine the presence or absence of a defect.
As an example, a marching test assuming a memory array having an X address of 4 bits and a Y address of 4 bits and a storage capacity of 256 bits will be described.
[Table 7]

In Table 7, symbols W and R are control codes that indicate read / write with respect to the memory described or defined in the control field MFd. This control code is represented by a bit corresponding to W and a bit corresponding to R, that is, 2 bits. The number described in the “PC address” column indicates the jump address, and means that after executing the microinstruction, the program jumps to the microinstruction of the number described in the PC column and loops or jumps. is doing. Further, the symbols X ← Xbase and Y ← Ybase described in the column “control instruction etc.” mean that the values of the base registers Xbase and Ybase are output as the X address and the Y address, respectively.
FIG. 18 and FIG. 19 show an example of a processing flow according to the microinstruction list in Table 7 when a marching test of the SRAM 140 is performed by a test circuit (ALPG) comprising a control unit and a calculation unit of the microprogram control system. Show. Among these, FIG. 18 shows a flow of sequence control by the operation code and the operand in the microinstruction. FIG. 19 shows a flow of generating test addresses and test data (write data, expected value data) using address operation codes and data generation codes executed in parallel with the sequence control flow shown in FIG. . These processes can be executed by operating the sequence control circuit 413, the address operation circuit 414, and the data generation circuit 415 using the instruction codes described in Tables 1 to 6 above.
Hereinafter, the marching test procedure will be described with the steps of FIGS. 18 and 19 corresponding to each other.
When the address of the first instruction shown in the list of Table 7 is set to the program counter 412 from the outside as the start address, the flow of FIGS. 18 and 19 is started. First, when the first microinstruction in Table 7 is read from the instruction memory 411, since the operation code is “nop”, the sequence control circuit 413 does nothing and advances the program counter 412 by one (step S201). On the other hand, the address calculation circuit 414 and the data generation circuit 415 set the initial value “0” stored in the initial value registers Xhold, Yhold, and Told to the base registers Xbase, Ybase, and Tp, respectively (step S221).
Next, since the program counter 412 has been incremented in step S201, the second microinstruction in Table 7 is read. Since the operation code of the second microinstruction is “index1”, the sequence control circuit 413 sets the number of operand repetitions in the index register idx1 (step S202).
The first set value of the index register idx1 corresponds to the capacity (number of bytes or number of words) of the memory array 1. On the other hand, the address calculation circuit 414 outputs the values of the base registers Xbase and Ybase as the X address and the Y address by the operation codes X ← Xbase and Y ← Ybase, respectively. The value “0” of the register Tp is output from the data generation circuit 415. At this time, the control signal W (write) is output. As a result, in the memory array 1, the memory cell corresponding to the X and Y addresses output from the address arithmetic circuit 414 is selected and data “0” is written (step S222).
The sequence control circuit 413 decrements the value of the index register idx1 by the operation code “jindex1”, puts it in the working register idxw, and repeats the same instruction until it becomes “0” (steps S203 and S204).
Further, the address calculation circuit 414 increments the value of the base register Xbase, that is, the X address by the operation code Xbase ← Xbase + 1, and increments the Y address when the base register Xbase reaches the maximum value by Ybase ← Ybase + 1 (BR). Since the first set value of the index register idx1 is the same as the capacity of the memory array 1, data “0” is sequentially written in all the memory cells in the memory array 1 by repeating the above operation (step S223, step S223). S224).
When the value of the working register idxw becomes “0”, the sequence control circuit 413 increments the value of the program counter 412 and reads the third microinstruction in Table 7. Since the operation code is “nop”, the sequence control circuit 413 does nothing and advances the program counter 412 by one (step S205).
On the other hand, the address calculation circuit 414 increments the X and Y addresses according to the operation code of the third microinstruction and outputs the values stored in the base registers Xbase and Ybase as the X address and Y address, respectively. At this time, the values of the base registers Xbase and Ybase have returned to “0”. At this time, the data generation circuit 415 outputs “0”. Further, a control signal R (readout) is output according to the control code of the control field MFd. As a result, the data at the address is read and compared with the expected value data “0” (steps S225 and S226).
Next, since the program counter 412 is incremented in step S205, the fourth microinstruction in Table 7 is read. Since the operation code of the fourth microinstruction is “index1”, the sequence control circuit 413 sets the number of operand repetitions in the index register idx1 (step S206). The first set value of the index register idx1 corresponds to the capacity (number of bytes or number of words) of the memory array 1. However, the jind1 instruction code of the fourth instruction has a PC address (jump address) different from the jindex1 instruction code of the second instruction, and therefore returns to the third instruction (opcode is “nop”) after execution.
On the other hand, the address calculation circuit 414 outputs the values of the base registers Xbase and Ybase as the X address and the Y address by the operation codes X ← Xbase and Y ← Ybase, respectively. In addition, data “1” obtained by inverting the value “0” of the register Tp is output from the data generation circuit 415 by the data generation code Dinvert. At this time, the control signal W (write) is output. As a result, in the memory array 1, the data “1” is written into the output memory cell at the X and Y addresses (step S227).
The sequence control circuit 413 decrements the value of the index register idx1 by the operation code “jindex1”, puts it in the working register idxw, and returns to the “nop” instruction and repeats it until it becomes “0” (steps S207 and S208). Further, the address calculation circuit 414 increments the value of the base register Xbase, that is, the X address by the operation code Xbase ← Xbase + 1, and increments the Y address when the base register Xbase reaches the maximum value by Ybase ← Ybase + 1 (BX). Since the first set value of the index register idx1 is the same as the capacity of the memory array 1, all the memory cells in the memory array 1 are sequentially read and compared with the expected value by the above procedure. The operation of writing “1” to the address is repeated (steps S227 and S228).
Next, the fifth microinstruction in Table 7 is read. Since the operation code of the fifth microinstruction is “index1”, the sequence control circuit 413 sets the number of operand repetitions in the index register idx1 (step S209). The first set value of the index register idx1 corresponds to the capacity (number of bytes or number of words) of the memory array 1. This fifth jindex1 instruction code has the same PC address as the second jindex1 instruction code, and is an instruction that repeats the same instruction. On the other hand, the address calculation circuit 414 outputs the values of the base registers Xbase and Ybase as the X address and the Y address by the operation codes X ← Xbase and Y ← Ybase, respectively. In addition, data “1” obtained by inverting the value “0” of the register Tp is output from the data generation circuit 415 by the data generation code Dinvert. At this time, a control signal R (write) is output. As a result, in the memory array 1, data is read from the memory cell designated by the outputted X and Y addresses (step S229).
The sequence control circuit 413 decrements the value of the index register idx1 by the operation code “jindex1”, puts it in the working register idxw, and repeats the “jindex1” instruction until it becomes “0” (steps S210 and S11). Further, the address calculation circuit 414 increments the value of the base register Xbase, that is, the X address by the operation code Xbase ← Xbase + 1, and increments the Y address when the base register Xbase reaches the maximum value by Ybase ← Ybase + 1 (BR). Since the first set value of the index register idx1 is the same as the capacity of the memory array 1, all the memory cells in the memory array 1 are sequentially read out by repeating the above operation, and the expected value “1” is obtained. They are compared (steps S230 and S231).
Next, the sixth microinstruction in Table 7 is read. Since the operation code of the sixth microinstruction is “jxd”, the sequence control circuit 413 jumps to the jump address indicated by the PC address in the address field MFc. In this embodiment, the process returns to the second instruction “index1” in Table 7. When the jindex1 instruction is read again, the flag dflg is set to “1”. Thus, in the second round of the sequencing process, “YES” is determined in step S212 in FIG. 18, and the marching test is terminated.
On the other hand, when the microinstruction list for the second round is executed, in steps S222 to S231 in FIG. 19, the data generation circuit 414 writes the write data and the expected value data as “1” continuously to all the bits. The written data is read bit by bit and the inverted data “0” is written therein, and then all bits are continuously read. In the flow of FIG. 19, in step S232, it is determined whether or not data writing / reading reverse to the first round in steps S222 to S231 has been completed (reverse data end determination). ing. The back data generation for performing the inspection using the back data is generated by controlling the INVERT and dflg of the Thold in FIG.
As described above, the control according to the flow of FIG. 18 and FIG. 19 uses the instruction codes described in Tables 1 to 6 to change the microinstructions in the instruction memory 411 as shown in the following instruction list in Table 7. The marching test can be executed with only six micro instructions.
Further, in the test circuit (ALPG) of the embodiment, by using the instruction codes described in Tables 1 to 6, “0” or “1” is set in all the memory cells in addition to the marching test. An all “0” determination test or an all “1” determination test for checking whether writing is possible, or so-called N for writing “1” in a certain bit and checking all other bits for erroneous writing. ² A square pattern test (or galloping test) or the like can also be performed.
Table 8 shows N ² A microinstruction list for a power pattern test is shown. Note that ixd is a command for generating a back test pattern by controlling the inverter INVERT controlled by the flag dflg under the initial value register Thold. When the flag dflg is 0, the value of the initial value register Thold is directly stored in the register Tp. When the flag dflg is 1, the opposite pattern is set in the register Tp.
[Table 8]

In the above embodiment, the value initially set in the program counter 412 is changed to the instruction address of the first microinstruction shown in Table 7 or Table 8, so that the marching test or N ² A square pattern test can be started.
Next, details of a logic tester built in the FPGA 120 when the custom logic unit 110 and the CPU 130 are inspected will be described.
The logic tester has a configuration similar to the ALPG shown in FIG. 12 that generates the test pattern of the memory. For example, as shown in FIG. 20, a plurality of logic testers described according to a predetermined test pattern generation algorithm are used. An instruction memory 411 storing a microprogram consisting of a group of microinstructions, a program counter 412 for designating a microinstruction to be read from the instruction memory 411, and an instruction code in the microinstruction read out from the instruction memory 411 are decoded. An instruction decoding control circuit 430 that forms a control signal for the circuits in the control unit 400 such as the program counter 412, a timing generation unit 420 that forms a timing control signal based on the reference clock φ 0, and a timing setting bit MFd (TS in the microinstruction Bit) Data register set 417 for outputting control data to the grayed generator 420, and a like decoder 418 to read the control data by decoding the timing setting bits MFd in microinstruction (TS bits) from the data register set 417.
In addition, in the case of a circuit whose function is specified among the logic circuits to be tested (for example, ALU: Arithmetic Logic Unit), an appropriate test pattern forming method is often already established. By using the test pattern assets, it is possible to generate an efficient test pattern. As for the combinational logic circuit, an efficient test pattern generation method called a D-algorithm based on the fault assumption method and the idea of a single fault that one circuit has one fault is known. By using this method, a microprogram for generating a test pattern can be shortened, and an increase in the capacity of the instruction memory 411 can be suppressed to a realizable level.
In this embodiment, although not particularly limited, the timing setting bit TS decoded by the decoder 418 is composed of 2 bits, and the data register set 417 stores seven control data. One of these control data is data “RATE” that defines a test cycle, and the remaining six control data give the output timing of a high level or low level signal for each signal line of the tester dedicated bus 2. The control data “ACLK1” and “ACLK2” of the type, the two types of control data “BCLK1” and “BCLK2” for giving rise timing of the pulse signal, and the comparison output timing of the fall timing and expected value of the pulse signal are given. Two types of control data “CCLK1” and “CCLK2”.
When each of these control data is supplied to the timing generator 420, a signal RATE having a predetermined timing is supplied to the program counter 412 with respect to the control data RATE, and the microinstruction code is fetched from the instruction memory 411. Is called. When “ACLK1” to “CCLK2” are supplied to the timing generator 420 as control data, a clock corresponding to the control code is output from the timing clocks ACLK1 to CCLK2 to the signal generator / comparator 300. Connection and selection for use of each clock are appropriately performed as necessary.
Further, the program counter 412 selects either the incrementer 421 for incrementing the value of the program counter 412 to “+1” or the jump address in the incrementer 421 or the address field MFa. Multiplexer 422 to be supplied to, index register 423 for holding the number of repetitions in the operand field MFc, decrementer 424 for decrementing the value of the index register 423, and holding the value decremented by “−1” A working register 425, a flag 427 indicating whether or not an operand used in a predetermined instruction is transferred to the program counter 412, a multiplexer 428 for selectively supplying the values of the registers 423 and 425 to the decrementer 424, Such a demultiplexer 429 is provided to distribute the value of Rimenta 424 to one of the plane of the working register 425.
In this logic tester, an operand field MFc for storing the number of instruction repetitions is provided in the microinstruction code, and an index register 423 for holding the number of repetitions is provided. Therefore, when the same test signal is repeatedly generated, The number of necessary microinstructions can be reduced and the microprogram can be shortened. In this embodiment, since the index register 423, working register 425, and flag 427 are provided with a plurality of planes (four in the figure), sub-loop processing within a certain loop processing, and further sub-loop processing within the sub-loop processing. Can be easily executed, and the microprogram can be shortened.
FIG. 21 shows an embodiment of the signal forming / comparing unit 300. In the circuit of FIG. 21, only the driver / comparator circuit corresponding to one of the signal lines constituting the tester dedicated bus 220 is representatively shown, but actually the tester dedicated bus 220 is configured. 21 is provided as many as the number of signal lines.
As shown in FIG. 21, the driver / comparator circuit of this embodiment compares a driver circuit (signal forming circuit) 340 that forms a signal to be output to a tester dedicated bus with a signal on the tester dedicated bus and an expected value signal. Thus, the comparator circuit (comparing circuit) 350 for comparing the coincidence / non-coincidence and the switching circuit 360 for switching the driver circuit 340 and the comparator circuit 350 are configured. The switching circuit 360 includes a transmission gate TG1 provided between the driver circuit 340 and the input / output node Nio, and a transmission gate TG2 provided between the input / output node Nio and the comparator circuit 50. The control unit One of them is opened according to the input / output control bit I / O supplied from 400, and the other is shut off.
The driver circuit 340 includes an edge-triggered flip-flop 341 that captures and holds the input / output control bit TP by the timing clock ACLKi supplied from the timing generator 420, and timing clocks BCLKi and CCLKi supplied from the timing generator 420. An OR gate 342 for taking a logical sum, a J / K flip-flop 343 having the output of the OR gate 342 and the output of the edge trigger flip-flop 341 as input signals, the output of the J / K flip-flop 343, and a control unit An AND gate 344 having the input / output control bit CONT supplied from 400 as an input signal, and an AND having the output of the edge trigger flip-flop 341 and the input / output control bit CONT supplied from the controller 400 as input signals Gate 45, and a driver 346 that drives the tester en by the output of these AND gates 344 and 345.
On the other hand, the comparator circuit 350 includes an AND gate 351 having the timing clock CCLKi supplied from the timing generator 420 and the input / output control bit CONT supplied from the controller 400 as input signals, and the output of the D-type flip-flop 341. An exclusive OR gate 352 having (expected value) and a signal on the tester dedicated bus supplied via the transmission gate TG2 as input signals, and outputs from the exclusive OR gate 352 and the AND gate 351 as input signals. An AND gate 353 and a flip-flop 354 that latches the output of the AND gate 353 are configured, and a signal obtained by logically summing the outputs of all the comparator circuits 350 is output as a total fail signal TFL. . The input / output control bits I / O, TP, and CONT correspond to the control signals.
As shown in FIG. 20, the microinstruction in the test circuit of this embodiment stores an address field MFa in which a PC address indicating a jump address of an instruction used in the jump instruction is stored, and a sequence control code. An operation code field MFb, an operand field MFc in which the number of instruction repetitions and the like are stored, and a timing setting field MFd in which a timing setting bit TS for reading a control signal for the timing generator 420 from the data register set 14 is stored. The input / output control field MFe in which the input / output control bits of the signal forming / comparing unit 300 are stored.
The timing setting bit TS stored in the timing setting field MFd is 2 bits in this embodiment as described above, but 3 or more bits may be provided. The input / output control bits stored in the input / output control field MFe correspond to the three signal lines of the tester dedicated bus 220, ie, 3 bits of driver bit TP, I / O bit, and control bit CONT. Is one set, and only n sets are provided. Among these bits, the I / O bit is a control bit for designating whether it is an input or an output. When it is “1”, the transmission gate TG1 is opened and TG2 is shut off, and the driver output signal corresponds to the tester dedicated bus 220. When it is “0”, the transmission gate TG 1 is shut off and TG 2 is opened to input the signal on the corresponding signal line of the tester dedicated bus 220 to the comparison gate 352. The driver bit TP and the control bit CONT specify whether the output is high output or low output, positive pulse or negative pulse output, input invalid state, or output high impedance state according to the combination.
Table 9 shows the relationship between the input / output control bits TP, I / O, CONT and the operation state of the signal forming / comparing unit 300.
[Table 9]

As shown in Table 9, when the input / output control bits TP, I / O, and CONT are “111”, the driver circuit 340 outputs a high level signal, and when it is “011”, the driver circuit 340 A low level signal is output. When “110”, the driver circuit 340 outputs a positive pulse signal, and when “110”, the driver circuit 340 outputs a negative pulse signal. When the input / output control bits TP, I / O, and CONT are “101”, the comparator circuit 350 expects a high level input signal, and when it is “001”, the comparator circuit 350 expects a low level input signal. When “100”, the control is performed so as to invalidate the input signal.
In the signal forming / comparing unit 300 of this embodiment, the state where the control bits TP, I / O, and CONT are “000” has no meaning. However, when the control bits TP, I / O, and CONT are “000”, for example, the transmission gate TG1 is closed and TG2 is opened, and the exclusive OR gate 352 operates at two levels between the high level and the low level. The signal forming / comparing unit 300 is configured so that the state (high impedance state) in which the potential of the input / output node Nio connected to the tester dedicated bus 220 exists between the two levels as a Schmitt circuit to be compared can be compared. Is also possible.
FIG. 22 shows an example of the timing clocks ACLK1 to CCLK2 supplied from the timing generation unit 420 and signals output from the signal formation / comparison unit 300 onto the tester dedicated bus 220 in the above embodiment. 22, (a) is a reference clock φ0 supplied from the outside, (b) to (g) are waveforms of timing clocks ACLK1 to CCLK2, and (h) is “1” as an output test signal in Table 9. The waveform of the output signal of the terminal which is designated and ACLK1 is selected as the clock is shown. Further, (i) shows the waveform of the output signal of a terminal in which “0” is designated as the output test signal in Table 9 and ACLK2 is selected as the clock. Further, (j) shows a waveform of an output signal at a terminal in which “P” is designated as the output test signal in Table 9 and BCLK1 and CCLK1 are selected as clocks. Further, (k) shows the waveform of the output signal at the terminal where “N” is designated as the output test signal in Table 9 and BCLK2 and CCLK2 are selected as the clock.
As can be seen from FIG. 22, a high-level signal as shown in FIG. 22 (h) is output from the terminal where the input / output control bits TP, I / O, CONT are set to “111” and the clock ACLK1 is designated according to the clock ACLK1. 22 is output from a terminal to which TP, I / O, CONT are set to “011” and the clock ACLK2 is designated in accordance with the clock ACLK2, and TP, I / O, From the terminal where CONT is set to “110” and the clocks ACLK1, BCLK1, and CCLK1 are designated, a positive pulse as shown in FIG. 22 (j) having BCLK1 and CCLK1 as an edge is output according to the data set by the clock ACLK1. TP, I / O, CONT are set to “010” and clocks ACLK2, BCLK2, CCLK2 Negative pulse as shown in FIG. 22, the edge of BCLK2, CCLK2 accordance with the data which is set by the clock ACLK2 from the designated terminal (k) is output.
Further, although not shown in the figure, at the terminal where the input / output control bits TP, I / O, CONT are set to “101” and the clock CCLK1 is designated, the expected value is set to the high level and the clock CCLK1 in FIG. Comparison is performed, and at the terminals where TP, I / O, and CONT are set to “001” and the clock CCLK2 is designated, the expected value is the low level, and the comparison is performed using the clock CCLK2 of FIG. Note that the selection of the clock is not limited to the above, and can be any combination.
As described above, in the above-described embodiment, a signal indicating whether the circuit is normal or abnormal can be output for each basic logic cell consisting of a plurality of basic logic cells (cell logic blocks) on the semiconductor chip, and any logic can be output. A variable logic circuit such as a configurable FPGA (Field Programmable Gate Array) is mounted. Thereby, it is possible to know that there is a defective part and its position in the variable logic circuit (FPGA) without using an external tester. In addition to improving the yield by avoiding defective parts and configuring the logic, a failure of the test circuit itself occurs when a test circuit is built using this variable logic circuit (FPGA) to test other internal circuits. It is possible to avoid outputting an erroneous test result due to.
The semiconductor integrated circuit testing method according to the present invention includes a variable logic circuit (FPGA) capable of outputting a signal indicating whether the circuit is normal or abnormal and capable of configuring any logic, and a memory circuit capable of reading and writing. In a built-in semiconductor integrated circuit, first, a self-test is performed by the above-described variable logic circuit (FPGA), and only a basic logic cell excluding the defective portion is obtained according to a predetermined algorithm using information indicating the defective portion obtained as a result. A memory test circuit for inspecting the circuit was constructed to inspect the memory circuit. As a result, it is possible to test the memory circuit inside the LSI without using a high-function external tester.
Further, another test method for a semiconductor integrated circuit according to the present invention includes a custom logic circuit such as a user logic circuit in which the semiconductor integrated circuit constitutes a CPU (Central Processing Unit) and a logic function requested by a user together with a memory circuit. In such a case, a test circuit (logic tester) for generating a test signal and an expected value signal for the CPU and custom logic circuit in accordance with a predetermined algorithm is constructed in the FPGA, and the test is already determined to be normal by the test. The test circuit or test pattern generation program is stored in the memory circuit, and the test circuit built in the FPGA is activated to test the CPU and custom logic circuit. As a result, it is possible to test the CPU and logic circuit in the LSI without using a high-function external tester.
Furthermore, in the method of manufacturing a semiconductor integrated circuit according to the present invention, first, a self-test is performed by the variable logic circuit, and the defective portion is removed from the variable logic circuit by using information obtained as a result of the self-test. Constructing a memory test circuit for inspecting the first memory circuit according to a predetermined algorithm using only the basic logic cell, inspecting the first memory circuit,
Next, in the variable logic circuit, a logic test circuit for inspecting a custom logic circuit or a central processing unit according to a predetermined algorithm with only basic logic cells excluding defective portions is constructed and tested in the first memory circuit. Store the pattern or test pattern generation program, inspect the custom logic circuit or central processing unit,
After that, in the variable logic circuit, a memory test circuit for inspecting the second memory circuit according to a predetermined algorithm with only basic logic cells excluding defective portions is constructed, and the second memory circuit is inspected,
Thereafter, based on the inspection result of the second memory circuit, a bit relief process is performed in which a defective bit in the second memory circuit is replaced with a spare bit using a redundant circuit associated with the second memory circuit. Thus, the bit repair of the memory circuit can be automatically performed, and the yield and productivity of the semiconductor integrated circuit can be improved.
In the method of manufacturing a semiconductor integrated circuit according to the present invention, a desired logic is configured in the variable logic circuit after the bit relief process of the second memory circuit. Since no useless circuit remains, there is an effect that the hardware overhead associated with providing the test circuit inside the LSI can be reduced.
In the semiconductor integrated circuit manufacturing method according to the present invention, the information indicating the position of the defective bit is stored in the first memory circuit when the second memory circuit is inspected. There is an effect that failure analysis can be easily performed by reading information stored in one memory circuit.
The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above embodiment, the output state of the exclusive OR gate circuit LG2 that detects and outputs whether or not the circuit in the cell logic block CLB is normal is stored in the memory cell SMC in the crosspoint switch circuit CSW. However, it may be configured to output to the outside of the LSI chip.
In the above embodiment, the fail memory for storing the position of the defective bit when the DRAMs 150 to 180 are tested is configured in the SRAM 140. However, the fail memory may be provided in an external tester. Good. Furthermore, in the above embodiment, TAP defined by IEEE is used as a test interface circuit. However, the present invention is not limited to this, and a dedicated interface circuit suitable for this embodiment is separately designed and provided. You may do it.
Industrial applicability
In the above description, the self-verification method in a system LSI having a CPU, SRAM, DRAM, and custom logic circuit, which is a field of use that is based on the invention made by the present inventor, has been described as an example. However, the present invention is not limited thereto, and a logic LSI including a CPU and SRAM and a custom logic circuit, a logic LSI including a CPU and a DRAM and a custom logic circuit, a logic LSI including a CPU and a custom logic circuit, an SRAM and a DRAM, and a custom logic circuit The present invention can also be used in a logic integrated circuit or a semiconductor integrated circuit in which an analog circuit is mounted in addition to the digital circuit as described above.
[Brief description of the drawings]
FIG. 1 is a block diagram showing the overall configuration of an embodiment of a logic LSI to which the present invention is applied.
FIG. 2 is a circuit configuration diagram showing one embodiment of a variable logic circuit (FPGA) provided in a logic LSI to which the present invention is applied.
FIG. 3 is a block diagram showing a specific example of the crosspoint switch constituting the FPGA.
FIG. 4 is a logic circuit diagram and a conceptual diagram showing a specific example of a cell logic block constituting the FPGA.
FIG. 5 is a logic circuit diagram showing another example of the cell logic block constituting the FPGA.
FIG. 6 is a block diagram showing a configuration example of a test interface circuit provided in a logic LSI to which the present invention is applied.
FIG. 7 is a flowchart showing an example of an internal circuit inspection procedure in the logic LSI to which the present invention is applied.
FIG. 8 is a flowchart showing specific contents of the inspection procedure of the FPGA unit in steps S1 to S3 of the flowchart of FIG.
FIG. 9 is a flowchart showing specific contents of the inspection procedure of the SRAM unit in steps S4 to S5 of the flowchart of FIG.
FIG. 10 is a flowchart showing specific contents of the inspection procedure of the custom logic circuit and the CPU unit in steps S6 to S8 of the flowchart of FIG.
FIG. 11 is a flowchart showing specific contents of the inspection procedure of the DRAM unit in steps S9 to S12 of the flowchart of FIG.
FIG. 12 is a block diagram showing the configuration of the ALPG built in the FPGA.
FIG. 13 is a block diagram illustrating a configuration example of a bus when testing a memory circuit using ALPG.
FIG. 14 is an explanatory diagram showing a configuration example of an instruction format of a microinstruction stored in the instruction memory of the ALPG.
FIG. 15 is a block diagram illustrating a configuration example of an ALPG sequence control unit.
FIG. 16 is a block diagram illustrating a configuration example of an ALPG address calculation unit.
FIG. 17 is a block diagram illustrating a configuration example of an ALPG test data generation calculation unit.
FIG. 18 is a flowchart showing an example of a sequence control procedure using an opcode and operand of a microinstruction when the memory circuit is inspected by ALPG.
FIG. 19 is a flowchart showing an example of a procedure for generating and outputting a test address and data using an operation code and data generation code of a microinstruction when the memory circuit is inspected by ALPG.
FIG. 20 is a block diagram illustrating a configuration example of a logic tester built in the FPGA.
FIG. 21 is a logic circuit diagram showing a specific example of signal forming / comparing means in the logic tester.
FIG. 22 is a waveform diagram showing an example of a test signal waveform formed by a logic tester.

Claims (11)

A plurality of basic logics which can output a signal indicating whether each basic logic cell is normal or abnormal and each output a normal signal on the semiconductor chip. A semiconductor integrated circuit in which a variable logic circuit capable of configuring arbitrary logic in a cell is mounted,
The variable logic circuit includes a basic logic cell comprising a two-line line logic circuit capable of outputting a complementary signal and a determination means for comparing the output signals of the two-line line logic circuit to determine the presence or absence of an abnormality, and A plurality of variable switch circuits capable of switching the connection of signal lines between basic logic cells, and arbitrary logic can be configured by switching the connection by the variable switch circuit, and output from the two-line line logic circuit Is supplied to a two-line line logic circuit in another basic logic cell, and the output signal of the determination means is output from each basic logic cell as a signal indicating whether the circuit is normal or abnormal. ,
The variable switch circuit includes a switch element capable of disconnecting and connecting signal lines intersecting each other, and a readable / writable storage element for storing information for controlling the state of the switch element, and is output from the determination means. A semiconductor integrated circuit characterized in that a signal indicating whether the circuit is normal or abnormal is stored in the memory element. A semiconductor integrated circuit comprising at least a plurality of logic cells and capable of outputting a signal indicating whether the circuit is normal or abnormal for each logic cell and including a variable logic circuit capable of configuring arbitrary logic and a readable / writable memory circuit An inspection method,
A self-test is performed by the variable logic circuit, and a predetermined test signal and an expected value signal are generated in a normal logic cell according to a predetermined algorithm in the variable logic circuit by using information indicating a defective portion obtained as a result. to the test signal is supplied to the memory circuit, the memory test to output the result notes to form a signal indicating the failure when the output signals obtained does not match by comparing the expected value signal from Li circuit outside the chip A method for inspecting a semiconductor integrated circuit, wherein a circuit is configured to inspect the memory circuit.   3. The semiconductor integrated circuit inspection method according to claim 2, wherein the memory circuit is a static random access memory.   3. The semiconductor integrated circuit inspection method according to claim 2, wherein the memory circuit is a dynamic random access memory. A variable logic circuit that can output a signal indicating whether the circuit is normal or abnormal for each logic cell and that can configure any logic, a read / write memory circuit, a custom logic circuit, or a central circuit A method for inspecting a semiconductor integrated circuit including a processing unit,
A self-test is performed by the variable logic circuit, and a predetermined test signal and an expected value are generated in a normal logic cell in accordance with a predetermined algorithm in the variable logic circuit using information indicating a defective portion obtained as a result. Te a memory test circuit that outputs a test signal to form a signal indicating the failure when they do not match by comparing the expected value signal and the output signal obtained from the supply to the memory circuit the result memory circuit outside the chip And inspecting the memory circuit with the memory test circuit,
Next, in the variable logic circuit, a predetermined test signal and an expected value signal are generated in accordance with a predetermined algorithm in a normal logic cell, and the test signal is supplied to the custom logic circuit or the central processing unit. As a result, the custom logic circuit Or, if the output signal obtained from the central processing unit and the expected value signal are not matched, a logic test circuit is formed that forms a signal indicating a failure and outputs the signal to the outside of the chip. A semiconductor integrated circuit inspection method characterized by storing a test pattern generation program and activating the logic test circuit to inspect the custom logic circuit or the central processing unit.   6. The semiconductor integrated circuit inspection method according to claim 5, wherein the memory circuit is a static random access memory.   6. The method of testing a semiconductor integrated circuit according to claim 5, wherein the memory circuit is a dynamic random access memory. A variable logic circuit capable of outputting a signal indicating whether the circuit is normal or abnormal for each logic cell and comprising any logic; a first memory circuit not including a redundant circuit; A method of manufacturing a semiconductor integrated circuit including a second memory circuit having a redundant circuit and a custom logic circuit or a central processing unit,
A self-test is performed by the variable logic circuit, and a predetermined test signal and an expected value signal are generated in a normal logic cell according to a predetermined algorithm in the variable logic circuit by using information indicating a defective portion obtained as a result. Then, a test signal is supplied to the first memory circuit, and as a result, an output signal obtained from the first memory circuit is compared with an expected value, and a signal indicating a defect is formed and output to the outside of the chip. A memory test circuit for inspecting the first memory circuit by the memory test circuit,
Next, in the variable logic circuit, a predetermined test signal and an expected value signal are generated in accordance with a predetermined algorithm in a normal logic cell, and the test signal is supplied to the custom logic circuit or the central processing unit. As a result, the custom logic circuit Alternatively, when the output signal obtained from the central processing unit and the expected value signal are not matched, a logic test circuit for forming a signal indicating a defect and outputting the signal to the outside of the chip is constructed, and the first memory circuit is provided. Store the test pattern or test pattern generation program, start the logic test circuit and inspect the custom logic circuit or central processing unit,
Thereafter, a predetermined test signal and an expected value signal are generated in a normal logic cell in the variable logic circuit according to a predetermined algorithm, and the test signal is supplied to the second memory circuit. As a result, the second memory circuit is generated. When the output signal obtained from the above and the expected value signal are not matched, a memory test circuit for forming a signal indicating a failure and outputting the signal to the outside of the chip is constructed, and the second memory circuit is inspected,
Thereafter, based on the inspection result of the second memory circuit, a bit relief process is performed in which a defective bit in the second memory circuit is replaced with a spare bit using a redundant circuit associated with the second memory circuit. A method of manufacturing a semiconductor integrated circuit, wherein   9. The semiconductor integrated circuit manufacturing method according to claim 8, wherein the first memory circuit is a static random access memory, and the second memory circuit is a dynamic random access memory. Method.   10. The method of manufacturing a semiconductor integrated circuit according to claim 8, wherein a desired logic is configured in the variable logic circuit after the bit relief processing of the second memory circuit.   11. The semiconductor integrated circuit according to claim 8, 9 or 10, wherein information indicating a position of a defective bit is stored in the first memory circuit when the second memory circuit is inspected. Manufacturing method.

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