JP4133637B2 - Electromagnetic wave shielding sheet for semiconductor element adhesion and semiconductor device - Google Patents

Electromagnetic wave shielding sheet for semiconductor element adhesion and semiconductor device Download PDF

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JP4133637B2
JP4133637B2 JP2003196102A JP2003196102A JP4133637B2 JP 4133637 B2 JP4133637 B2 JP 4133637B2 JP 2003196102 A JP2003196102 A JP 2003196102A JP 2003196102 A JP2003196102 A JP 2003196102A JP 4133637 B2 JP4133637 B2 JP 4133637B2
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semiconductor element
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electromagnetic wave
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浩二 續山
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Mitsui Chemicals Inc
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Description

【０００１】
【発明の属する技術分野】
本発明は、積層された半導体素子相互間の電気信号の干渉を防止し、また半導体素子に混入するノイズを低減するための半導体素子接着用電磁波遮断シート、半導体装置および半導体素子接着用電磁波遮断シートの製造方法に関する。
【０００２】
【従来の技術】
近年、電子機器の小形化の要求に伴い、表面高密度実装にさらに拍車がかかり、複数の半導体素子を同一パッケージ内に積層したいわゆるスタックパッケージの利用が増加している（特許文献１参照）。
【０００３】
電子機器のディジタル化、高速化、高周波化が進むにつれて、ノイズ問題が重要性を増してきている。スタックパケージにおいては特に、半導体素子を近接して積層するため、従来のような半導体素子外部から到来するノイズの問題以外に、積層された素子間の信号干渉が発生するという問題がある。先行技術では、このようなスタックパケージにおける素子間の信号干渉を抑制できる対策材料は提供されていない。
【０００４】
小型のＣＳＰ（Chip Size Package）におけるノイズ問題の対策のために、ノイズ低減効果を得るためにフェライトペースト層を導入した先行技術が存在する（特許文献２参照）。このペーストは、フェライト粉末を用いたものであり、フェライト間にペーストの母材と成る樹脂が挿入されているので、ノイズ対策効果が少ないという問題がある。
【０００５】
このように、複数の半導体素子を積層するスタックパッケージにおいて、半導体素子間の信号干渉を抑制する材料は提供されていない。さらに、従来の小型ＣＳＰ用のノイズ対策ペーストでは、そのノイズ対策効果が小さいという問題がある。
【０００６】
【特許文献１】
特開２００２−２５２３２号公報
【特許文献２】
特開２００１−２４１０８号公報
【０００７】
【発明が解決しようする課題】
本発明は、かかる点に鑑みてなされたものであり、充分なノイズ低減効果および複数の半導体素子間の信号干渉の抑制を発揮することができる半導体素子接着用電磁波遮断シート、半導体装置および半導体素子接着用電磁波遮断シートの製造方法を提供することを目的とする。
【０００８】
【課題を解決するための手段】
本発明は、電気絶縁層と、
電気絶縁層の片面に設けられるフェライト層と、
前記電気絶縁層と前記フェライト層とから成る積層体の最外方の両面に設けられる粘着層とを含むことを特徴とする半導体素子接着用電磁波遮断シートである。
また本発明は、電気絶縁層と、
電気絶縁層の両面に設けられるフェライト層と、
前記電気絶縁層と前記フェライト層とから成る積層体の最外方の両面に設けられる粘着層とを含むことを特徴とする半導体素子接着用電磁波遮断シートである。
また本発明は、前記電気絶縁層は、ポリイミドから成ることを特徴とする。
また本発明は、前記フェライト層の厚みは、１００ｎｍから１０μｍであることを特徴とする。
また本発明は、前記粘着層の厚みは、１μｍ〜１０μｍであることを特徴とする。
また本発明は、各粘着層上に剥離除去可能に貼着される剥離シート１ｅ，１ｆ；２ｆ，２ｇをさらに含むことを特徴とする。
また本発明は、電気絶縁性材料から成る基板３ａと、
基板３ａの一方面上に固定されるスペーサ３ｄと、
スペーサ３ｄ上に固定される第１半導体素子３ｂと、
前記半導体素子３ｂ上に固定されるシート３ｅと、
前記シート３ｅ上に固定される第２半導体素子３ｃと、
基板３ａの他表面上に設けられ、外部電気回路と接続される電気接続部３ｉと、
第１半導体素子３ｂと前記電気接続部３ｉとを電気的に接続する第１接続部３ｇと、
第２半導体素子３ｃを、第１半導体素子３ｂまたは前記電気接続部３ｉと電気的に接続する第２接続部３ｆと、
第１および第２半導体素子３ｂ，３ｃと、スペーサ３ｄと、シート３ｅと、第１および第２接続部３ｆとを封止して外部環境から守る封止材３ｈとを含む半導体装置に用いられる前記スペーサ３ｄであって、
前記スペーサ３ｄは、前述の半導体素子接着用電磁波遮断シートであることを特徴とする半導体装置に用いられるスペーサである。
また本発明は、電気絶縁性材料から成る基板３ａと、
基板３ａの一方面上に固定されるスペーサ３ｄと、
スペーサ３ｄ上に固定される第１半導体素子３ｂと、
前記半導体素子３ｂ上に固定されるシート３ｅと、
前記シート３ｅ上に固定される第２半導体素子３ｃと、
基板３ａの他表面上に設けられ、外部電気回路と接続される電気接続部３ｉと、
第１半導体素子３ｂと前記電気接続部３ｉとを電気的に接続する第１接続部３ｇと、
第２半導体素子３ｃを、第１半導体素子３ｂまたは前記電気接続部３ｉと電気的に接続する第２接続部３ｆと、
第１および第２半導体素子３ｂ，３ｃと、スペーサ３ｄと、シート３ｅと、第１および第２接続部３ｆとを封止して外部環境から守る封止材３ｈとを含む半導体装置に用いられる前記シート３ｅであって、
前記シート３ｅは、前述の半導体素子接着用電磁波遮断シートであることを特徴とする半導体装置に用いられるシートである。
【０００９】
また本発明は、前記両面に粘着層が設けられた半導体素子接着用電磁波遮断シートを介在して、半導体素子が積層されることを特徴とする半導体装置である。
また本発明は、電気絶縁性材料から成る基板３ａと、
基板３ａの一方面上に固定されるスペーサ３ｄと、
スペーサ３ｄ上に固定される第１半導体素子３ｂと、
前記半導体素子３ｂ上に固定されるシート３ｅと、
前記シート３ｅ上に固定される第２半導体素子３ｃと、
基板３ａの他表面上に設けられ、外部電気回路と接続される電気接続部３ｉと、
第１半導体素子３ｂと前記電気接続部３ｉとを電気的に接続する第１接続部３ｇと、
第２半導体素子３ｃを、第１半導体素子３ｂまたは前記電気接続部３ｉと電気的に接続する第２接続部３ｆと、
第１および第２半導体素子３ｂ，３ｃと、スペーサ３ｄと、シート３ｅと、第１および第２接続部３ｆとを封止して外部環境から守る封止材３ｈとを含む半導体装置であって、
前記スペーサ３ｄと前記シート３ｅとは、前述の半導体素子接着用電磁波遮断シートであることを特徴とする半導体装置である。
【００１０】
本発明に従えば、電気絶縁層によって補強されたフェライト層は、たとえば積層された半導体素子相互間で干渉を生じる電気信号の漏洩を、フェライト層の磁気損失特性によって減衰させる。また半導体素子に混入するノイズを、フェライト層の磁気損失特性によって減衰させ、ノイズの混入を防ぐ。こうして本発明のシートによって、電磁波を遮蔽し、半導体素子の電気信号の干渉を防止し、またノイズの混入を防ぐ。
【００１１】
フェライトとは、化学式ＭＯ・Ｆｅ２Ｏ３（ＭはＦｅ以外の２価の金属で、たとえばＭｎ、Ｚｎ、Ｎｉが等が挙げられる。）で表される磁性酸化物の総称である。本発明のこれらの酸化物系軟質磁性材料には、高透磁率、高磁束密度のＭｎ−Ｚｎ系と、比抵抗が極めて高いＮｉ−Ｚｎ系が好適する。フェライトは、高周波磁気特性に優れる。
【００１２】
本件シートの電気絶縁層とフェライト層とから成る積層体の最外方の両面に粘着層が形成されることによって、本件シートを半導体素子またはパッケージなどに接着する作業を容易に行うことができ、作業性が向上される。
【００１３】
粘着層が本件シートの両面に形成されることによって、各粘着層に半導体素子を接着し、半導体素子を積層することができ、あるいはまた半導体素子をパッケージに接着して装着することが容易である。
【００１４】
また本発明は、表面にＯＨ基を有する電気絶縁層を、２価鉄イオンＦｅ２＋と必要により他の金属イオンとを含むめっき反応液中に浸すことによって、電気絶縁層の両面に、この２価鉄イオンＦｅ２＋および他の金属イオンをＯＨ基を介して吸着させ、
酸化剤または陽極電流によって、Ｆｅ２＋の一部をＦｅ２＋→Ｆｅ３＋の酸化反応を行うことによって、すでに吸着していた前記金属イオンに再び２価鉄イオンＦｅ２＋を吸着させつつ、加水分解を行いながら、
電気絶縁層の前記両面に、スピネル生成反応を生じさせ、スピネル形フェライト層を形成し、次いで、最外方の両面に粘着層を設けることを特徴とする。
【００１５】
本発明に従えば、電気絶縁層の両面に、いわゆるフェライトめっきと呼ばれるフェライト層を、常温〜１００℃未満の比較的低い温度でフェライト層を形成することが容易に可能となる。
【００１６】
金属イオンの吸着席となるＯＨ基が表面に有する固体基板である電気絶縁層を、２価鉄イオンＦｅ２＋を含む反応液に浸すと、これらのイオンがＯＨ基を介して固体表面に吸着される。次に亜硝酸ナトリウムＮａＮＯ２、空気（Ｏ２）などの酸化剤または陽極電流によって、Ｆｅ２＋→Ｆｅ３＋の酸化反応を行うと、すでに吸着していた金属イオン上に再びＦｅ２＋が吸着しつつ、加水分解を伴いながら、スピネル生成反応が起こる。この吸着→酸化→スピネル生成というプロセスが繰返され、スピネル膜または粒子が成長してゆく。このフェライト層生成の反応式は、次のように表される。
【００１７】

Figure 0004133637
Ｆｅのみを含むマグネタイトめっきでは、（３）式でＭ＝Ｆｅとおいて、
３Ｆｅ２＋＋４Ｈ２Ｏ ←→ Ｆｅ３Ｏ４＋８Ｈ＋＋２ｅ− …（４）
【００１８】
フェライトめっきは、酸化剤（Ｏ２，ＮａＮＯ２など）を用いた場合、一種の無電解めっきに相当する。フェライトめっきは、酸化反応である。
【００１９】
このように１００℃以下の水溶液中で結晶質フェライトを合成できるのは、現在のところ、スピネル形に限定されている。その理由は、スピネル形フェライトが遷移金属イオンのみしか含まないために、結晶化に必要とする活性化エネルギが低いためである。
【００２０】
【発明の実施の形態】
以下、本発明の実施の形態について、添付図面を参照して詳細に説明する。
【００２１】
図１は、本発明の一実施の形態に係る半導体素子接着用電磁波遮断シート１を示す断面図である。図１において、絶縁基材である電気絶縁層１ａ上の片面にフェライト層１ｂが形成されており、フェライト層１ｂの面上および電気絶縁層１ａの反対側の面上に、接着層である粘着層１ｃおよび１ｄが形成される。
【００２２】
電気絶縁層１ａとしては、ポリイミド等の有機材料から成る合成樹脂シート、アルミナに代表されるセラミック基板等を用いることができる。落下時の破損の心配が無いことや、厚みを薄くできる点、さらには、製造上の取扱い易さの点から、有機材料から成るシートが好ましい。さらに、電気絶縁性の性能に優れ、さらには難燃性を確保できるという点からポリイミドから成るシートが好ましい。
【００２３】
フェライト層１ｂは、種々の方法で電気絶縁層１ａ上に形成することができる。電気絶縁層１ａ上へフェライト層１ｂを形成する方法としては、（１）フェライトめっき法（たとえば松下、他；日本応用磁気学会誌、Vol.26、No.4、p.475（2002）参照）によって電気絶縁層１ａ上にフェライト層１ｂを形成する方法が好ましいが、そのほか（２）フェライト粉末を燒結した燒結フェライトシートを接着剤等を用いて電気絶縁層に接着する方法や、（３）電気絶縁層上にスパッタやＣＶＤ（化学的気相成長法）等の真空蒸着法により成膜する方法を選ぶことができる。この中でも、前述のフェライトめっき法にてフェライト層１ｂを電気絶縁層１ａ上に形成する方法は、低温でのフェライト形成が可能であり、さらには、電気絶縁層１ａの両面へ一度に形成できるという点で好ましい。このように、面上にフェライト層１ｂを形成することにより、不要電磁波の吸収および／または遮蔽の機能をシートに付与することができる。このフェライト層１ｂの厚みは、たとえば１０ｎｍ〜１ｍｍであってもよく、好ましくは１００ｎｍ〜１０μｍである。
【００２４】
粘着層１ｃ，１ｄとしては、半導体素子間を接着する機能を持ち、熱サイクル時の信頼性が確保でき、さらには、接合時への半導体素子へのダメージが少ないものであればよく、これらを満足するものであれば、熱可塑性樹脂または熱硬化性樹脂のいずれでも用いることができる。これらの信頼性を確保するために、熱可塑性樹脂の場合には、ガラス転移温度が６０℃以上２５０℃以下の材料、さらには１２０℃以上２５０℃以下の材料が好ましい。すなわち、ガラス転移温度が６０℃未満の場合には、パッケージング後の熱サイクル信頼性が低下し、好ましくない場合がある。また、ガラス転移温度が２５０℃を超える場合には、半導体集積回路素子を積層する際の作業性の低下および半導体集積回路素子へのダメージが発生する場合があり好ましくない。電気絶縁層１ａ、粘着層１ｃ，１ｄの厚みは、フェライト層１ｂの厚みと同様であってもよく、たとえば０．１μｍ〜１００μｍであってもよく、さらに厚くてもよいが、好ましくは１μｍ〜１０μｍである。
【００２５】
粘着層１ｃ，１ｄとして好適する熱可塑性樹脂としては、ポリイミド、ポリイミドアミド、ポリエーテルスルホン、ポロエーテルエーテルケトン、ポリエステル、ポリスルホン、ポリフェニレンエーテル、ポリアミド、ポリ（メタ）アクリル酸エステル、エチレン酢ビコポリマー、エチレンアクリルコポリマーおよびポリエチレン、ポリプロピレン等のポリオレフィン類の単独またはこれらの混和物が例示される。
【００２６】
粘着層１ｃ，１ｄとして好適する熱硬化性樹脂の場合には、硬化後のガラス転移温度が６０℃以上３００℃以下の材料、さらには１２０℃以上３００℃以下の材料が好ましい。すなわち、ガラス転移温度が６０℃未満の場合には、パッケージング後の熱サイクル信頼性が低下し、好ましくない場合がある。また、ガラス転移温度が３００℃を超える場合には、硬化応力による集積回路素子へのダメージが発生するため好ましくない場合がある。熱硬化性樹脂としては、エポキシ樹脂、ビスマレイミド樹脂、ベンゾシクロフラン樹脂、シアン酸エステル樹脂、フェノール樹脂の単独または混和物が例示される。また、これら熱硬化性樹脂には熱可塑性樹脂あるいは各種ゴム成分を加えてもかまわない。
【００２７】
粘着層１ｃ，１ｄの外表面には、剥離シート１ｅ，１ｆが、剥離可能に貼着される。半導体素子の接着に先立ち、剥離シート１ｅ，１ｆが除去され、粘着層１ｃ，１ｄによって接着機能が達成される。
【００２８】
図２は、本発明の実施の他の形態にかかる半導体素子接着用電磁波遮断シート２を示す断面図である。図２において、電気絶縁層２ａ上の両面にフェライト層２ｂおよび２ｅが形成されており、フェライト層２ｂおよび２ｅの上にそれぞれ粘着層２ｃおよび２ｄが形成される。電気絶縁層２ａは、前述の図１の電気絶縁層１ａと同様な構成を有し、フェライト層２ｂ，２ｅは、前述のフェライト層１ｂと同様な構成を有し、粘着層２ｃ，２ｄは、前述の粘着層１ｃ，１ｄと同様な構成を有する。図２の実施の形態においても、前述の剥離シート１ｅ，１ｆと同様な剥離シート２ｆ，２ｇが剥離可能に同様に設けられてもよい。
【００２９】
図３は、本発明の一実施の形態に係る半導体装置３を示す断面図である。図３において、１つの半導体素子３ｂが、スペーサ３ｄを介して電気絶縁層１ａと同様な電気絶縁性材料から成るパッケージ本体である基板３ａ上に搭載され、ワイヤ等の接続部３ｇによって半導体素子３ｂと基板３ａの電気接続部３ｉとは電気的に接続されている。スペーサ３ｄは半導体素子３ｂを基板３ａの一方面上に固定するために用いられるものである。
【００３０】
このスペーサ３ｄとして、本発明の半導体素子接着用電磁波遮断シート１または２を用いる。半導体素子３ｂ上に積層されるもう一つの半導体素子３ｃは、本発明のフェライト層を含む半導体素子接着用電磁波遮断シート３ｅを介して積層される。すなわちこのシート３ｅは、前述の本発明の半導体素子接着用電磁波遮断シート１または２であってもよい。半導体素子３ｃは、ワイヤ等の接続部３ｆにて半導体素子３ｂまたは基板３ａの電気接続部３ｉと電気的に接続される。このようにスペーサ３ｄとシート３ｅとで積層された半導体素子３ｂ，３ｃと接続部３ｆ，３ｇとは、封止材３ｈで封止することによって外部環境から守られる。さらに、このような半導体装置３は、基板３ａの他方面に設けられた前記電気接続部３ｉを介して外部電気回路と接続される。
【００３１】
前述の図３では、積層される半導体素子が２つの場合を示しているが、積層される半導体素子の数は特に制限されるものでない。このようにフェライト層を含む本発明のシートを半導体素子間の半導体素子接着用電磁波遮断シートとして用いることによって、半導体素子間の電気信号の干渉を効率よく抑制することができる。こうして本発明の半導体素子接着用電磁波遮断シートを、前述のスペーサ３ｄおよびシート３ｅにおいて用いることによって、積層スタックパッケージにおいて、半導体素子間の電気信号の干渉が少ない半導体装置を実現することができるとともに、外部からのノイズの混入を抑制することができる。
【００３２】
【発明の効果】
本発明によれば、半導体素子の電気信号が相互に干渉することを防止し、またノイズが混入することを防止する半導体素子接着用電磁波遮断シートが実現される。本件半導体素子接着用電磁波遮断シートのフェライト層を、前述のいわゆるフェライトめっき法で製造することによって、たとえば積層された半導体素子の電気信号の干渉を防止し、またパッケージなどのノイズ混入を防止するのに充分な厚みを有するフェライト層を、容易に得ることができる。
【図面の簡単な説明】
【図１】本発明の一実施の形態に係る半導体素子接着用電磁波遮断シート１を示す断面図である。
【図２】本発明の実施の他の形態にかかる半導体素子接着用電磁波遮断シート２を示す断面図である。
【図３】本発明の一実施の形態に係る半導体装置３を示す断面図である。
【符号の説明】
１，２，３ｅ 半導体素子接着用電磁波遮断シート
１ａ，２ａ 電気絶縁層
１ｂ，２ｂ，２ｅ フェライト層
１ｃ，１ｄ，２ｃ，２ｄ 粘着層
３ 半導体装置
３ａ 基板
３ｂ，３ｃ 半導体素子
３ｄ スペーサ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electromagnetic wave shielding sheet for adhering a semiconductor element, a semiconductor device, and an electromagnetic wave shielding sheet for adhering a semiconductor element for preventing interference of electric signals between stacked semiconductor elements and reducing noise mixed in the semiconductor element It relates to the manufacturing method.
[0002]
[Prior art]
In recent years, along with the demand for miniaturization of electronic equipment, the surface high-density mounting has been further spurred, and the use of a so-called stack package in which a plurality of semiconductor elements are stacked in the same package is increasing (see Patent Document 1).
[0003]
As electronic devices become more digital, faster, and higher in frequency, noise issues are becoming increasingly important. Particularly in the stack package, since the semiconductor elements are stacked close to each other, there is a problem that signal interference occurs between the stacked elements in addition to the conventional problem of noise coming from outside the semiconductor element. The prior art does not provide a countermeasure material that can suppress signal interference between elements in such a stack package.
[0004]
There is a prior art in which a ferrite paste layer is introduced in order to obtain a noise reduction effect as a countermeasure for noise problems in a small CSP (Chip Size Package) (see Patent Document 2). This paste uses ferrite powder, and since a resin as a base material of the paste is inserted between the ferrites, there is a problem that the noise countermeasure effect is small.
[0005]
Thus, in a stack package in which a plurality of semiconductor elements are stacked, a material that suppresses signal interference between the semiconductor elements is not provided. Furthermore, the conventional noise suppression paste for small CSP has a problem that its noise suppression effect is small.
[0006]
[Patent Document 1]
JP 2002-25232 A [Patent Document 2]
Japanese Patent Laid-Open No. 2001-24108
[Problems to be solved by the invention]
The present invention has been made in view of such a point, and an electromagnetic wave shielding sheet for adhering a semiconductor element, a semiconductor device, and a semiconductor element capable of exhibiting a sufficient noise reduction effect and suppression of signal interference between a plurality of semiconductor elements. It aims at providing the manufacturing method of the electromagnetic wave shielding sheet for adhesion | attachment.
[0008]
[Means for Solving the Problems]
The present invention includes an electrical insulating layer;
A ferrite layer provided on one surface of the electrically insulating layer,
An electromagnetic wave shielding sheet for adhering a semiconductor element, comprising an adhesive layer provided on both outermost surfaces of a laminate comprising the electrical insulating layer and the ferrite layer .
The present invention also provides an electrical insulating layer;
A ferrite layer provided on both sides of the electrical insulating layer;
An electromagnetic wave shielding sheet for adhering a semiconductor element, comprising an adhesive layer provided on both outermost surfaces of a laminate comprising the electrical insulating layer and the ferrite layer.
In the invention, it is preferable that the electrical insulating layer is made of polyimide.
In the invention, it is preferable that the ferrite layer has a thickness of 100 nm to 10 μm.
Moreover, this invention is characterized by the thickness of the said adhesion layer being 1 micrometer-10 micrometers.
Moreover, this invention is characterized by further including peeling sheet 1e, 1f; 2f, 2g stuck on each adhesion layer so that peeling removal is possible.
The present invention also includes a substrate 3a made of an electrically insulating material,
A spacer 3d fixed on one surface of the substrate 3a;
A first semiconductor element 3b fixed on the spacer 3d;
A sheet 3e fixed on the semiconductor element 3b;
A second semiconductor element 3c fixed on the sheet 3e;
An electrical connection 3i provided on the other surface of the substrate 3a and connected to an external electrical circuit;
A first connection part 3g for electrically connecting the first semiconductor element 3b and the electrical connection part 3i;
A second connection part 3f for electrically connecting the second semiconductor element 3c to the first semiconductor element 3b or the electrical connection part 3i;
Used in a semiconductor device including first and second semiconductor elements 3b and 3c, a spacer 3d, a sheet 3e, and a sealing material 3h that seals the first and second connection portions 3f and protects them from the external environment. The spacer 3d,
The spacer 3d is a spacer used in a semiconductor device, which is the above-described electromagnetic wave shielding sheet for adhering semiconductor elements.
The present invention also includes a substrate 3a made of an electrically insulating material,
A spacer 3d fixed on one surface of the substrate 3a;
A first semiconductor element 3b fixed on the spacer 3d;
A sheet 3e fixed on the semiconductor element 3b;
A second semiconductor element 3c fixed on the sheet 3e;
An electrical connection 3i provided on the other surface of the substrate 3a and connected to an external electrical circuit;
A first connection part 3g for electrically connecting the first semiconductor element 3b and the electrical connection part 3i;
A second connection part 3f for electrically connecting the second semiconductor element 3c to the first semiconductor element 3b or the electrical connection part 3i;
Used in a semiconductor device including first and second semiconductor elements 3b and 3c, a spacer 3d, a sheet 3e, and a sealing material 3h that seals the first and second connection portions 3f and protects them from the external environment. The sheet 3e,
The sheet 3e is a sheet used for a semiconductor device, which is the above-described electromagnetic wave shielding sheet for bonding semiconductor elements.
[0009]
The present invention is also a semiconductor device in which semiconductor elements are stacked with an electromagnetic wave shielding sheet for adhering a semiconductor element provided with an adhesive layer on both sides.
The present invention also includes a substrate 3a made of an electrically insulating material,
A spacer 3d fixed on one surface of the substrate 3a;
A first semiconductor element 3b fixed on the spacer 3d;
A sheet 3e fixed on the semiconductor element 3b;
A second semiconductor element 3c fixed on the sheet 3e;
An electrical connection 3i provided on the other surface of the substrate 3a and connected to an external electrical circuit;
A first connection part 3g for electrically connecting the first semiconductor element 3b and the electrical connection part 3i;
A second connection part 3f for electrically connecting the second semiconductor element 3c to the first semiconductor element 3b or the electrical connection part 3i;
A semiconductor device including a first and second semiconductor elements 3b and 3c, a spacer 3d, a sheet 3e, and a sealing material 3h that seals the first and second connection portions 3f and protects them from the external environment. ,
The spacer 3d and the sheet 3e are the above-described semiconductor element bonding electromagnetic wave shielding sheet, which is a semiconductor device.
[0010]
According to the present invention, the ferrite layer reinforced by the electrical insulating layer attenuates, for example, leakage of electrical signals that cause interference between stacked semiconductor elements by the magnetic loss characteristics of the ferrite layer. In addition, the noise mixed in the semiconductor element is attenuated by the magnetic loss characteristic of the ferrite layer to prevent the noise from being mixed. Thus, the sheet of the present invention shields electromagnetic waves, prevents electrical signal interference of the semiconductor element, and prevents noise from being mixed.
[0011]
Ferrite is a general term for magnetic oxides represented by the chemical formula MO.Fe 2 O 3 (M is a divalent metal other than Fe, and examples thereof include Mn, Zn, Ni, etc.). For these oxide-based soft magnetic materials of the present invention, a Mn—Zn system having a high magnetic permeability and a high magnetic flux density and a Ni—Zn system having a very high specific resistance are suitable. Ferrite has excellent high frequency magnetic properties.
[0012]
By forming an adhesive layer on the outermost surfaces of the laminate composed of the electrical insulating layer and ferrite layer of the present sheet, the work of adhering the present sheet to a semiconductor element or a package can be easily performed. Workability is improved.
[0013]
By forming the adhesive layer on both sides of the sheet, it is possible to adhere the semiconductor elements to each adhesive layer and stack the semiconductor elements, or it is easy to attach the semiconductor elements to the package. .
[0014]
The present invention is an electrically insulating layer having an OH group on the surface, by immersion in the plating reaction solution containing the other metal ions necessary and divalent iron ions Fe 2+, both surfaces of the electrical insulating layer, the Adsorb divalent iron ions Fe 2+ and other metal ions via OH groups;
The oxidizing agent or the anode current, a part of the Fe 2+ by an oxidation reaction of Fe 2+ → Fe 3+, while already adsorbed again divalent iron ions Fe 2+ adsorption to have said metal ions, the hydrolysis While doing
Before SL both sides of the electrically insulating layer, causing a spinel formation reaction to form a spinel type ferrite layer, then characterized by providing an adhesive layer on both sides of the outermost.
[0015]
According to the invention, on both faces of the electrically insulating layer, a ferrite layer so-called ferrite plating, to form a ferrite layer is readily possible at relatively low temperatures below room temperature to 100 ° C..
[0016]
When an electrical insulating layer, which is a solid substrate having OH groups on the surface serving as adsorption sites for metal ions, is immersed in a reaction solution containing divalent iron ions Fe 2+ , these ions are adsorbed on the solid surface via the OH groups. The Next, when an oxidation reaction of Fe 2+ → Fe 3+ is performed by an oxidizing agent such as sodium nitrite NaNO 2 and air (O 2 ) or an anode current, Fe 2+ is adsorbed again on the metal ions that have already been adsorbed. A spinel formation reaction occurs with hydrolysis. This process of adsorption → oxidation → spinel generation is repeated, and a spinel film or particles grow. The reaction formula for generating the ferrite layer is expressed as follows.
[0017]
Figure 0004133637
In magnetite plating containing only Fe, M = Fe in the equation (3),
3Fe 2+ + 4H 2 O ← → Fe 3 O 4 + 8H + + 2e − (4)
[0018]
Ferrite plating corresponds to a kind of electroless plating when an oxidizing agent (O 2 , NaNO 2 or the like) is used. Ferrite plating is an oxidation reaction.
[0019]
Thus, the ability to synthesize crystalline ferrite in an aqueous solution at 100 ° C. or lower is currently limited to the spinel form. The reason is that the spinel type ferrite contains only transition metal ions, so that the activation energy required for crystallization is low.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0021]
FIG. 1 is a cross-sectional view showing an electromagnetic wave shielding sheet 1 for adhering semiconductor elements according to an embodiment of the present invention. In FIG. 1, a ferrite layer 1b is formed on one side of an electrical insulating layer 1a, which is an insulating substrate, and an adhesive layer is an adhesive layer on the surface of the ferrite layer 1b and on the opposite side of the electrical insulating layer 1a. Layers 1c and 1d are formed.
[0022]
As the electrical insulating layer 1a, a synthetic resin sheet made of an organic material such as polyimide, a ceramic substrate typified by alumina, or the like can be used. A sheet made of an organic material is preferable from the viewpoint that there is no fear of breakage at the time of dropping, the thickness can be reduced, and the ease of handling in manufacturing. Furthermore, the sheet | seat which consists of polyimide is preferable from the point which is excellent in the electrical insulation performance and can ensure a flame retardance.
[0023]
The ferrite layer 1b can be formed on the electrical insulating layer 1a by various methods. As a method of forming the ferrite layer 1b on the electrical insulating layer 1a, (1) Ferrite plating method (for example, see Matsushita, et al .; Journal of Japan Society of Applied Magnetics, Vol.26, No.4, p.475 (2002)) The method of forming the ferrite layer 1b on the electrical insulating layer 1a is preferable, but in addition, (2) a method of adhering a sintered ferrite sheet sintered with ferrite powder to the electrical insulating layer using an adhesive or the like; A method of forming a film on the insulating layer by a vacuum deposition method such as sputtering or CVD (chemical vapor deposition method) can be selected. Among these, the method of forming the ferrite layer 1b on the electrical insulating layer 1a by the above-described ferrite plating method can form ferrite at a low temperature, and can be formed on both surfaces of the electrical insulating layer 1a at a time. This is preferable. Thus, by forming the ferrite layer 1b on the surface, the function of absorbing and / or shielding unnecessary electromagnetic waves can be imparted to the sheet. The ferrite layer 1b may have a thickness of, for example, 10 nm to 1 mm, and preferably 100 nm to 10 μm.
[0024]
The adhesive layers 1c and 1d have a function of adhering between semiconductor elements, can ensure reliability at the time of thermal cycling, and have only a small damage to the semiconductor elements at the time of bonding. If it is satisfactory, either a thermoplastic resin or a thermosetting resin can be used. In order to ensure these reliability, in the case of a thermoplastic resin, a material having a glass transition temperature of 60 ° C. or higher and 250 ° C. or lower, and further a material of 120 ° C. or higher and 250 ° C. or lower is preferable. That is, when the glass transition temperature is less than 60 ° C., the thermal cycle reliability after packaging is lowered, which may be undesirable. In addition, when the glass transition temperature exceeds 250 ° C., workability when stacking the semiconductor integrated circuit elements and damage to the semiconductor integrated circuit elements may occur. The thickness of the electrical insulating layer 1a and the adhesive layers 1c and 1d may be the same as the thickness of the ferrite layer 1b. For example, the thickness may be 0.1 μm to 100 μm, and may be thicker, preferably 1 μm to 10 μm.
[0025]
Examples of the thermoplastic resin suitable as the adhesive layers 1c and 1d include polyimide, polyimide amide, polyethersulfone, polyetheretherketone, polyester, polysulfone, polyphenylene ether, polyamide, poly (meth) acrylic acid ester, ethylene vinyl acetate copolymer, Examples thereof include ethylene acrylic copolymers and polyolefins such as polyethylene and polypropylene, alone or in admixture thereof.
[0026]
In the case of a thermosetting resin suitable as the adhesive layers 1c and 1d, a material having a glass transition temperature after curing of 60 ° C. or higher and 300 ° C. or lower, and further a material of 120 ° C. or higher and 300 ° C. or lower is preferable. That is, when the glass transition temperature is less than 60 ° C., the thermal cycle reliability after packaging is lowered, which may be undesirable. Further, when the glass transition temperature exceeds 300 ° C., damage to the integrated circuit element due to curing stress may occur, which may not be preferable. Examples of the thermosetting resin include epoxy resins, bismaleimide resins, benzocyclofuran resins, cyanate ester resins, and phenol resins alone or in admixture. In addition, thermoplastic resins or various rubber components may be added to these thermosetting resins.
[0027]
Release sheets 1e and 1f are detachably attached to the outer surfaces of the adhesive layers 1c and 1d. Prior to the bonding of the semiconductor element, the release sheets 1e and 1f are removed, and the bonding function is achieved by the adhesive layers 1c and 1d.
[0028]
FIG. 2 is a cross-sectional view showing an electromagnetic wave shielding sheet 2 for adhering semiconductor elements according to another embodiment of the present invention. In FIG. 2, ferrite layers 2b and 2e are formed on both surfaces of the electrical insulating layer 2a, and adhesive layers 2c and 2d are formed on the ferrite layers 2b and 2e, respectively. The electrical insulating layer 2a has the same configuration as the electrical insulating layer 1a of FIG. 1 described above, the ferrite layers 2b and 2e have the same configuration as the previously described ferrite layer 1b, and the adhesive layers 2c and 2d are It has the same structure as the above-mentioned adhesive layers 1c and 1d. Also in the embodiment of FIG. 2, release sheets 2 f and 2 g similar to the above-described release sheets 1 e and 1 f may be similarly provided so as to be peelable.
[0029]
FIG. 3 is a cross-sectional view showing a semiconductor device 3 according to an embodiment of the present invention. In FIG. 3, one semiconductor element 3b is mounted on a substrate 3a, which is a package body made of an electrically insulating material similar to the electrical insulating layer 1a, via a spacer 3d, and the semiconductor element 3b is connected by a connecting portion 3g such as a wire. And the electrical connection portion 3i of the substrate 3a are electrically connected . The spacer 3d is used for fixing the semiconductor element 3b on one surface of the substrate 3a.
[0030]
As the spacer 3d, the electromagnetic wave shielding sheet 1 or 2 for adhering semiconductor elements of the present invention is used. Another semiconductor element 3c laminated on the semiconductor element 3b is laminated via the electromagnetic wave shielding sheet 3e for bonding a semiconductor element including the ferrite layer of the present invention. That is, the sheet 3e may be the above-described electromagnetic wave shielding sheet 1 or 2 for bonding semiconductor elements of the present invention. The semiconductor element 3c is electrically connected to the semiconductor element 3b or the electrical connection part 3i of the substrate 3a through a connection part 3f such as a wire. Thus, the semiconductor elements 3b and 3c and the connecting portions 3f and 3g laminated by the spacer 3d and the sheet 3e are protected from the external environment by sealing with the sealing material 3h. Further, such a semiconductor device 3 is connected to an external electric circuit via the electric connection portion 3i provided on the other surface of the substrate 3a .
[0031]
Although FIG. 3 described above shows a case where two semiconductor elements are stacked, the number of stacked semiconductor elements is not particularly limited. Thus, by using the sheet | seat of this invention containing a ferrite layer as an electromagnetic wave shielding sheet for semiconductor element adhesion between semiconductor elements, the interference of the electrical signal between semiconductor elements can be suppressed efficiently. Thus, by using the electromagnetic wave shielding sheet for adhering a semiconductor element of the present invention in the spacer 3d and the sheet 3e described above, in the stacked stack package, it is possible to realize a semiconductor device with less interference of electric signals between the semiconductor elements, Mixing of external noise can be suppressed.
[0032]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, the electromagnetic wave shielding sheet for semiconductor element adhesion which prevents that the electrical signal of a semiconductor element mutually interferes, and prevents that a noise mixes is implement | achieved. By manufacturing the ferrite layer of the electromagnetic wave shielding sheet for adhering the semiconductor element by the above-described so-called ferrite plating method, for example, it is possible to prevent interference of electric signals of stacked semiconductor elements and to prevent contamination of a package or the like. Therefore, a ferrite layer having a sufficient thickness can be easily obtained.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an electromagnetic wave shielding sheet for adhering a semiconductor element 1 according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing an electromagnetic wave shielding sheet 2 for adhering semiconductor elements according to another embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a semiconductor device 3 according to an embodiment of the present invention.
[Explanation of symbols]
1, 2 and 3e Electromagnetic wave shielding sheet 1a, 2a for semiconductor element adhesion Electrical insulation layers 1b, 2b, 2e Ferrite layer 1c, 1d, 2c, 2d Adhesion layer 3 Semiconductor device 3a Substrate 3b, 3c Semiconductor element 3d Spacer

Claims (11)

電気絶縁層と、
電気絶縁層の片面に設けられるフェライト層と、
前記電気絶縁層と前記フェライト層とから成る積層体の最外方の両面に設けられる粘着層とを含むことを特徴とする半導体素子接着用電磁波遮断シート。An electrical insulation layer;
A ferrite layer provided on one surface of the electrically insulating layer,
An electromagnetic wave shielding sheet for adhering a semiconductor element, comprising an adhesive layer provided on both outermost surfaces of a laminate comprising the electrical insulating layer and the ferrite layer . 電気絶縁層と、
電気絶縁層の両面に設けられるフェライト層と、
前記電気絶縁層と前記フェライト層とから成る積層体の最外方の両面に設けられる粘着層とを含むことを特徴とする半導体素子接着用電磁波遮断シート。 An electrical insulation layer;
A ferrite layer provided on both sides of the electrical insulating layer;
An electromagnetic wave shielding sheet for adhering a semiconductor element , comprising an adhesive layer provided on both outermost surfaces of a laminate comprising the electrical insulating layer and the ferrite layer . 前記電気絶縁層は、ポリイミドから成ることを特徴とする請求項１または２記載の半導体素子接着用電磁波遮断シート。 The electrically insulating layer, according to claim 1 or 2 semiconductor element adhesive electromagnetic wave shielding sheet according to, characterized in that it consists of polyimide. 前記フェライト層の厚みは、１００ｎｍ〜１０μｍであることを特徴とする請求項１〜３のうちの１つに記載の半導体素子接着用電磁波遮断シート。4. The electromagnetic wave shielding sheet for adhering a semiconductor element according to claim 1, wherein the ferrite layer has a thickness of 100 nm to 10 μm. 前記粘着層の厚みは、１μｍ〜１０μｍであることを特徴とする請求項１〜４のうちの１つに記載の半導体素子接着用電磁波遮断シート。5. The electromagnetic wave shielding sheet for adhering a semiconductor element according to claim 1, wherein the adhesive layer has a thickness of 1 μm to 10 μm. 各粘着層上に剥離除去可能に貼着される剥離シート１ｅ，１ｆ；２ｆ，２ｇをさらに含むことを特徴とする請求項１〜５のうちの１つに記載の半導体素子接着用電磁波遮断シート。6. The electromagnetic wave shielding sheet for adhering semiconductor elements according to claim 1, further comprising release sheets 1 e, 1 f; 2 f, 2 g which are detachably attached to each adhesive layer. . 電気絶縁性材料から成る基板３ａと、A substrate 3a made of an electrically insulating material;
基板３ａの一方面上に固定されるスペーサ３ｄと、A spacer 3d fixed on one surface of the substrate 3a;
スペーサ３ｄ上に固定される第１半導体素子３ｂと、A first semiconductor element 3b fixed on the spacer 3d;
前記半導体素子３ｂ上に固定されるシート３ｅと、A sheet 3e fixed on the semiconductor element 3b;
前記シート３ｅ上に固定される第２半導体素子３ｃと、A second semiconductor element 3c fixed on the sheet 3e;
基板３ａの他表面上に設けられ、外部電気回路と接続される電気接続部３ｉと、An electrical connection 3i provided on the other surface of the substrate 3a and connected to an external electrical circuit;
第１半導体素子３ｂと前記電気接続部３ｉとを電気的に接続する第１接続部３ｇと、A first connection part 3g for electrically connecting the first semiconductor element 3b and the electrical connection part 3i;
第２半導体素子３ｃを、第１半導体素子３ｂまたは前記電気接続部３ｉと電気的に接続する第２接続部３ｆと、A second connection part 3f for electrically connecting the second semiconductor element 3c to the first semiconductor element 3b or the electrical connection part 3i;
第１および第２半導体素子３ｂ，３ｃと、スペーサ３ｄと、シート３ｅと、第１および第２接続部３ｆとを封止して外部環境から守る封止材３ｈとを含む半導体装置に用いられる前記スペーサ３ｄであって、Used in a semiconductor device including first and second semiconductor elements 3b and 3c, a spacer 3d, a sheet 3e, and a sealing material 3h that seals the first and second connection portions 3f and protects them from the external environment. The spacer 3d,
前記スペーサ３ｄは、請求項１〜６のうちの１つに記載の半導体素子接着用電磁波遮断シートであることを特徴とする半導体装置に用いられるスペーサ。The spacer 3d is an electromagnetic wave shielding sheet for adhering a semiconductor element according to one of claims 1 to 6, wherein the spacer is used for a semiconductor device. 電気絶縁性材料から成る基板３ａと、A substrate 3a made of an electrically insulating material;
基板３ａの一方面上に固定されるスペーサ３ｄと、A spacer 3d fixed on one surface of the substrate 3a;
スペーサ３ｄ上に固定される第１半導体素子３ｂと、A first semiconductor element 3b fixed on the spacer 3d;
前記半導体素子３ｂ上に固定されるシート３ｅと、A sheet 3e fixed on the semiconductor element 3b;
前記シート３ｅ上に固定される第２半導体素子３ｃと、A second semiconductor element 3c fixed on the sheet 3e;
基板３ａの他表面上に設けられ、外部電気回路と接続される電気接続部３ｉと、An electrical connection 3i provided on the other surface of the substrate 3a and connected to an external electrical circuit;
第１半導体素子３ｂと前記電気接続部３ｉとを電気的に接続する第１接続部３ｇと、A first connection part 3g for electrically connecting the first semiconductor element 3b and the electrical connection part 3i;
第２半導体素子３ｃを、第１半導体素子３ｂまたは前記電気接続部３ｉと電気的に接続する第２接続部３ｆと、A second connection part 3f for electrically connecting the second semiconductor element 3c to the first semiconductor element 3b or the electrical connection part 3i;
第１および第２半導体素子３ｂ，３ｃと、スペーサ３ｄと、シート３ｅと、第１および第２接続部３ｆとを封止して外部環境から守る封止材３ｈとを含む半導体装置に用いられる前記シート３ｅであって、Used in a semiconductor device including first and second semiconductor elements 3b and 3c, a spacer 3d, a sheet 3e, and a sealing material 3h that seals the first and second connection portions 3f and protects them from the external environment. The sheet 3e,
前記シート３ｅは、請求項１〜６のうちの１つに記載の半導体素子接着用電磁波遮断シートであることを特徴とする半導体装置に用いられるシート。The said sheet | seat 3e is an electromagnetic wave shielding sheet for semiconductor element adhesion | attachment as described in one of Claims 1-6, The sheet | seat used for the semiconductor device characterized by the above-mentioned. 請求項１または２の半導体素子接着用電磁波遮断シートを介在して、半導体素子が積層されることを特徴とする半導体装置。3. A semiconductor device, wherein semiconductor elements are stacked with the electromagnetic wave shielding sheet for adhering semiconductor elements according to claim 1 interposed therebetween. 電気絶縁性材料から成る基板３ａと、A substrate 3a made of an electrically insulating material;
基板３ａの一方面上に固定されるスペーサ３ｄと、A spacer 3d fixed on one surface of the substrate 3a;
スペーサ３ｄ上に固定される第１半導体素子３ｂと、A first semiconductor element 3b fixed on the spacer 3d;
前記半導体素子３ｂ上に固定されるシート３ｅと、A sheet 3e fixed on the semiconductor element 3b;
前記シート３ｅ上に固定される第２半導体素子３ｃと、A second semiconductor element 3c fixed on the sheet 3e;
基板３ａの他表面上に設けられ、外部電気回路と接続される電気接続部３ｉと、An electrical connection 3i provided on the other surface of the substrate 3a and connected to an external electrical circuit;
第１半導体素子３ｂと前記電気接続部３ｉとを電気的に接続する第１接続部３ｇと、A first connection part 3g for electrically connecting the first semiconductor element 3b and the electrical connection part 3i;
第２半導体素子３ｃを、第１半導体素子３ｂまたは前記電気接続部３ｉと電気的に接続する第２接続部３ｆと、A second connection part 3f for electrically connecting the second semiconductor element 3c to the first semiconductor element 3b or the electrical connection part 3i;
第１および第２半導体素子３ｂ，３ｃと、スペーサ３ｄと、シート３ｅと、第１および第２接続部３ｆとを封止して外部環境から守る封止材３ｈとを含む半導体装置であって、A semiconductor device including a first and second semiconductor elements 3b and 3c, a spacer 3d, a sheet 3e, and a sealing material 3h that seals the first and second connection portions 3f and protects them from the external environment. ,
前記スペーサ３ｄと前記シート３ｅとは、請求項１〜６のうちの１つに記載の半導体素子接着用電磁波遮断シートであることを特徴とする半導体装置。The semiconductor device according to claim 1, wherein the spacer 3 d and the sheet 3 e are an electromagnetic wave shielding sheet for adhering a semiconductor element according to claim 1. 表面にＯＨ基を有する電気絶縁層を、２価鉄イオンＦｅAn electrically insulating layer having an OH group on its surface is formed by divalent iron ion Fe ２＋2+ と必要により他の金属イオンとを含むめっき反応液中に浸すことによって、電気絶縁層の両面に、この２価鉄イオンＦｅAnd, if necessary, by dipping in a plating reaction solution containing other metal ions, the divalent iron ions Fe are formed on both surfaces of the electrical insulating layer. ２＋2+ および他の金属イオンをＯＨ基を介して吸着させ、And adsorb other metal ions through OH groups,
酸化剤または陽極電流によって、ＦｅDepending on the oxidant or anodic current, Fe ２＋2+ の一部をＦｅA part of Fe ２＋2+ →Ｆｅ→ Fe ３＋3+ の酸化反応を行うことによって、すでに吸着していた前記金属イオンに再び２価鉄イオンＦｅBy carrying out the oxidation reaction of divalent iron ions Fe again to the metal ions that had already been adsorbed ２＋2+ を吸着させつつ、加水分解を行いながら、While adsorbing, hydrolyzing,
電気絶縁層の前記両面に、スピネル生成反応を生じさせ、スピネル形フェライト層を形成し、次いで、最外方の両面に粘着層を設けることを特徴とする請求項２記載の半導体素子接着用電磁波遮断シートの製造方法。3. An electromagnetic wave for bonding a semiconductor element according to claim 2, wherein a spinel-forming ferrite layer is formed on both surfaces of the electrical insulating layer to form a spinel ferrite layer, and then an adhesive layer is provided on both outermost surfaces. A manufacturing method of the shielding sheet.
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