JP4095602B2 - Receiver - Google Patents

Description

  The present invention relates to a receiving apparatus that receives signals from a plurality of antennas.

  With the widespread use of mobile phones and PHS, it has become commonplace for individual consumers to communicate “anytime, anywhere, with anyone”, and wireless communication has become very familiar. Also, for PC users, an indoor LAN can be constructed wirelessly, and the suitability for high-speed data transmission and the ubiquitous nature independent of the location have been effective, and the wireless LAN (Local Area Network) has been spreading explosively. ing.

  In a system using radio, adaptive signal processing is performed on the transmission side or reception side using a plurality of antennas, so that reception quality can be improved and transmission speed or throughput can be improved. Such technologies include (1) diversity technology, (2) space-time coding or MIMO (Multi-Input Multi-Output) technology. The diversity technique is a technique for selecting a signal having a good reception state from signals received by a plurality of antennas. In the MIMO technology, the transmission side transmits different data series corresponding to the difference in the reception state at a plurality of antennas, and the reception side separates and extracts them to obtain N times (N: maximum number of transmission antennas) data. This is a technique that enables simultaneous demodulation. In any case, demodulation algorithms for effective selection / synthesis / separation of received signals on the receiving side have been studied.

Here, a series of reception circuits that perform frequency conversion from an antenna and a high frequency to a baseband and convert it to a digital signal state are collectively defined as a “reception branch” and are distinguished from an “antenna”.
In a method that performs combining diversity by digital signal processing in the baseband, an adaptive array antenna that performs weighted combining of amplitude or phase for each antenna for directivity control, and a method called a smart antenna, the receiver itself has multiple digital signals. It has a configuration having an area receiving unit.

  By the way, in order to demodulate the received signal in the digital domain, AFC (Automatic Frequency Control) for correcting the carrier frequency error is used in the receiver. This is because a VCO (Voltage Controlled Oscillator) differs between the transceivers, so that a carrier frequency offset (hereinafter referred to as “frequency error”) occurs between the transceivers.

In a receiver having a plurality of antennas, a common frequency synthesizer is usually used in the branches in order to suppress cost, circuit scale, and variation, and ideally no frequency error occurs between the branches.
However, in practice, the frequency error estimation value varies from branch to branch. This is because (1) frequency conversion is performed using a separate mixer in each branch, and (2) a signal including the influence of fading and noise in each branch is used for frequency error estimation in each branch. Etc. is the cause. In addition, when a wireless module (for example, a broadcast tuner) in which a separate frequency synthesizer is incorporated in each branch is used, the frequency synthesizer in each branch is in a free-run state and is not synchronized with each other and is large. Frequency error may occur.

The following techniques are disclosed regarding frequency error correction in a system having a plurality of antennas.
A technique for measuring a frequency error using a radio signal from an antenna having a maximum reception power is disclosed (see Patent Document 1, paragraph number 0035). In addition, a technique is disclosed that uses an average value of two frequency offset values as a frequency offset value when communication is performed in the MIMO scheme (see Patent Document 2, paragraph number 0114).
JP20032404043 JP 2003-283359 A

Correction of the frequency error in a system having a plurality of antennas has the following difficulties.
(1) If frequency errors are estimated and corrected independently for each branch, the circuit scale and power consumption of the entire configuration increase corresponding to the number of branches, resulting in smaller size, lower power consumption, and lower cost. It becomes difficult. In addition, due to the influence of fading or the like, there is a possibility that the estimated value of the frequency error varies as a result of the variation in the received signal power and hence the S / N in each branch.
(2) If the frequency of all branches is corrected based on the frequency error estimated in a specific branch, the frequency error is corrected when the S / N of the selected branch is poor or the estimation accuracy is insufficient. As a result, the demodulation performance may deteriorate as a result.
(3) If the frequency of all branches is corrected by averaging the frequency errors estimated in all branches, the reliability of the frequency error estimated value may be deteriorated when there is a branch with excessive reception intensity. is there.

  In view of the above, an object of the present invention is to provide a receiving apparatus that can reduce the influence of frequency error estimation value variation on a frequency correction for each branch.

  A. In order to achieve the above object, a receiving apparatus according to the present invention detects first and second frequency error detections for detecting frequency errors of first and second signals received by first and second antennas, respectively. Means, first and second signal intensity detecting means for detecting the signal intensity of each of the first and second signals, and based on the signal intensity detection results of the first and second signal intensity detecting means. A frequency error synthesis means for weighting and synthesizing the frequency errors detected by the first and second frequency error detection means, and a first and second reception based on the frequency error synthesized by the frequency error synthesis means. First and second phase correction means for correcting the phase of each signal, and demodulation means for performing demodulation using the first and second signals corrected by the first and second phase correction means, It is characterized by comprising.

  B. The receiving apparatus according to the present invention includes a signal combining unit that performs weighted combining of the first and second signals received by the first and second antennas, and an S / N ratio of the signal combined by the signal combining unit. S / N ratio detecting means for detecting signal, weight determining means for determining weight used for signal synthesis in the signal synthesizing means based on the detection result in the S / N ratio detecting means, and the signal synthesizing means Frequency error detecting means for detecting the frequency error of the signal synthesized in step (1), and first and second corrections for the phases of the first and second received signals based on the frequency error detected by the frequency error detecting means. A second phase correcting unit; and a demodulating unit that performs demodulation using the first and second signals corrected by the first and second phase correcting units.

  ADVANTAGE OF THE INVENTION According to this invention, the receiver which can reduce the influence which the variation in the frequency error estimated value for every branch has on frequency correction can be provided.

Hereinafter, the present embodiment will be described in detail with reference to the drawings.
(First embodiment)
FIG. 1 is a block diagram showing a configuration of a receiver 100 according to the first embodiment of the present invention.
Receiver 100 includes antennas 101 and 102, multipliers 103 and 104, NCO (Numerical Controlled Oscillator) 105 and 106, diversity demodulation circuit 107, frequency error detection circuit 115, RSSI measurement circuits 111 and 112, comparator 113, and operation switching. A determination circuit 114, high-frequency circuits 116 and 117, and A / D converters 118 and 119 are included.

The antennas 101 and 102 are receiving elements that receive radio waves, and their reception states are different because their arrangement is different. In this embodiment, only the case where the two-element antennas 101 and 102 are used has been described. However, the number of antennas and reception branches may be more than two.
Each of the high frequency circuits 116 and 117 includes a filter, an amplifier, a down converter, a quadrature demodulator, and the like, and reduces the frequency of the signal received by the antennas 101 and 102 from the carrier band to the baseband band.
The A / D converters 118 and 119 convert analog signals output from the high-frequency circuits 116 and 117 into digital signals, respectively.

The frequency error detection circuit 115 includes individual frequency error detection circuits 108 and 109 and a correction amount weighting synthesis circuit 110, and detects a total frequency error of signals output from the A / D converters 118 and 119.
The individual frequency error detection circuits 108 and 109 detect a frequency error (carrier frequency offset) based on signals output from the A / D converters 118 and 119, respectively. For the detection (or estimation) of the frequency error, for example, a preamble or header near the beginning of the frame of the received signal or a pilot signal included in the received frame is used to track changes in the phase of such known information. You can do it. In the OFDM system, the frequency error can also be detected by correlation with a guard interval portion obtained by copying and adding a part of a signal.

  The frequency error signals output from the individual frequency error detection circuits 108 and 109 do not necessarily match. This is because (1) variations in down-converters (specifically, mixers) that perform frequency conversion in the high-frequency circuits 116 and 117, and (2) frequency error detection results in the individual frequency error detection circuits 108 and 109, respectively. It is affected by fading and noise at the branch, and (3) by using a tuner for each branch. For this reason, even if the frequency synthesizer is common to all branches, the frequency error estimation value varies for each branch.

The correction amount weighting synthesis circuit 110 calculates a total frequency error by weighting and synthesizing the frequency error signals output from the individual frequency error detection circuits 108 and 109. The weighting coefficient at this time can be determined based on, for example, the signal strength (RSSI value or the like) of the signals received by the antennas 101 and 102 and the AGC gain control state.
NCOs (Numerical Controlled Oscillators) 105 and 106 are numerically controlled oscillators, and based on the synthesized frequency error signal output from the correction amount weighting synthesis circuit 110, the correction frequency (phase rotation) component e ^ (− jθ) A signal (correction frequency signal) is generated.
Multipliers 103 and 104 multiply the signals output from A / D converters 118 and 119 by the correction frequency signals output from NCOs 105 and 106, respectively. As a result, the phase of the signal can be changed.

The diversity demodulation circuit 107 performs diversity demodulation / decoding based on the signal with the corrected frequency error output from the multipliers 103 and 104. Diversity demodulating circuit 107 selects a signal in a good reception state from signals received by antennas 101 and 102.
Instead of diversity demodulation circuit 107, it is also possible to use a MIMO (Multi-Input Multi-Output) demodulation processing circuit that separates and extracts a plurality of different transmission data sequences. Corresponding to the difference in reception state between the antennas 101 and 102, the transmitting side transmits different data series, and the receiving side separates and extracts them, and N times (N: maximum number of transmitting antennas, here N = 2) Can be demodulated simultaneously.

The RSSI measurement circuits 111 and 112 measure RSSI (Receive Signal Strength Indication) values of signals output from the high frequency circuits 116 and 117, respectively.
The RSSI measurement circuits 111 and 112 perform RSSI measurement (A-RSSI measurement) based on analog signals from the high-frequency circuits 116 and 117, but instead of this, digital signals from the A / D converters 118 and 119 are used. RSSI measurement based on the signal (D-RSSI measurement) may be performed.

The comparator 113 compares the RSSI values output from the RSSI measurement circuits 111 and 112 and determines which is larger.
The operation switching determination circuit 114 determines the selection of the antennas 101 and 102 to be used for frequency error detection in the frequency error detection circuit 115 based on the comparison result in the comparator 113, and the frequency error detection circuit based on the determination result. 115 is controlled. The operation switching determination circuit 114 determines and switches and controls which one of the frequency error signals output from the individual frequency error detection circuits 108 and 109 is used for frequency error correction according to the received signal level.

When one of the frequency error signals is used, frequency error correction is performed using the signal of one reception branch. At this time, only one of the individual frequency error detection circuits 108 and 109 operates. Further, the correction amount weighting synthesis circuit 110 outputs the input frequency error value as it is to the NCO 105 or 106 without performing any particular calculation.
When both frequency error signals are used, frequency error correction is performed based on a value obtained by weighting and combining detected values of frequency errors detected independently in a plurality of branches according to the AGC gain control state for each branch. At this time, all of the individual frequency error detection circuits 108 and 109, the correction amount weighting synthesis circuit 110, and the NCOs 105 and 106 operate.

For example, when the RSSI of a certain branch is larger than a first predetermined value, only the individual frequency error detection circuits 108 and 109 of that branch are turned on (operating state), and the other individual frequency error detection circuits 108 and 109 and The correction amount weighting synthesis circuit 110 is turned off (stopped). This is because a signal having a signal strength of a certain level (a weak signal) is considered to have low reliability.
Specifically, when the RSSI value of a specific branch is 20 dB or more of the RSSI value of another branch, or when all RSSIs other than the specific branch are less than -70 dBm, the individual frequency error detection of the specific branch is performed. Only the circuits 108 and 109 are operated. As can be seen, this switching determination can be made based on either the absolute value of RSSI or the relative value between branches.

  Further, when the RSSI of a certain branch is larger than the second predetermined value, the individual frequency error detection circuits 108 and 109 of the branch are stopped, and the other individual frequency error detection circuits 108 and 109 are operated. Can do. This is because a signal having an excessive signal strength is saturated, and it is considered that the reliability is poor.

  On the other hand, when the RSSI values of all branches are approximately the same, all the individual frequency error detection circuits 108 and 109 are turned on to perform weighted synthesis of frequency errors. For example, a signal whose signal intensity is greater than or equal to a first predetermined value and less than or equal to a second predetermined value is set as a weighted synthesis target.

As described above, the operation switching determination circuit 114 can switch the operation / stop of the individual frequency error detection circuits 108 and 109, whereby the operation state of the frequency error detection circuit 115 can be controlled.
Instead of stopping the operations of the individual frequency error detection circuits 108 and 109, the weighting coefficient for the correction amount weighting synthesis in the correction amount weighting synthesis circuit 110 may be adjusted. For example, by setting the frequency error weighting coefficient in a specific branch to 0, it is possible to obtain substantially the same effect as when the individual frequency error detection circuits 108 and 109 in that branch are stopped.

(Operation of receiver 100)
Next, the operation of the receiver 100 will be described.
Signals received by the antennas 101 and 102 are lowered to the baseband by the high frequency circuits 116 and 117 and converted into digital signals by the A / D converters 118 and 119. This digital signal includes a frequency error from the transmission frequency on the transmission side.
The received signal converted into the digital signal is multiplied by the correction frequency signal generated by the NCOs 105 and 106 in the multipliers 103 and 104 to remove the frequency error, and is demodulated and decoded by the diversity demodulation circuit 107. The

  The RSSI value of the received signal is measured by the RSSI measurement circuits 111 and 112 and compared by the comparator 113. In the operation switching determination circuit 114, according to the received signal level, (1) a frequency error detection value of one reception branch, (2) a weighted composite value of frequency error detection values in a plurality of branches (for example, AGC for each branch) The frequency error correction is switched based on which of the weighted and synthesized values according to the gain control state.

In the present embodiment, the following effects can be expected.
(1) Even when the S / N of all receiving systems is poor or when the frequency error estimated value varies from antenna to antenna, a highly reliable estimated value can be determined, and the receiving characteristics can be improved. That is, by using the detected reception level (for example, RSSI value) as a coefficient of branch reliability and using it for weighted synthesis of the frequency error estimation value in AFC, highly reliable AFC can be performed. That is, reception quality can be improved by robust AFC with high error correction accuracy.
If the intensity of the input signal is excessive and the signal quality deteriorates even if AGC is performed, the accuracy of this estimation is improved by not using the excessively strong signal for frequency error estimation. be able to.

(2) Only one or all of the individual frequency error detection circuits 108 and 109 for AFC can be switched according to the state of the reception level at each antenna 101 and 102, thereby reducing power consumption. Can be planned.

(Modification of the first embodiment)
FIG. 2 is a block diagram showing a configuration of a receiver 100a according to a modification of the first embodiment of the present invention.
The receiver 100a includes antennas 101 and 102, multipliers 103 and 104, NCO (Numerical Controlled Oscillator) 105 and 106, a diversity demodulation circuit 107, a frequency error detection circuit 115, A-RSSI measurement circuits 111a and 112a, and a D-RSSI measurement. Circuits 111b and 112b, comparator 113, operation switching determination circuit 114, high frequency circuits 116 and 117, A / D converters 118 and 119, AGC amplifiers 120 and 121, AGC control circuits 122 and 123, weight coefficient determination unit 126, look An up table (LUT) 127 is included.

  That is, the receiver 100a replaces the RSSI measurement circuits 111 and 112 of the receiver 100 with A-RSSI measurement circuits 111a and 112a, and D-RSSI measurement circuits 111b and 112b, and AGC amplifiers 120 and 121, AGC control circuits 122 and 123, A weighting factor determination unit 126 and a lookup table (LUT) 127 are added.

The A-RSSI measurement circuits 111a and 112a measure the RSSI values of the analog signals output from the high frequency circuits 116 and 117, respectively.
The D-RSSI measurement circuits 111b and 112b measure the RSSI values of the digital signals output from the A / D converters 118 and 119, respectively.
The AGC amplifiers 120 and 121 are variable amplification factor amplifiers that amplify signals output from the high frequency circuits 116 and 117, respectively, and are used for AGC (Automatic Gain Control). The signal amplitude gain is adjusted so that it falls within the input range of the A / D converters 118 and 119.
The AGC control circuits 122 and 123 are control circuits that control the amplification factors of the AGC amplifiers 120 and 121 based on the RSSI values output from the A-RSSI measurement circuits 111a and 112a and the D-RSSI measurement circuits 111b and 112b, respectively. Used for AGC of signals output from the high-frequency circuits 116 and 117.

  The weighting factor determination unit 126 refers to the lookup table 127, and estimates frequency errors detected from the individual frequency error detection circuits 108 and 109 based on the A-RSSI values output from the A-RSSI measurement circuits 111a and 112a. A weighting factor for weighting and combining values is determined, and the determined weighting factor is output.

  The look-up table 127 is a table that represents a reception level (for example, an A-RSSI value) and a weighting coefficient Mj. This weight is considered to represent the reliability of the received signal in each branch. The look-up table 127 can be accessed and determined in a short time by storing it in the memory. At this time, the memory can be rewritten by register settings in the circuit.

FIG. 3 is a schematic diagram illustrating an example of the lookup table 127. The reception level (signal strength) is divided into areas A to E according to the reception level (for example, A-RSSI value), and a weighting coefficient Mj is determined corresponding to this area.
As shown in this figure, in regions A to C, the weight coefficient Mj increases as the received signal strength increases. This is because the signal strength is considered to be higher when the signal strength is higher to some extent.
On the other hand, in areas D and E, the weight coefficient Mj decreases on the contrary when the received signal strength increases, and in area E, the weight coefficient Mj becomes 0. This is because the weight coefficient Mj (priority) is determined in consideration of the possibility that the received signal is saturated. That is, the weight of the signal that enters the saturation region because the received signal power is too large is reduced.
Note that the boundary threshold value and the number of regions for region determination are not limited to those in FIG. 3, and there are various combinations.

(Operation of receiver 100a)
Next, the operation of the receiver 100a will be described.
Usually, a synchronization signal for demodulation such as AGC or AFC uses a preamble or header near the beginning of the frame of the received signal, or a pilot signal included in the received frame.
In the weighted AFC processing based on the reception level, it is desirable that the measurement accuracy of the reception level is high. For this purpose, it is conceivable to perform AFC processing using a reception signal obtained by averaging A / D converted samples after completion of adjustment of the A / D converter input range in AGC. However, when waiting for completion of the AGC process, it may take time for the initial synchronization of the frequency in the AFC.

Here, it is considered that the AFC process can be executed without waiting for the completion of the AGC process. In particular, the determination of the likelihood (weighting coefficient) when performing weighted synthesis with AFC will be described.
In the present embodiment, the likelihood is assigned to each of the antennas 101 and 102 at the time when AGC gain switching is performed stepwise and a rough region determination is performed by AGC.
As a result, AFC can be started in the middle of AGC processing (before or simultaneously with gain switching of AGC), AFC is performed at an early stage of the preamble, and early synchronization pull-in can be completed early. Further, instead of early completion of the initial synchronization pull-in, it is possible to take time for the initial synchronization pull-in and to establish synchronization with higher accuracy.

FIG. 4 is a flowchart illustrating an example of a processing procedure in the receiver 100a.
(1) The intensity (for example, analog RSSI) of the signals received by the high frequency circuits 116 and 117 is measured by the A-RSSI measurement circuits 111a and 112a (step S11).
Further, the reception area is determined using the measured reception level (S12). This determination result is used for gain adjustment as the first stage of AGC.

(2) After this determination, AGC and AFC can be executed substantially in parallel. That is, as shown below, AFC can be executed without waiting for completion of AGC.
a. AGC processing An AGC initial gain is obtained based on the determined reception area (S13), and the gains of the AGC amplifiers 120 and 121 are controlled from the AGC control circuits 122 and 123 based on the initial gain.
Thereafter, as a second stage of AGC, the digital RSSI is measured by the D-RSSI measuring circuits 111b and 112b using the digital signal after A / D conversion (S14), and more precise AGC control is performed based on the measured digital RSSI. (S15)

b. AFC Processing In parallel with the AGC processing, the weighting coefficient determination unit 126 refers to the look-up table (LUT) 127 (S16), and obtains a weighted synthesis coefficient of the frequency error estimated value by AFC.
Specifically, the weighted synthesis coefficient W_i is calculated by the following equation (1).
W_i = Mi / Σ (Mj) ...... Formula (1)
Using the obtained weighting coefficient, the correction amount weighting synthesis circuit 110 performs weighting synthesis (S17). Thereby, the dispersion | variation in the correction amount detected in each branch is smoothed.

In the present embodiment, in addition to the effects (1) and (2) in the first embodiment, the following effect (3) can be expected.
(3) AGC processing and AFC processing that have been conventionally performed serially, but AFC processing can be started in the middle of AGC processing. That is, the reception level (for example, RSSI) detected by the analog unit is used for rough reception area determination as the first stage of AGC, and the determined area information is used for weighted synthesis of frequency error estimation values in AFC.
For this reason, the frequency pull-in can be made faster. Sufficient time can be secured until the demodulation process is started, and as a result, stable frequency acquisition can be realized.
Further, the accuracy of frequency error estimation can be further increased by using the remaining time.

(Second Embodiment)
FIG. 5 is a block diagram showing a configuration of a receiver 200 according to the second embodiment of the present invention.
Receiver 200 includes antennas 201 and 202, multipliers 203 and 204, NCO (Numerical Controlled Oscillator) 205 and 206, diversity demodulation circuit 207, frequency error detection circuit 208, S / N maximum value detection circuit 209, and S / N measurement. A circuit 210, a memory 211, a lookup table 212, a multiplier 213, an adder 214, a frequency error determination circuit 215, high frequency circuits 216 and 217, and A / D converters 218 and 219 are included.

The antennas 201 and 202 are receiving elements that receive radio waves, and the reception states thereof are different because the arrangement thereof is different. In the present embodiment, only two antennas 201 and 202 are described. However, the number of antennas and reception branches may be more than two.
Each of the high frequency circuits 216 and 217 includes a filter, an amplifier, a down converter, a quadrature demodulator, and the like, and reduces the frequency of the signal received by the antennas 201 and 202 from the carrier band to the base band.
The A / D converters 218 and 219 convert analog signals output from the high frequency circuits 216 and 217, respectively, into digital signals and output the digital signals.

NCO (Numerical Controlled Oscillators) 205 and 206 are numerically controlled oscillators, and based on the frequency error signal output from the frequency error determination circuit 215, a signal (correction frequency) of a correction frequency (phase rotation) component e ^ (− jθ). Signal).
Multipliers 203 and 204 multiply the reception signals output from the A / D converters 218 and 219 by the correction frequency signals output from the NCOs 205 and 206, respectively. As a result, the phase of the complex signal can be changed.
The diversity demodulation circuit 207 performs diversity demodulation / decoding based on the signal with the frequency error corrected from the multipliers 203 and 204 corrected.
Instead of diversity demodulation circuit 207, a MIMO demodulation processing circuit that separates and extracts a plurality of different transmission data sequences can be used.

The look-up table 212 is a table that stores sets of orthogonal weights (for example, phase shift sets of 0 °, 90 °, and 180 °).
FIG. 6 is a schematic diagram showing an example of the lookup table 212. A set of orthogonal weights W1 to W3 of the antennas 1 and 2 (corresponding to the antennas 201 and 202) is shown.
The reason why a plurality of sets are represented is to select an optimum one (specifically, one having the maximum S / N ratio) from the set. This is equivalent to S / N improvement by extending a spatial orthogonal beam in principle. When the spatial correlation between the antennas 201 and 202 is high, or when the received signal is phase-synthesized by multipath or the like, the signal level is increased. In such a case, the S / N ratio can be improved.

  FIG. 7 is a schematic diagram showing another example of the lookup table. A set of orthogonal weights W1 to W4 of the antennas 1 to 4 is shown. That is, this figure shows a look-up table when the antenna has four elements. 5, two sets of antennas 201 and 202, multipliers 203 and 204, NCOs (Numerical Controlled Oscillators) 205 and 206, multipliers 213, high-frequency circuits 216 and 217, and A / D converters 218 and 219 are provided. This is a case of having four sets.

  Multiplier 213 adds orthogonal weights based on lookup table 212 to reception signals output from antennas 201 and 202. The adder 214 adds the reception signals obtained by integrating the orthogonal weights by the multiplier 213. These multiplier 213 and adder 214 perform orthogonal weight calculation (generally weighted synthesis) of signals.

The frequency error detection circuit 208 detects the frequency error of the orthogonal weight weighted signal output from the adder 214.
The S / N measurement circuit 210 measures the S / N ratio of the orthogonal weight weighted signal output from the adder 214.
The memory 211 stores the frequency error detected by the frequency error detection circuit 208 and the S / N ratio measured by the S / N measurement circuit 210. That is, trial / measurement results of each of a plurality of sets of orthogonal weights stored in the lookup table 212 are stored in the memory 211.
The S / N maximum value detection circuit 209 selects the maximum value from the S / N ratios stored in the memory 211. Further, the S / N maximum value detection circuit 209 selects a set of orthogonal weights at this time from the look-up table 212 and uses them for the orthogonal weight calculation by the multiplier 213 and the multiplier 213.
The frequency error determination circuit 215 selects a frequency error corresponding to the maximum S / N ratio detected by the S / N maximum value detection circuit 209 from the memory 211.

(Operation of receiver 200)
Next, the operation of the receiver 200 will be described.
Signals received by the antennas 201 and 202 are weighted with orthogonal weights by the multiplier 213 and the adder 214, and a frequency error (Δf) is detected.
The received signal is weighted by each of a plurality of sets of orthogonal weights represented in the lookup table 212, and the S / N measurement circuit 210 measures the S / N while calculating the frequency error by the frequency error determination circuit 215. . Trial / measurement results for each set of orthogonal weights are sequentially stored in the memory 211.
After all the sets of orthogonal weights have been tried, the S / N maximum value detection circuit 209 detects the highest S / N, and the frequency error Δf corresponding to the set of orthogonal weights at this time is selected.
The accuracy of frequency error estimation can be improved by trying a plurality of orthogonal weight groups and forcibly creating a signal with a high S / N ratio.

(Modification of the second embodiment)
A modification of the second embodiment will be described below.
(1) In the second embodiment, weighting is performed using a set of orthogonal weights. That is, the phase is rotated. On the other hand, it is possible to weight not only the phase but also the amplitude of the signals received by the antennas 201 and 202, and the S / N is further improved. For this weighting, for example, an AGC control amplitude or an RSSI value can be used.

(2) In the second embodiment, all fixed weights described in the lookup table 212 are tried as they are. On the other hand, it is also possible to adaptively change the weight by training using a received signal and a known signal.
This training method uses beam forming algorithms based on MMSE (Minimum Mean Square Error) such as LMS (Least Mean Squares), SMI (Sample Matrix Inverse), and RLS (Recursive Least Square). it can. As a result, a more accurate frequency error Δf can be obtained, and AFC with higher reliability is possible.

In the LMS algorithm, the following equation (2) is sequentially updated so as to minimize the error signal ε (t), and the converged weight is used as a solution.
W (k) = W (k) + ε * (k) x (k)
y (k) = W ^H (k) x (k)
ε (k) = r (k) −y (k)
W (k) = [W ₁ (k), W ₂ (k),... W _M (k)] ^T ...... Equation (2)
Here, x (k) is an input signal vector, y (k) is an output signal vector, w (k) is a weight vector, r (k) is a predetermined reference signal sequence, * is a complex conjugate, and ^H is a complex conjugate transpose. Means. Here, the weight update is performed for each sample k.

(3) As another form of the weighting circuit, a frequency response estimation value corresponding to the norm of the transmission channel response estimation value of each branch is obtained by using the transmission channel response obtained in the subsequent diversity demodulation circuit or MIMO demodulation circuit. Weighting can also be performed. The transmission path response can be estimated by performing a correlation process with a received signal using a known pilot signal or the like, and is an essential process in the MIMO demodulation process and the synthesis diversity process.
With such a configuration, it is possible to grasp the reception state with high accuracy by digital signal processing, and it is possible to realize more precise frequency error correction.

For example, when the transmission path response of the antenna 101 is H ₁ = h ₀ δ (t) + h ₁ δ (t−τ ₁ ) + h ₂ δ (t−τ ₂ ), 1-norm: ‖H ₁ ‖ _1, the 2-norm: ‖H ₁ ‖ ₂ is expressed by the following equation (3).
‖H _{1 １ 1} = | h ₀ | + | h ₁ | + | h ₂ |
‖H ₁ ‖ ₂ = (| h ₀ | ² + | h ₁ | ² + | h ₂ | ² ) ^1/2 …… Formula (3)
Here, h0, h1, h2 is the delay time _0, τ _1, represents the complex amplitude in tau _2. By measuring the norms H ₁ and H ₂ for each of the antennas 101 and 102, weighting proportional to the size of the essential path component of the received signal can be performed instead of the reception level.

(4) In some communication systems, follow-up AFC may be performed to sequentially correct frequency errors even after initial frequency synchronization is established. For example, the AFC process is repeated periodically. In this case, all the above methods can be applied, and the same effect can be obtained.

(Other embodiments)
The present invention is not limited to the above-described embodiment, and the constituent elements can be expanded and modified without departing from the gist thereof. Extended and modified embodiments are also included in the technical scope of the present invention.
In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

It is a figure showing the receiver which concerns on 1st Embodiment of this invention. It is a figure showing the receiver which concerns on the modification of 1st Embodiment of this invention. It is a schematic diagram showing an example of a lookup table. FIG. 3 is a flowchart illustrating an example of a processing procedure in the receiver illustrated in FIG. 2. It is a block diagram which shows the structure of the receiver which concerns on the 2nd Embodiment of this invention. It is a schematic diagram showing an example of a lookup table. It is a schematic diagram showing the other example of a lookup table.

Explanation of symbols

  100, 100a, 200 ... receiver, 101, 102, 201, 202 ... antenna, 103, 104, 203, 204 ... multiplier, 105, 106, 205, 206 ... NCO, 107, 207 ... diversity demodulation circuit, 108, 109, 208 ... Individual frequency error detection circuit, 110 ... Synthesis circuit, 111, 112 ... RSSI measurement circuit, 111a, 112a ... A-RSSI measurement circuit, 111b, 112b ... D-RSSI measurement circuit, 113 ... Comparator, 114 ... Operation switching determination circuit, 115 ... frequency error detection circuit, 116, 117, 216, 217 ... high frequency circuit, 118, 119, 218, 219 ... A / D converter, 120, 121 ... AGC amplifier, 122, 123 ... AGC control Circuit 126 ... Weight coefficient determination unit 127, 212 ... Look-up table 209 ... S / N the maximum value detecting circuit, 210 ... S / N measuring circuit, 211 ... memory, 213 ... multiplier, 214 ... adder, 215 ... frequency error determining circuit

Claims (4)

Signal combining means for weighted combining the first and second signals received by the first and second antennas;
S / N ratio detection means for detecting the S / N ratio of the signal synthesized by the signal synthesis means;
Weight determination means for determining weights used for signal synthesis in the signal synthesis means based on the detection result in the S / N ratio detection means;
Frequency error detection means for detecting a frequency error of the signal synthesized by the signal synthesis means;
First and second phase correcting means for correcting the phases of the first and second received signals based on the frequency error detected by the frequency error detecting means;
Demodulation means for performing demodulation using the first and second signals corrected by the first and second phase correction means;
A receiving apparatus comprising: A table representing a plurality of combinations of weights for weighting and synthesizing the first and second signals by the signal synthesis means;
The weight determining means includes means for selecting a weighting combination from the table;
Claim 1 Symbol placement of the receiving apparatus, characterized in that. The combination of the weighting represented in the table, the first, claim 2 Symbol placement of the receiving apparatus, characterized in that the relative phase of the second signal is a combination of approximately 90 ° alters weighted. The combination of the weighting represented in the table, the first, receiving apparatus according to claim 2 Symbol mounting characterized in that it is a combination of weighting to change the relative intensity of the second signal.

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