JP3965805B2 - Code sequence generator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a code sequence generator, and more particularly to a code sequence generator that generates a code sequence such as a longest sequence (M sequence) or a Gold sequence.
[0002]
[Prior art]
Digital code sequences are used in a wide range of fields such as concealing digital information and spreading codes for signal band expansion in spread spectrum communication. In particular, the M-sequence is used as a random code or a noise source because its period is very long and the autocorrelation characteristics are impulse-like.
[0003]
FIG. 4 is a block diagram illustrating a schematic configuration of a code sequence generator 101 that has been conventionally used to generate an M sequence.
The M-sequence code sequence generator 101 includes an initial value setting unit 102, a shift register 103, and an exclusive OR operation circuit 104.
[0004]
The shift register 103 having an n + 1 bit length is configured by connecting flip-flops D0 to Dn in an n + 1 stage series.
The exclusive OR operation circuit 104 outputs the output of the last stage (n + 1 stage) flip-flop Dn in the shift register 103 and any stage flip-flop (for example, the third stage flip-flop corresponding to the code sequence to be generated). The exclusive OR with the output of D2) is taken, and the result is fed back to the first flip-flop D0.
[0005]
Initial values C (= c0, c1, c2,..., Cn−1, cn) set by the user using the initial value setting unit 102 are set in the flip-flops D0 to Dn, respectively. Then, a clock (not shown) is given to each of the flip-flops D0 to Dn, and the contents are sequentially shifted to the flip-flops of the next stage, so that the cycle 2 ^{n + 1} −1 M-sequence code sequences are generated, and the code sequences are sequentially output from the flip-flop Dn according to the clock.
[0006]
In the code sequence generator 101 configured in this manner, when an arbitrary number of clocks are given after setting an arbitrary initial value C, a code sequence shifted by the number of clocks is generated. That is, by changing the number of clocks to be given, a code sequence can be generated from an arbitrary phase corresponding to the number of clocks. Using this, a method has been proposed in which two code sequences having a phase shift by an arbitrary number of clocks are simultaneously generated by using two code sequence generators 101.
[0007]
FIG. 5 is a block diagram showing a schematic configuration of a code sequence generator 201 capable of generating two M-sequence codes whose phases are shifted by an arbitrary number of clocks.
The code sequence generator 201 includes two code sequence generators 101 that share the initial value setting unit 102 (hereinafter referred to as “101a” and “101b” to distinguish the two).
[0008]
FIG. 6 is a timing chart showing the operation of the code sequence generator 201.
In order to operate the code sequence generator 201, first, the same initial value C set by the user using the initial value setting unit 102 for each of the flip-flops D0 to Dn constituting the code sequence generators 101a and 101b. (= C0, c1, c2... Cn-1, cn) is set. Next, an arbitrary number of clocks are given in advance to the flip-flops D0 to Dn of the code sequence generator 101b, and the contents are sequentially shifted to the next flip-flop. Thereafter, the same clock is applied to the flip-flops D0 to Dn of the code sequence generators 101a and 101b. As a result, with respect to the code sequence α generated by the code sequence generator 101a, the code sequence generator 101b generates a code sequence β whose phase has been advanced by a predetermined number of clocks. That is, an offset amount corresponding to the number of clocks previously given to the code sequence generator 101b is generated in the code sequences α and β generated by the code sequence generators 101a and 101b.
[0009]
Here, in order to increase the offset amount of the code sequences α and β of the code sequence generators 101a and 101b, it is necessary to increase the number of clocks given in advance to the code sequence generator 101b, and the initial value C It takes a very long time to start generation of code sequences α and β whose phases are shifted from the respective code sequence generators 101a and 101b.
[0010]
By the way, even when a code sequence having an arbitrary phase is generated from the code sequence generator 101, in order to generate a code sequence from an arbitrary phase in a code sequence having a very long period, the number of clocks given in advance is increased. It takes a very long time from the setting of the initial value C to the start of generation of a desired code sequence.
[0011]
[Problems to be solved by the invention]
Therefore, as disclosed in Japanese Patent Application Laid-Open No. 8-18550, by repeatedly performing linear transformation defined by (n + 1) × (n + 1) matrix A on n-bit data X stored in a register. A code sequence generator for generating a code sequence Y = AmX (m is a positive integer) has been proposed. The code sequence generator generates a matrix A raised to the power of pj (A) for each of predetermined t + 1 positive integers pj (j = 0, 1, 2,..., T). ^pj ), Means for decomposing the integer m into the form of the primary expression m = k0 + k1p1 + k2p2 +... Ktpt (k0, k1, k2..., Kt is 0 or an integer), k0, k1, Selection means for sequentially selecting a corresponding matrix from the storage means for non-zero among k2..., kt, and matrix operation Y = (A for non-zero among k0, k1, k2,. ^p0 (A ^p1 ) ^k1 (A ^p2 ) ^k2 ... (A ^pt ) ^kt Computing means for executing X. Therefore, by using a plurality of matrices selected by the selection means in combination, it is possible to set the register state at high speed and generate a code sequence from an arbitrary phase.
[0012]
However, in the code sequence generator described in the publication, the control for making the selection means sequentially select a combination of corresponding matrices from the storage means is complicated, and a large-scale circuit configuration is used for the control. There was a problem of requiring a control circuit. The present invention has been made to solve the above problems, and its purpose is to generate a plurality of code sequences of the same sequence with an arbitrary offset amount before the start of code sequence generation. An object of the present invention is to provide a code sequence generator with a small circuit scale that can shorten the time required. Another object of the present invention is to provide a code sequence generator with a small circuit scale that can reduce the time required to start generation of a code sequence when generating a code sequence from an arbitrary phase. It is in.
[0013]
[Means for Solving the Problems]
Made to achieve this goal First The invention includes a first code sequence generator, a second code sequence generator, and an arithmetic means. The first code sequence generator takes an exclusive OR of the first shift register and the output of the final stage of the first shift register and the output of an arbitrary stage, and the exclusive OR is calculated as the first shift register. A first exclusive OR circuit that feeds back to the first stage of the first shift register, sets an initial value to each stage of the first shift register, provides a clock to each stage of the first shift register, and sequentially describes the contents of each stage. A first code sequence is generated by shifting to the next stage, and the first code series is sequentially output from the last stage of the first shift register according to the clock. The second code sequence generator takes an exclusive OR of the second shift register and the output of the final stage of the second shift register and the output of an arbitrary stage, and the exclusive OR is calculated as the second shift register. And a second exclusive OR circuit that feeds back to the first stage, sets initial values to each stage of the second shift register, provides a clock to each stage of the second shift register, and sequentially describes the contents of each stage. A second code sequence is generated by shifting to the next stage, and the second code series is sequentially output from the last stage of the second shift register according to the clock. The computing means includes an initial value set in each stage of the second shift register, and a matrix composed of matrix elements set in advance corresponding to an offset amount between the first code sequence and the second code sequence. Matrix operation is performed, and the matrix operation result is set as an initial value of each stage of the first shift register.
[0014]
Therefore, First According to this invention, it is not necessary to give a clock to only the first code sequence generator in advance in order to set the offset amount between the first code sequence and the second code sequence. Further, the time required for matrix calculation in the calculation means corresponds to the number of clocks given in advance to the first code sequence generator in order to set the offset amounts of the first and second code sequences in the conventional code sequence generator. It is very short compared to the time to do. for that reason, First According to this invention, it is possible to reduce the time required from the initial value to the generation start of the first and second code sequences in which an arbitrary offset amount is set.
[0015]
next, Second The invention includes a first code generator and an arithmetic means. The first code generator takes an exclusive OR of the first shift register and the output of the last stage of the first shift register and the output of an arbitrary stage, and the exclusive OR is obtained from the first shift register. A first exclusive OR circuit that feeds back to the first stage, sets an initial value to each stage of the first shift register, applies a clock to each stage of the first shift register, and sequentially follows the contents of each stage. The first code sequence is generated by shifting to the stage, and the first code series is sequentially output from the last stage of the first shift register according to the clock. The calculation means performs a matrix calculation of an initial value corresponding to each stage of the first shift register and a matrix composed of matrix elements set in advance corresponding to an arbitrary phase of the first code sequence, and the matrix An operation result is set as an initial value of each stage of the first shift register.
[0016]
Therefore, Second According to this invention, when generating a code sequence of an arbitrary phase, it is not necessary to give a clock to the first code sequence generator in advance. Further, the time required for the matrix calculation in the calculation means is compared with the time corresponding to the number of clocks given in advance to the first code sequence generator when generating a code sequence of an arbitrary phase in the conventional code sequence generator. Very short. for that reason, Second According to this invention, it is possible to reduce the time required from the setting of the initial value to the start of generation of a code sequence having an arbitrary phase.
[0017]
by the way, Third Like the invention of First Or Second of invention The computing means includes a plurality of computing units respectively corresponding to the respective stages of the first shift register, and each of the computing units includes a matrix element of the matrix corresponding to each stage of the first shift register and the initial stage. You may make it perform matrix operation with a value.
[0018]
In this way, since the matrix operation of the matrix element of the matrix corresponding to each stage of the first shift register and the initial value are simultaneously calculated by the separate arithmetic units, the initial value is set. It is possible to further reduce the time required to start generating a code sequence having an arbitrary phase.
[0019]
Also, 4th Like the invention of First Or Second of invention The computing means includes a computing unit that sequentially performs matrix computation of the matrix elements of the matrix corresponding to each stage of the first shift register and the initial value for each stage, and the computing unit sequentially calculates the computing unit. There may be provided switching means for switching and setting the matrix operation result for each stage of the first shift register as the initial value of each stage of the first shift register for each stage.
[0020]
In this way, the matrix operation of the matrix element of the matrix corresponding to each stage of the first shift register and the initial value is performed only by providing one arithmetic unit, and the matrix operation result is obtained as the first shift register. The initial value of each stage can be switched and set for each stage. Therefore, as compared with the case where a plurality of arithmetic units corresponding to the respective stages of the first shift register are provided, the overall circuit scale can be reduced by the amount that the number of arithmetic units can be reduced.
[0021]
next, 5th The invention includes a code generator and an arithmetic means. The code generator takes an exclusive OR of the shift register and the output of the last stage of the shift register and the output of an arbitrary stage, and returns the exclusive OR to the first stage of the shift register. A first code sequence is generated by setting an initial value to each stage of the shift register, supplying a clock to each stage of the shift register, and sequentially shifting the contents of each stage to the next stage, The first code sequence is sequentially output from the last stage of the shift register according to the clock. The computing means uses the output of each stage of the shift register as an initial value, and a matrix composed of the initial value and a matrix element set in advance corresponding to the offset amount between the first code sequence and the second code sequence. The second code sequence is generated by performing the matrix operation.
[0022]
Therefore, 5th According to this invention, it is not necessary to give a clock to the code sequence generator in advance in order to set the offset amount between the first code sequence and the second code sequence. Further, the time required for matrix calculation in the calculation means is a time corresponding to the number of clocks given in advance to the code sequence generator in order to set the offset amounts of the first and second code sequences in the conventional code sequence generator. It is very short compared to. for that reason, First According to this invention, it is possible to reduce the time required from the initial value to the generation start of the first and second code sequences in which an arbitrary offset amount is set. Further, the computing means can generate the second code sequence by providing only one computing unit. The first and second code sequences can be generated only by providing one code sequence generator including a shift register and an exclusive OR circuit. for that reason, First Compared with the case where the first and second code sequence generators are provided as in the present invention, the overall circuit scale can be reduced.
[0023]
by the way, 6th Like the invention of 1st to 5th Any of Invention In the above, a setting means for setting the matrix may be provided, and the calculation means may perform a matrix calculation of a matrix element corresponding to an arbitrary matrix set by the setting means and the initial value.
[0024]
In this way, when changing the offset amount of the first and second code sequences or changing the phase of the code sequence, each matrix element of the matrix set using the setting means can be changed as appropriate to facilitate the change. Can respond. That is, since it becomes easy to set in advance a matrix representing the register states of the first shift registers that are discretely separated corresponding to the offset amounts of the first and second code sequences, This is particularly effective when two code sequences are generated or when a code sequence is generated from an arbitrary phase in a code sequence having a very long period.
[0025]
In the embodiments of the invention described below, the “first code sequence generator” described in the claims or the means for solving the problem corresponds to the code sequence generator 101b, and similarly “second code sequence”. The “sequence generator” corresponds to the code sequence generator 101a, the “first code sequence” corresponds to the code sequence β, the “second code sequence” corresponds to the code sequence α, and the “calculation means” calculates The device group 3 or the arithmetic unit 14 and the switching circuit 15 are configured. Similarly, the “setting means” includes the matrix element setting unit 2 or the memory 12 and the reading circuit 13.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. In the first embodiment, the same constituent members as those of the conventional embodiment shown in FIG. 5 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0027]
FIG. 1 is a block diagram illustrating a schematic configuration of a code sequence generator 1 according to the first embodiment.
The code sequence generator 1 includes an initial value setting unit 102, code sequence generators 101a and 101b, a matrix element setting unit 2, and a computing unit group 3.
[0028]
The computing unit group 3 is composed of n + 1 computing units P0 to Pn.
Initial values C (= c0, c1, c2,..., Cn−1, cn) set by the user using the initial value setting unit 102 are the flip-flops D0 to Dn that constitute the shift register 103 of the code sequence generator 101a. And set to each of the calculators P0 to Pn of the calculator group 3. That is, the initial value c0 is set in the flip-flop D0, the initial value c1 is set in the flip-flop D1,..., And the initial value cn is set in the flip-flop Dn. For the flip-flops D0 to Dn, initial values c0 to cn corresponding to the ascending order of the number of stages of the flip-flops (ascending order of the signs) are set one by one in ascending order. Further, initial values C (all initial values c0 to cn) are set in the respective arithmetic units P0 to Pn.
[0029]
The matrix elements a0, a1, a2,..., An−1, an of the (n + 1) × (n + 1) matrix A set by the user using the matrix element setting unit 2 are assigned to the calculators P0 to Pn of the calculator group 3, respectively. Set. That is, the matrix element a0 is set in the computing unit P0, the matrix element a1 is set in the computing unit P1,..., And the matrix element an is set in the computing unit Pn. The matrix elements a0 to an corresponding to the ascending order of the arithmetic unit are set one by one in ascending order.
[0030]
Each of the arithmetic units P0 to Pn performs a matrix operation on the set initial value C (= c0 to cn) and the matrix elements a0 to an, and calculates each matrix operation result c′0 to c′n. That is, the calculator P0 calculates the matrix calculation result c′0 of the initial value C and the matrix element a0, and the calculator P1 calculates the matrix calculation result c′1 of the initial value C and the matrix element a1. The calculators Pn calculate the matrix calculation results c′n of the initial values C and the matrix elements an, and the calculators P0 to Pn calculate the matrix calculation results c′0 to c′n, respectively.
[0031]
The matrix calculation results c′0 to c′n are set as initial values in the flip-flops D0 to Dn constituting the shift register 103 of the code sequence generator 101b. That is, the matrix operation result c′0 is set in the flip-flop D0, the matrix operation result c′1 is set in the flip-flop D1,..., And the matrix operation result c′n is set in the flip-flop Dn. , For each flip-flop D0 to Dn connected to the n + 1 stage series, the matrix operation results (initial values) c′0 to c′n corresponding to the ascending order (sign ascending order) of the flip-flops are in ascending order. Set one by one.
[0032]
As described above, the initial values c0 to cn are set in the flip-flops D0 to Dn of the code sequence generator 101a, and the initial values c′0 are set in the flip-flops D0 to Dn of the code sequence generator 101b. In the state where .about.c'n is set, the same clock is given to each flip-flop D0 to Dn of each code sequence generator 101a, 101b. As a result, the cycle 2 from the code sequence generator 101a. ^{n + 1} −1 M-sequence code sequence α is generated at the same time as a cycle 2 from the code sequence generator 101b. ^{n + 1} −1 M-sequence code sequence β is generated.
[0033]
Here, in order to generate a desired offset amount in each of the code sequences α and β, the offset amount may be set for each of the initial values c0 to cn and each of the initial values c′0 to c′n. For this purpose, the matrix element a0 is set so that the offset amount is set to each initial value c0, c′0, and the matrix element a1 is set so that the offset amount is set to each initial value c1, c′1. Set ..... matrix A including matrix elements a0 to an corresponding to the offset amount, such as setting the matrix element an so that the offset amount is set to the initial values cn and c'n. Should be set.
[0034]
That is, in the conventional code sequence generator 201 shown in FIG. 5, an arbitrary number of clocks are given in advance only to the flip-flops D0 to Dn of the code sequence generator 101b, and then each code sequence generator 101a, By giving the same clock to each of the flip-flops D0 to Dn of 101b, an offset amount corresponding to the number of clocks previously given to the code sequence generator 101b is generated in each of the code sequences α and β. Therefore, as shown in FIG. 6, the code sequence generator is set between the time when the initial value C is set and the generation of the code sequences α and β having offset amounts from the code sequence generators 101 a and 101 b. A time corresponding to the number of clocks previously given to 101b is required.
[0035]
On the other hand, in the code sequence generator 1 of the first embodiment, a matrix A composed of the matrix elements a0 to an corresponding to the offset amounts of the code sequences α and β is previously stored using the matrix element setting unit 2. The matrix calculation result of the initial value C to be given to the code sequence generator 101a and each matrix element a0 to an is calculated by each of the calculators P0 to Pn, and the matrix calculation result of the code sequence generator 101b is set. The initial values c′0 to c′n are given.
[0036]
Therefore, the code sequence generator 1 does not need to provide a clock only to the code sequence generator 101b in advance in order to set the offset amount of each code sequence α, β. In addition, the time required for matrix calculation in each of the calculators P0 to Pn is the number of clocks that are given in advance to the code sequence generator 101b in order to set the offset amounts of the code sequences α and β in the conventional code sequence generator 201. It is very short compared to the time equivalent to minutes.
[0037]
Therefore, according to the code sequence generator 1, it is possible to shorten the time required from the setting of the initial value C to the start of generation of the code sequences α and β for which an arbitrary offset amount is set.
In order to change the offset amounts of the code sequences α and β, the matrix elements a0 to an of the matrix A set using the matrix element setting unit 2 may be changed as appropriate. That is, a matrix A that represents the register states (contents of the flip-flops D0 to Dn) of the shift registers 103 that are discretely separated corresponding to the offset amounts of the code sequences α and β may be set in advance. Therefore, the code sequence generator 1 is particularly effective when generating each code sequence α, β having a large offset amount.
[0038]
The control operation of the code sequence generator 1 is almost the same as the control operation of the conventional code sequence generator 201, and the circuit scale of a control circuit (not shown) for performing the control does not increase.
(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to the drawings. In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
[0039]
FIG. 2 is a block diagram illustrating a schematic configuration of the code sequence generator 11 of the second embodiment.
The code sequence generator 11 includes an initial value setting unit 102, code sequence generators 101 a and 101 b, a memory 12, a reading circuit 13, a computing unit 14, and a switching circuit 15.
[0040]
The initial value C (= c0 to cn) set by the user using the initial value setting unit 102 is set in each of the flip-flops D0 to Dn constituting the shift register 103 of the code sequence generator 101a and the arithmetic unit 14 Set to
The memory 12 stores an (n + 1) × (n + 1) matrix A composed of matrix elements a0 to an.
[0041]
The reading circuit 13 sequentially reads the matrix elements a0 to an stored in the memory 12 in ascending order of the signs, and sets the read matrix elements am (m = 0, 1, 2,..., N) in the arithmetic unit 14. To do.
The computing unit 14 performs a matrix operation on the set matrix element am and the initial value C (= c0 to cn), and sequentially calculates each matrix operation result c′0 to c′n. That is, the computing unit 14 first calculates a matrix operation result c′0 between the initial value C and the matrix element a0, and then calculates a matrix operation result c′1 between the initial value C and the matrix element a1. ... Finally, the matrix calculation results c′0 to c′n are sequentially calculated such that the matrix calculation result c′n between the initial value C and the matrix element an is calculated.
[0042]
The switching circuit 15 selects and switches one by one the matrix calculation results c′0 to c′n calculated by the calculator 14, and uses the matrix calculation result that has been switched as an initial value as a shift register of the code sequence generator 101b. 103 is set in each flip-flop D0 to Dn. That is, the matrix operation result c′0 is set in the flip-flop D0, the matrix operation result c′1 is set in the flip-flop D1,..., And the matrix operation result c′n is set in the flip-flop Dn. , For each flip-flop D0 to Dn connected to the n + 1 stage series, the matrix operation results (initial values) c′0 to c′n corresponding to the ascending order (sign ascending order) of the flip-flops are in ascending order. One by one is set sequentially.
[0043]
As described above, the initial values c0 to cn are set in the flip-flops D0 to Dn of the code sequence generator 101a, and the initial values c′0 are set in the flip-flops D0 to Dn of the code sequence generator 101b. In the state where .about.c'n is set, the same clock is given to each flip-flop D0 to Dn of each code sequence generator 101a, 101b. As a result, the cycle 2 from the code sequence generator 101a. ^{n + 1} −1 M-sequence code sequence α is generated at the same time as a cycle 2 from the code sequence generator 101b. ^{n + 1} −1 M-sequence code sequence β is generated.
[0044]
Therefore, according to the code sequence generator 11 of the second embodiment, the same operation and effect as the code sequence generator 1 of the first embodiment can be obtained.
However, in the code sequence generator 11, the matrix elements a 0 to an of the matrix A stored in the memory 12 are sequentially read out by the reading circuit 13 and set in the calculator 14, and the matrix calculation results calculated by the calculator 14 are set. (Initial value) c′0 to c′n are selected and switched by the switching circuit 15 and set in the flip-flops D0 to Dn of the code sequence generator 101b. That is, by providing the readout circuit 13, it is possible to generate the n + 1-bit initial values c′0 to c′n with only one arithmetic unit 14. By providing the switching circuit 15, the initial values c′0 to c′n calculated by one arithmetic unit 14 can be set in the flip-flops D0 to Dn of the code sequence generator 101b, respectively. .
[0045]
On the other hand, in the code sequence generator 1 of the first embodiment, the initial values c′0 to c′n are calculated separately, and the initial values c′0 to c′n are calculated as the code sequence generator. In order to set the flip-flops D0 to Dn of the 101b, n + 1 computing units P0 to Pn are provided.
[0046]
Therefore, according to the code sequence generator 11, as compared with the code sequence generator 1, the entire circuit scale can be reduced by the amount that the number of arithmetic units can be reduced.
However, in the code sequence generator 11, first, the matrix elements a0 to an stored in the memory 12 are sequentially read out by the reading circuit 13, and then the initial values c'0 to 0 are calculated by the computing unit 14 based on the matrix elements. c′n is sequentially calculated, and then the initial value is sequentially set by the switching circuit 15 in each of the flip-flops D0 to Dn of the code sequence generator 101b. Therefore, compared to the code sequence generator 1, the code sequences α and β each having an arbitrary offset amount are set by the time required for these operations (operations of the readout circuit 13, the arithmetic unit 14, and the switching circuit 15). The time required to start generation becomes longer.
[0047]
However, the time required for the operations (operations of the readout circuit 13, the arithmetic unit 14, and the switching circuit 15) is determined by the code sequence generator in order to set the offset amounts of the code sequences α and β in the conventional code sequence generator 201. Compared with the time corresponding to the number of clocks given in advance to 101b, it is very short. Therefore, the code sequence generator 11 can also shorten the time required to start generating the code sequences α and β in which arbitrary offset amounts are set, as compared with the conventional code sequence generator 201.
[0048]
In addition, the operations of the readout circuit 13 and the switching circuit 15 simply perform predetermined procedures in sequence, and the control of the operation is simple. Therefore, the circuit scale of the control circuit (not shown) for performing the control is as follows. This is smaller than the circuit scale of the control circuit of the code sequence generator described in the above publication (Japanese Patent Laid-Open No. 8-18550). Therefore, according to the code sequence generator 11, as compared with the code sequence generator described in the publication, it is possible to reduce the overall circuit scale by an amount corresponding to a reduction in the circuit scale of the control circuit.
[0049]
(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to the drawings. In the second embodiment, the same components as those in the second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
[0050]
FIG. 3 is a block diagram illustrating a schematic configuration of the code sequence generator 21 of the third embodiment.
The code sequence generator 21 includes an initial value setting unit 102, a code sequence generator 101, a memory 12, a reading circuit 13, a computing unit 14, and a switching circuit 15.
[0051]
The initial value C (= c0 to cn) set by the user using the initial value setting unit 102 is set in each flip-flop D0 to Dn constituting the shift register 103 of the code sequence generator 101. Then, a clock (not shown) is given to each of the flip-flops D0 to Dn, and the contents are sequentially shifted to the flip-flops of the next stage, so that the cycle 2 ^{n + 1} −1 M-sequence code sequence α is generated, and the code sequence is sequentially output from the flip-flop Dn according to the clock. At this time, the outputs of the flip-flops D0 to Dn are set in the computing unit 14 as the initial value C.
[0052]
The memory 12 stores an (n + 1) × (n + 1) matrix A composed of matrix elements a0 to an.
The reading circuit 13 sequentially reads the matrix elements a0 to an stored in the memory 12 in ascending order of the signs, and sets the read matrix elements am (m = 0, 1, 2,..., N) in the arithmetic unit 14. To do.
[0053]
The computing unit 14 performs a matrix operation on the set matrix element am and the initial value C (output of each flip-flop D0 to Dn), and sequentially calculates each matrix operation result c′0 to c′n. A code sequence β including the matrix operation results c′0 to c′n is generated.
[0054]
Thus, in the code sequence generator 21 of the third embodiment, the operations of the memory 12, the readout circuit 13, and the computing unit 14 are the same as those of the code sequence generator 11 of the second embodiment.
That is, in the code sequence generator 11, the initial values c′0 to c′n are generated using the memory 12, the reading circuit 13, the arithmetic unit 14, and the switching circuit 15, and then the initial values c′0 to c′0 are generated. The code sequence β is generated from the code sequence generator 101b by setting c′n to each flip-flop D0 to Dn of the code sequence generator 101b.
[0055]
On the other hand, in the code sequence generator 21, the outputs of the flip-flops D0 to Dn of the code sequence generator 101 are set as the initial value C in the calculator 14, and each matrix calculation result c ′ calculated by the calculator 14 is set. The code sequence β is 0 to c′n.
Therefore, the code sequence generator 21 differs from the code sequence generator 11 only in the method of generating the initial value C. Therefore, the other functions and effects similar to those of the code sequence generator 11 can be obtained. it can. Then, according to the code sequence generator 21, it is only necessary to provide one code sequence generator 101 as compared with the code sequence generator 11 provided with two code sequence generators 101a and 101b. Can be small.
[0056]
In addition, this invention is not limited to said each embodiment, You may change as follows, Even in that case, the effect | action and effect similar to said each embodiment can be acquired.
(1) In the first embodiment, the code sequence generator 101a may be omitted from the code sequence generator 1, and the code sequence β having an arbitrary phase may be generated from the code sequence generator 101b. In this case, using the matrix element setting unit 2, a matrix A including matrix elements a0 to an corresponding to an arbitrary phase is set in advance. In this way, even when a code sequence is generated from an arbitrary phase in a code sequence having a very long period, the time from when the initial value C is set until the generation of a desired code sequence β is started is shortened. This is particularly effective when generating a code sequence having a long period.
[0057]
(2) In the second embodiment, the code sequence generator 101a may be omitted from the code sequence generator 11, and the code sequence β having an arbitrary phase may be generated from the code sequence generator 101b. In this case, a matrix A composed of matrix elements a0 to an corresponding to an arbitrary phase is stored in the memory 12. In this way, even when a code sequence is generated from an arbitrary phase in a code sequence having a very long period, the time from when the initial value C is set until the generation of a desired code sequence β is started is shortened. This is particularly effective when generating a code sequence having a long period.
[0058]
(3) In the second and third embodiments, not only one type of matrix A is stored in the memory 12, but also each matrix element is appropriately set corresponding to the offset amount of each code sequence α, β. A plurality of matrices may be stored, and a matrix element of an arbitrary matrix may be read by the reading circuit 13. That is, a matrix X corresponding to the offset amount x and a matrix Y corresponding to the offset amount y are stored in the memory 12, and when the offset amount x is required for each code sequence α, β, the readout circuit 13 performs the matrix. Each matrix element of X is read, and when the offset amount y is required for each code sequence α, β, the matrix element of the matrix Y is read by the reading circuit 13. In this way, it is possible to arbitrarily generate code sequences α and β having different offset amounts.
[0059]
(4) In the first embodiment, a plurality of sets of matrix element setting unit 2, operator group 3, code sequence generator 101b are provided, and each set is operated in parallel using a matrix composed of different matrix elements. It may be possible to simultaneously generate three or more code sequences in which an offset amount is set.
[0060]
(5) In the second embodiment, by providing a plurality of sets of the readout circuit 13, the arithmetic unit 14, the switching circuit 15, and the code sequence generator 101 b and operating each of these groups in parallel using a matrix composed of different matrix elements, It may be possible to simultaneously generate three or more code sequences in which offset amounts are set.
[0061]
(6) In the third embodiment, a plurality of sets of readout circuits 13 and computing units 14 are provided, and each set is operated in parallel using a matrix composed of different matrix elements. The above code sequences may be generated simultaneously.
[0062]
(7) The present invention may be applied to a code sequence generator of a Gold sequence instead of an M sequence.
FIG. 7 is a block diagram showing a schematic configuration of a code sequence generator 301 that is generally used conventionally to generate a Gold sequence.
[0063]
The gold sequence code sequence generator 301 includes an initial value setting unit 102, code sequence generators 101 c and 101 d, and an exclusive OR 302.
The exclusive OR circuit 104 of the code sequence generator 101c outputs the output of the final flip-flop Dn in the shift register 103 and the x-th stage (x = 0, 1, 2,..., N corresponding to the code sequence to be generated. And the output of the flip-flop Dx is fed back to the first flip-flop D0. Further, the exclusive OR circuit 104 of the code sequence generator 101d outputs the output of the final flip-flop Dn in the shift register 103 and the y-th stage (y = 0, 1, 2,...) Corresponding to the code sequence to be generated. , N, y ≠ x) and an exclusive OR with the output of the flip-flop Dy, and the result is fed back to the first flip-flop D0.
[0064]
The exclusive OR 302 calculates the exclusive OR of the code sequence α generated from the code sequence generator 101c and the code sequence β generated from the code sequence generator 101d, and generates a Gold sequence code sequence. .
In the first embodiment, in order to generate a gold-sequence code sequence instead of an M-sequence, the code sequence generators 101a and 101b shown in FIG.
[0065]
Further, in the second embodiment, in order to generate a Gold-sequence code sequence instead of an M-sequence, the code sequence generators 101a and 101b shown in FIG.
In the third embodiment, the code sequence generator 101 shown in FIG. 3 may be replaced with the code sequence generator 301 in order to generate a gold sequence code sequence instead of an M sequence.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a first embodiment embodying the present invention.
FIG. 2 is a block diagram showing a schematic configuration of a second embodiment embodying the present invention.
FIG. 3 is a block diagram showing a schematic configuration of a third embodiment embodying the present invention.
FIG. 4 is a block diagram showing a schematic configuration of a conventional form.
FIG. 5 is a block diagram showing a schematic configuration of a conventional form.
FIG. 6 is a timing chart showing the operation of a conventional form.
FIG. 7 is a block diagram showing a schematic configuration of a conventional form.
[Explanation of symbols]
2 ... Matrix element setting unit 3 ... Operator group P0 to Pn, 14 ... Operator
12 ... Memory 13 ... Reading circuit 15 ... Switching circuit
101: Code sequence generator 101a: Second code sequence generator
101b: first code sequence generator 103: shift register
104: Exclusive OR circuit

Claims (4)

First exclusive OR of the first shift register and the output of the final stage of the first shift register and the output of any stage is taken, and the exclusive OR is fed back to the first stage of the first shift register And an initial value is set to each stage of the first shift register, a clock is applied to each stage of the first shift register, and the contents of each stage are sequentially shifted to the next stage. A first code sequence generator that generates one code sequence and sequentially outputs the first code sequence from the last stage of the first shift register according to a clock;
A second exclusive-OR that takes the exclusive OR of the second shift register and the output of the final stage of the second shift register and the output of an arbitrary stage and feeds back the exclusive OR to the first stage of the second shift register And an initial value is set to each stage of the second shift register, a clock is applied to each stage of the second shift register, and the contents of each stage are sequentially shifted to the next stage. A second code sequence that generates two code sequences and sequentially outputs the second code sequence from the last stage of the second shift register according to a clock; an initial value set in each stage of the second shift register; Matrix calculation is performed on a matrix composed of matrix elements set in advance corresponding to the offset amount between the first code sequence and the second code sequence, and the matrix calculation result is stored at the initial stage of each stage of the first shift register. As value Code sequence generator characterized by comprising calculating means for Tsu bets. The code sequence generator according to claim 1, wherein
The computing means includes a plurality of computing units corresponding to the respective stages of the first shift register, and the computing units correspond to the matrix elements of the matrix and the initial values corresponding to the respective stages of the first shift register. A code sequence generator characterized by performing a matrix operation. The code sequence generator according to claim 1, wherein
The computing means sequentially performs a matrix operation of the matrix elements corresponding to the respective stages of the first shift register and the initial value for each stage, and the arithmetic unit sequentially calculates the first. A code sequence generator, comprising: switching means for switching and setting a matrix operation result for each stage of the shift register for each stage as an initial value of each stage of the first shift register. The code sequence generator according to any one of claims 1 to 3 ,
A code sequence generator comprising: setting means for setting the matrix, wherein the calculation means performs a matrix calculation of a matrix element corresponding to an arbitrary matrix set by the setting means and the initial value .

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