JP3882844B2 - Display control circuit, electro-optical device, display device, and display control method - Google Patents

Description

  The present invention relates to a display control circuit, an electro-optical device using the same, a display device, and a display control method.

  For example, a liquid crystal panel is used for a display portion of an electronic device such as a mobile phone, and the power consumption and size and weight of the electronic device are reduced. As for this liquid crystal panel, when still images and moving images having high information properties are distributed due to the popularization of mobile phones in recent years, higher image quality is required.

  An active matrix liquid crystal panel using a thin film transistor (hereinafter abbreviated as TFT) liquid crystal is known as a liquid crystal panel that realizes high image quality in the display unit of such an electronic device. An active matrix type liquid crystal panel using TFT liquid crystal realizes high-speed response and high contrast compared to a simple matrix type liquid crystal panel using STN (SuperTwisted Nematic) liquid crystal by dynamic drive, and is suitable for displaying moving images and the like. .

  However, an active matrix liquid crystal panel using TFT liquid crystal consumes a large amount of power, and is difficult to employ as a display unit of a portable electronic device that is driven by a battery such as a cellular phone. Therefore, if low power consumption of the active matrix liquid crystal panel can be realized, it will be very useful. At that time, it is desirable not to reduce the image quality of the active matrix liquid crystal panel as much as possible.

  The present invention has been made in view of the technical problems as described above, and an object of the present invention is to provide a display control circuit suitable for an active matrix type liquid crystal panel that achieves both high image quality and low power consumption. Another object is to provide an electro-optical device, a display device, and a display control method using the same.

In order to solve the above-described problems, the present invention includes pixels specified by first to Nth (N is a natural number) scanning lines and first to Mth (M is a natural number) signal lines that intersect with each other. A display control circuit for performing display control of an electro-optical device,
A display control circuit for performing display control of an electro-optical device having pixels specified by first to Nth (N is a natural number) scanning lines and first to Mth (M is a natural number) signal lines intersecting each other Because
Area block display control data for storing area block display control data for designating a display area or a non-display area in units of area blocks divided for each given signal line and each given scan line Storage means;
Based on the area block display control data, a display area or a non-display area is defined as the area block for a scan driving circuit that sequentially scans at least a scan line corresponding to the display area among the first to Nth scan lines. Scan drive circuit setting means for setting in units;
Based on the area block display control data, a display area or a non-display area is determined in units of area blocks for a signal driving circuit that drives a signal line corresponding to the display area among the first to Mth signal lines. Signal driving circuit setting means for setting; and
Means for controlling the scan driving circuit to scan-drive the first to Nth scan lines in a given odd frame period of 3 or more with respect to a given reference frame,
Means for controlling the scan driving circuit;
The display scan line corresponding to the display area among the first to Nth scan lines is scan-driven at every frame period, and
Of the first to Nth scan lines, the non-display scan lines that are the scan lines excluding the display scan line are scan-driven in the odd frame period regardless of the voltages of the first to Mth signal lines. The present invention relates to a display control circuit that controls the scan driving circuit.

In the display control circuit according to the present invention,
Band partial display control data holding means for holding band partial display control data for designating a display area or a non-display area in units of line blocks divided for a given plurality of scanning lines;
Mode switching means for switching between the first mode and the second mode;
Including
In the first mode,
Based on the area block display control data, a display area or a non-display area is set in the area block unit for the scanning drive circuit and the signal drive circuit,
In the second mode,
Based on the band partial display control data, a display area or a non-display area can be set for each line block for the scan driving circuit.

The present invention also provides
A display control circuit that performs display control of an electro-optical device having pixels specified by first to Nth scanning lines and first to Mth signal lines intersecting each other,
Means for setting a display area or a non-display area for a scan driving circuit that scans and drives the first to Nth scan lines;
A display scan line, at least a part of which is included in the display area, is scan-driven at every frame period, and the first to Nth scan lines are among the first to Nth scan lines. Means for controlling the scan driving circuit so that a non-display scan line which is a scan line excluding the display scan line is scan-driven at an odd frame period of 3 or more with respect to a given reference frame;
Including
Means for controlling the scan driving circuit;
Of the first to Nth scanning lines, the display scanning lines are scanned at every frame period, and among the first to Nth scanning lines, the non-displaying scanning lines are the first to Mth scanning lines. A display control circuit that controls the scan driving circuit to scan and drive the first to Nth scan lines in the odd frame period by controlling the scan driving in the odd frame period regardless of the signal line voltage of Involved.

In the display control circuit according to the present invention,
A frame counter that counts the number of frames;
A frame interval register for designating the odd frame period;
Regardless of the display scan line or the non-display scan line, in the frame in which the set value of the frame interval register matches the count value of the frame counter, or the frame following the frame in which a given display control event has occurred. The first to Nth scanning lines can be controlled to be scanned.

In the display control circuit according to the present invention,
The given reference frame may be a frame next to a frame in which a given display control event has occurred.

In the display control circuit according to the present invention,
The non-display scan line can be scan-driven in at least one scan period after the occurrence of the display control event in the frame in which the given display control event has occurred.

In the display control circuit according to the present invention,
The given display control event may be an event that occurs based on at least one of generation, disappearance, movement, and size change of a display area or a non-display area.

The present invention also provides
Pixels specified by the first to Nth scan lines and the first to Mth signal lines intersecting each other;
A scan driving circuit for scanning and driving the first to Nth scan lines;
A signal driving circuit for driving the first to Mth signal lines based on image data;
The present invention relates to an electro-optical device including any one of the display control circuits described above.

In the electro-optical device according to the invention,
The signal driving circuit includes:
Block output selection data holding means for holding block output selection data for designating whether or not to drive a signal in units of line blocks divided for each given signal line;
Partial display data holding means for holding partial display data for designating a display area or a non-display area in units of line blocks divided for each of the given signal lines;
With respect to the signal line of the line block designated to be driven by the block output selection data, the output to the signal line of the line block designated not to be driven by the block output selection data is set to a high impedance state. Based on the partial display data, signal line driving means for performing either signal driving according to image data or supply of a given non-display level voltage;
Have
The display control circuit includes:
Block output selection data setting means for setting the block output selection data in the block output selection data holding means of the signal driving circuit;
The first partial display data that designates a display area or a non-display area with the line block as a unit, and the Pth (P is a natural number) block designated in the display area is not signal-driven by the block output selection data. Partial display data conversion means for converting the first partial display data into second partial display data obtained by shifting the data of the Pth block as data of the (P + 1) th block when designated as a block; ,
Partial display data setting means for setting second partial display data in the partial display data holding means of the signal driving circuit;
Can be included.

In the electro-optical device according to the invention,
The Pth block designated as the display area by the first partial display data designating the display area or the non-display area with the line block divided for each of the given signal lines as a unit is the block. When the output selection data designates a block that is not signal-driven, the first image data supplied to the signal driving circuit is the first image data corresponding to the P-th block among the first image data (P + 1). Image data generating means for generating second image data shifted as the image data of the block of
Image data supply means for supplying the second image data to the signal drive circuit;
Can be included.

The present invention also provides
An electro-optical device having pixels specified by the first to Nth scanning lines and the first to Mth signal lines intersecting each other;
A scan driving circuit for scanning and driving the first to Nth scan lines;
A signal driving circuit for driving the first to Mth signal lines based on image data;
The present invention relates to a display device including any one of the display control circuits described above.

The present invention also provides
A display control method for controlling display of an electro-optical device having pixels specified by first to Nth scanning lines and first to Mth signal lines intersecting each other,
A signal driving circuit for driving the first to Mth signal lines specified in units of line blocks divided for each given signal line; and a line divided for each given scan line A display area or a non-display area is set for each line block unit with respect to the scan drive circuit that sequentially scans and drives the first to Nth scan lines specified in units of blocks.
Supplying image data corresponding to the display area to the signal driving circuit;
When driving display based on the image data,
A given non-display level voltage is supplied to the signal line of the line block set in the non-display area, and the signal line of the line block set in the display area is driven with a drive voltage corresponding to the image data. And
The scanning line of the line block set in the display area is scanned and driven every frame period, and the scanning line of the line block set in the non-display area is scanned and driven in the odd frame period regardless of the signal line voltage. Thus, the present invention relates to a display control method in which the first to Nth scan lines are scan-driven in the odd frame period.

In the display control method according to the present invention,
The given reference frame may be a frame next to a frame in which a given display control event has occurred.

In the display control method according to the present invention,
The non-display scan line can be scan-driven in at least one scan period after the occurrence of the display control event in the frame in which the given display control event has occurred.

In the display control method according to the present invention,
The given display control event may be an event that occurs based on at least one of generation, disappearance, movement, and size change of a display area or a non-display area.

  The present invention also provides display control of an electro-optical device having pixels specified by first to Nth (N is a natural number) scanning lines and first to Mth (M is a natural number) signal lines intersecting each other. Display control circuit for performing display, and area block display control for designating a display area or a non-display area in units of area blocks divided for a plurality of given signal lines and a plurality of given scanning lines Area block display control data storage means for storing data and a scan drive circuit for sequentially scanning and driving at least the scan lines corresponding to the display area among the first to Nth scan lines. Based on the scanning drive circuit setting means for setting the display area or the non-display area in the area block unit, and the first to Mth signal lines. A signal driving circuit setting means for setting a display area or a non-display area in units of the area block based on the area block display control data, for a signal driving circuit for driving a signal line corresponding to the display area. It is characterized by including.

  Here, as the electro-optical device, for example, a plurality of scanning lines and a plurality of signal lines intersecting each other, a switching unit connected to the scanning line and the signal line, and a pixel electrode connected to the switching unit are provided. You may comprise so that it may have.

  An area block is a block specified by a line block divided for a given plurality of scanning lines and a line block divided for a given plurality of signal lines. The scan lines divided into line block units may be a plurality of scan lines adjacent to each other, or may be a plurality of arbitrarily selected scan lines. Further, the signal lines divided into line block units may be a plurality of signal lines adjacent to each other, or may be a plurality of arbitrarily selected signal lines.

  In the present invention, an area block display control data storage means is provided, a display area or a non-display area is designated in units of area blocks, and the signal drive circuit setting means or the scan drive circuit setting means provides the signal drive circuit or the scan drive circuit. On the other hand, a display area or non-display area can be set for each line block. Therefore, by driving only the display area, when performing partial display control that enables reduction of power consumption accompanying driving of the non-display area, compared to setting the display area in pixel units, The memory capacity can be greatly reduced, and the consumption can be reduced with a simple configuration.

  Further, the display control circuit according to the present invention provides a band partial display that holds band partial display control data for designating a display area or a non-display area in units of line blocks divided for a given plurality of scanning lines. Control data holding means, and mode switching means for switching between the first mode and the second mode. In the first mode, based on the area block display control data, the scanning drive circuit and the A display area or a non-display area is set for each signal block for the signal drive circuit. In the second mode, a display area or a non-display area is set for the scan drive circuit based on the band partial display control data. It is set by the line block unit.

  According to the present invention, the band partial display control data holding means is further provided, and the display area or the non-display area is set in units of line blocks on the basis of the band partial display control data. It becomes possible to perform partial display control with reduced memory capacity required for partial display control.

  The display control circuit according to the present invention is a display control circuit that performs display control of an electro-optical device having pixels specified by the first to Nth scanning lines and the first to Mth signal lines that intersect each other. Band partial display data holding means for holding band partial display control data for designating a display area or a non-display area in units of area blocks divided for a given plurality of scanning lines; A scan driving circuit setting means for setting a display area or a non-display area in units of the area blocks based on the band partial display control data with respect to a scan driving circuit that scans and drives the Nth scanning line; Features.

  According to the present invention, the band partial display control data holding means is provided, and based on the band partial display control data, the scanning line is set as a display area or a non-display area in units of area blocks. It is possible to reduce the memory capacity required for partial display control and simplify the setting of display areas and non-display areas that can be reduced in consumption.

  In the display control circuit according to the present invention, among the first to Nth scanning lines, a display scanning line that is a scanning line corresponding to the display area is scan-driven every frame period, and the first to first scanning lines are scanned. Among the N scan lines, the non-display scan line that is a scan line excluding the display scan line is scan-driven so as to be scan-driven at a given odd frame period of 3 or more based on a given reference frame. Means for controlling the circuit is included.

  Here, a given odd frame period of 3 or more based on a given reference frame is the third frame, the fifth frame,... (2k + 1) when the given reference frame is 0 frame. ) (K is a natural number) A period in which the frame is the last frame.

  From the viewpoint of reducing power consumption, it is desirable that the frame period during which the non-display scanning line is scan-driven is longer.

  According to the present invention, the display area is scanned and driven every frame period, but the non-display area is scanned and driven at an odd frame period of 3 or more. It is possible to prevent adverse effects and reduce power consumption by reducing unnecessary scanning drive.

  According to another aspect of the invention, there is provided a display control circuit that performs display control of an electro-optical device having pixels specified by the first to Nth scanning lines and the first to Mth signal lines that intersect each other. A means for setting a display area or a non-display area for a scan driving circuit that scans and drives the Nth scan line, and at least a part of the first to Nth scan lines is included in the display area. A display scan line that is a scan line is driven to scan every frame period, and a non-display scan line that is a scan line excluding the display scan line among the first to Nth scan lines is a given reference frame. And a means for controlling the scanning drive circuit so as to perform scanning driving with an odd frame period of 3 or more as a reference.

  According to the present invention, when partial display control is performed, the display area is scanned at every frame period, but the non-display area is scanned at an odd frame period of 3 or more. For example, adverse effects due to TFT leakage can be prevented, and power consumption can be reduced by reducing unnecessary scanning drive.

  The display control circuit according to the present invention is characterized in that the given reference frame is a frame next to a frame in which a given display control event has occurred.

  According to the present invention, by the occurrence of a given display control event, a display area or a non-display area that has been changed so far can be avoided, for example, a deterioration in display quality in which the non-display area becomes dark for a moment. it can.

  The display control circuit according to the present invention scans the non-display scan line in at least one scan period after the occurrence of the display control event in the frame in which the given display control event has occurred. .

  According to the present invention, in the frame in which the display control event has occurred, since the non-display scan line is driven to scan for at least one scanning period after the occurrence timing, the display quality deteriorates due to the occurrence of the event. Can be inconspicuous.

  In the display control circuit according to the present invention, the given display control event is an event that occurs based on at least one of generation, disappearance, movement, and size change of a display area or a non-display area. And

  According to the present invention, it is possible to prevent deterioration in display quality due to any one of generation, disappearance, movement, and size change of a window.

  The electro-optical device according to the present invention scans the pixels specified by the first to Nth scanning lines and the first to Mth signal lines intersecting each other and the first to Nth scanning lines. It includes a drive circuit, a signal drive circuit that drives the first to Mth signal lines based on image data, and any one of the display control circuits described above.

  According to the present invention, it is possible to provide an electro-optical device capable of reducing the memory capacity associated with partial display control capable of realizing low consumption and simplifying designation of a display area or a non-display area. . Therefore, it is possible to reduce the cost of the electro-optical device that reduces the consumption.

  Also, in the electro-optical device according to the invention, the signal drive circuit specifies block output selection data for designating whether to drive the signal in units of line blocks divided for the given signal lines. A block output selection data holding means for holding a partial display data for specifying a display area or a non-display area in units of line blocks divided for each of the given signal lines. A holding block and a signal of a line block designated to be driven by the block output selection data by setting the output to the signal line of the line block designated not to be driven by the block output selection data to a high impedance state. Based on the partial display data for the line, the image data Signal line driving means for performing either a signal driving or a supply of a given non-display level voltage, and the display control circuit uses the block output selection data as the block output selection data of the signal driving circuit. The block output selection data setting means that is set in the holding means and the first partial display data that designates the display area or the non-display area in units of the line block, and the Pth (P is a natural number) designated in the display area. Is designated as a block that is not signal-driven by the block output selection data, the second partial display data is obtained by shifting the P partial block data to the (P + 1) -th block data. Partial display data conversion means for converting the partial display data into a second partial display The chromatography data, characterized in that it comprises a partial display data setting means for setting the partial display data holding means of said signal driving circuit.

  In the present invention, in the signal driving circuit, the block output selection data specifies that the output to the signal line of the line block designated not to drive the signal in units of line blocks is in a high impedance state and is signal driven. When a signal line corresponding to image data or a given non-display level voltage is supplied to a signal line of a line block based on partial display data, a partial display data conversion means is provided in the display control circuit. I made it. In the partial display conversion means, in the first partial display data that designates a display area or a non-display area in line block units, the Pth block designated as the display area is a block that is not signal-driven by the block output selection data. When designated, the first partial display data is converted into second partial display data obtained by shifting the data of the Pth block as the data of the (P + 1) th block.

  In this way, the block output selection data can provide a signal driving circuit that can easily cope with a change in the panel size of the display panel, and the first partial display data can be designated according to the image data. In this case, it is not necessary to consider the set value of the block output selection data, and for example, user convenience can be improved.

  The electro-optical device according to the present invention may be designated as a display area by first partial display data for designating a display area or a non-display area in units of line blocks divided for the given signal lines. When the designated Pth block is designated as a block that is not signal-driven by the block output selection data, the first image data supplied to the signal driving circuit is changed to the Pth of the first image data. Image data generating means for generating second image data obtained by shifting image data corresponding to the block as image data of the (P + 1) -th block, and supplying the second image data to the signal driving circuit And image data supply means.

  In the present invention, the image data generating means is provided, and the Pth block designated in the display area is selected as the block output selection by the first partial display data designating the display area or non-display area in units of line blocks. When the data is designated as a block that is not signal-driven, the first image data is shifted to the image data corresponding to the P-th block of the first image data as the image data of the (P + 1) -th block. The second image data is generated, and the second image data is supplied to the signal driving circuit. As a result, even with respect to the signal drive circuit that can easily cope with the change in the panel size of the display panel based on the block output selection data, only the signal line of the line block designated as the signal-driven line block is the second. Since the image data can be supplied, it is not necessary for the image creator, for example, the user to consider the setting value of the block output selection data.

  The display device according to the invention includes an electro-optical device having pixels specified by the first to Nth scanning lines and the first to Mth signal lines intersecting each other, and the first to Nth scanning lines. It includes a scan driving circuit that scans, a signal driving circuit that drives the first to Mth signal lines based on image data, and the display control circuit described above.

  ADVANTAGE OF THE INVENTION According to this invention, the memory capacity accompanying the partial display control which can implement | achieve reduction of consumption can be reduced, and the display apparatus which can aim at simplification of designation | designated of a display area or a non-display area can be provided. Therefore, it is possible to reduce the cost of a display device that achieves low consumption.

  The present invention also provides a display control method for controlling display of an electro-optical device having pixels specified by first to Nth scanning lines and first to Mth signal lines intersecting each other. Area block display control data for designating a display area or a non-display area in units of area blocks divided for each of a plurality of signal lines and a given plurality of scanning lines, Based on the area block display control data, a display area or a non-display area is set as the area block unit for a scan driving circuit that scans and drives a scan line and a signal drive circuit that drives the first to Mth signal lines. It is characterized by being set by.

  According to the present invention, on the basis of area block display control data for designating a display area or a non-display area in area block units, a display area or a non-display area is set in line block units for the signal drive circuit or the scan drive circuit, respectively. Enabled to set. Therefore, by driving only the display area, when performing partial display control that enables reduction of power consumption accompanying driving of the non-display area, compared to setting the display area in pixel units, The memory capacity can be greatly reduced, and the consumption can be reduced with a simple configuration.

  The display control method according to the present invention is a display control method for controlling display of an electro-optical device having pixels specified by the first to Nth scanning lines and the first to Mth signal lines intersecting each other. The band partial display control data for designating a display area or a non-display area is held in units of line blocks divided for a given plurality of scanning lines, and the first to Nth scanning lines are stored. A display area or a non-display area is set for each line block based on the band partial display control data for a scanning drive circuit that performs scanning driving.

  According to the present invention, a display area or a non-display area is set for each scan area block based on the band partial display control data, so that the memory capacity required for the partial display control in the scan line direction is reduced. In addition, it is possible to simplify the setting of display areas and non-display areas that can be reduced in consumption.

  The present invention also provides a display control method for controlling display of an electro-optical device having pixels specified by first to Nth scanning lines and first to Mth signal lines intersecting each other. A signal driving circuit for driving the first to Mth signal lines specified in units of line blocks divided for each of the plurality of signal lines, and a line block divided for each given plurality of scanning lines With respect to the scan drive circuit that sequentially scans and drives the first to Nth scan lines specified as a unit, a display area or a non-display area is set for each line block unit, and image data corresponding to the display area is obtained. It supplies to the said signal drive circuit, It is characterized by the above-mentioned.

  According to the present invention, an image to be displayed in a display area after setting a display area or a non-display area in units of line blocks each divided into a plurality of lines for the signal drive circuit and the scan drive circuit. Since the display drive control is performed by supplying data, the partial display control can be performed to reduce the power consumption accompanying the signal drive in the non-display area.

  In the display control method according to the present invention, when display driving is performed based on the image data, a given non-display level voltage is supplied to the signal line of the line block set in the non-display area, and the display area The signal line of the line block set to the signal line is driven with the driving voltage corresponding to the image data, the scanning line of the line block set to the display area is sequentially scanned, and the line set to the non-display area The block scan lines are driven with a given odd frame period of 3 or more.

  According to the present invention, the scanning lines of the line block set in the non-display area are scanned and driven with an odd frame period of 3 or more. For example, a liquid crystal panel using TFTs is used as an electro-optical device, for example. To solve the problem that power consumption has been large and dynamic partial display has not been possible due to TFT leakage, and to provide a display control method that achieves both high image quality and low consumption. it can.

  According to another aspect of the invention, there is provided a display control method for controlling display of an electro-optical device having pixels specified by the first to Nth scanning lines and the first to Mth signal lines intersecting each other. A display area or a non-display area is set in this area, and at least a part of the first to Nth scan lines is a scan line included in the display area, and the display scan line is scanned at a period of every frame. The non-display scan line, which is a scan line excluding the display scan line among the first to Nth scan lines, is driven to scan at a given odd frame period of 3 or more based on a given reference frame. It is characterized by doing.

  According to the present invention, when partial display control is performed, the display area is scanned at every frame period, but the non-display area is scanned at an odd frame period of 3 or more. For example, adverse effects due to TFT leakage can be prevented, and power consumption can be reduced by reducing unnecessary scanning drive.

  The display control method according to the present invention is characterized in that the given reference frame is a frame next to the frame in which the given display control event has occurred.

  According to the present invention, by the occurrence of a given display control event, a display area or a non-display area that has been changed so far can be avoided, for example, a deterioration in display quality in which the non-display area becomes dark for a moment. it can.

  The display control method according to the present invention is characterized in that the non-display scan line is scan-driven in at least one scan period after the occurrence of the display control event in the frame in which the given display control event has occurred. .

  According to the present invention, in the frame in which the display control event has occurred, since the non-display scan line is driven to scan for at least one scanning period after the occurrence timing, the display quality deteriorates due to the occurrence of the event. Can be inconspicuous.

  In the display control method according to the present invention, the given display control event is an event that occurs based on at least one of generation, disappearance, movement, and size change of a display area or a non-display area. And

  According to the present invention, it is possible to prevent deterioration in display quality due to any one of generation, disappearance, movement, and size change of a window.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

1. 1. Display Device 1.1 Configuration of Display Device FIG. 1 shows an outline of a configuration of a display device to which a display control circuit (LCD controller, display controller) in this embodiment is applied.

  A liquid crystal device 10 as a display device includes a liquid crystal display (hereinafter abbreviated as LCD) panel 20, a signal driver (signal driving circuit) (a source driver in a narrow sense) 30, a scanning driver (scanning driving circuit). (Gate driver in a narrow sense) 50, LCD controller 60, and power supply circuit 80 are included.

The LCD panel (electro-optical device in a broad sense) 20 is formed on a glass substrate, for example. On this glass substrate, a plurality of scanning lines (in a narrow sense, gate lines) G _{1 to} G _N (N is a natural number of 2 or more) and a plurality of arrays in the X direction are arranged in the Y direction. Signal lines (source lines in the narrow sense) S _{1 to} S _M (M is a natural number of 2 or more) extending in the Y direction are arranged. The TFT 22 _nm (switching means in a broad sense) corresponds to the intersection of the scanning line G _n (1 ≦ n ≦ N, n is a natural number) and the signal line S _m (1 ≦ m ≦ M, m is a natural number). ) Is provided.

The gate electrode of the TFT 22 _nm is connected to the scanning line G _n . The source electrode of the TFT 22 _nm is connected to the signal line S _m. A drain electrode of the TFT 22 _nm is connected to a pixel electrode 26 _nm of a liquid crystal capacitor (liquid crystal element in a broad sense) 24 _nm .

In the liquid crystal capacitance 24 _nm , liquid crystal is sealed between the counter electrode 28 _nm facing the pixel electrode 26 _nm and the transmittance of the pixel changes according to the applied voltage between these electrodes. Yes.

The counter electrode voltage Vcom generated by the power supply circuit 80 is supplied to the counter electrode 28 _nm .

The signal driver 30 drives the signal lines S _{1 to} S _M of the LCD panel 20 based on the image data of one horizontal scanning unit.

The scan driver 50 sequentially scans and drives the scan lines G _{1 to} G _N of the LCD panel 20 in synchronization with the horizontal synchronizing signal within one vertical scanning period.

  The LCD controller 60 controls the signal driver 30, the scan driver 50, and the power supply circuit 80 according to the contents set by a host such as a central processing unit (hereinafter abbreviated as CPU) (not shown). More specifically, the LCD controller 60 sets, for example, an operation mode and supplies an internally generated vertical synchronization signal and horizontal synchronization signal to the signal driver 30 and the scan driver 50, and supplies to the power supply circuit 80. Supplies the polarity inversion timing of the counter electrode voltage Vcom.

  The power supply circuit 80 generates a voltage level necessary for driving the liquid crystal of the LCD panel 20 and a counter electrode voltage Vcom based on a reference voltage supplied from the outside. The voltage level necessary for driving the liquid crystal of the LCD panel 20 is supplied to, for example, the signal driver 30, the scanning driver 50, and the LCD panel 20. The counter electrode voltage Vcom is supplied to a counter electrode provided to face the pixel electrode of the TFT of the LCD panel 20.

  In the liquid crystal device 10 having such a configuration, the signal driver 30, the scanning driver 50, and the power supply circuit 80 cooperate to display and drive the LCD panel 20 based on image data supplied from outside under the control of the LCD controller 60. To do.

  In FIG. 1, the liquid crystal device 10 includes the LCD controller 60, but the LCD controller 60 may be provided outside the liquid crystal device 10. Alternatively, a host may be included in the liquid crystal device 10 together with the LCD controller 60.

  In FIG. 1, the signal driver 30 and the scanning driver 50 are provided outside the LCD panel 20, but at least one of the signal driver 30 and the scanning driver 50 is disposed on the same glass substrate as the LCD panel 20. Can be formed.

1.2 Signal Driver FIG. 2 shows an outline of the configuration of the signal driver shown in FIG.

  The signal driver 30 includes a shift register 32, line latches 34 and 36, a digital / analog conversion circuit (drive voltage generation circuit in a broad sense) 38, and a signal line drive circuit 40.

  The shift register 32 has a plurality of flip-flops, and these flip-flops are sequentially connected. When the shift register 32 holds the enable input / output signal EIO in synchronization with the clock signal CLK, the shift register 32 sequentially shifts the enable input / output signal EIO to the adjacent flip-flops in synchronization with the clock signal CLK.

  The shift register 32 is supplied with a shift direction switching signal SHL. The shift register 32 switches the shift direction of the image data (DIO) and the input / output direction of the enable input / output signal EIO by the shift direction switching signal SHL. Therefore, even if the position of the LCD controller 60 that supplies image data to the signal driver 30 differs depending on the mounting state of the signal driver 30, the shift direction is switched by the shift direction switching signal SHL. Flexible mounting can be achieved without increasing the mounting area by routing the wiring.

  For example, image data (DIO) is input to the line latch 34 from the LCD controller 60 in units of 18 bits (6 bits (gradation data) × 3 (RGB colors)). The line latch 34 latches the image data (DIO) in synchronization with the enable input / output signal EIO sequentially shifted by each flip-flop of the shift register 32.

  The line latch 36 latches the image data of one horizontal scanning unit latched by the line latch 34 in synchronization with the horizontal synchronization signal LP supplied from the LCD controller 60.

  The DAC 38 generates an analog drive voltage for each signal line based on the image data.

  The signal line drive circuit 40 drives the signal line based on the drive voltage generated by the DAC 38.

  Such a signal driver 30 sequentially takes in image data of a given unit (for example, 18-bit unit) sequentially input from the LCD controller 60, and lines the image data of one horizontal scanning unit in synchronization with the horizontal synchronization signal LP. Once held by the latch 36. Then, each signal line is driven based on the image data. As a result, the drive voltage based on the image data is supplied to the source electrode of the TFT of the LCD panel 20.

  The signal driver 30 can perform high-impedance control on the output of a line block divided for each given signal line as a unit. Therefore, as shown in FIG. 3, the signal driver 30 has a block output selection register (block output selection data holding means), and outputs a signal line drive circuit that drives the signal lines of each block in units of line blocks. Block output selection data (control instruction data in a broad sense) BLK0 to BLKQ for setting whether to perform impedance control are held.

  In this block output selection data, the signal line of the line block set to ON (“1”) is signal-driven by the signal line driving circuit, and the signal line of the block set to OFF (“0”) is in the high impedance state. It becomes. As a result, the signal line drive circuit connected to the signal line of the LCD panel 20 can be arbitrarily selected in units of line blocks, and the size change of the LCD panel 20 can be easily handled. Further, current consumption associated with impedance conversion performed in a signal line driving circuit that does not require driving is reduced.

The signal driver 30 can set a display area or a non-display area for each line block. Therefore, as shown in FIG. 4, the signal driver 30 has a partial display selection register (partial display data holding means) and determines whether or not to drive the signal lines of each block based on image data in units of line blocks. Is stored as partial display data (control instruction data in a broad sense) PART _S 0 to PART _S Q.

  In the partial display data, for the signal line of the line block set to ON (“1”), signal driving is performed based on the image data as a display area, and the block set to OFF (“0”). A given non-display level voltage is supplied as a non-display area to these signal lines. As a result, the current consumption of the operational amplifier circuit as the impedance conversion means for driving the signal line in the non-display area can be reduced, and the consumption of the LCD panel using the high-quality TFT can be reduced. become. At the same time, an appropriate voltage for non-display is applied to the liquid crystal capacitor connected to the signal line to which the non-display level voltage is supplied via the TFT.

In the signal driver 30, the block which is the control unit described above is set to 8 pixel units. Here, one pixel consists of 3 bits of RGB signals. Therefore, the signal driver 30 sets a total of 24 outputs (for example, S _{1 to} S ₂₄ ) as one line block. Thus, the display area of the LCD panel 20 can be set in units of character characters (1 byte). Therefore, in an electronic device that displays character characters such as a mobile phone, the display area can be efficiently set and its image is displayed. Display is possible.

  FIG. 5 shows an outline of the configuration of a line block unit that is a control unit of the signal driver 30.

The signal driver 30 has 288 signal line outputs (S _{1 to} S ₂₈₈ ).

That is, the signal driver 30 has the configuration shown in FIG. 5 in units of 24 output terminals (S _{1 to} S ₂₄ , S _{25 to} S ₄₈ ,..., S _{265 to} S ₂₈₈ ), and has a total of 12 line blocks. (B0-B11). In the following, FIG. 5 will be described as showing the block B0, but the same applies to the other blocks B1 to B11.

Block B0 of the signal driver 30, in response to each signal line of the signal lines S ₁ to S _24, the data bypass circuit 142 _0, including a shift register 140 _0, line latch 36 _0, the drive voltage generating circuit 38 _0, the signal line It includes a drive circuit 40 _0. Here, the shift register 140 ₀ has a function of a shift register 32 and the line latch 34 shown in FIG.

The shift register 140 ₀ included in the data bypass circuit 142 ₀ includes SR _0-1 to SR _0-24 corresponding to each signal line. Line latch 36 ₀ includes LAT _0-1 to LAT _0-24 correspond to the signal lines. The drive voltage generation circuit 38 ₀ includes DAC _0-1 to DAC _0-24 corresponding to each signal line. Signal line drive circuit 40 ₀ includes SDRV _0-1 ~SDRV _0-24 correspond to the signal lines.

As described above, the signal driver 30 has a block output selection register and a partial display selection register, and block output selection data and partial display data are set for each line block. For example, for block B0 shown in FIG. 5, a block output select data BLK0 shown in FIG. 3 BLK, the partial display data PART _S 0 shown in FIG. 4 as a PART, are supplied.

Data bypass circuit 142 ₀ is synchronized to the enable input-output signal EIO is shifted from ROUT direction or RIN in LOUT direction from LIN, captures image data DIO. At that time, the data bypass circuit 142 _0, when the block output select data BLK is set to "0", the switching circuit SWB _1-0 for bypassing the enable input-output signal EIO shifted to the line block, Includes SWB _0-0 .

The switching circuit SWB _1-0 outputs the output data of SR _0-24 as the right direction data output signal ROUT when the block output selection data BLK is “1” (logic level “H”). On the other hand, when the block output selection data BLK is “0” (logic level “L”), the switching circuit SWB _1-0 shifts the image data (block B 0 of the block B 0) from the line block input as the left direction data input signal LIN. In this case, DIO) is output as the right direction data output signal ROUT.

The switching circuit SWB _0-0 outputs the output data of SR _0-1 as the left direction data output signal LOUT when the block output selection data BLK is “1” (logic level “H”). On the other hand, when the block output selection data BLK is “0” (logic level “L”), the switching circuit SWB _0-0 converts the image data shifted from the line block input as the right direction data input signal RIN to the left direction data. Output as an output signal LOUT.

SR _0-1 to SR _0-24 corresponding to the signal lines S _{1 to} S ₂₄ shift the enable input / output signal EIO supplied as LIN or RIN, and synchronize with the shifted enable input / output signal EIO. Capture image data DIO.

FIG. 6 schematically shows the configuration of SR _0-1 constituting the shift register 140 ₀ .

Although the configuration of SR _0-1 is shown here, the other SR _0-2 to SR _0-24 can be configured in the same manner.

SR _0-1 includes FF _LR , FF _RL , FF _DIO , and SW1.

For example, the FF _LR latches the enable input / output signal EIO as the left data input signal LIN input to the D terminal in synchronization with the rising edge of the clock signal input to the CK terminal. Then, the left data input signal LIN is supplied from the Q terminal to the D terminal of SR _0-2 as the right data output signal ROUT.

For example, the FF _RL latches the enable input / output signal EIO as the right data input signal RIN input to the D terminal in synchronization with the rising edge of the clock signal input to the CK terminal. Then, the left data output signal LOUT is output from the Q terminal.

The right direction data output signal ROUT output from the Q terminal of the FF _LR is also supplied to SW1. The left direction output signal LOUT output from the Q terminal of FF _RL is also supplied to SW1.

SW1 selects either the right direction data output signal ROUT or the left direction data output signal LOUT in accordance with the shift direction switching signal SHL and supplies it to the CK terminal of the FF _DIO .

The FF _DIO latches the image data DIO in synchronization with the SW1 selection output signal supplied to the CK terminal. The latched image data is output from the Q terminal LAT _0-1 line latch 36 _0.

In this manner, the image data stored in the SR _0-1 to SR _0-24 of shift register 140 _0, each LAT _0-1 to LAT _0, respectively in synchronism with the horizontal synchronizing signal LP line latch 36 _{0 Latched} to _-24 .

(Line latch)
Image data corresponding to the signal lines S ₁ to S ₂₄ which is latched in the line latch LAT _0-1 to LAT _0-24 is supplied to the DAC _0-1 to DAC _0-24 of each drive voltage generating circuit.

(Drive voltage generation circuit)
The DAC _{0-1 to} DAC _0-24 are based on, for example, 6-bit gradation data supplied from the corresponding LAT _0-1 to LAT _0-24 when the DAC enable signal DACen is at the logic level “H”. Thus, a gradation voltage of 64 levels is generated.

  The DAC enable signal DACen is generated by the logical product of the enable signal dacen0 and the block output selection data BLK. The enable signal dacen0 is generated by a logical product of the DAC control signal dacen generated by a control circuit (not shown) of the signal driver 30 and the partial display data PART.

That, DAC enable signal DACen, when the block output select data BLK is "0", regardless of the settings of the partial display data PART, driving voltage generating circuit 38 ₀ in BLK0 stops operating. When the block output selection data BLK is “1”, the DAC operation is performed only when the partial display area is set. On the other hand, when the block output selection data BLK is set as the partial non-display area, the DAC operation is stopped and the ladder resistance is set. To reduce the current consumption of current.

The DAC enable signal DACen is similarly supplied to the DAC _0-2 to DAC _0-24 corresponding to the other signal lines S _{2 to} S ₂₄ , and DAC operation control is performed in units of line blocks.

(Signal line drive circuit)
SDRV _0-1 ~SDRV signal line drive circuit 40 _{0 0-24,} an operational amplifier OP _0-1 ~OP _0-24 which is voltage-follower-connected as each impedance conversion means, partial non-display level voltage supply circuit VG _{0 -1 to} VG _0-24 are included.

The output terminals of the operational amplifiers OP _{0-1 to} OP _0-24 connected to the voltage follower are negatively fed back, the input impedance of the operational amplifier becomes extremely large, and the input current hardly flows. When the operational amplifier enable signal OPen is at a logic level “H”, the drive voltages generated by the corresponding DAC _0-1 to DAC _0-24 are impedance-converted to drive the signal lines S _{1 to} S ₂₄ . Thereby, signal driving can be performed without depending on the output loads of the signal lines S _{1 to} S ₂₄ .

  The operational amplifier enable signal OPen is generated by a logical product of the enable signal open0 and the block output selection data BLK. The enable signal open0 is generated by a logical product of the operational amplifier control signal open generated by a control circuit (not shown) of the signal driver 30 and the partial display data PART.

  That is, when the block output selection data BLK is “0”, the operational amplifier enable signal OPen stops the operation of the operational amplifier BLK0 regardless of the setting value of the partial display data PART (the operational amplifier current source is stopped). , Reduce current consumption). When the block output selection data BLK is “1”, the drive voltage generated by the drive voltage generation circuit is impedance-converted only when the partial display area is set to drive the corresponding signal line. When set as a partial non-display area, the operation of the operational amplifier is stopped to reduce current consumption.

(Partial non-display level voltage supply circuit)
The partial non-display level voltage supply circuits VG _{0-1 to} VG _0-24 are arranged in the non-display area (output is turned off) in the above-described partial display selection register when the non-display level voltage supply enable signal LEVen is at the logic level “H”. ), A given non-display level voltage V _PART-LEVEL supplied to each signal line is generated.

Here, the non-display level voltage V _PART-LEVEL is the following (1) with respect to a given threshold V _{CL at} which the transmittance of the pixel changes and the counter electrode voltage Vcom of the counter electrode facing the pixel electrode. It has a formula relationship.

｜ V _PART-LEVEL −Vcom | <V _CL (1)
That is, when the non-display level voltage V _PART-LEVEL is applied to the pixel electrode connected to the drain electrode of the TFT connected to the signal line to be driven, the applied voltage of the liquid crystal capacitance is the given threshold V _CL. The voltage level does not exceed.

The non-display level voltage V _PART-LEVEL is desirably a voltage level equivalent to the counter electrode voltage Vcom in view of ease of generation and control of the voltage level. For example, when a voltage level equivalent to the counter electrode voltage Vcom is supplied, the color when the liquid crystal is off is displayed in the non-display area of the LCD panel 20.

Further, the non-display level voltage supply circuits VG _{0-1 to} VG _0-24 can selectively output either the voltage level V0 or V8 at both ends of the gradation level voltage as the non-display level voltage V _PART-LEVEL. It has become. Here, the voltage level V0 or V8 at both ends of the gradation voltage level is a voltage level that is alternately output for each frame by the inversion driving method. In this case, the non-display level voltage V _PART-LEVEL can be selected by the selection signal SEL designated by the user as the counter electrode voltage Vcom or the voltage level V0 or V8 at both ends of the gradation level voltage. . Thereby, the user can raise the freedom degree of selection of the color of a non-display area.

The non-display level voltage supply enable signal LEVen is generated by a logical product of a non-display level voltage supply circuit control signal left generated by a control circuit (not shown) of the signal driver 30 and inversion of the partial display data PART. That is, only when a non-display area (output is off) is set, a given non-display level voltage is driven to the signal line, and when the display area (output is on) is set, a non-display level voltage supply circuit The outputs of VG _{0-1 to} VG _0-24 are in a high impedance state and do not drive the signal line.

The operational amplifier enable signal OPen and the non-display level voltage supply enable signal LEVen are also supplied to the SDRV _0-2 to SDRV _0-24 corresponding to the other signal lines S _{2 to} S ₂₄ in the same manner. Drive control of the signal line is performed.

1.3 Scan Driver FIG. 7 shows an outline of the configuration of the scan driver shown in FIG.

  The scanning driver 50 includes a shift register 52, level shifters (hereinafter abbreviated as L / S) 54 and 56, and a scanning line driving circuit 58.

  The shift register 52 is sequentially connected to flip-flops provided corresponding to the scanning lines. When the shift register 52 holds the scan enable input / output signal GEIO in the flip-flop in synchronization with the clock signal CLK, the shift register 52 sequentially shifts the scan enable input / output signal GEIO to the adjacent flip-flop in synchronization with the clock signal CLK. The scan enable input / output signal GEIO input here is a vertical synchronization signal supplied from the LCD controller 60.

  The L / S 54 shifts to a voltage level corresponding to the liquid crystal material of the LCD panel 20. As this voltage level, for example, a high voltage level of 20 V to 50 V is required, and therefore a high breakdown voltage process different from other logic circuit units is used.

  The scanning line driving circuit 58 performs CMOS driving based on the driving voltage shifted by the L / S 54. The scan driver 50 has an L / S 56, and a voltage shift of the output enable signal XOEV supplied from the LCD controller 60 is performed. The scanning line driving circuit 58 is on / off controlled by the output enable signal XOEV shifted by the L / S 56.

  In such a scan driver 50, the enable input / output signal GEIO input as a vertical synchronization signal is sequentially shifted to each flip-flop of the shift register 52 in synchronization with the clock signal CLK. Since each flip-flop of the shift register 52 is provided corresponding to each scanning line, the scanning lines are alternatively sequentially selected by the pulse of the vertical synchronizing signal held in each flip-flop. The selected scan line is driven by the scan line driving circuit 58 at the voltage level shifted by the L / S 54. As a result, a given scanning drive voltage is supplied to the TFT gate electrode of the LCD panel 20 in one vertical scanning cycle. At this time, the drain electrode of the TFT of the LCD panel 20 has substantially the same potential corresponding to the potential of the signal line connected to the source electrode.

The scanning driver 50 can set a display area or a non-display area in units of line blocks divided for a given plurality of scanning lines. Therefore, as shown in FIG. 8, the scan driver 50 has a partial scan display selection register, and the partial scan display for setting whether or not to sequentially scan the scan lines of each line block in units of the line block. Data (control instruction data in a broad sense) PART _G 0 to PART _G R are held.

  In this partial scan display data, the scan lines of the line block set to ON (“1”) are sequentially scanned and the scan lines of the line block set to OFF (“0”) are scanned. Not driven. As a result, the circuit operation can be stopped for the scanning lines in the non-display area, and the consumption of the LCD panel using the high-quality TFT can be reduced.

  Further, the scan driver 50 uses the above-described control unit line block as eight scan line units. Thus, the display area of the LCD panel 20 can be set in units of character characters (1 byte). Therefore, in an electronic device that displays character characters such as a mobile phone, the display area can be efficiently set and its image is displayed. Display is possible.

  FIG. 9 shows an example of a specific configuration of such a scan driver 50.

In the shift register 52, FF _G1 to FF _GN (first to Nth FFs) provided corresponding to each of the scanning lines G _{1 to} G _N (first to Nth scanning lines) are connected in series. The The scan enable input / output signal GEIO supplied from the LCD controller 60 is supplied to FF _G1 (first FF). Similarly, the clock signal CLK supplied from the LCD controller 60 is supplied to FF _{G1 to} FF _GN . FF _{G1 to} FF _GN sequentially shift the scan enable input / output signal GEIO (given pulse signal) in synchronization with the clock signal CLK.

  The enable input / output signal GEIO supplied from the LCD controller 60 is a vertical synchronization signal. The clock signal CLK supplied from the LCD controller 60 is a horizontal synchronization signal.

L / S54 has a scanning line G ₁ ~G level shifter circuit provided corresponding to each of the _N LS _{1 ~LS N} (LS circuit of first to N), the corresponding FF _G1 to ff The voltage level on the high potential side of the held data of _GN is shifted to a voltage level of 20 V to 50 V, for example.

  The L / S 56 shifts the voltage level on the high potential side of the inverted signal (output enable signal) of the output enable signal XOEV supplied from the LCD controller 60 to a voltage level of 20 V to 50 V, for example.

Scan line driving circuit 58, corresponding to each of the scan lines G ₁ ~G _N, and an AND circuit 230 ₁ to 230 _N, CMOS buffer circuit 232 ₁ ~232 _N as a mask circuit. The AND circuits 230 _{1 to} 230 _N and the CMOS buffer circuits 232 _{1 to} 232 _N are formed by a high breakdown voltage process that can operate at the voltage level of, for example, 20 V to 50 V described above. This voltage level is determined according to, for example, the liquid crystal material of the LCD panel 20 to be driven.

The AND circuits 230 _{1 to} 230 _N output the logical levels of the output nodes of FF _G1 to FF _GN that have been level shifted by LS _{1 to} LS _N and the output enable signal XOEV level-shifted by L / S 56 in units of line blocks. Mask with specified block selection data. More specifically, when the partial scan display data is set to “0”, the logical levels of the output nodes of LS _{1 to} LS _N are masked to “L” regardless of the logical level of the output enable signal XOEV. . When the partial scan display data is set to “1”, the output enable signal XOEV masks the logic levels of the output nodes LS ₁ to LS _N to “L”.

Partial scan display data is held in FF _B0 to FF _BR provided in line block units. Partial scan display data PART _G serially input from the LCD controller 60 is supplied to FF _B0 . The FF _{B0 to} FF _BR are commonly supplied from the LCD controller 60 with a clock signal BCLK for sequentially fetching serially input partial scan display data PART _G. FF _{B0 to} FF _BR sequentially shift the partial scan display data PART _G supplied to FF _B0 in synchronization with the clock signal BCLK.

Further, the scan driver 50 is provided with data switching circuits (bypass means) 234 _{0 to} 234 _R-1 for bypassing the scan enable input / output signal GEIO in units of line blocks.

For example, when it is specified by the block selection data that the scan line drive of the block B1 is not performed, the scan enable input / output signal GEIO supplied to the FF _G1 of the block B0 is synchronized with the clock signal CLK by the FF _{G2 to} FF _G8. While being shifted Te, the data switching circuit 234 ₁ provided corresponding to the FF _G9 block B1, so that the shift output of the FF _G8 to FF _G17 block B2 is supplied.

That is, ₀ data switching circuit 234 provided corresponding to the block B0 is shifted output supplied from the preceding line block (the scan enable input and output signals GEIO supplied to the block B0 FF _G1), the line block The shift output of the final stage FF (shift output output from FF _{G8 in the} block B0) is switched by the block selection data of the line block. The output signal was switched et al by the data switching circuit 234 ₀ is supplied to the block B1.

  Note that such a data switching circuit may be provided on the opposite side of each line block so that the shift direction of the scan enable input / output signal GEIO can be switched by a given shift direction switching signal SHL. Is possible. In this case, a data switching circuit corresponding to the blocks BQ to B1 is provided.

In the scan driver 50 having such a configuration, for the FF _B0 to FF _BR provided in each line block, the block selection data of the line block set in the display area is “1”, and the line set in the non-display area. The block selection data of the block is set to “0”.

Then, a vertical synchronization signal and a horizontal synchronization signal are supplied from the LCD controller 60. In the state where the output enable signal XOEV is at the logic level “L”, when the block selection data set for each line block is “0”, the CMOS buffer circuits 232 _{1 to} 232 _N are connected to the logic of the output node of the LS by the AND circuit. Since the level is masked to the logic level “L”, the scanning line is not driven.

1.4 LCD Controller FIG. 10 shows an outline of the configuration of the LCD controller shown in FIG.

The LCD controller 60 includes a control circuit 62, a random access memory (Random
Access Memory: hereinafter abbreviated as RAM. ) (Storage means in a broad sense) 64, host input / output circuit (I / O) 66, and LCD input / output circuit 68. Further, the control circuit 62 includes a command sequencer 70, a command setting register 72, and a control signal generation circuit 74.

  The control circuit 62 performs various operation mode settings and synchronization control of the signal driver 30, the scan driver 50, and the power supply circuit 80 in accordance with the contents set by the host. More specifically, the command sequencer 70 generates synchronization timing with the control signal generation circuit 74 based on the contents set in the command setting register 72 according to an instruction from the host, Or set a given mode of operation.

  The RAM 64 has a function as a frame buffer for displaying an image and also serves as a work area for the control circuit 62.

  The LCD controller 60 is supplied with image data and command data for controlling the signal driver 30 and the scan driver 50 via the host I / O 66.

  More specifically, the host I / O 66 is connected to a CPU (not shown), a digital signal processor (DSP), or a microprocessor unit (MPU). The LCD controller 60 is supplied with still image data as image data from a CPU (not shown) via the host I / O 66, or with moving image data from a DSP or MPU. Further, the LCD controller 60 supplies the contents of registers for controlling the signal driver 30 or the scan driver 50 and data for setting various operation modes as command data from a CPU (not shown) via the host I / O 66. Is done.

  Image data and command data may be supplied through separate data buses, or the data buses may be shared. In this case, for example, by making it possible to identify whether the data on the data bus is image data or command data based on the signal level input to the command (CoMmanD: CMD) terminal, the image data and the command data can be identified. Sharing is easy, and the mounting area can be reduced.

  When the image data is supplied, the LCD controller 60 holds the image data in the RAM 64 as a frame buffer. On the other hand, when command data is supplied, the LCD controller 60 holds it in the command setting register 72 or the RAM 64.

  The command sequencer 70 causes the control signal generation circuit 74 to generate various timing signals according to the contents set in the command setting register 72. Further, the command sequencer 70 sets the mode of the signal driver 30, the scanning driver 50, or the power supply circuit 80 via the LCD input / output circuit 68 according to the contents set in the command setting register 72.

  The command sequencer 70 generates image data of a given format from the image data stored in the RAM 64 according to the display timing generated by the control signal generation circuit 74, and an LCD input / output circuit (LCD I / O) 68. The signal is supplied to the signal driver 30.

1.5 Inversion Driving Method By the way, when driving a liquid crystal, it is necessary to periodically discharge the charge accumulated in the liquid crystal capacitor from the viewpoint of durability and contrast of the liquid crystal. Therefore, in the liquid crystal device 10 described above, the polarity of the voltage applied to the liquid crystal is reversed at a given period by alternating drive. As this alternating drive method, for example, there are a frame inversion drive method and a line inversion drive method.

  The frame inversion driving method is a method of inverting the polarity of the voltage applied to the liquid crystal capacitor for each frame. On the other hand, the line inversion driving method is a method of inverting the polarity of the voltage applied to the liquid crystal capacitance for each line. Also in the case of the line inversion driving method, if attention is paid to each line, the polarity of the voltage applied to the liquid crystal capacitor in the frame period is also inverted.

  FIGS. 11A and 11B are diagrams for explaining the operation of the frame inversion driving method. FIG. 11A schematically shows waveforms of the signal line driving voltage and the counter electrode voltage Vcom by the frame inversion driving method. FIG. 11B schematically shows the polarity of the voltage applied to the liquid crystal capacitance corresponding to each pixel for each frame when the frame inversion driving method is performed.

In the frame inversion driving method, as shown in FIG. 11A, the polarity of the driving voltage applied to the signal line is inverted every frame period. That is, the voltage V _S supplied to the source electrode of the TFT connected to the signal line is positive “+ V” in the frame f1 and negative “−V” in the subsequent frame f2. On the other hand, the counter electrode voltage Vcom supplied to the counter electrode facing the pixel electrode connected to the drain electrode of the TFT is also inverted in synchronization with the polarity inversion period of the drive voltage of the signal line.

  Since a voltage difference between the pixel electrode and the counter electrode is applied to the liquid crystal capacitor, a positive polarity voltage is applied to the frame f1 and a negative polarity voltage is applied to the frame 2 as shown in FIG. 11B. Become.

  12A and 12B are diagrams for explaining the operation of the line inversion driving method.

  FIG. 12A schematically shows waveforms of the signal line driving voltage and the counter electrode voltage Vcom by the line inversion driving method. FIG. 12B schematically shows the polarity of the voltage applied to the liquid crystal capacitance corresponding to each pixel for each frame when the line inversion driving method is performed.

In the line inversion driving method, as shown in FIG. 12A, the polarity of the driving voltage applied to the signal line is inverted every horizontal scanning period (1H) and every frame period. That is, the voltage V _S supplied to the source electrode of the TFT connected to the signal line is positive “+ V” at 1H of the frame f1 and negative “−V” at 2H. The voltage Vs has a negative polarity “−V” at 1H of the frame f2 and a positive polarity “+ V” at 2H.

  On the other hand, the counter electrode voltage Vcom supplied to the counter electrode facing the pixel electrode connected to the drain electrode of the TFT is also inverted in synchronization with the polarity inversion period of the drive voltage of the signal line.

  Since the voltage difference between the pixel electrode and the counter electrode is applied to the liquid crystal capacitor, the polarity is inverted for each scanning line, so that the polarity is set for each line in the frame period as shown in FIG. Will be applied respectively.

  In general, the line inversion driving method has a change cycle of one line cycle compared to the frame inversion driving method, which contributes to improvement in image quality but consumes more power.

1.6 Liquid Crystal Drive Waveform FIG. 13 shows an example of the drive waveform of the LCD panel 20 of the liquid crystal device 10 having the above-described configuration. Here, a case of driving by a line inversion driving method is shown.

  As described above, in the liquid crystal device 10, the signal driver 30, the scan driver 50, and the power supply circuit 80 are controlled according to the display timing generated by the LCD controller 60. The LCD controller 60 sequentially transfers the image data of one horizontal scanning unit to the signal driver 30 and supplies the internally generated horizontal synchronization signal and the polarity inversion signal POL indicating the inversion driving timing. In addition, the LCD controller 60 supplies an internally generated vertical synchronization signal to the scan driver 50. Further, the LCD controller 60 supplies the common electrode voltage polarity inversion signal VCOM to the power supply circuit 80.

  Thereby, the signal driver 30 drives the signal line based on the image data of one horizontal scanning unit in synchronization with the horizontal synchronizing signal. The scan driver 50 sequentially scans the scan lines connected to the gate electrodes of the TFTs arranged in a matrix on the LCD panel 20 with the drive voltage Vg using the vertical synchronization signal as a trigger. The power supply circuit 80 supplies the internally generated counter electrode voltage Vcom to each counter electrode of the LCD panel 20 while performing polarity inversion in synchronization with the counter electrode voltage polarity inversion signal VCOM.

The liquid crystal capacitor is charged with a charge corresponding to the voltage Vcom between the pixel electrode connected to the drain electrode of the TFT and the counter electrode. Therefore, an image can be displayed when the pixel electrode voltage Vp held by the charge accumulated in the liquid crystal capacitor exceeds a given threshold value _VCL . When the pixel electrode voltage Vp exceeds a given threshold value _VCL , the transmittance of the pixel changes according to the voltage level, and gradation expression becomes possible.

1.7 Partial Display Control The LCD controller 60 in the present embodiment that controls the display of the liquid crystal device 10 having the above-described configuration sets the block output selection data and the partial display data to the signal driver 30, thereby Partial display control in which a display area and a non-display area are set for each line block in the arrangement direction is possible. Similarly, the LCD controller 60 sets the partial scan display data to the scan driver 50, whereby the display area and the non-display area are set in units of line blocks in the scan line arrangement direction. Is possible.

  FIGS. 14A, 14B, and 14C schematically show an example of partial display control by the LCD controller 60 in the present embodiment.

  Assume that the signal driver 30 and the scan driver 50 are arranged as shown in FIG. 14A on the LCD panel 20 in which the scan lines are arranged in the A direction and the signal lines are arranged in the B direction. For example, when the display unit of the cellular phone is configured by such an LCD panel 20, as shown in FIG. 14B, the radio wave reception state and time are displayed on the display area AA, and the display area BA is in the standby state. It can be a non-display area. Moreover, you may make it display moving image information, an email, and other information suitably on display area CA and DA.

  Further, as shown in FIG. 14C, by setting the boundaries between the display areas AA to DA and performing partial display control so as to be arranged in an arbitrary area, it is possible to provide a user-friendly screen. It becomes.

  Thus, by partial display control, window display can be performed, and the reduction of the consumption of the LCD panel using the TFT capable of providing high-quality image quality can be greatly promoted. Further, since the operability is reduced as the screen size is increased, the operability for the user can be improved by adopting such partial display control.

  FIGS. 15A, 15B, and 15C schematically show other examples of partial display control by the LCD controller 60 in the present embodiment.

  As shown in FIG. 15A, the signal driver 30 and the scan driver 50 are arranged on the LCD panel 20 in which the signal lines are arranged in the A direction and the scan lines are arranged in the B direction. Also in this case, as shown in FIGS. 14B and 14C, as shown in FIGS. 15B and 15C, window display can be performed by partial display control, and high-quality image quality is provided. Therefore, it is possible to greatly reduce the consumption of LCD panels using TFTs. Further, since the operability is reduced as the screen size is increased, the operability for the user can be improved by employing such partial display control.

  In particular, by performing partial display control for the signal driver 30 and the scanning driver 50 by the LCD controller 60, a window is displayed at an arbitrary position in the display area of the LCD panel 20, and appropriate information is displayed in the window. Can be made.

2. Next, the LCD controller 60 that enables such partial display control will be described in more detail.

2.1 Specific Example of Configuration FIG. 16 shows an example of a main part of the functional block configuration of the LCD controller 60 in the present embodiment.

  However, the same parts as those of the LCD controller 60 shown in FIG.

  The control circuit 62 further includes an image data generation circuit (image data generation means in a broad sense) 300.

  The image data generation circuit 300 converts, for example, image image data temporarily stored in the RAM 64 into image data of a given format. The converted image data is supplied to the signal driver 30 by, for example, a command sequencer (image data supply means in a broad sense) 70.

  More specifically, the command setting register 72 of the control circuit 62 includes a signal driver setting register 310, a scanning driver setting register 320, and a control register 330.

  The signal driver setting register 310 holds block output selection data 312 and partial display data 314 to be set in the signal driver 30 in order to perform partial display control. The block output selection data 312 and the partial display data 314 are set by a host (not shown) via the host I / O 66.

  The scan driver setting register 320 holds partial scan display data 322 to be set in the scan driver 50 in order to perform partial display control. The partial scan display data 322 is set by a host (not shown) via the host I / O 66.

  The control register 330 holds controller control data for performing operation control of the LCD controller 60. The controller control data is set by a host (not shown) via the host I / O 66. The command sequencer 70 of the LCD controller 60 performs operation control based on the controller control data set in the control register 330, and can perform partial display control for the signal driver 30 and the scan driver 50.

  FIG. 17 shows an example of controller control data held in such a control register 330.

  The control register 330 includes a display data size setting register 332, a mode setting register 336, and a band partial data register (band partial display control data holding unit) 338.

  In the display data size setting register 332, a display data size for specifying an image size displayed on the LCD panel 20 is set. The display data size is set by a host (not shown) via the host I / O 66.

  The mode setting register 336 is set with mode setting data for setting various modes for performing partial display control. As the mode setting data, for example, when data corresponding to each mode is set in the mode setting register 336 by a host (not shown), the command sequencer (mode switching means in a broad sense) 70 operates in the mode. The LCD controller 60 in the present embodiment performs window management that differs depending on the mode, and performs optimum partial display control for the signal driver 30 and the scan driver 50, respectively.

  The band partial data register 338 holds band partial data which is display control data for performing partial display control only in the arrangement direction of the scanning lines. The band partial data is set by a host (not shown) via the host I / O 66. In the present embodiment, partial display control based on the band partial data is performed when a given operation mode is designated by the mode setting register 336 described above.

  For such an LCD controller 60, for example, an operation mode is designated in advance by a mode setting register 336 by a host (not shown). When band partial data is used, the band partial data register 338 is set after the mode setting register 336 sets a given operation mode. In other operation modes, a memory area for managing one or a plurality of windows whose partial display is controlled in the RAM 64 is secured.

  Thereafter, when various data in the signal driver setting register 310 and the scan driver setting register 320 are set by a host (not shown), the LCD controller 60 is set by the command sequencer 70 via the LCD I / O 68 and the signal driver 30 and the scan driver 50. In contrast, a display area and a non-display area are set. More specifically, the command sequencer 70 sets block output selection data and partial display data for the signal driver 30 and sets partial scan display data for the scan driver 50.

  At this time, the LCD controller 60 refers to the display control data or band partial data managed on the memory secured in the RAM 64 according to the operation mode set by the mode setting register 336, and scans the signal driver 30 and the scanning. A display area (non-display area) is set for the driver 50.

  Thereafter, image data generated by a host (not shown) is temporarily stored in the RAM 64, and the image data generation circuit 300 generates given standard image data with reference to the display data size setting register 332, for example. The LCD controller 60 supplies a given display timing to the scanning driver 50 and supplies the generated image data to the signal driver 30 in synchronization with the display timing.

2.2 Partial display control 2.2.1 Refreshing In the past, active matrix liquid crystal panels using TFTs have not performed partial display control that can be dynamically switched. As described above, the AC drive is performed, for example, every 1/60 second in relation to the life of the liquid crystal. However, since the liquid crystal deteriorates if the gate electrode is turned on while the charge is accumulated in the liquid crystal capacitor, it is necessary to discharge the charge accumulated in the liquid crystal capacitor. Therefore, in an active matrix liquid crystal panel using TFTs, the potential difference between the pixel electrode and the counter electrode of the liquid crystal capacitor is set to 0 or a potential difference with some offset is applied to the non-display area.

However, since the charge gradually accumulates in the liquid crystal capacitor due to the leakage of the TFT, even if the gate electrode of the TFT is kept off, the charge exceeding the threshold V _CL is eventually accumulated. As a result, the transmittance of the pixel changes, for example, gray display, and so-called partial display cannot be performed.

  That is, in the case of a passive matrix type liquid crystal panel using STN liquid crystal, the partial display control method that can be easily realized without scanning driving cannot be directly applied to an active matrix type liquid crystal panel using TFTs. Therefore, until now, when a non-display area is set in an active matrix type liquid crystal panel using TFTs, it has only to be fixedly set when the power is turned on, and partial display control capable of dynamically switching cannot be performed.

  On the other hand, in this embodiment, the partial display control which can be switched dynamically is realized by controlling the voltage of the gate electrode of the TFT. And by this partial display control, it becomes possible to reduce or reduce the electric power consumed for the scanning drive of a non-display area.

  More specifically, the scan driver 50 scans the scan lines set in the display area in units of line blocks in one frame cycle, and performs all scans including the scan lines set in the non-display area in units of line blocks. The line is scanned and driven at an arbitrary odd frame period of 3 frames or more. Here, the odd-numbered frame period of 3 or more means that the third frame, the fifth frame,..., (2k + 1) (k is a natural number) is the last frame when a given reference frame is 0 frame. This is the period used as a frame.

  FIGS. 18A and 18B show an example of the operation of the scan driver 50 controlled by the LCD controller 60 in the present embodiment.

  For example, when a plurality of scanning lines extending in the B direction are arranged in the A direction of the LCD panel 20, display areas and non-display areas J and K are set for each line block as shown in FIG. It shall be.

  For example, as shown in FIG. 18B, the scan driver 50 has two frames as shown in FIG. 18B when the first frame is a frame that sequentially scans all scan lines including the line blocks of the display area and the non-display areas J and K. In the empty fourth frame, all the scanning lines of the LCD panel 20 are sequentially scanned and driven. That is, in FIG. 18B, all the scanning lines of the LCD panel 20 are scan-driven at a period of 3 frames.

  For example, when the polarity of the applied voltage of the liquid crystal capacitor in the first frame is positive, the polarity of the applied voltage of the liquid crystal capacitor in the fourth frame is negative, and the polarity of the applied voltage of the liquid crystal capacitor in the seventh frame is positive. AC drive can be realized. Moreover, since the scanning lines corresponding to the non-display areas J and K are not scanned and driven in the second and third frames between the frames (first and fourth frames) in which all the scanning lines are scanned and driven. It becomes possible to reduce power consumption.

  As described above, in an active matrix liquid crystal panel using TFTs, the scan lines of the non-display area are refreshed at an odd number of 3 or more (hereinafter, the same applies unless otherwise specified), thereby reducing the liquid crystal capacitance. The polarity of the applied voltage is reversed, the harmful effects of TFT leakage are prevented, and power consumption can be reduced by reducing unnecessary scanning drive.

2.2.2 Refresh Control With the refresh described above, the active matrix liquid crystal panel using TFTs can be reduced in power consumption, which could not be realized before. In order to further reduce the consumption, the frame frequency is lowered or the refresh cycle described above is lengthened.

  However, in this case, particularly when performing window display by partial display control, window access (the above-mentioned various registers for setting the display area) such as window generation, disappearance, movement or size change during the frame period. When the status of the window to be displayed changes due to access control (display control event), display quality may be degraded due to flickering. This is considered to be caused by, for example, product variations such as TFT leakage, and it is desirable to perform appropriate refresh control to prevent this deterioration in display quality.

  Therefore, in this embodiment, the full scan (full screen scan) is performed in the frame next to the frame in which the window is accessed as described above, thereby avoiding the adverse effects caused by TFT leakage. Then, the full scan frame is used as a reference frame, and thereafter a partial scan is performed with an odd frame period.

  Here, full scan refers to scanning all scan lines regardless of the display area and the non-display area. Further, the partial scan refers to scanning the scan line corresponding to the display area at every frame period and scanning the scan line corresponding to the non-display area at an odd frame period.

  By so doing, it is possible to perform partial display control that can prevent a reduction in display quality due to factors such as product variations and achieve low consumption.

  As specific methods for realizing such refresh control, for example, there are the following three methods. Hereinafter, these methods will be described in detail.

2.2.3 First Method As described above, a frame counter that counts the number of frames is provided in order to scan and drive scan lines corresponding to non-display areas at given odd frame periods of 3 or more. . For example, this frame counter sets a frame to be fully scanned to “0” and increments every frame. For example, when the given number of frames held in the frame interval register matches the counter value of the frame counter, the counter value of the frame counter can be reset to “0”.

  With this configuration, a full scan is performed when a frame whose counter value of the frame counter is “0” is detected, and thereafter a full scan is performed at a cycle of the number of frames held in the frame interval register.

  Therefore, in the first method, the counter value of the frame counter is forcibly reset to “0” in the frame next to the frame that has been accessed.

  FIG. 19 is a diagram for explaining a refresh operation when there is no window access as a comparative example.

  Here, consider a case where the window WID is set in the display area of the LCD panel 20 by the signal driver 30 and the scanning driver 50. Within this window WID, still images and moving images such as text and characters are displayed as a display area.

  In the following description, it is assumed that the 0th frame is used as a reference frame, and a full scan is performed at an odd frame period, for example, at 5 frame periods. That is, the scanning lines corresponding to the display area are scanned at a cycle of every frame, but the scanning lines corresponding to the non-display area are scanned at a cycle of 5 frames. Here, the scan line corresponding to the display area refers to a scan line (display scan line) at least a part of which is included in the display area, and the scan line corresponding to the non-display area is the other scan line (display scan). Non-display scanning lines except lines).

  In the full scan and the partial scan, the polarity of the liquid crystal capacitance applied to the TFT is reversed for each frame by the frame inversion driving method or the line inversion driving method.

  As shown in FIG. 19, in the 0th frame, scanning is performed for all scanning lines in the display area of the LCD panel 20 regardless of the display area and the non-display area because of positive polarity (+) (full scan). ).

  In the next first to fourth frames, the scanning drive is performed only on the scanning lines corresponding to the window WID as a display area while inverting the polarity for each frame (partial scan).

  From the 0th frame to the 4th frame, the number of frames is counted by the frame counter, and the counter value is reset to “0” at the next frame of the 4th frame. However, the positive polarity (+) of the fourth frame is inverted to become negative polarity (−).

  In the fifth frame (0 frame), full scan is performed with negative polarity (-), and in the subsequent 6th to 9th frames (1st to 4th frames), partial scan is performed while inverting the polarity for each frame. Is done.

  Further, in the next tenth frame, the counter value is reset again to “0”, and the full scan is performed with the positive polarity (+) obtained by inverting the negative polarity (−) in the ninth frame, and this is repeated thereafter.

  FIG. 20 is a diagram for explaining the refresh operation when there is a window access in the first method.

  Here, a case where the size is changed from the window WID to the window WID1 during the frame period of the second frame is shown.

  In the first method, as described above, when there is window access in the second frame (positive polarity (+)) in which partial scanning is performed, full scanning is performed in the next third frame (negative polarity (-)). I do.

  Then, in the next fourth frame (positive polarity (+)), a partial scan is performed on the window WID1 after the size change, and then a full scan is performed again in the fifth frame (0 frame) (negative polarity (-)). Do.

  In subsequent 6th to 9th frames (1st to 4th frames), partial scan is performed while inverting the polarity for each frame.

  Further, in the next tenth frame, the counter value is reset again to “0”, and the full scan is performed with the positive polarity (+) obtained by inverting the negative polarity (−) in the ninth frame, and this is repeated thereafter.

  In this way, even when flickering is visible due to window access such as resizing, it is possible to reduce the consumption without degrading the display quality.

  FIG. 21 shows an example of a circuit configuration for realizing the first method.

  Here, ACC is a signal that becomes a logic level “H” when the above-described window access occurs. FR is a polarity inversion signal and is a pulse signal supplied for each frame. FRC <0: 7> is an 8-bit signal with a frame period set in the frame interval register. VCOM is a timing signal for inverting the polarity of the counter electrode. As shown in FIG. 21, VCOM is a signal that is inverted in synchronization with the FR signal. FULLSCAN is a signal for performing the above-described full scan. When the logical level of FULLSCAN is “H” at the scanning timing of the scanning line, scanning driving is performed regardless of the display area and the non-display area.

  FR is supplied to the clock (C) terminals of SDFF1, SDFF2, DFF1, DFF2, and FC. SDFF1 and SDFF2 are D flip-flops with a set, and DFF1 and DFF2 are D flip-flops. FC is an 8-bit frame counter which is incremented by 1 in synchronization with the edge of the signal input to the C terminal, and the internal counter value is reset by the signal input to the reset (R) terminal.

  The inverted output data (XQ) terminal of DFF2 is mutually connected to the data (D) terminal, and the output data (Q) terminal is VCOM.

  ACC is supplied to the set (S) terminal of SDFF1.

  The D terminals of SDFF1 and SDFF2 are connected to the ground level, and the D terminal of DFF1 is connected to the Q terminal of SDFF1.

  FRC <0: 7> is supplied to COMP. COMP is an 8-bit comparator, and can determine whether or not the 8-bit output C <0: 7> of FC matches FRC <0: 7> for each bit.

  The output of COMP is supplied to the S terminal of SDFF2 and the R terminal of FC via DLY. DLY is a delay element. When the FC output coincides with FRC <0: 7>, the FC counter value is reset after a given delay time has elapsed.

  The logical sum of the output from the Q terminal of DFF1 and the output from the Q terminal of SDFF2 is FULLSCAN.

  FIGS. 22A, 22B, 22C, and 22D show timing charts in the circuit shown in FIG.

  Here, FIG. 22A is a timing chart showing the refresh control by the circuit when there is a window access when VCOM is positive logic in the second frame. FIG. 22B is a timing chart showing the refresh control by the circuit when there is a window access when VCOM is negative logic in the second frame. FIG. 22C is a timing chart showing refresh control by the circuit when there is a window access when VCOM is positive logic in the third frame. FIG. 22D is a timing chart showing the refresh control by the circuit when there is a window access when VCOM is negative logic in the third frame.

  In this way, the logical level of FULLSCAN is “H” in the frame next to the frame that has been accessed. For example, when FULLSCAN becomes a logic level “H”, the LCD controller 60 sends a command to the gate driver 50 and sets the scanning line to scan regardless of the display area and the non-display area. . By doing so, the gate driver 50 performs a full scan.

2.2.4 Second Method In the first method, when there is a window access, the full scan is performed in the next frame while fixing the frame period for performing the full scan. Therefore, for example, as shown in FIG. 20, the full scan is performed in the third frame and the fifth frame, but since both are performed with negative polarity (-), a sense of incongruity is coordinated for the viewer watching the screen. There is.

  Therefore, in the second method, a full scan is performed at the frame next to the window accessed frame, the counter value of the frame counter is reset, and thereafter, the full scan is performed at a given odd frame period of 3 or more. Like to do.

  FIG. 23 is a diagram for explaining a refresh operation when there is a window access in the second method.

  Here, a case where the size is changed from the window WID to the window WID1 during the frame period of the second frame is shown.

  In the second method, as described above, when window access is performed in the second frame (positive polarity (+)) in which partial scanning is performed, full scanning is performed in the next frame (third frame). At this time, the frame counter is reset, and full scan is performed again with the negative polarity (−) in which the polarity of the second frame is inverted.

  In subsequent 4th to 7th frames (1st to 4th frames), partial scan is performed while inverting the polarity for each frame.

  Further, in the next 8th frame, the counter value is reset to “0” again, the full scan is performed with the positive polarity (+) in which the negative polarity (−) of the 7th frame is inverted, and this is repeated thereafter.

  By doing this, there is no case where a sense of incongruity is emphasized by a full scan of the same polarity by window access such as size change, and the display quality can be further improved.

  FIG. 24 shows an example of a circuit configuration for realizing the second method.

  However, the same parts as those of the circuit shown in FIG.

  The circuit shown in FIG. 24 differs from the circuit shown in FIG. 21 in that an AND output of the inverted output from SDFF1 and the output of DLY is supplied to the R terminal of FC.

  FIGS. 25A, 25B, 25C, and 25D show timing charts in the circuit shown in FIG.

  Here, FIG. 25A is a timing chart showing refresh control by the circuit when there is a window access when VCOM is positive logic in the second frame. FIG. 25B is a timing chart showing refresh control by the circuit when there is a window access when VCOM is negative logic in the second frame. FIG. 25C is a timing chart showing refresh control by the circuit when there is a window access when VCOM is positive logic in the third frame. FIG. 25D is a timing chart showing refresh control by the circuit when there is a window access when VCOM is negative logic in the third frame.

  As described above, the FULLSCAN logical level becomes “H” and the FC counter value is also reset to “0” in the frame next to the frame that has been accessed. Therefore, after that, a full scan is performed in a given odd frame period of 3 or more held in the frame interval register with reference to the frame next to the frame accessed by the window.

2.2.5 Third Method In the second method, when there is a window access, a full scan is performed in the next frame, and then a full scan is performed with an odd frame period thereafter on the basis of the next frame. It was.

  However, particularly when the frame frequency is low, the display quality may be degraded for a frame that has been window accessed.

  Therefore, in the third method, in addition to the second method, a frame that has undergone window access is also fully scanned after the timing at which window access occurs.

  FIG. 26 is a diagram for explaining a refresh operation when window access is performed in the third method.

  Here, a case where the size is changed from the window WID to the window WID1 during the frame period of the second frame is shown.

  In the third method, as described above, when window access is performed in the second frame (positive polarity (+)) in which partial scanning is performed, full scanning is performed in the next frame (third frame). At this time, in the second frame in which window access is made, for example, the timing at which window access occurs is between the scan timing of the (N0-1) -th scan line and the scan timing of the N0-th scan line. In this case, for the N0th and subsequent lines, the scanning lines are scan-driven regardless of the display area and the non-display area.

  Then, in the fourth to seventh frames (1 to 4 frames) following the third frame (0 frame) in which the full scan is performed, the partial scan is performed while inverting the polarity for each frame.

  Further, in the next 8th frame, the counter value is reset to “0” again, the full scan is performed with the positive polarity (+) in which the negative polarity (−) of the 7th frame is inverted, and this is repeated thereafter.

  In this way, even when the frame frequency is low, the display quality does not deteriorate in a frame that has undergone window access such as a size change. Therefore, it is possible to achieve both reduction in power consumption due to a decrease in frame frequency and prevention of deterioration in display quality.

  FIG. 27 shows an example of a circuit configuration for realizing the third method.

  However, the same parts as those of the circuit shown in FIG.

  The circuit shown in FIG. 27 is different from the circuit shown in FIG. 24 in that SDFF 3 is provided instead of DFF 1. ACC is supplied to the S terminal of SDFF3.

  With this configuration, the data held in the SDFF 3 is set asynchronously with the FR in accordance with the timing at which window access occurs. Then, due to the set retained data, the logical level of FULLSCAN becomes “H” in the middle of the frame in which window access occurs.

  28A, 28B, 28C, and 28D are timing charts in the circuit shown in FIG.

  Here, FIG. 28A is a timing chart showing refresh control by the circuit when there is a window access when VCOM is positive logic in the second frame. FIG. 28B is a timing chart showing refresh control by the circuit when there is a window access when VCOM is negative logic in the second frame. FIG. 28C is a timing chart showing the refresh control by the circuit when there is a window access when VCOM is positive logic in the third frame. FIG. 28D is a timing chart showing refresh control by the circuit when there is a window access when VCOM is negative logic in the third frame.

  In this way, the logical level of FULLSCAN becomes “H” in synchronization with the ACC in the middle of the frame in which the window is accessed. Further, the logical level of FULLSCAN also becomes “H” in the next frame, and the FC counter value is also reset to “0”.

  Therefore, in a frame in which window access has been performed, the scan lines after the window access occurrence timing are scanned regardless of the display area and the non-display area. Thereafter, a full scan is performed at a given odd frame period held in the frame interval register with reference to the frame next to the frame accessed by the window.

  A circuit that embodies the third method may be configured as follows. That is, for example, when a full scan is performed with an N1 (odd) frame period, when the window is accessed, the counter value of the frame counter is not reset but (N1-1) is forcibly set. To load. Therefore, in the next frame, since the counter value of the frame counter is reset, the same operation as the above-described circuit can be performed.

  FIG. 29 shows a modification of the circuit configuration for realizing the third method.

  However, the same parts as those of the circuit shown in FIG.

  The circuit shown in FIG. 29 differs from the circuit shown in FIG. 27 in that the FC is provided with a load (L) terminal and a DATA <0: 7> terminal, and the output of DLY is sent to the S terminal of SDFF2 and the R terminal of FC. It is a point that is supplied to.

  ACC is supplied to the L terminal of the FC. FRC-1 <0: 7> is supplied to the DATA <0: 7> terminal of the FC. FRC-1 <0: 7> is 8-bit data obtained by subtracting 1 from the 8-bit data represented by FRC <0: 7>.

  When the logic level of the signal input to the L terminal becomes “H”, the FC loads the 8-bit data input to the DATA <0: 7> terminal into the internal counter value.

  Even with this configuration, the data held in the SDFF 3 is set asynchronously with the FR in accordance with the timing at which the window access occurs. Then, due to the set retained data, the logical level of FULLSCAN becomes “H” in the middle of the frame in which window access occurs.

  Then, in the next frame in which window access has been made, the FC counter value becomes “0”, and the FULLSCAN logical level becomes “H”.

2.3 Window Management As described above, the LCD controller 60 in the present embodiment can perform window display by setting a display area and a non-display area for the signal driver 30 and the scan driver 50, respectively.

  In the present embodiment, in order to manage one or a plurality of windows on the screen of the LCD panel 20, window management data (partial display control data in a broad sense) is stored in the RAM 64, and each window management data is based on the window management data. Control window display. More specifically, window management data is associated with the display area of the LCD panel 20, and one or more windows displayed on the LCD panel 20 are managed based on the window management data corresponding to the display area.

  For example, the display position of the LCD panel 20 corresponding to the address whose window management data is set to “1” is used as the display area, and the display of the LCD panel 20 corresponding to the address whose window management data is set to “0” is displayed. The position can be a non-display area.

  In the present embodiment, display control of this window management data is performed in units of either an area block unit or a line block unit divided every 8 scan lines specified by the band partial data according to each operation mode. I do.

  FIGS. 30A, 30B, and 30C are schematic diagrams for explaining window management data in each operation mode.

  Here, the screen size (display area) of the LCD panel 20 is 176 × 144 pixels.

  For example, when the display area or non-display area set for the screen of the LCD panel 20 is set in units of pixels, the LCD controller 60 displays an image of 176 × 144 pixels as shown in FIG. It is necessary to secure a memory area for 18 bits of data (6 bits (gradation data) × 3 (RGB colors)).

  In contrast, in the first mode set by the mode setting register 336 in the present embodiment, the display area or non-display area set for the screen of the LCD panel 20 is set in units of area blocks.

  Here, the area block has an area obtained by dividing a signal line in units of 8 pixels and dividing a scanning line in units of 8 lines.

  Therefore, as shown in FIG. 30B, the LCD controller 60 secures a memory area for image data of 22 × 18 area blocks. As a result, the memory area to be secured in the RAM 64 can be greatly reduced.

  In the second mode set by the mode setting register 336, the display area or non-display area set for the screen of the LCD panel 20 is 8 scan lines only in the direction in which the scan lines are arranged according to the band partial data. Set in units.

  Therefore, the LCD controller 60 holds the band partial data for 18 line blocks in the band partial data register 338 of the control register 330 as shown in FIG. This eliminates the need to secure a memory area in the RAM 64.

2.3.1 First Mode In the first mode, a window is displayed at a corresponding position in the display area of the LCD panel 20 based on window management data managed in units of area blocks.

  As a comparative example, FIG. 31 schematically shows coordinate designation when performing window display based on window management data managed in units of pixels.

In this case, in order for the LCD controller 60 to display a rectangular window in the display area 502 of the display area 500 of the LCD panel 20, the upper left coordinates LU (X _S , Y _S ) and the lower right coordinates RD (X _E , Y _E ) are specified.

  Therefore, when the window management data is managed in units of pixels, the number of bits necessary for designating each coordinate to specify 176 × 144 pixels is “8”. That is, in order to designate the display area 502, at least 32 bits ((8 bits + 8 bits) × 2) are required. When three windows can be managed simultaneously by the window management data, 96 bits are required to specify the display area.

  FIG. 32 schematically shows the designation of coordinates when performing window display based on window management data managed in area block units in the first mode.

In the first mode, the LCD controller 60 displays the upper left coordinates LU (XB _S , YB _S ) and lower right coordinates of the display area 512 in order to display a rectangular window in the display area 512 of the display area 510 of the LCD panel 20. Specify RD (XB _E , YB _E ).

  In the window management data (area block display control data) managed in area block units, the number of bits required for each coordinate position is “5” in order to identify any area block of 22 × 18 area blocks. Become. That is, in order to specify the display area 512, at least 20 bits ((5 bits + 5 bits) × 2) are required. When three windows can be managed at the same time using window management data, only 60 bits are required to designate the display area, and the window designation can be made more efficient than when managing windows in units of pixels. .

  Here, when the scanning line extends in the B direction of the LCD panel 20, it is assumed that the scanning driver 50 that scans the scanning line is disposed at a position shown in FIG. 33 with respect to the LCD panel 20.

  First, the LCD controller 60 sets window management data corresponding to a display area or a non-display area by the host.

  The LCD controller 60 that performs the partial display control described above scans the window management data 520 set for each area block unit along the scan direction 522 in the first mode.

  When the window management data 520 is scanned for each line along the scan direction 522 and there is at least one area block with “1” set, it is determined that the corresponding scan line is turned on. Then, the command sequencer (scan driving circuit setting means, signal driving circuit setting means in a broad sense) 70 of the LCD controller 60 sets a display area for the scanning driver 50 and the signal driver 30. More specifically, the command sequencer 70 sets the partial scan display selection register of the scan driver 50 based on the partial scan display data 322, and sets the block output selection register and the partial display selection register of the signal driver 30 to block output. This is set based on the selection data 312 and the partial scan data 314. Then, the command sequencer 70 supplies the scan driver 50 with the scan enable input / output signal GEIO in accordance with the scan timing of the scan line, and supplies the scan line 50 to the signal driver 30 with a given horizontal scan period. Image data is sequentially supplied to the signal driver 30 every minute.

  On the other hand, when all the area blocks for one line are set to “0” when data is scanned along the scan direction 522, it is determined that the scan line is in the scan drive off state. . As described above, it is necessary to periodically scan and drive the LCD panel 20 to discharge charges accumulated in the liquid crystal capacitance due to TFT leakage. For this reason, the scan line determined to be in the scan drive off state is scan-driven in an arbitrary odd frame period with a given reference frame as a reference, and is not driven in other periods. Therefore, the LCD controller 60 (command sequencer 70) supplies the output enable signal XOEV in accordance with the scanning timing of the scanning line only in the scanning drive frame.

  Here, as a given reference frame, for example, an event such as generation, disappearance, or change of a window occurs, and access to any of the signal driver setting register 310, the scan driver setting register 320, or the control register 330 described above is performed. A frame corresponding to the timing. That is, by accessing these various registers, the scanning lines in the non-display area are scan-driven at any odd frame period with reference to the frame in which the displayed window is changed.

  As described above, since the signal driver 30 and the scan driver 50 are output controlled in units of 24 outputs and 8 scan lines, each window is designated in units of 24 outputs and 8 scan lines. However, the present invention is not limited to this, and the LCD controller 60 can also manage window management data in units of pixels.

  Here, each line block serving as an output control unit of the signal driver 30 and the scanning driver 50 has been described in units of 24 outputs or 8 scanning lines. However, the present invention is not limited to this. It is possible to use 24 outputs or less or 8 scan lines or less as a unit.

2.3.2 Second Mode FIG. 34 schematically shows coordinate designation when performing window display based on band partial data in the second mode.

  In the second mode, the LCD controller 60 sets the display area 552 in the display area 550 of the LCD panel 20, in accordance with the band partial data (band partial display control data). Specify an area.

  Accordingly, in order to specify the display area 552, the number of bits required is only 1 bit in units of 8 scan lines. As a result, the number of bits for designating the display area can be greatly reduced.

  Here, as shown in FIG. 33, assuming that the scanning line extends in the B direction of the LCD panel 20, the LCD controller 60 first sends band partial data corresponding to the display area or non-display area by a host (not shown). Is set.

  In the second mode, the LCD controller 60 that performs the partial display control described above refers to the band partial data, and determines that the scanning line of the line block in which “1” is set is on for scanning driving. In this case, the command sequencer (scan drive circuit setting means in a broad sense) 70 of the LCD controller 60 sets a display area for the scan driver 50. More specifically, the command sequencer 70 sets the partial scan display selection register of the scan driver 50 based on the partial scan display data 322. Then, the command sequencer 70 supplies a scan enable input / output signal GEIO to the scan driver 50 in accordance with the scan timing of the scan line. The command sequencer 70 sequentially supplies image data to the signal driver 30 for each scanning line in a given horizontal scanning cycle.

  On the other hand, the scanning line of the line block in which the band partial data is set to “0” is determined to be scanning driving off. As described above, it is necessary to periodically scan and drive the LCD panel 20 to discharge charges accumulated in the liquid crystal capacitance due to TFT leakage. For this reason, the scan line determined to be in the scan drive off state is scan-driven in an arbitrary odd frame period with a given reference frame as a reference, and is not driven in other periods. Therefore, the LCD controller 60 (command sequencer 70) supplies the output enable signal XOEV in accordance with the scanning timing of the scanning line only in the scanning drive frame.

  The LCD controller 60 in the present embodiment realizes such mode switching by the mode setting register 336, thereby improving the memory capacity efficiency and simplifying the display window designation.

2.4 Generation of Standard Data The LCD controller 60 sets a display area for the signal driver 30 and the scanning driver 50 as described above, and transmits image data corresponding to the display area to the signal driver 30. Supply. This image data is created by a user, for example, and supplied to the LCD controller 60.

  By the way, the signal driver 30 described above can cope with a change in the panel size of the LCD panel 20 based on the block output selection data. Therefore, signal driving is not performed for signal lines of unnecessary line blocks. Therefore, in this state, when supplying the created image data to the LCD controller 60, the user needs to know which line block of the signal line is not signal-driven. That is, the user needs to process the generated image data and supply it to the LCD controller 60 so that a normal image can be displayed when signal driving is performed with the line block excluded.

  Therefore, the LCD controller 60 according to the present embodiment can generate image data for the signal driver 30 in accordance with the block output selection data in order to improve the user-friendliness. As a result, the user does not recognize the block output selection data set in the signal driver 30 (there is no need to grasp which signal line of the line block does not perform signal driving), and the generated image data is used as it is. It only needs to be supplied to the LCD controller 60.

  Below, this point is demonstrated concretely.

  Here, the display area of the LCD panel 20 is divided into 6 line blocks in the B direction, and the A direction is not considered. Further, the signal driver 30 is assumed to be able to drive a signal line of, for example, an 8-line block divided into 24 output units.

  When signal driving is performed on the LCD panel 20 by the signal driver 30, in order to drive the signal lines for 6 line blocks, 2 line blocks near the center are excluded by block output selection data. That is, as shown in FIG. 35, for example, when the system is turned on, “11100111” is set by the block output selection data.

  Therefore, the signal driver 30 drives only the signal lines BLK0 to BLK2 and BLK5 to BLK7, and sets the outputs of the signal line driving circuits BLK3 and BLK4 to a high impedance state. BLK0 to BLK2 and BLK5 to BLK7 of the signal driver 30 drive the signal lines of the block numbers 0 to 5 of the LCD panel 20, respectively.

  Consider a case where the user generates image data for four line blocks in the B direction on such an LCD panel 20.

  FIG. 36 schematically shows an image created by a user, for example.

  When the user creates an image image of one frame for four line blocks in the B direction and displays it in the display area 602 of the display area of the LCD panel 20, the user displays a partial display for six line blocks as the display area. For data, the line block corresponding to the display area is set to “1”.

  Generally, the user (image developer) does not know which line block is used for the signal driver 30 that drives the LCD panel 20. This is because which signal line of the signal driver 30 for driving the LCD panel 20 is arbitrarily determined by the design policy of the manufacturer. Therefore, the user sets a total of four line blocks of block numbers 1 to 4 among the block numbers 0 to 5 of the line blocks as a display area. That is, the user sets “011110” as the partial display data PARTu.

  In this case, as shown in FIG. 37, the display areas set by the user by the partial display data PARTu are set redundantly for BLK3 and BLK4 of the signal driver 30. Therefore, even if an image stream (image data) is supplied corresponding to the partial display data PARTu, only the line block in which both the block output selection data and the partial display data are set to “1” is signal-driven. As a result, the image 610 is displayed.

  Therefore, in the present embodiment, by shifting the partial display data PARTu corresponding to the line block for which “0” is set in the block output selection data, the user can correctly correct the setting value of the block output selection data without considering it. An image corresponding to the display area can be displayed. Corresponding to this, the image stream is shifted to generate a standard format image stream.

  More specifically, as shown in FIG. 38, the partial display data PARTu corresponding to the line block set to “0” in the block output selection data is changed to the line block set to “1” in the block output selection data. Is converted to partial display data PART shifted up to. Then, the partial display data PART is supplied to the signal driver 30. Then, dummy image data is inserted into the image stream corresponding to the position shifted during the conversion. By doing so, signal drive based on the image stream corresponding to BLK5 and BLK6 of the signal driver 30 can be performed on the signal lines of the block numbers 3 and 4 of the LCD panel 20, and the correct image 620 is displayed in the display area. To be able to.

  Therefore, the LCD controller 60 in the present embodiment includes a partial display data conversion circuit that converts the partial display data PART from such partial display data PARTu.

  FIG. 39 shows an example of this partial display data conversion circuit.

FF _{BLK0 to} FF _BLK7 are reset by a reset signal RESET, and latch a total of 8 bits of block output selection data BLK <0: 7> in synchronization with the clock signal BCLK.

FF _PART0 to ff _PART7 is reset by a reset signal RESET, respectively in synchronism with the clock signal PCLK, partial display data PARTu set by the user <0: 7> to latch the eight bits in total.

Each Q terminal of the _{FF BLK0 ~FF BLK7, FF PART0 ~FF} PART7 is connected to the selector circuit SEL.

The selector circuit SEL _ab to which each Q terminal of FF _BLKa and FF _PARTb is connected is output from the Q terminal of FF _PARTa-1 when the block output selection data output from the Q terminal of FF _BLKa is “0”. Select and output partial display data. The selector circuit SEL _ab where each Q terminal of FF _BLKa and FF _{Part B} is connected, when the block output select data output from the Q terminal of the FF _BLKa is "1", is output from the Q terminal of the FF _parta Select and output partial display data.

  Therefore, partial display data PART (second partial display data) in which partial display data PARTu (first partial display data) is sequentially shifted is generated for a line block whose block output selection data is set to “0”. Will be.

  The LCD controller 60 (command sequencer (block output selection data setting means, partial display data setting means in a broad sense) 70) sends the partial display data PART together with the block output selection data to the corresponding register of the signal driver 30. Will be set.

  Similarly, the image data generation circuit 300 generates image data in which dummy image data is inserted into the shifted line block, and supplies a regular image stream for eight line blocks to the signal driver 30.

  More specifically, the image data generation circuit 300 includes the P-th block designated in the display area by the partial display data PARTu (first partial display data) by the user who designates the display area or the non-display area. When image data supplied to the signal driver 30 is designated as a line block that is not signal-driven by the block output selection data, the image data corresponding to the P-th block is the image data of the (P + 1) -th block. As a shifted image stream. Then, the command sequencer 70 supplies the converted image stream to the command sequencer 70.

  By doing this, as described above, the user does not recognize the set value of the block output selection data, and the display area set using the signal driver 30 that can be flexibly adapted to the panel size of the LCD panel 20 A correct image can be displayed.

2.5 Command Specification The LCD controller 60 can supply an image stream to the signal driver 30 as follows.

  That is, as shown in FIG. 40A, a series of image streams is supplied after a command (CMDD) for designating a display area is transmitted, and a series of image streams as shown in FIG. In some cases, a command (CMDD) for designating a display area is transmitted after transmitting. Here, the command (CMDD) includes, for example, setting of a block output selection register of the signal driver 30 and a partial display selection register.

  As shown in FIG. 40A, in the case of supplying a series of image streams after transmitting a command (CMDD) for designating a display area, only image data corresponding to the display area needs to be supplied. The amount of image data to be reduced can be reduced. In addition, since the image stream is captured after receiving the command, the capturing of the image data in the non-display area specified by the command can be stopped, and the consumption can be reduced accordingly.

  On the other hand, as shown in FIG. 40B, when a command (CMDD) for designating a display area is transmitted after transmitting a series of image streams, it is necessary to supply image data for the entire display area. However, the generation processing of the image data to be supplied is simplified, and stable image data can be supplied even when the time to be processed becomes shorter as the frame frequency increases or the image size increases.

2.6 Example of Display Control Timing An example of partial display control by the LCD controller 60 in the present embodiment will be specifically described.

  FIG. 41 shows an example of the operation timing of the signal driver 30 that is subjected to partial display control by the LCD controller 60 in the present embodiment.

  As described above, in the signal driver 30 in which the display area or the non-display area is set in units of line blocks by the LCD controller 60, the shift register shifts the enable input / output signal EIO in synchronization with the clock signal CLK. EIO1 to EIOL (L is a natural number of 2 or more) are generated. Then, the image data (DIO) is sequentially latched in the line latch in synchronization with each of the EIO1 to EIOL.

  The line latch 36 latches image data for one horizontal scanning unit in synchronization with the rising edge of the horizontal synchronizing signal LP, and the signal line is driven by the DAC 38 and the signal line driving circuit 40 from the falling edge.

  For the signal lines of the line block set in the display area by the LCD controller 60, the signal lines are driven based on the drive voltage generated based on the gradation data. On the other hand, for the signal lines of the line block set in the non-display area, the LCD controller 60 selectively outputs one of the counter electrode voltage Vcom and the voltage at both ends of the gradation voltage level.

  Further, the signal line of the line block for which the block output non-selection is selected is set to a high impedance state (not shown).

  FIG. 42 shows an example of the operation timing of the scan driver 50 that is subjected to partial display control by the LCD controller 60 in the present embodiment.

  Here, it is assumed that only the block B1 is set as the display area and the blocks B0, B2,... Are set as the non-display area by the LCD controller 60.

  As described above, the scan driver 50 sequentially scans all the scan lines corresponding to the blocks B0 to BQ in the first frame and the fourth frame, for example, and is set in the display area in the second frame and the third frame, for example. Only the scanning lines of the block B1 are scanned.

  More specifically, the scan driver 50 supplies the enable input / output signal EIO only to the scan lines of the line block set in the display area in the second and third frames. Therefore, the scan driver 50 scans and drives only the period T11 corresponding to the display area. At this time, the signal driver 30 controlled by the LCD controller 60 drives the signal line based on the image data corresponding to the display area. In this way, it is sufficient to drive only at the scanning timing corresponding to the display area, and the scanning drive stop period T12 can be provided in the second frame and the third frame.

  For this reason, in the second frame and the third frame, it is not necessary to perform the scanning driving for the scanning driving stop period, so that the consumption can be reduced correspondingly.

  Here, in each frame, a given non-display level voltage is supplied to the signal line in the non-display area by the signal driver 30 so that the voltage applied to the liquid crystal capacitance does not exceed a given threshold. Therefore, it is possible to set a window for displaying a desired image only in the set display area.

2.7 Start-up Sequence The LCD controller 60 as described above controls the display of the LCD panel by controlling the signal driver 30 and the scan driver 50 in accordance with the contents set by the host such as a CPU.

  Accordingly, when the display device according to this embodiment is activated individually without any consideration regarding the sequence after activation of the display device (particularly the sequence after activation of the LCD controller), parameters are transmitted to a circuit that has not been activated, etc. It may not work properly due to a bug in the system.

  In the present embodiment, a desired image is displayed after the signal driver 30 and the scan driver 50 are activated in the following procedure.

  FIG. 43 schematically shows a startup sequence of the display device in the present embodiment.

  First, when system power is turned on, resets are activated all at once, and then the LCD controller 60 is activated from the host (CPU 1). This can be realized, for example, by releasing the reset of the LCD controller 60.

  The LCD controller 60 is activated in response to this (CNT1).

  In addition, the host transmits parameters such as the frequency of the step-up / step-down clock that determines the step-up efficiency and step-down efficiency of the power supply circuit to the LCD controller 60 (CNT2). In the present embodiment, the power supply circuit is controlled by the LCD controller 60. Therefore, the LCD controller 60 activates the power supply circuit (releases the reset) (CNT2) and waits for a given wait cycle to pass (CNT3). The LCD controller 60 activates the signal driver 30 (cancels reset) (CNT4) and activates the scanning driver 50 (CNT5) after a given wait cycle has elapsed (CNT3).

  As a result, the signal driver 30 and the scan driver 50 that have received an instruction from the LCD controller 60 are activated (SDR1, GDR1).

  Next, the LCD controller 60 transmits a system enable signal to notify the host that the display device is ready to be activated (CNT6). Receiving this, the host initializes the system (CPU 3).

  Further, the host transmits the signal driver parameters and the scan driver parameters to the LCD controller 60 (CPU4, CPU5). Here, the parameter for the signal driver means, for example, setting data of the block output selection register, setting data of the partial display selection register, or the like. The scan driver parameter refers to, for example, setting data of a partial scan display selection register.

  When the LCD controller 60 receives the parameter for the signal driver from the host, the LCD controller 60 performs processing for setting the signal driver 30 according to the content (CNT7, SDR2). When the LCD controller 60 receives a scan driver parameter from the host, the LCD controller 60 performs processing for setting the scan driver 50 in accordance with the content (CNT8, GDR2).

  Then, the host transmits the image stream to the LCD controller 60 (CPU 6), and the LCD controller 60 performs display control on the signal driver 30 and the scanning driver 50 as described above (CNT9). The signal driver 30 and the scanning driver 50 perform signal driving (SDR3) and scanning driving (GDR3) to display an image on the liquid crystal panel of the display device.

3. Others In the present embodiment, a liquid crystal device provided with an LCD panel using TFT liquid crystal has been described as an example. However, the present invention is not limited to this. For example, the present invention can also be applied to a signal driver and a scan driver that display-drive an organic EL panel including an organic EL element provided corresponding to a pixel specified by a signal line and a scan line.

  FIG. 44 shows an example of a two-transistor pixel circuit in an organic EL panel whose display is controlled by such a signal driver and scan driver.

The organic EL panel has a driving TFT 800 _nm , a switch TFT 810 _nm , a holding capacitor 820 _nm, and an organic LED 830 _{nm at} the intersection of the signal line S _m and the scanning line G _n . The driving TFT 800 _nm is configured by a p-type transistor.

The driving TFT 800 _nm and the organic LED 830 _nm are connected in series to the power supply line.

Switch TFT 810 _nm has a gate electrode of the driving TFT 800 _nm, it is inserted between the signal line S _m. The gate electrode of the switching TFT 810 _nm is connected to the scanning line G _m.

The holding capacitor 820 _nm is inserted between the gate electrode of the driving TFT 800 _nm and the capacitor line.

In such an organic EL element, when the scanning line G _n is driven and the switch TFT 810 _nm is turned on, the voltage of the signal line S _m is written to the holding capacitor 820 _nm and applied to the gate electrode of the driving TFT 800 _nm . The gate voltage Vgs of the driving TFT 800 _nm is determined by the voltage of the signal line S _m, the current flowing through the driving TFT 800 _nm is determined. Since the driving TFT 800 _nm and the organic LED 830 _nm are connected in series, the current flowing through the driving TFT 800 _nm becomes the current flowing through the organic LED 830 _{nm as} it is.

Therefore, by holding the gate voltage Vgs corresponding to the voltage of the signal line S _m by the hold capacitor 820 _nm, for example, during one frame period, by flowing a current corresponding to the gate voltage Vgs to the organic LED 830 _nm, the frame A pixel that continues to shine can be realized.

  FIG. 45A shows an example of a 4-transistor pixel circuit in an organic EL panel whose display is controlled by the signal driver and scan driver described above. FIG. 45B shows an example of the display control timing of this pixel circuit.

Again, the organic EL panel includes a drive TFT 900 _nm, a switch TFT 910 _nm, a storage capacitor 920 _nm, and an organic LED 930 _nm.

A difference from the two-transistor pixel circuit shown in FIG. 44 is that a constant current Idata from a constant current source 950 _nm is supplied to the pixel via a p-type TFT 940 _nm as a switching element instead of a constant voltage. The point is that the power supply line is connected to the holding capacitor 920 _nm and the driving TFT 900 _nm via the p-type TFT 960 _nm as a switching element.

In such an organic EL element, first, the p-type TFT 960 is turned off by the gate voltage Vgp to cut off the power supply line, the p-type TFT 940 _nm and the switch TFT 910 _nm are turned on by the gate voltage Vsel, and the constant current source 950 _nm A constant current Idata is passed through the driving TFT 900 _nm .

Until the current flowing through the driving TFT 900 _nm is stabilized, the holding capacitor 920 _nm holds a voltage corresponding to the constant current Idata.

Then, turn off the p-type TFT 940 _nm and the switch TFT 910 _nm by the gate voltage Vsel, further to turn on the p-type TFT 960 _nm by the gate voltage Vgp, to electrically connect the driving TFT 900 _nm and the organic LED 930 _nm and a power supply line. At this time, the voltage held in the hold capacitor 920 _nm, or approximately equal to the constant current Idata, or the magnitude of the current corresponding thereto is supplied to the organic LED 930 _nm.

  In such an organic EL element, for example, the scanning line can be configured as a gate voltage Vsel and the signal line can be configured as a data line.

  In the organic LED, a light emitting layer may be provided on the transparent anode (ITO), and a metal cathode may be provided on the light emitting layer. A light emitting layer, a light transmitting cathode, and a transparent seal may be provided on the metal anode. However, the present invention is not limited to the element structure.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention. For example, the present invention can be applied to a plasma display device.

It is a block diagram which shows the outline | summary of a structure of the display apparatus to which the display control circuit (LCD controller) in this embodiment is applied. FIG. 2 is a block diagram illustrating an outline of a configuration of a signal driver illustrated in FIG. 1. It is explanatory drawing which shows the outline | summary of a structure of a block output selection register. It is explanatory drawing which shows the outline | summary of a structure of a partial display selection register. It is a block diagram which shows the outline | summary of a structure of the line block unit of a signal driver. It is a block diagram which shows an example of a structure of SR which comprises the shift register of a signal driver. FIG. 2 is a block diagram illustrating an outline of a configuration of a scan driver illustrated in FIG. 1. It is explanatory drawing which shows the outline | summary of a structure of the partial scanning display selection register. It is a block diagram which shows the structure principal part of a scanning driver. It is a block diagram which shows the outline | summary of a structure of the LCD controller shown in FIG. FIG. 11A is a schematic diagram schematically showing waveforms of the signal line drive voltage and the counter electrode voltage Vcom by the frame inversion drive method. FIG. 11B is a schematic diagram schematically showing the polarity of the voltage applied to the liquid crystal capacitor corresponding to each pixel for each frame when the frame inversion driving method is performed. FIG. 12A is a schematic diagram schematically showing the waveform of the signal line drive voltage and the counter electrode voltage Vcom by the line inversion drive method. FIG. 12B is a schematic diagram schematically showing the polarity of the voltage applied to the liquid crystal capacitance corresponding to each pixel for each frame when the line inversion driving method is performed. It is explanatory drawing which shows an example of the drive waveform of the LCD panel of a liquid crystal device. FIGS. 14A, 14B, and 14C are explanatory views schematically showing an example of partial display control realized by the LCD controller in the present embodiment. FIGS. 15A, 15 </ b> B, and 15 </ b> C are explanatory diagrams schematically showing another example of partial display control realized by the LCD controller in the present embodiment. It is a block diagram which shows the principal part of a structure of the LCD controller in this embodiment. It is explanatory drawing which shows the outline | summary of a structure of the control register in this embodiment. 18A and 18B are explanatory diagrams showing an example of the operation of the scan driver. It is explanatory drawing for demonstrating the refresh operation | movement when there is no window access. It is explanatory drawing for demonstrating the refresh operation | movement when there exists window access in the 1st method of implement | achieving the refresh control in this embodiment. It is an example of the circuit block diagram for implement | achieving the 1st method in this embodiment. 22A, 22B, 22C, and 22D are timing charts showing an example of the timing of the circuit configuration diagram for realizing the first method in the present embodiment. It is explanatory drawing for demonstrating the refresh operation | movement when there exists window access in the 2nd method of implement | achieving the refresh control in this embodiment. It is an example of the circuit block diagram for implement | achieving the 2nd method in this embodiment. FIGS. 25A, 25 </ b> B, 25 </ b> C, and 25 </ b> D are timing charts showing an example of timing of a circuit configuration diagram for realizing the second method in the present embodiment. It is explanatory drawing for demonstrating the refresh operation | movement when there exists window access in the 3rd method of implement | achieving the refresh control in this embodiment. It is an example of the circuit block diagram for implement | achieving the 3rd method in this embodiment. FIGS. 28A, 28 </ b> B, 28 </ b> C, and 28 </ b> D are timing charts showing an example of the timing of the circuit configuration diagram for realizing the third method in the present embodiment. It is a modification of the circuit block diagram for implement | achieving the 3rd method in this embodiment. FIGS. 30A, 30B, and 30C are explanatory diagrams for explaining window management data in each operation mode. It is explanatory drawing for demonstrating the case where a window is managed per pixel. It is explanatory drawing for demonstrating the case where a window is managed per area block. It is explanatory drawing for demonstrating the scanning drive control at the time of managing a window per area block. It is explanatory drawing for demonstrating the case where a window is managed by belt | band | zone partial data. It is explanatory drawing which shows an example of the mounting state of a signal driver. It is explanatory drawing for demonstrating the partial display data corresponding to the image produced by the user. It is explanatory drawing for demonstrating the relationship between the partial display data corresponding to the image produced by the user, and block output selection data. It is explanatory drawing for demonstrating the necessity of conversion of the partial display data corresponding to the image produced by the user based on block output selection data. It is a block diagram which shows an example of a structure of a partial display data conversion circuit. FIG. 40A is an explanatory diagram schematically illustrating a case where a series of image streams is supplied after a command for designating a display area is transmitted. FIG. 40B is an explanatory diagram schematically illustrating a case where a command for designating a display area is transmitted after a series of image streams is transmitted. FIG. 5 is a timing diagram illustrating an example of operation timing of a signal driver that is subjected to partial display control by the LCD controller according to the present embodiment. FIG. 5 is a timing diagram illustrating an example of operation timing of a scan driver that is subjected to partial display control by the LCD controller according to the present embodiment. It is explanatory drawing which shows typically the initialization sequence of the display apparatus in this embodiment. It is a circuit diagram which shows an example of the pixel circuit of a 2 transistor system in an organic electroluminescent panel. FIG. 45A is a circuit diagram illustrating an example of a four-transistor pixel circuit in an organic EL panel. FIG. 45B is a timing diagram illustrating an example of display control timing of a four-transistor pixel circuit.

Explanation of symbols

10 liquid crystal device (display device), 20 LCD panel (display panel, electro-optical device),
22 _nm TFT, 24 _nm liquid crystal capacitance, 26 _nm pixel electrode, 28 _nm counter electrode,
30 signal driver (signal drive circuit), 32,52,140 ₀ shift register,
34,36,36 ₀ line latch, 38, 38 ₀ DAC (driving voltage generating circuit),
40,40 ₀ signal line driving circuit, 50 a scanning driver (scanning drive circuit),
54, 56 L / S, 58 scan line driving circuit,
60 LCD controller (display control circuit), 62 control circuit 64 RAM
66 host I / O, 68 LCD input / output (I / O) circuit,
70 command sequencer, 72 command setting register,
74 Control signal generating circuit, 80 a power supply circuit, 142 ₀ data bypass circuit,
210 _{1 to} 210 _N , 230 _{1 to} 230 _N AND circuit,
212 _{1 to} 212 _N , 232 _{1 to} 232 _N CMOS buffer circuit,
234 _{1 to} 234 _Q-1 data switching circuit, 300 image data generation circuit,
310 signal driver setting register, 312 block output selection data,
314 partial display data, 320 scan driver setting register,
322 partial scan display data, 330 control register,
332 display data size setting register, 336 mode setting register,
338 band partial data register

Claims (11)

A display control circuit for performing display control of an electro-optical device having pixels specified by first to Nth (N is a natural number) scanning lines and first to Mth (M is a natural number) signal lines intersecting each other Because
Area block display control data for storing area block display control data for designating a display area or a non-display area in units of area blocks divided for each given signal line and each given scan line Storage means;
Based on the area block display control data, a display area or a non-display area is defined as the area block for a scan driving circuit that sequentially scans at least a scan line corresponding to the display area among the first to Nth scan lines. Scan drive circuit setting means for setting in units;
Based on the area block display control data, a display area or a non-display area is determined in units of area blocks for a signal driving circuit that drives a signal line corresponding to the display area among the first to Mth signal lines. Signal driving circuit setting means for setting; and
Means for controlling the scan driving circuit to scan-drive the first to Nth scan lines in a given odd frame period of 3 or more with respect to a given reference frame,
Means for controlling the scan driving circuit;
The display scan line corresponding to the display area among the first to Nth scan lines is scan-driven at every frame period, and
Of the first to Nth scan lines, the non-display scan lines that are the scan lines excluding the display scan line are scan-driven in the odd frame period regardless of the voltages of the first to Mth signal lines. Controlling the scan driving circuit,
When activated by the host, after activating the signal driving circuit and the scan driving circuit, the host is notified of the activation of the signal driving circuit and the scanning driving circuit, and then receives the parameters from the host and receives the signal A display control circuit for controlling a driving circuit and the scanning driving circuit. In claim 1,
Band partial display control data holding means for holding band partial display control data for designating a display area or a non-display area in units of line blocks divided for a given plurality of scanning lines;
Mode switching means for switching between the first mode and the second mode;
Including
In the first mode,
Based on the area block display control data, a display area or a non-display area is set in the area block unit for the scanning drive circuit and the signal drive circuit,
In the second mode,
A display control circuit, wherein a display area or a non-display area is set in units of the line block for the scan driving circuit based on the band partial display control data. A display control circuit for performing display control of an electro-optical device having pixels specified by first to Nth (N is a natural number) scanning lines and first to Mth (M is a natural number) signal lines intersecting each other Because
Means for setting a display area or a non-display area for a scan driving circuit that scans and drives the first to Nth scan lines;
A display scan line, at least a part of which is included in the display area, is scan-driven at every frame period, and the first to Nth scan lines are among the first to Nth scan lines. Means for controlling the scan driving circuit so that a non-display scan line which is a scan line excluding the display scan line is scan-driven at an odd frame period of 3 or more with respect to a given reference frame;
Including
Means for controlling the scan driving circuit;
Of the first to Nth scanning lines, the display scanning lines are scanned at every frame period, and among the first to Nth scanning lines, the non-displaying scanning lines are the first to Mth scanning lines. The scan driving circuit is controlled to scan and drive the first to Nth scan lines in the odd frame period regardless of the voltage of the signal line.
When activated by the host, the scan drive circuit is activated, then the host is notified of the activation of the scan drive circuit, and then the scan drive circuit is controlled in response to parameters from the host. Display control circuit. In any one of Claims 1 thru | or 3,
A frame counter that counts the number of frames;
A frame interval register for designating the odd frame period;
Regardless of the display scan line or the non-display scan line, in the frame in which the set value of the frame interval register matches the count value of the frame counter, or the frame following the frame in which a given display control event has occurred. A display control circuit which controls to scan-drive the first to Nth scanning lines. In any one of Claims 1 thru | or 4,
The display control circuit, wherein the given reference frame is a frame next to a frame in which a given display control event has occurred. In claim 5,
A display control circuit that scans and drives all non-display scanning lines after the occurrence of the display control event in a frame in which the given display control event has occurred. In any one of Claims 4 thru | or 6.
The display control circuit according to claim 1, wherein the given display control event is an event that occurs based on at least one of generation, disappearance, movement, and size change of a display area or a non-display area. Pixels specified by the first to Nth scan lines and the first to Mth signal lines intersecting each other;
A scan driving circuit for scanning and driving the first to Nth scan lines;
A signal driving circuit for driving the first to Mth signal lines based on image data;
A display control circuit according to any one of claims 1 to 7;
An electro-optical device comprising: In claim 8,
The signal driving circuit includes:
Block output selection data holding means for holding block output selection data for designating whether or not to drive a signal in units of line blocks divided for each given signal line;
Partial display data holding means for holding partial display data for designating a display area or a non-display area in units of line blocks divided for each of the given signal lines;
With respect to the signal line of the line block designated to be driven by the block output selection data, the output to the signal line of the line block designated not to be driven by the block output selection data is set to a high impedance state. Based on the partial display data, signal line driving means for performing either signal driving according to image data or supply of a given non-display level voltage;
Have
The display control circuit includes:
Block output selection data setting means for setting the block output selection data in the block output selection data holding means of the signal driving circuit;
The first partial display data that designates a display area or a non-display area with the line block as a unit, and the Pth (P is a natural number) block designated in the display area is not signal-driven by the block output selection data. Partial display data conversion means for converting the first partial display data into second partial display data obtained by shifting the data of the Pth block as data of the (P + 1) th block when designated as a block; ,
Partial display data setting means for setting second partial display data in the partial display data holding means of the signal driving circuit;
An electro-optical device comprising: In claim 9,
The Pth block designated as the display area by the first partial display data designating the display area or the non-display area with the line block divided for each of the given signal lines as a unit is the block. When the output selection data designates a block that is not signal-driven, the first image data supplied to the signal driving circuit is the first image data corresponding to the P-th block among the first image data (P + 1). Image data generating means for generating second image data shifted as the image data of the block of
Image data supply means for supplying the second image data to the signal drive circuit;
An electro-optical device comprising: An electro-optical device having pixels specified by the first to Nth scanning lines and the first to Mth signal lines intersecting each other;
A scan driving circuit for scanning and driving the first to Nth scan lines;
A signal driving circuit for driving the first to Mth signal lines based on image data;
A display control circuit according to any one of claims 1 to 7;
A display device comprising:

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