JP3760318B2 - Recording media playback device - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording medium playback apparatus for playing back a recording medium recorded by modulating main data and subcode as subdata, such as a compact disk, and in particular, a recording medium having a buffer memory for prefetching data The present invention relates to a playback device.
[0002]
[Prior art]
When a track jump occurs during playback due to vibration, etc., the pickup is returned to the position immediately before the track jump occurs, playback starts again from that position, and a track jump occurs using a large-capacity buffer memory. There is an earthquake-resistant compact disc player that plays music without interruption by connecting playback main data obtained after resumption of playback to the main data immediately before.
[0003]
By the way, the compact disc has only a subcode which is subdata as an information index. Therefore, the subcode information is used in the track jump in the earthquake resistant compact disc player. However, the main data, which is music data, is once written to and read from the memory for deinterleaving, but because there is jitter between the write clock and the read clock, a time fluctuation occurs between the main data and the subcode, and the It is difficult to connect.
[0004]
Therefore, in “Reproduction data processing circuit of disc player” of Japanese Patent Laid-Open No. 5-282785, the position of the main data on the time axis is determined by adding the time axis correction similar to the main data to the subcode delimiter information detected from the subcode. The subcode block delimiter is recognized based on the subcode delimiter information so that the main data is connected in units of subcode blocks.
[0005]
[Problems to be solved by the invention]
However, in the seismic compact disc player configured as described above, the main data and the subcode as the subdata are not stored in the buffer memory in conjunction with each other. For example, to output optical digital output based on the IEC958 standard for sending data to the outside for recording, etc., and to send the main data and subcode in conjunction with the signal processing circuit added after the buffer memory. It was difficult. SUMMARY OF THE INVENTION An object of the present invention is to provide a recording medium playback apparatus that can store a subcode in a buffer memory in synchronization with main data and read it out in synchronization.
[0006]
[Means for Solving the Problems]
In the present invention, subcode as subdata is also stored in a memory for deinterleaving or error correction so that the subcode can be output synchronously when the main data is output. Is the most important feature.
[0007]
To achieve this, the main data converts the symbol position into a relative address and adds it to the counter indicating the frame position to generate the memory address. In the subcode, the write and read positions are relative addresses behind the main data. The memory address is generated by adding to a counter indicating the frame position.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
In the present invention, main data and a subcode as subdata are stored in a memory for interleaving or error correction in synchronization with each other, and in main data, a symbol position is converted into a relative address to indicate a frame position. The memory address is generated by adding to the counter. In the subcode, the write / read position is placed at a fixed relative address behind the main data and added to the counter indicating the frame position to generate the memory address. Thus, it is possible to provide a recording media reproducing apparatus that can easily output digital output to a signal processing circuit added to the subsequent stage of optical digital output or buffer memory including subcode included in main data.
[0009]
【Example】
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, in which 1 is a demodulation circuit, 2 is a write symbol counter, 3 is a write frame counter, 4 is an address generation circuit, 5 is a data selection circuit, and 6 is a memory. 7 is a block synchronization signal buffer, 8 is an error correction circuit, 9 is a buffer memory control circuit, 10 is a read symbol counter, 11 is a read frame counter, and 12 is a buffer memory.
[0010]
FIG. 2 is an explanatory diagram of a frame structure including a subcode of a compact disk, which is described as an example of a recording medium, and the demodulating circuit 1. The frame structure and the operation of the demodulating circuit 1 will be described using this. On the compact disc, a frame synchronization signal, main data, and a subcode as subdata are recorded as a modulation signal modulated by a modulation method suitable for recording. The modulation signal has a frame structure (a) described below. have. (A) is a subcode frame structure of a compact disc, and the frame is composed of a frame synchronization signal, one subcode, and 32 main data of symbol data 0 to 31. (B) is a frame synchronization signal generated in the demodulation circuit 1, (c) is a symbol synchronization signal generated in the demodulation circuit 1, and (d) is demodulated data in the frame and synchronized with the symbol synchronization signal. (E) is a subcode selection signal for distinguishing whether the demodulated data is subcode or main data.
[0011]
FIG. 3 is an explanatory diagram of the block structure of the compact disk. The subcode is divided into one block with 98 frames, and the subcode at the head of the block is a block synchronization signal modulated with a special code called S0 or S1. Subsequently, 96 subcodes have information such as a series of addresses.
[0012]
The modulation signal read from the compact disk is demodulated by the demodulation circuit 1, and the symbol synchronization signal output from the demodulation circuit 1 is counted in 32 digits by the write symbol counter 2 except for the symbol synchronization signal indicating the subcode, The synchronization signal is counted by the write frame counter 3, and the address generation circuit 4 distinguishes between the subcode and the main data by the subcode selection signal, and the write address to the memory 6 is output by the outputs of the write symbol counter 2 and the write frame counter 3. Is generated. The demodulated data output from the demodulating circuit 1 is selected at the time of writing by the data selecting circuit 5 for selecting whether to write, read or correct, and is written to the address generated by the address generating circuit 4 of the memory 6.
[0013]
In addition, since the written main data includes an error, the error correction circuit 8 corrects the error data in the memory 6 by designating and reading back the error address by specifying the error address.
[0014]
On the data reading side, the output of the read symbol counter 10 counted by the read symbol synchronization signal output from the buffer memory control circuit 9, the output of the read frame counter 11 counted by the read frame synchronization signal, and frame synchronization Then, a subcode reading timing signal for reading the subcode at the head of the frame is input to the address generation circuit 4 to generate a read address, which is selected at the time of reading by the data selection circuit 5 and the contents of the memory 6 are read. Then, the main data and subcode are stored in the buffer memory 12 for earthquake resistance in units of blocks, divided into a main data portion and a subcode portion. The stored data is read out by the buffer memory control circuit 9 as necessary and output to the outside.
[0015]
A block synchronization signal is written in the block synchronization signal buffer 7 at a position corresponding to the lower bit of the write frame counter 3, and is read out from the position corresponding to the lower bit of the read frame counter 11 by the buffer memory control circuit 9. The delay is the same as the main data delay by the memory 6. The lower bits referred to here are, for example, lower 3 bits if the jitter absorption margin (32 and 33 in FIG. 5 described later) of the memory 6 is 3 frames each on the advance side and the lag side.
[0016]
Here, the block synchronization signal is delayed by the block synchronization signal buffer 7, but may be stored in the memory 6 in the same manner as the subcode. In addition, one bit called P code among the subcodes is not used for optical digital out based on the IEC958 standard, so that a block synchronization signal may be stored instead of this bit.
[0017]
FIG. 4 is a block diagram of the address generation circuit 4 according to an embodiment of the present invention. Reference numerals 21 and 22 denote selectors, 23 denotes conversion means, and 24 denotes an adder.
[0018]
The selector 21 is a symbol address selection circuit, which receives the output of the write symbol counter 2, the output of the read symbol counter 11, and the correction symbol address from the correction circuit 8, outputs the selected signal, and converts the signal 23. Is composed of a conversion table using a ROM or a gate, and generates a relative address from the symbol position.
[0019]
The selector 22 is a frame address selection circuit. The output of the write frame counter 3, the output of the read frame counter 10, and the correction frame address from the correction circuit 8 are input, the selected signal is output, and the conversion means 23. The output of the selector 22 is added by an adder 24 to synthesize the address of the memory 6. Further, since the carry of the adder 24 is discarded, the memory 6 operates in a ring shape.
[0020]
The conversion means 23 outputs a subcode selection signal output from the demodulation circuit 1 for generating an address at the time of writing the subcode and a buffer memory control circuit 9 for generating an address at the time of reading the subcode. The subcode read timing signal is input, and the subcode write position and the relative address of the read position are generated when the subcode is written at the start of the demodulated frame and when read at the start of the read frame.
[0021]
FIG. 5 is a map of memory 6 in one embodiment of the present invention, where addresses are allocated starting at 0 in the upper left and moving down to A-1, then starting from the top of the right column and starting at A. Addresses are assigned up to B-1, and then addresses are assigned from B to C-1 toward the right. (A, B, C... Indicate the number of symbols in the vertical direction.) Write addresses are sequentially written from left to right at position 31. (In fact, it is stored in zigzag by C1 scrambling, but it is not related to the present invention, so it is omitted and simplified.) 32 prevents overflow when writing is too early due to jitter A buffer area 33 for absorbing jitter, and a buffer area 33 for preventing underflow when writing is too slow due to jitter. Since it is interleaved during reading, the direction 34 Read to. (In actuality, the position read by C2 scrambling is shifted or moved back and forth, but since it is not essentially related to the present invention, it is omitted and simplified.)
[0022]
Reference numeral 35 denotes a subcode storage area, which is arranged at a relative address at the rear of an address for storing data. The relative address is written at a position 36, which is a fixed position, and is read from a position 37, where the relative address is a fixed position.
As the write progresses, the value of the write frame counter 3 increases, so the write starts at the lower address. When the read progresses, the value of the read frame counter 11 increases, so the lower address is read, and the lower address Since is a value obtained by adding +1 to the upper address, the data is discarded from the place where the reading is completed, and the memory operates in a ring shape.
[0023]
When a track jump is caused by vibration, the playback position is kicked back and the main data and subcode can be connected by overwriting the storage position from the head data of the block that has not been stored in the buffer memory 12 and overwriting. Can be reproduced without interruption of sound and data.
[0024]
Although the present embodiment has been described using a compact disc, any disc, tape, or other media can be similarly implemented as long as it is a device that reproduces media on which main data and sub data are recorded.
[0025]
【The invention's effect】
As described above, since the recording medium playback apparatus of the present invention can store the subcode in the buffer memory in synchronization with the main data, it can output digital output to the optical digital output that outputs the main data including the subcode. , It is easy to send the main data and subcode synchronously to the signal processing circuit added to the subsequent stage of the buffer memory, and the data connection after the track jump is easily connected in block units using the subcode There is an advantage that you can. Also, any device that reproduces not only compact discs but also media on which main data and sub-data are recorded has the same advantage with any disc, tape, or other media.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is an explanatory diagram of a subcode frame structure of a compact disk and a demodulation circuit.
FIG. 3 is an explanatory diagram of a block structure of a compact disc.
FIG. 4 is a block diagram of an address generation circuit in an embodiment of the present invention.
FIG. 5 is a memory map in one embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Demodulator 2 Write symbol counter 3 Write frame counter 4 Address generation circuit 5 Data selection circuit 6 Memory 7 Block synchronization signal buffer 8 Error correction circuit 9 Buffer memory control circuit 10 Read symbol counter 11 Read frame counter 12 Buffer memory 21, 22 Selector 23 Conversion means 24 Adder

Claims (5)

A demodulating circuit for demodulating a signal read from a recording medium in which main data and sub data are recorded, and a memory for deinterleaving the main data demodulated by the demodulating circuit or performing error correction When an address generating circuit for generating addresses of said memory, comprising a block synchronization signal buffer for storing the detected block synchronization signal by the demodulating circuit, the sub-data demodulated by the demodulator circuit main data in said memory And a block synchronization signal stored in the block synchronization signal buffer in synchronization with main data . 2. A recording medium reproducing apparatus according to claim 1, further comprising a control circuit for controlling reading of data from said memory, wherein said control circuit reads sub-data and a block synchronization signal in synchronization with main data. . Conversion means for converting a symbol position into a relative address, a write frame counter indicating a write frame position, and an adder for adding the output of the conversion means and the output of the counter to generate the memory address. and the relative address of the storage location of the sub-data is given a fixed value in the conversion means, the position of the block synchronization signal buffer block synchronizing signal is stored Ru positions der corresponding to the lower bits of the write frame counter The recording media reproducing apparatus according to claim 1, wherein: Conversion means for converting a symbol position into a relative address, a read frame counter indicating a read frame position, and an adder for adding the output of the conversion means and the output of the counter to generate the memory address. and the relative address of the read position of the sub-data is given a fixed value in the conversion means, the position of the block synchronization signal buffer block synchronization signal is read out position der Rukoto corresponding to the lower bits of the read frame counter The recording media reproducing device according to claim 1, wherein: 2. The sub data storage and reading position in the conversion means is arranged at a relative address behind the main data position , and the block synchronization signal buffer is a buffer independent of the memory. The recording medium playback device described.

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