JP3712141B2 - Phase-locked loop device - Google Patents

Phase-locked loop device Download PDF

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Publication number
JP3712141B2
JP3712141B2 JP31728595A JP31728595A JP3712141B2 JP 3712141 B2 JP3712141 B2 JP 3712141B2 JP 31728595 A JP31728595 A JP 31728595A JP 31728595 A JP31728595 A JP 31728595A JP 3712141 B2 JP3712141 B2 JP 3712141B2
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frequency
output
input
signal
controlled oscillator
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JPH09135167A (en
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佐田夫 石井
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Yaskawa Electric Corp
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Yaskawa Electric Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range

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Description

【０００１】
【発明の属する技術分野】
本発明は、直交位相変調された信号の受信回路等に使用される位相同期ループ装置で、周波数引込み範囲を拡張した位相同期ループ装置に関するものである。
【０００２】
【従来の技術】
従来の位相同期ループ装置は図４に示すようになっている。図において１は入力端子、２は位相比較器（ＰＣ）、３はループフィルタ、４は電圧制御発振器（ＶＣ０）、９は出力端子である。入力端子１からの信号と電圧制御発振動器４からの出力信号が位相比較器２へ入力され、位相比較器２の出力はループフィルタ３を介して電圧制御発振器４へ入力される。出力端子９は電圧制御発振器４の出力端子である。
【０００３】
次に位相同期ループ装置の動作を説明する。入力端子１に入力信号が無い場合、電圧制御発振器（ＶＣＯ）４はある周波数で自走発振している。入力端子１に信号が入力されると、位相比較器（ＰＣ）２では、入力端子１の入力信号周波数と電圧制御発振器（ＶＣＯ）４の信号周波数の周波数及び位相差に対応する信号を発生する。この信号はループフィルタ３に入り高調波成分が除去され、低周波成分だけが電圧制御発振器（ＶＣＯ）４の発振周波数を変化させる。
電圧制御発振器（ＶＣＯ）４は、その周波数が周波数引込み範囲であれば、位相比較器（ＰＣ）２の出力直流成分が小さくなるような周波数が発振するように働くため、その発振周波数は次第に入力端子１に入力されている信号の周波数と位相に同期する（第１の従来技術）。
また別の従来の位相同期ループ装置は図５に示すようになっている（例えば特開平５−２９１９４８）。図において、入力端子１、位相比較器（ＰＣ）２、ループ・フィルタ３、電圧制御発振器（ＶＣＯ）４、乗算器５、固定発振器６、ローパスフィルタ（ＬＰＦ）７、レベル変換器８、出力端子９で構成される。
入力端子１は位相比較器（ＰＣ）２の片方の信号入力と接続され、その出力はループ・フィルタ３の入力と接続され、ループ・フィルタ３の出力は電圧制御発振器（ＶＣＯ）４の入力と接続され、その出力は乗算器５の片方の入力と接続される。又、固定発振器６の出力は乗算器５のもう一方と接続され、乗算器５の出力はローパスフィルタ７の入力と接続される。更にローパスフィルタ７の出力はレベル変換器８の入力と接続され、その出力は出力端子９及び位相比較器（ＰＣ）２の一方の入力と接続される。
図５に示す構成の位相同期ループ方式において、始めに入力端子１に信号が無い場合、電圧制御発振器（ＶＣＯ）４はある周波数で自走発振している。
又、固定発振器６も常に一定周波数の発振をしており、乗算器５ではこの二つの信号の乗算が行われ、その二つの信号周波数の和の周波数成分と、差の周波数成分が出力される。ローパスフィルタ７では、乗算器出力の周波数成分の内、低い周波数成分である差の周波数成分のみが通過し、レベル変換器８に入力される。 レベル変換器８では信号をクリップして一定振幅の信号に変換する。本実施例では電圧制御発振器（ＶＣＯ）４の自走振周波数は２０ＭＨｚ、固定発振器６の発振周波数は１５ＭＨｚとしてあり、その差の５ＭＨｚの周波数信号が位相比較器２の片方の入力に加わっている。
次に入力端子１に信号が入力された場合、位相比較器（ＰＣ）２では入力端子１の入力信号周波数と、レベル変換器８からの５ＭＨｚの信号の周波数及び位相差に対応する信号を発生する。この信号は次のループフィルタ３に入り高周波成分が除去され、低周波成分だけが電圧制御発振器（ＶＣＯ）４の入力に入り、電圧制御発振器（ＶＣＯ）４の発振周波数を変化させる。
電圧制御発振器（ＶＣＯ）４は、位相比較器（ＰＣ）２の出力の直流成分が小さくなるような周波数を発振するように働くため、電圧制御発振器（ＶＣＯ）４の発振周波数は、電圧制御発振器（ＶＣＯ）４の発振周波数−固定発振器６の発振周波数＝入力端子１の信号周波数に近づいていき、最後に差の信号は入力端子１の信号に同期する。この差の周波数信号が出力となる。
【０００４】
【発明が解決しようとする課題】
しかしながら、第１の従来技術では周波数引込み範囲は電圧制御発振器（ＶＣＯ）４の性能に関係し、また、自走発振周波数以下の周波数には追従できない問題があった。
第２の従来技術では電圧制御発振器（ＶＣＯ）４の自走発振周波数以下の周波数に追従できるが、周波数引込み範囲は第１の従来技術と同様に狭かった。
本発明は自走発振周波数以下の周波数に追従し広い周波数引き込み範囲を持つ位相同期ループ装置を提供することを目的とする。
【０００５】
【課題を解決するための手段】
上記問題を解決するために、本発明は、位相比較器とループフィルタと電圧制御発振器で構成された位相同期ループ装置において、入力信号とフィードバック信号が入力される前記位相比較器と、前記位相比較器の出力信号が入力される前記ループフィルタと、前記ループフィルタからの出力信号と一定電圧VREFとを入力する差動増幅器と、前記差動増幅器からの出力信号を入力する第２の電圧制御発振器と、前記ループフィルタの出力信号を入力する第１の電圧制御発振器と、前記第１の電圧制御発振器の出力周波数 f １ と前記第２の電圧制御発振器の出力周波数 f ２ との各々の出力信号の差信号(f １ − f ２ )を前記位相比較器へフィードバックする手段とを設け、前記フィードバックする手段は、前記差信号(f １ − f ２ )を分周器を通して前記位相比較器へフィードバックするようにしたものである。
【０００６】
【発明の実施の形態】
以下、本発明の実施の形態を図面に基づいて説明する。図１は本発明の位相同期ループ装置の実施例を示すブロック図である。従来の技術ででてきた名称と同じものには同一符号をつけ、重複説明を省略する。従来の技術（図４）と比較して異なる部分は、ループフィルタ３からの出力信号と一定電圧ＶREF を入力する差動増幅器１０、差動増幅器１０からの出信号を入力し、周波数ｆ2 を乗算器５へ出力する第２の電圧制御発振器１１を備える点にある。
入力端子１は位相比較器２の片方の信号入力と接続され、その出力はループフィルタ３の入力に接続される。ループフィルタ３の出力は第１の電圧制御発振器の入力と接続され、その出力は乗算器５の片方の入力と接続される。また、ループフィルタ３の出力は差動増幅器１０の（−）端子にも接続され、その出力は第２の電圧制御発振器１１の入力と接続され、その出力は乗算器５のもう一方の入力と接続される。差動増幅器１０の（＋）の出力端子は一定の電圧が印加されている。さらに、乗算器５の出力はローパスフィルタ７の入力に接続され、その出力はレベル変換器８の入力と接続され、その出力は出力端子９及び位相比較器（ＰＣ）２のもの一方の入力と接続される。
【０００７】
次に、図３は動作の説明図である。図１と図３を基にして動作の説明をする。第１の電圧制御発振器４の入力電圧をＶ1 、出力周波数をｆ1 、また第２の電圧制御発振器１１の出力周波数をｆ2 、周波数引き込み範囲をｆRNG とし、Ｖ1 が０ＶからＶREF まで変化したときに出力端子９に現われる周波数の変化する幅とする。差動増幅器の片方に印加されている一定の電圧をＶREF とする。図２に示すとおり、Ｖ1 が増加すると、ｆ1 は増加、ｆ2 は減少する。乗算器５の出力する電圧はｆ1 ＋ｆ2 、及び、ｆ1 −ｆ2 の周波数を含む高調波で、ローパスフィルタ７でｆ1 ＋ｆ2 の周波数成分を取り除けば、出力端子９にはｆ1 −ｆ2 の周波数成分が現われる。この時のＶ1 とｆ1 −ｆ2 の関係は図３の破線となる。図６は第２の従来の技術で示された方法での出力端子９に現れる周波数引込み範囲を示す。Ｖ1 ＝０Ｖの時の出力端子９に現われる周波数は第２の従来技術と等しいが、Ｖ1 ＝ＶREF の時の出力端子９に現われる周波数は第２の従来技術の場合より大きく、周波数引込み範囲が拡大する。
上記手段によって、前記ループフィルタの出力信号に対応して、第２の電圧制御発振器の出力周波数が変化するため、自走発振周波数以下の周波数に追従し、かつ、広い周波数引き込み範囲を持つようになる。
【０００８】
【発明の効果】
以上述べたように、本発明によれば、前記ループフィルタの出力信号に対応して、第２の電圧制御発振器の出力周波数が変化し、自走発振周波数以下の周波数に追従し、かつ、広い周波数引込み範囲を持つ位相同期ループ装置が実現できるという効果がある。
【図面の簡単な説明】
【図１】 本発明のブロック図
【図２】 本発明のブロック図
【図３】 本発明の特性図
【図４】 第１の従来技術のブロック図
【図５】 第２の従来技術のブロック図
【図６】 第２の従来技術の特性図
【符号の説明】
１ 入力端子
２ 位相比較器
３ ループフィルタ
４ 第１の電圧制御発振器（ＶＣＯ）
５ 乗算器
６ 固定発振器
７ ローパスフィルタ（ＬＰＦ）
８ レベル変換器
９ 出力端子
１０ 差動増幅器
１１ 第２の電圧制御発振器（ＶＣＯ）
１２ 一定電圧（ＶREF ）
１３ 分周器[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a phase-locked loop device that is used in a quadrature-phase-modulated signal receiving circuit or the like and has an expanded frequency pull-in range.
[0002]
[Prior art]
A conventional phase-locked loop device is as shown in FIG. In the figure, 1 is an input terminal, 2 is a phase comparator (PC), 3 is a loop filter, 4 is a voltage controlled oscillator (VC0), and 9 is an output terminal. A signal from the input terminal 1 and an output signal from the voltage controlled oscillator 4 are input to the phase comparator 2, and an output of the phase comparator 2 is input to the voltage controlled oscillator 4 through the loop filter 3. The output terminal 9 is an output terminal of the voltage controlled oscillator 4.
[0003]
Next, the operation of the phase locked loop device will be described. When there is no input signal at the input terminal 1, the voltage controlled oscillator (VCO) 4 is free-running at a certain frequency. When a signal is input to the input terminal 1, the phase comparator (PC) 2 generates a signal corresponding to the frequency and phase difference between the input signal frequency of the input terminal 1 and the signal frequency of the voltage controlled oscillator (VCO) 4. . This signal enters the loop filter 3 to remove harmonic components, and only the low frequency component changes the oscillation frequency of the voltage controlled oscillator (VCO) 4.
Since the voltage controlled oscillator (VCO) 4 operates so that the frequency in which the output DC component of the phase comparator (PC) 2 becomes small if the frequency is within the frequency pull-in range, the oscillation frequency is gradually input. It synchronizes with the frequency and phase of the signal input to the terminal 1 (first prior art).
Another conventional phase-locked loop device is as shown in FIG. 5 (for example, JP-A-5-291948). In the figure, an input terminal 1, a phase comparator (PC) 2, a loop filter 3, a voltage controlled oscillator (VCO) 4, a multiplier 5, a fixed oscillator 6, a low pass filter (LPF) 7, a level converter 8, an output terminal 9 is composed.
The input terminal 1 is connected to one signal input of the phase comparator (PC) 2, the output is connected to the input of the loop filter 3, and the output of the loop filter 3 is connected to the input of the voltage controlled oscillator (VCO) 4. The output is connected to one input of the multiplier 5. The output of the fixed oscillator 6 is connected to the other side of the multiplier 5, and the output of the multiplier 5 is connected to the input of the low-pass filter 7. Further, the output of the low-pass filter 7 is connected to the input of the level converter 8, and the output is connected to the output terminal 9 and one input of the phase comparator (PC) 2.
In the phase-locked loop system having the configuration shown in FIG. 5, when there is no signal at the input terminal 1 first, the voltage controlled oscillator (VCO) 4 is free-running at a certain frequency.
The fixed oscillator 6 always oscillates at a constant frequency, and the multiplier 5 multiplies these two signals, and outputs the frequency component of the sum of the two signal frequencies and the difference frequency component. . In the low-pass filter 7, only the difference frequency component which is a low frequency component among the frequency components of the multiplier output passes and is input to the level converter 8. The level converter 8 clips the signal and converts it to a signal having a constant amplitude. In this embodiment, the free-running oscillation frequency of the voltage controlled oscillator (VCO) 4 is 20 MHz, the oscillation frequency of the fixed oscillator 6 is 15 MHz, and a difference 5 MHz frequency signal is added to one input of the phase comparator 2. .
Next, when a signal is input to the input terminal 1, the phase comparator (PC) 2 generates a signal corresponding to the input signal frequency of the input terminal 1 and the frequency and phase difference of the 5 MHz signal from the level converter 8. To do. This signal enters the next loop filter 3 to remove the high frequency component, and only the low frequency component enters the input of the voltage controlled oscillator (VCO) 4 to change the oscillation frequency of the voltage controlled oscillator (VCO) 4.
Since the voltage controlled oscillator (VCO) 4 operates to oscillate a frequency at which the DC component of the output of the phase comparator (PC) 2 becomes small, the oscillation frequency of the voltage controlled oscillator (VCO) 4 is the voltage controlled oscillator. The oscillation frequency of (VCO) 4−the oscillation frequency of the fixed oscillator 6 = the signal frequency of the input terminal 1 is approached. Finally, the difference signal is synchronized with the signal of the input terminal 1. The frequency signal of this difference becomes the output.
[0004]
[Problems to be solved by the invention]
However, in the first prior art, the frequency pull-in range is related to the performance of the voltage controlled oscillator (VCO) 4, and there is a problem that it cannot follow the frequency below the free-running oscillation frequency.
In the second prior art, the frequency controlled oscillator (VCO) 4 can follow the frequency below the free-running oscillation frequency, but the frequency pull-in range is narrow as in the first prior art.
It is an object of the present invention to provide a phase-locked loop device that follows a frequency below the free-running oscillation frequency and has a wide frequency pull-in range.
[0005]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides a phase locked loop device including a phase comparator, a loop filter, and a voltage controlled oscillator , the phase comparator to which an input signal and a feedback signal are input, and the phase comparison. The loop filter to which the output signal of the amplifier is input, the differential amplifier for inputting the output signal from the loop filter and the constant voltage V REF, and the second voltage control for inputting the output signal from the differential amplifier oscillator and a first voltage controlled oscillator for receiving the output signal of the loop filter, each output of the output frequency f 2 of the first output frequency f 1 and the second voltage controlled oscillator of the voltage controlled oscillator signal difference signal - and means for feeding back (f 1 f 2) to the phase comparator is provided, means for the feedback, the difference signal - through (f 1 f 2) frequency divider Serial is obtained so as to feedback to the phase comparator.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a phase-locked loop device according to the present invention. The same reference numerals are given to the same names as those used in the prior art, and duplicate descriptions are omitted. The difference from the conventional technique (FIG. 4) is that the output signal from the loop filter 3 and the differential amplifier 10 that receives the constant voltage V REF are input, the output signal from the differential amplifier 10 is input, and the frequency f 2 Is provided with a second voltage-controlled oscillator 11 for outputting to the multiplier 5.
The input terminal 1 is connected to one signal input of the phase comparator 2, and its output is connected to the input of the loop filter 3. The output of the loop filter 3 is connected to the input of the first voltage controlled oscillator, and the output is connected to one input of the multiplier 5. The output of the loop filter 3 is also connected to the (−) terminal of the differential amplifier 10, its output is connected to the input of the second voltage controlled oscillator 11, and its output is connected to the other input of the multiplier 5. Connected. A constant voltage is applied to the (+) output terminal of the differential amplifier 10. Further, the output of the multiplier 5 is connected to the input of the low-pass filter 7, the output is connected to the input of the level converter 8, and the output is one of the input of the output terminal 9 and the phase comparator (PC) 2. Connected.
[0007]
Next, FIG. 3 is an explanatory diagram of the operation. The operation will be described with reference to FIGS. V 1 the input voltage of the first voltage controlled oscillator 4, the output frequency f 1, also f 2 to the output frequency of the second voltage controlled oscillator 11, the frequency acquisition range and f RNG, until V REF V1 from 0V When the frequency changes, the frequency that appears at the output terminal 9 changes. A constant voltage applied to one side of the differential amplifier is defined as V REF . As shown in FIG. 2, when V 1 increases, f 1 increases and f 2 decreases. The voltage output from the multiplier 5 is a harmonic including the frequencies of f 1 + f 2 and f 1 −f 2. If the low frequency filter 7 removes the frequency component of f 1 + f 2 , the output terminal 9 has f 1. A frequency component of −f 2 appears. The relationship between V 1 and f 1 −f 2 at this time is a broken line in FIG. FIG. 6 shows the frequency pull-in range appearing at the output terminal 9 in the method shown in the second prior art. The frequency appearing at the output terminal 9 when V 1 = 0V is equal to that of the second prior art, but the frequency appearing at the output terminal 9 when V 1 = V REF is greater than that of the second prior art, and the frequency pull-in. The range expands.
By the above means, since the output frequency of the second voltage controlled oscillator changes corresponding to the output signal of the loop filter, it follows the frequency below the free-running oscillation frequency and has a wide frequency pull-in range. Become.
[0008]
【The invention's effect】
As described above, according to the present invention, the output frequency of the second voltage controlled oscillator changes corresponding to the output signal of the loop filter, follows the frequency below the free-running oscillation frequency, and wide There is an effect that a phase locked loop device having a frequency pull-in range can be realized.
[Brief description of the drawings]
1 is a block diagram of the present invention. FIG. 2 is a block diagram of the present invention. FIG. 3 is a characteristic diagram of the present invention. FIG. 4 is a block diagram of a first prior art. [Fig. 6] Characteristic diagram of the second prior art [Explanation of symbols]
1 Input Terminal 2 Phase Comparator 3 Loop Filter 4 First Voltage Controlled Oscillator (VCO)
5 Multiplier 6 Fixed Oscillator 7 Low Pass Filter (LPF)
8 level converter 9 output terminal 10 differential amplifier 11 second voltage controlled oscillator (VCO)
12 Constant voltage (V REF )
13 divider

Claims (1)

位相比較器とループフィルタと電圧制御発振器で構成された位相同期ループ装置において、
入力信号とフィードバック信号が入力される前記位相比較器と、前記位相比較器の出力信号が入力される前記ループフィルタと、前記ループフィルタからの出力信号と一定電圧VREFとを入力する差動増幅器と、前記差動増幅器からの出力信号を入力する第２の電圧制御発振器と、前記ループフィルタの出力信号を入力する第１の電圧制御発振器と、前記第１の電圧制御発振器の出力周波数 f １ と前記第２の電圧制御発振器の出力周波数 f ２ との各々の出力信号の差信号(f １ − f ２ )を前記位相比較器へフィードバックする手段とを設け、前記フィードバックする手段は、前記差信号(f １ − f ２ )を分周器を通して前記位相比較器へフィードバックすることを特徴とする位相同期ループ装置。In a phase-locked loop device composed of a phase comparator, a loop filter, and a voltage controlled oscillator,
The phase comparator to which an input signal and a feedback signal are input, the loop filter to which an output signal of the phase comparator is input, and a differential amplifier that inputs an output signal from the loop filter and a constant voltage V REF A second voltage controlled oscillator that inputs an output signal from the differential amplifier, a first voltage controlled oscillator that inputs an output signal of the loop filter, and an output frequency f 1 of the first voltage controlled oscillator the difference signal of the second voltage controlled oscillator output signal of each of the output frequency f 2 with - a (f 1 f 2) is provided and means for feeding back to said phase comparator, said means for feedback, the difference signals (f 1 - f 2) phase-locked loop apparatus characterized by feeding back to the phase comparator through a frequency divider.
JP31728595A 1995-11-10 1995-11-10 Phase-locked loop device Expired - Fee Related JP3712141B2 (en)

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JP31728595A JP3712141B2 (en) 1995-11-10 1995-11-10 Phase-locked loop device

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JPH09135167A JPH09135167A (en) 1997-05-20
JP3712141B2 true JP3712141B2 (en) 2005-11-02

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US7054403B2 (en) * 2000-03-21 2006-05-30 Nippon Telegraph And Telephone Corporation Phase-Locked Loop
JP5867551B2 (en) * 2014-06-18 2016-02-24 沖電気工業株式会社 Optical phase-locked loop circuit
CN107395199B (en) * 2017-09-18 2023-11-24 江汉大学 Phase-locked loop circuit

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