JP3699783B2 - Chip-type semiconductor and manufacturing method thereof - Google Patents

Chip-type semiconductor and manufacturing method thereof Download PDF

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JP3699783B2
JP3699783B2 JP19344196A JP19344196A JP3699783B2 JP 3699783 B2 JP3699783 B2 JP 3699783B2 JP 19344196 A JP19344196 A JP 19344196A JP 19344196 A JP19344196 A JP 19344196A JP 3699783 B2 JP3699783 B2 JP 3699783B2
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sealing resin
mold frame
chip
type semiconductor
insulating substrate
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剛 三浦
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株式会社シチズン電子
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
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    • H01L2924/351—Thermal stress

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  • Engineering & Computer Science (AREA)
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Description

【０００１】
【発明の属する技術分野】
本発明は、発光ダイオード素子、フォトダイオード素子、フォトトランジスタ素子などの半導体素子を絶縁基板の上にダイボンドするタイプのチップ型半導体およびその製造方法に関するものである。
【０００２】
【従来の技術】
従来のチップ型半導体は、図７に示したように、ガラスエポキシ樹脂等からなる絶縁基板１と、絶縁基板１の上面にエッチング等によりパターン形成された一対の電極部２ａ，２ｂと、一方の電極部２ａ上に塗布した導電性の銀ペースト９を介してダイボンドされた半導体素子３と、この半導体素子３と他方の電極部２ｂとをワイヤボンディングした金属細線４と、受発光の指向性を調整すると共に外光を遮断するためのプラスチック等からなるモールド枠５と、半導体素子３及び金属細線４を封止するエポキシ樹脂等からなる封止用樹脂６と、絶縁基板１の下面に形成されたプリント基板用電極８とからなる。
【０００３】
この種のチップ型半導体１０を製造する手段としては、先ず絶縁基板１の電極部２ａ上に銀ペースト９を塗布し、その上に半導体素子３を載置したのちキュア炉で銀ペースト９を硬化して半導体素子３をダイボンドする。次いで半導体素子３と他の電極部２ｂとをワイヤボンディングしたのち、前記半導体素子３と金属細線４の周囲に接着剤１１を塗布し、その上にモールド枠５を載置したのち再びキュア炉に入れて接着剤１１を硬化する。そして、最後にモールド枠５の中に封止用樹脂６を充填し、再びキュア炉に入れて封止用樹脂６を固めて完成させる。
【０００４】
【発明が解決しようとする課題】
ところで、上記構成からなるチップ型半導体を１０をプリント基板１２に実装する際、プリント基板１２上に塗布した半田１３の上にチップ型半導体１０を載置した状態でリフローを通すため、チップ型半導体１０が高温にさらされることになる。この時、モールド枠５及び封止用樹脂６も一緒に熱膨張するが、封止用樹脂６の熱膨張係数がモールド枠５のそれよりも大きく、また封止用樹脂６がモールド枠５に密着していることから、封止用樹脂６の横方向への膨張がモールド枠５によって制限されることになる。その結果、図７に示したように、封止用樹脂６には横方向への伸びを妨げる熱応力Ｆが働くことになる。一方、封止用樹脂６は上下方向にも膨張しようとするが、下方向への膨張が絶縁基板１によって制限されることから、絶縁基板１による制限を受けない上方向に大きく膨張することになる。このように、横方向と縦方向の膨張の違いによって封止用樹脂６の内部にひずみが発生すると、何の制限も受けない上方向への膨張力が原因で半導体素子３が絶縁基板１の電極部２ａから剥離するという問題があった。
【０００５】
そこで、本発明は、チップ型半導体をプリント基板上に実装する際のリフロー等による高温加熱時において、封止用樹脂の内部ひずみの発生を周辺に拡散することで半導体素子が絶縁基板の電極部から剥離するのを防止するものである。
【０００６】
【課題を解決するための手段】
上記課題を解決するために、請求項１に係る発明は、絶縁基板と、その上面に形成された電極部にダイボンドされた発光ダイオード素子及びフォトトランジスタ素子と、これらの素子および素子にワイヤボンディングされた金属細線を素子ごとに封止する封止用樹脂と、これら封止用樹脂の周囲を取り囲むモールド枠とで構成されてなるチップ型半導体であって、前記モールド枠には前記封止用樹脂の間を仕切る中央壁が形成されており、封止用樹脂の周囲にはモールド枠およびモールド枠の中央壁との間にそれぞれ空隙部が設けられると共に、前記モールド枠及び中央壁の壁面は前記空隙部を介して封止用樹脂と対向する面が垂直であることを特徴とする。
【０００７】
また、請求項２に係る発明は、電極部が形成された絶縁基板上に仮枠を設置すると共に半導体素子をダイボンドし、仮枠内に封止用樹脂を充填固化したのち仮枠を取り外し、この封止用樹脂の周囲にモールド枠を載置し、上記封止用樹脂との間に空隙部を設けた状態でモールド枠を絶縁基板に固着したことを特徴とする。
【０００８】
【発明の実施の形態】
以下、添付図面に基づいて本発明に係るチップ型半導体の実施例を詳細に説明する。図１は本発明をフォトリフレクタ２０に適用した場合の斜視図、図２は図１のＡ−Ａ線断面図である。この実施例に係るフォトリフレクタ２０は、チップ型発光ダイオード２１と、チップ型フォトトランジスタ２２とを一体に並設したものである。フォトリフレクタ２０は、ガラスエポキシ樹脂等からなる絶縁基板２３と、絶縁基板２３の下面に形成された一対のプリント基板用電極２４，２５と、絶縁基板２３の上面にエッチング等により形成された電極部２８ａ，２８ｂおよび２９ａ，２９ｂと、一方の電極部２８ａ，２９ａの上に塗布された導電性の銀ペーストを介してダイボンドされる発光ダイオード素子２６及びフォトトランジスタ素子２７と、これら発光ダイオード素子２６及びフォトトランジスタ素子２７と他方の電極部２８ｂ，２９ｂとをそれぞれワイヤボンディングした金属細線３０と、発光ダイオード素子２６及びフォトトランジスタ素子２７を封止する透光性樹脂３１，３２と、透光性樹脂３１，３２の周りを取り囲むようにして発光ダイオード素子２６及びフォトトランジスタ素子２７を保護し且つ受発光の指向性を調整すると共に外光を遮断するためのプラスチック製モールド枠３３とからなる。モールド枠３３には透光性樹脂３１，３２間を仕切る中央壁３４が形成されており、発光ダイオード素子２６とフォトトランジスタ素子２７とが相互に影響し合わないように配慮してある。また、この実施例では透光性樹脂３１，３２の周囲とモールド枠３３との間に一定幅の空隙部３５が設けられている。この空隙部３５は、各透光性樹脂３１，３２とモールド枠３３の中央壁３４との間にも設けられている。なお、絶縁基板２３の側面にはスルーホール電極３６が形成されている。
【０００９】
上述のフォトリフレクタ２０は、発光ダイオードとフォトトランジスタの機能を兼ね備えた光検出素子として用いられる。チップ型発光ダイオード２１のプリント基板用電極２４からスルーホール電極３６、電極部２８ａ、発光ダイオード素子２６及び金属細線３０に電流が流れると、発光ダイオード素子２６が電気エネルギを光エネルギに変換して発光する。そして、発光した光は反射してチップ型フォトトランジスタ２２のフォトトランジスタ素子２７に受光され、電気信号に増幅変換される。
【００１０】
このような構成からなるフォトリフレクタ２０にあっては、図２に示したように、プリント基板１２上に実装する際にリフロー内で高温にさらされるが、上述したように透光性樹脂３１，３２とモールド枠３３との間に一定の空隙部３５が設けてあるので、透光性樹脂３１，３２の横方向への膨張がモールド枠３３によって制限されるといったことがなく、図２に二点鎖線で示したように、横方向に自由に膨張できる。それ結果、従来のように横方向での熱応力を受けるといったことがない。また、図２に示したように、透光性樹脂３１，３２は上方向にも自由に膨張できることから、熱応力による透光性樹脂３１，３２の内部ひずみの発生を拡散することができ、結果的に発光ダイオード素子２６及びフォトトランジスタ素子２７が電極部２８ａ，２９ａから剥離するのを防止できることになる。
なお、上記空隙部３５は、透光性樹脂３１，３２やモールド枠３３の熱膨張係数、フォトリフレクタ２０の大きさ、リフロー温度等を考慮に入れて必要最小限の間隔で設定される。
【００１１】
次に、上記フォトリフレクタ２０の製造方法を図３及び図４の概略図及び図５の工程図に基づいて説明する。なお、各部位の説明には上記実施例とは異なる符号を用いる。先ず、電極部４２ａ，４２ｂが形成された絶縁基板４１の上面に仮枠４３を配置する（ステップ１）。次いで、仮枠４３内において、電極部４２ａ上に半導体素子４４をダイボンドし（ステップ２）、更に金属細線４５にてワイヤボンディングした後（ステップ３）、前記仮枠１１内に封止用樹脂４６を充填し、キュア炉に入れて封止用樹脂４６を固化する（ステップ４）。
【００１２】
次いで、図４に示したように、仮枠４３を取り外して封止用樹脂４６の周囲を露出させる（ステップ５）。そして、仮枠４３を取り外した絶縁基板４１上に接着剤４７を塗布し、その上にモールド枠４８を載置したのち、キュア炉に入れてモールド枠４８を固定する（ステップ６）。モールド枠４８は仮枠４３より内周部が少し大きめに作られており、絶縁基板４１上に載置した時に封止用樹脂４６の周面との間に空隙部４９が形成される。なお、上記実施例では絶縁基板４１上に仮枠４３を設けてから半導体素子４４をダイボンドした場合について説明したが、先に半導体素子４４をダイボンドし、金属細線４５をワイヤボンディングしてから仮枠４３を設けてもよい。上述した製造方法は、上記実施例に係るフォトリフレクタ２０のみならず、チップ型発光ダイオード及びチップ型フォトトランジスタを単体で製造する場合にも適用することができる。
【００１３】
図６は本発明の他の実施例を示したものである。この実施例に係るチップ型半導体は、仮枠を用いた上述の製造方法とは異なって、絶縁基板４１上にダイボンドした半導体素子４４および金属細線４５の上に封止用樹脂４６をポッティングし、これをキュア炉で硬化したのち、その周囲にモールド枠４８を配置したものである。従って、この実施例においても、半導体素子４４の上にポッティングした封止用樹脂４６とモールド枠４８との間に空隙部４９が形成されるので、リフロー時にチップ型半導体が高温にさらされても封止用樹脂４６の膨張がモールド枠４８によって制限されるといったことがなく、封止用樹脂４６の内部ひずみの発生が空隙部４９に拡散されることになる。
【００１４】
【発明の効果】
以上説明したように、本発明に係るチップ型半導体によれば、絶縁基板上にダイボンドされた半導体素子の封止用樹脂と、その周面を取り囲むモールド枠との間に空隙部を設けたので、チップ型半導体をプリント基板上に実装する際の高温加熱下での封止用樹脂の膨張がモールド枠によって制限を受けることがなく、封止用樹脂の内部ひずみの発生が空隙部方向へ拡散することで、半導体素子が絶縁基板の電極部から剥離するのを防止することができた。
【００１５】
また、本発明に係るチップ型半導体の製造方法によれば、仮枠を配置した状態で封止用樹脂を充填固化し、仮枠を取り外したのちに封止用樹脂の周りにモールド枠を固着するようにしたので、封止用樹脂とモールド枠との間に所望の空隙部を容易且つ精度良く設けることが出来ると同時に、空隙部の調整を容易に行えるといった効果がある。
【図面の簡単な説明】
【図１】本発明に係るチップ型半導体の一実施例を示す斜視図である。
【図２】図１のＡ−Ａ線断面図である。
【図３】本発明のチップ型半導体の製造方法において、仮枠を配置した時の製造過程を示す断面図である。
【図４】上記製造方法において、仮枠を外した時の製造過程を示す断面図である。
【図５】本発明に係るチップ型半導体の製造工程図である。
【図６】本発明に係るチップ型半導体の他の実施例を示す断面図である。
【図７】従来のチップ型半導体の一例を示す断面図である。
【符号の説明】
２０ フォトリフレクタ（チップ型半導体）
２１ チップ型発光ダイオード（チップ型半導体）
２２ チップ型フォトトランジスタ（チップ型半導体）
２３ 絶縁基板
２６ 発光ダイオード素子（半導体素子）
２７ フォトトランジスタ素子（半導体素子）
２８ａ，２８ｂ 電極部
２９ａ，２９ｂ 電極部
３１，３２ 透光性樹脂（封止用樹脂）
３３ モールド枠
３５ 空隙部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a chip type semiconductor in which a semiconductor element such as a light emitting diode element, a photodiode element, and a phototransistor element is die-bonded on an insulating substrate, and a method for manufacturing the same.
[0002]
[Prior art]
As shown in FIG. 7, the conventional chip type semiconductor includes an insulating substrate 1 made of glass epoxy resin, a pair of electrode portions 2a and 2b patterned on the upper surface of the insulating substrate 1 by etching, and the like. A semiconductor element 3 die-bonded via a conductive silver paste 9 applied on the electrode part 2a, a metal wire 4 obtained by wire-bonding the semiconductor element 3 and the other electrode part 2b, and directivity of light reception and emission Formed on the lower surface of the insulating substrate 1 is a mold frame 5 made of plastic or the like for adjusting and blocking external light, a sealing resin 6 made of epoxy resin or the like for sealing the semiconductor elements 3 and the fine metal wires 4, and the like. And the printed circuit board electrode 8.
[0003]
As a means for manufacturing this type of chip-type semiconductor 10, first, a silver paste 9 is applied on the electrode portion 2a of the insulating substrate 1, and after placing the semiconductor element 3 thereon, the silver paste 9 is cured in a curing furnace. Then, the semiconductor element 3 is die-bonded. Next, after wire bonding the semiconductor element 3 and the other electrode portion 2b, the adhesive 11 is applied around the semiconductor element 3 and the fine metal wire 4, and the mold frame 5 is placed thereon, and then again in the curing furnace. Put the adhesive 11 to cure. Finally, the sealing resin 6 is filled in the mold frame 5 and is again put in a curing furnace to solidify the sealing resin 6 and complete.
[0004]
[Problems to be solved by the invention]
By the way, when the chip type semiconductor 10 having the above-described configuration is mounted on the printed board 12, the chip type semiconductor is used because the chip type semiconductor 10 is placed on the solder 13 applied on the printed board 12 and reflow is performed. 10 will be exposed to high temperatures. At this time, the mold frame 5 and the sealing resin 6 are also thermally expanded together, but the thermal expansion coefficient of the sealing resin 6 is larger than that of the mold frame 5, and the sealing resin 6 is in the mold frame 5. Because of the close contact, the expansion of the sealing resin 6 in the lateral direction is limited by the mold frame 5. As a result, as shown in FIG. 7, thermal stress F that hinders lateral expansion acts on the sealing resin 6. On the other hand, the sealing resin 6 tends to expand in the vertical direction, but since the downward expansion is limited by the insulating substrate 1, it is greatly expanded upward without being restricted by the insulating substrate 1. Become. As described above, when distortion occurs in the sealing resin 6 due to the difference between the expansion in the horizontal direction and the vertical direction, the semiconductor element 3 is formed on the insulating substrate 1 due to the upward expansion force without any limitation. There was a problem of peeling from the electrode part 2a.
[0005]
Accordingly, the present invention provides an electrode portion of an insulating substrate by diffusing the generation of internal strain of a sealing resin to the periphery during high-temperature heating such as reflow when mounting a chip-type semiconductor on a printed circuit board. It prevents peeling from.
[0006]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, an invention according to claim 1 includes an insulating substrate, a light-emitting diode element and a phototransistor element die-bonded to an electrode portion formed on the upper surface, and wire bonding to these elements and elements. and a sealing resin for sealing the thin metal wires for each device, a chip-type semiconductor formed is composed of a mold frame surrounding these sealing resin and the mold frame for resin the sealing A central wall is formed between the mold frame and the center wall of the mold frame, and the wall surface of the mold frame and the center wall is The surface facing the sealing resin through the gap is vertical .
[0007]
In the invention according to claim 2, the temporary frame is placed on the insulating substrate on which the electrode portion is formed and the semiconductor element is die-bonded, and after the sealing resin is filled and solidified in the temporary frame, the temporary frame is removed, A mold frame is placed around the sealing resin, and the mold frame is fixed to an insulating substrate with a gap provided between the sealing resin and the sealing resin.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of a chip-type semiconductor according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a perspective view when the present invention is applied to a photo reflector 20, and FIG. 2 is a cross-sectional view taken along line AA of FIG. The photoreflector 20 according to this embodiment has a chip-type light emitting diode 21 and a chip-type phototransistor 22 that are integrally arranged in parallel. The photo reflector 20 includes an insulating substrate 23 made of glass epoxy resin, a pair of printed circuit board electrodes 24 and 25 formed on the lower surface of the insulating substrate 23, and an electrode portion formed on the upper surface of the insulating substrate 23 by etching or the like. 28a, 28b and 29a, 29b, a light-emitting diode element 26 and a phototransistor element 27 which are die-bonded via a conductive silver paste applied on one electrode portion 28a, 29a, and the light-emitting diode element 26 and A thin metal wire 30 in which the phototransistor element 27 and the other electrode portions 28b and 29b are respectively wire-bonded, translucent resins 31 and 32 for sealing the light emitting diode element 26 and the phototransistor element 27, and a translucent resin 31 , 32 so as to surround the light emitting diode element 26 and the photo diode. Made of a plastic mold frame 33 for blocking the external light with adjusting the directivity of and protects the transistor element 27 emitting and receiving light. The mold frame 33 is formed with a central wall 34 for partitioning the translucent resins 31 and 32 so that the light emitting diode element 26 and the phototransistor element 27 do not affect each other. In this embodiment, a gap 35 having a constant width is provided between the periphery of the translucent resins 31 and 32 and the mold frame 33. The gap 35 is also provided between the translucent resins 31 and 32 and the central wall 34 of the mold frame 33. A through-hole electrode 36 is formed on the side surface of the insulating substrate 23.
[0009]
The above-described photo reflector 20 is used as a photodetecting element having the functions of a light emitting diode and a phototransistor. When current flows from the printed circuit board electrode 24 of the chip-type light emitting diode 21 to the through-hole electrode 36, the electrode portion 28a, the light emitting diode element 26, and the thin metal wire 30, the light emitting diode element 26 converts electric energy into light energy to emit light. To do. The emitted light is reflected and received by the phototransistor element 27 of the chip-type phototransistor 22 and amplified and converted into an electric signal.
[0010]
In the photo reflector 20 having such a configuration, as shown in FIG. 2, the photo reflector 20 is exposed to a high temperature in the reflow when being mounted on the printed circuit board 12. 2 is provided between the mold frame 33 and the mold frame 33, the lateral expansion of the translucent resins 31 and 32 is not limited by the mold frame 33. As indicated by the dotted line, it can expand freely in the lateral direction. As a result, the thermal stress in the lateral direction is not received as in the prior art. Moreover, as shown in FIG. 2, since the translucent resins 31 and 32 can freely expand upward, the generation of internal strain of the translucent resins 31 and 32 due to thermal stress can be diffused, As a result, the light emitting diode element 26 and the phototransistor element 27 can be prevented from being peeled off from the electrode portions 28a and 29a.
The gap portion 35 is set at a minimum necessary interval in consideration of the thermal expansion coefficients of the translucent resins 31 and 32 and the mold frame 33, the size of the photo reflector 20, the reflow temperature, and the like.
[0011]
Next, a method for manufacturing the photo reflector 20 will be described with reference to the schematic diagrams of FIGS. 3 and 4 and the process diagrams of FIG. In addition, the description different from the said Example is used for description of each site | part. First, the temporary frame 43 is disposed on the upper surface of the insulating substrate 41 on which the electrode portions 42a and 42b are formed (Step 1). Next, in the temporary frame 43, the semiconductor element 44 is die-bonded on the electrode portion 42 a (step 2) and further wire-bonded with the fine metal wire 45 (step 3), and then the sealing resin 46 is placed in the temporary frame 11. And is placed in a curing furnace to solidify the sealing resin 46 (step 4).
[0012]
Next, as shown in FIG. 4, the temporary frame 43 is removed to expose the periphery of the sealing resin 46 (step 5). Then, an adhesive 47 is applied on the insulating substrate 41 from which the temporary frame 43 has been removed, and the mold frame 48 is placed thereon, and then placed in a curing furnace to fix the mold frame 48 (step 6). The mold frame 48 has a slightly larger inner periphery than the temporary frame 43, and a gap 49 is formed between the mold frame 48 and the peripheral surface of the sealing resin 46 when placed on the insulating substrate 41. In the above embodiment, the case where the semiconductor element 44 is die-bonded after the provisional frame 43 is provided on the insulating substrate 41 has been described. However, the semiconductor element 44 is first die-bonded and the fine metal wire 45 is wire-bonded, and then 43 may be provided. The manufacturing method described above can be applied not only to the photo reflector 20 according to the above embodiment, but also to the case where a chip-type light emitting diode and a chip-type phototransistor are manufactured alone.
[0013]
FIG. 6 shows another embodiment of the present invention. Unlike the above-described manufacturing method using a temporary frame, the chip-type semiconductor according to this embodiment pots a sealing resin 46 on the semiconductor element 44 and the metal thin wire 45 die-bonded on the insulating substrate 41, After this is cured in a curing furnace, a mold frame 48 is arranged around it. Accordingly, also in this embodiment, since the gap 49 is formed between the sealing resin 46 potted on the semiconductor element 44 and the mold frame 48, even if the chip-type semiconductor is exposed to a high temperature during reflow. The expansion of the sealing resin 46 is not limited by the mold frame 48, and the occurrence of internal strain of the sealing resin 46 is diffused into the gap 49.
[0014]
【The invention's effect】
As described above, according to the chip-type semiconductor according to the present invention, the gap is provided between the resin for sealing the semiconductor element die-bonded on the insulating substrate and the mold frame surrounding the peripheral surface. The expansion of the sealing resin under high-temperature heating when mounting a chip-type semiconductor on a printed circuit board is not limited by the mold frame, and the generation of internal strain in the sealing resin diffuses toward the gap By doing so, it was possible to prevent the semiconductor element from being peeled off from the electrode portion of the insulating substrate.
[0015]
Further, according to the chip type semiconductor manufacturing method of the present invention, the sealing resin is filled and solidified in a state where the temporary frame is arranged, and the mold frame is fixed around the sealing resin after the temporary frame is removed. Thus, there is an effect that a desired gap can be easily and accurately provided between the sealing resin and the mold frame, and at the same time, the gap can be easily adjusted.
[Brief description of the drawings]
FIG. 1 is a perspective view showing an embodiment of a chip-type semiconductor according to the present invention.
FIG. 2 is a cross-sectional view taken along line AA in FIG.
FIG. 3 is a cross-sectional view showing a manufacturing process when a temporary frame is arranged in the chip type semiconductor manufacturing method of the present invention.
FIG. 4 is a cross-sectional view showing a manufacturing process when a temporary frame is removed in the manufacturing method.
FIG. 5 is a manufacturing process diagram of a chip-type semiconductor according to the present invention.
FIG. 6 is a cross-sectional view showing another embodiment of a chip-type semiconductor according to the present invention.
FIG. 7 is a cross-sectional view showing an example of a conventional chip type semiconductor.
[Explanation of symbols]
20 Photo reflector (chip type semiconductor)
21 Chip type light emitting diode (chip type semiconductor)
22 Chip type phototransistor (chip type semiconductor)
23 Insulating substrate 26 Light emitting diode element (semiconductor element)
27 Phototransistor element (semiconductor element)
28a, 28b Electrode part 29a, 29b Electrode part 31, 32 Translucent resin (sealing resin)
33 Mold frame 35 Cavity

Claims (3)

絶縁基板と、その上面に形成された電極部にダイボンドされた発光ダイオード素子及びフォトトランジスタ素子と、これらの素子および素子にワイヤボンディングされた金属細線を素子ごとに封止する封止用樹脂と、これら封止用樹脂の周囲を取り囲むモールド枠とで構成されてなるチップ型半導体であって、
前記モールド枠には前記封止用樹脂の間を仕切る中央壁が形成されており、封止用樹脂の周囲にはモールド枠およびモールド枠の中央壁との間にそれぞれ空隙部が設けられると共に、前記モールド枠及び中央壁の壁面は前記空隙部を介して封止用樹脂と対向する面が垂直であることを特徴とするチップ型半導体。An insulating substrate, a light emitting diode element and the phototransistor element is die-bonded to the electrode portions formed on the upper surface thereof, a sealing resin for sealing the wire bonded metal thin wire for each element in these devices and elements, a chip-type semiconductor formed is composed of a mold frame surrounding these sealing resin,
The mold frame is formed with a central wall that partitions the sealing resin, and a gap is provided between the mold frame and the central wall of the mold frame around the sealing resin. The chip-type semiconductor according to claim 1, wherein the mold frame and the wall surface of the center wall are perpendicular to the sealing resin through the gap . 前記封止用樹脂の周囲にはモールド枠およびモールド枠の中央壁との間にそれぞれ一定幅の空隙部が設けられる請求項１記載のチップ型半導体。The chip-type semiconductor according to claim 1, wherein a gap having a constant width is provided between the mold resin and a central wall of the mold frame around the sealing resin. 電極部が形成された絶縁基板上に仮枠を設置すると共に半導体素子をダイボンドし、仮枠内に封止用樹脂を充填固化したのち仮枠を取り外し、この封止用樹脂の周囲にモールド枠を載置し、上記封止用樹脂との間に空隙部を設けた状態でモールド枠を絶縁基板に固着したことを特徴とするチップ型半導体の製造方法。  A temporary frame is placed on the insulating substrate on which the electrode portion is formed and the semiconductor element is die-bonded. After the sealing resin is filled and solidified in the temporary frame, the temporary frame is removed, and the mold frame is formed around the sealing resin. And a mold frame is fixed to the insulating substrate in a state where a gap is provided between the sealing resin and the sealing resin.
JP19344196A 1996-07-23 1996-07-23 Chip-type semiconductor and manufacturing method thereof Expired - Fee Related JP3699783B2 (en)

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