JP3673025B2 - Packet transfer device - Google Patents

Description

【０３２６】
となる。ここで、出力ポートからの平均の出力レートＲ′0 は、
【数２】

【０３２７】
であるから、Ｑth＝( Ｒi −Ｒ′O ）×ｔT となり、この第８の実施形態のセルバッファ装置は、バックプレッシャのない単純なバッファ装置の場合のしきい値と同じしきい値を設定することにより、ほぼ同様の効果を得られると考えられる。
【０３２８】
なお、輻輳状態を判定する代わりに、セルの廃棄判定を行なう場合でも全く同じアルゴリズムが適用できる。
【０３２９】
以上説明したように、上記第８の実施形態に係るバックプレッシャ信号を考慮するセルバッファ装置によれば、キュー長の監視結果が外部条件の影響を受け難く、安定したキュー長の監視が容易である。
【０３３０】
４． 遅延を考慮したセル数情報の修正（第９の実施形態）
次に、本発明に係るセル数情報を修正するセルバッファ装置の実施形態について説明する。
【０３３１】
４．１ 第９の実施形態（遅延を考慮したセルバッファ装置）
図１９に、第９の実施形態に係る遅延を考慮したセルバッファ装置の構成を示す。
【０３３２】
図１９に示したセルバッファ装置は、大きく分けて、ひとつ以上のセルバッファＢ（Ｂａ、Ｂｂ、…）を複数段（図１９では２段）接続してなるセルバッファ網３００と、各セルバッファＢのセル数を入力してセルバッファＢへ転送指示を行なう管理部３０１とから構成される。
【０３３３】
管理部３０１は、転送指示の履歴３０２を保持し、新たな転送指示を決定する際にこの転送指示履歴３０２を使用することを特徴とする。
【０３３４】
前記管理部３０１は、セルバッファＢがセル数を管理部３０１へ送信した時刻から、管理部が決定する転送指示がそのセルバッファＢに作用する時刻までに、そのセルバッファＢに作用する転送指示の回数を前記転送指示履歴３０２より求め、その転送指示の回数とセル数から転送指示を決定する。
【０３３５】
図２０は、本発明の遅延を考慮したセルバッファ装置におけるセル数情報の修正原理を説明する図である。
【０３３６】
入力リンク＃１、＃２から入力したセルは、それぞれ前段のセルバッファＢa1、Ｂa2に一時的に蓄積される。管理部３０１の転送指示に従いセルはセルバッファＢb に転送され、セルバッファＢb はセルを出力リンクへ出力する。
【０３３７】
管理部３０１には、Ｂa2のセル数Ｎa2と、Ｂb のセル数Ｎb が伝送され、Ｂa1、Ｂa2に対して転送指示を出力する。
【０３３８】
今、Ｂa2からセル数情報が管理部３０１に到着し、その情報から転送指示を決定してＢa2に転送を指示して、この転送指示によりＢa2のセル数が変化するまでの遅延時間をＤセル周期とする。また、Ｂb からセル数情報が管理部に到着し、その情報から転送指示を決定してＢa1、Ｂa2に転送を指示して、この転送指示によりＢa1またはＢa2からＢb へセルが転送されＢb のセル数が変化するまでの遅延時間も、説明を簡単にするため同じＤセル周期であるとする。
【０３３９】
ここで、図２０を、セルバッファＢa1、Ｂa2が図５３のクラス１セル蓄積部、クラス２セル蓄積部に相当し、セルバッファＢb がセル多重化ＦＩＦＯに相当する優先制御を行なうセルバッファ装置と考える。Ｂa1、Ｂa2、Ｂb のセルバッファ間のセル転送の方針は図５３と同じである。つまりＢb の蓄積セル数を少なくすることが必要であるが、Ｂb を努めて空にしない（＝アンダフローしない）ように転送指示をする。さらに、転送指示は空指示をしないように行なう（Ｂa2に蓄積セルが存在する場合にのみＢa2に対して転送指示を行なう）。
【０３４０】
さて、時刻ｔ2 でＢa2から出力されたセル数情報Ｎa2が管理部３０１へ到着し、時刻ｔ3 に管理部３０１が転送指示を行なって時刻ｔ4 にその転送指示によりＢa2からセルが出力したとする。管理部３０１が知りたい情報は、転送指示が実際にＢa2に作用する時刻ｔ4 におけるＢa2のセル数である。この時点を図２０に白丸で示した。
【０３４１】
Ｂa2が時刻ｔ2 からｔ4 の時間（＝Ｄセル周期）でＭa2回の転送指示を受け付けたとすると、この間にＢa2はＭa2セル出力したことになり、時刻ｔ4 におけるＢa2のセル数はＮa2−Ｍa2である（Ｂa2へセルが入力しなかった場合）。
【０３４２】
通常、管理部３０１からＢa2までの転送指示の伝送遅延は一定だから、Ｂa2が受信する転送指示回数Ｍa2は、ｔ4 −ｔ2 ＝Ｄ＝ｔ3 −ｔ1 となるようなｔ1 とｔ3 間で管理部３０１が出力した転送指示の回数と等しい。従って、転送指示履歴３０２より転送指示回数Ｍa2を知ることにより、時刻ｔ2 からｔ4 におけるＢa2の減少セル数を正確に求めることができる。
【０３４３】
Ｂb に関しても同様に考えることができ、時刻ｔ2 からｔ4 におけるＢb のセル数の増加量（Ｂa2からの転送セルによる増加量）を正確に求めることができる。
【０３４４】
時刻ｔ2 からｔ4 でのＢa2への入力セル数は、管理部３０１は知ることができない。Ｂa2に対して空指示しないようにするためには、Ｂa2のセル数を少なめに見積もればよい。従って、入力リンクからＢa2へのセル入力は、時刻ｔ2 からｔ4 においてなかったと仮定する。
【０３４５】
また時刻ｔ2 からｔ4 でのＢb からのセル出力は、管理部３０１は知ることができない。Ｂb がアンダフローしないようにするためには、Ｂb のセル数を少なめに見積もる必要がある。従って、Ｂb からのセル出力は、時刻ｔ2 からｔ4 において常に出力し続けたと仮定する（Ｄセル周期であるので、Ｄセルと仮定する）。さらに、Ｂa1からの入力セルもゼロと仮定する。
【０３４６】
まとめると、修正されたＮa2、Ｎb をそれぞれＮ′a2、Ｎ′b とすると、
Ｎ′a2＝Ｎa2＋０−Ｍa2
Ｎ′b ＝Ｎb ＋Ｍa2−Ｄ
である。よって管理部３０１がＢa2へ転送指示を行なう条件は、
（Ｎ′b ≦Ｔｈ）ａｎｄ（Ｎ′a ＞０）
で与えられる。Ｂa1への転送指示は、
（Ｎ′b ≦Ｔｈ）ａｎｄ（Ｎ′a ≦０）
の条件で行なう。Ｔｈは通常は「１」である。以上のようにセル数を修正することにより、アンダフローや空指示を努めて少なくしつつ転送を指示することができる。
【０３４７】
４．２ 一般的なバッファ網におけるセル数の修正方法
次に、一般的なバッファ網におけるセル数の修正方法について説明する。
【０３４８】
基本原理の説明には図２１を用いる。図２１には、すでに述べたようにセルバッファ網３００と管理部３０１がある。セルバッファ網３００は、着目しているセルバッファＢx を含む。セルバッファＢｘは物理的には複数のバッファであっても良い。管理部はこのセルバッファＢｘからセル数情報を得て転送指示を与える。まず本発明を説明する際に使用する用語の定義を行う。
【０３４９】
４．２．１． 用語の定義
時刻は、特に断らない限り現在時刻をゼロとする相対時刻とし、セル周期経過毎に１ずつ増加するものとする。このような時刻の定義は他の表現方法に変換可能であり一般性がある。また、ある時刻ｔ１からある時刻ｔ２までの期間をｐなどと表すことがあり、これをｐ＝［ｔ１、ｔ２）と表す。この期間ｐは時刻ｔ１を含み、ｔ２は含まない。
【０３５０】
セルバッファＢｘの蓄積セル数をＮｘで表す。Ｎｘは現在時刻（ｔ＝０）に管理部３０１に到着した蓄積セル数である。
【０３５１】
セルバッファＢｘに対し管理部３０１が時刻ｔ（ｔ＜０）に出力した転送指示をＩｘ（ｔ）で表す。転送を指示した場合はＩｘ（ｔ）＝１であり、転送を指示しない場合はＩｘ（ｔ）＝０である。
【０３５２】
時刻ｔ（ｔ＜０）に管理部３０１に到着したセルバッファＢｘのＨＯＬセル数をＨｘ（ｔ）で表す。
【０３５３】
ＨＯＬセル数とは、１回の転送指示でセルバッファから一度に転送される可能性のあるセル数である。特に、現在時刻に管理部３０１に到着したＨＯＬセル数情報ＨｘをＨｘ（０）と表す。
【０３５４】
本発明の管理部３０１は、時刻ｔ（ｔ＜０）において得たセルバッファＢｘのＨＯＬセル数Ｈｘ（ｔ）および自らがセルバッファＢｘへ出力した転送指示Ｉｘ（ｔ）を履歴として記憶する。
【０３５５】
ある期間ｐに管理部がセルバッファＢｘに転送を指示した回数をＳｍｘ（ｐ）と表す。ｐ＝［ｔ１、ｔ２）のとき、Ｍｘ［ｔ１、ｔ２）とも表す。つまり、
【数３】

【０３５６】
図２３に、セルバッファＢｘから管理部３０１へのセル数情報の流れと、管理部３０１からセルバッファＢｘへの転送指示の流れを表したタイムチャートを示す。
【０３５７】
この図の様に、時刻ｔｆ、ｔｔ、ｔｈを定める。時刻ｔｆにおけるセルバッファＢｘの蓄積セル数Ｎｘおよび時刻ｔｈにおけるセルバッファＢｘのＨＯＬセル数Ｈｘは、管理部３０１が現在時刻においてセルバッファＢｘに関し直接知り得る最新の情報であるとする。このとき管理部３０１は、時刻ｔｔにおけるセルバッファＢｘの蓄積セル数を予測したいものとする。
【０３５８】
時刻ｔｆ、ｔｔ、ｔｈに対して、時刻ｔ１、ｔ３、ｔ２を定める。時刻ｔ１に管理部３０１が出力した転送指示がセルバッファＢｘに届く時刻をｔｆとし、時刻ｔ２に管理部３０１が出力した転送指示がセルバッファＢｘに届く時刻をｔｔとする。同様に時刻ｔ３に管理部３０１が出力した転送指示がセルバッファＢｘに届く時刻をｔｈとする。
【０３５９】
時刻ｔ１、ｔ２、ｔ３は現在時刻より過去の時刻であるとする。つまり、ｔ１＜ｔ２＜０、ｔ３＜０とする。
【０３６０】
４．２．２． 基本原理
ここで本発明の基本原理を説明する。本発明の管理部３０１は転送指示の履歴から蓄積セル数の変化を予測する。前述のセルバッファＢｘについて、時刻ｔｔの蓄積セル数を求めたい場合、それより過去にの時刻ｔｆにおける蓄積セル数Ｎｘに対して、転送指示の履歴を用いてこの期間に転送指示により転送されたセル数を予測して修正する。修正は、１回の転送指示により転送されるセル数が１以上であることに基づく。特に時刻ｔｈ以降の最初の転送指示により転送されるセル数についてはＨＯＬセル数Ｈｘ以上であることに基づく。
【０３６１】
４．２．３． ３つの関数
以上の基本原理より修正に使用する３つの関数、ｆ（ ）、ｇ（ ）、Ｓｃ（）を定める。これらの関数は、時刻ｔｆから時刻ｔｔにおいてセルバッファＢｘが転送指示によるセルの転送でどのくらい変化するかを求めるものである。ｔｆ、ｔｔと比較してｔｈがどのような値であるかにより３通りの場合に分類でき、適用する関数が異なる。
【０３６２】
（１） 関数ｆ（ ）
関数ｆ（ ）は、ｔｈ＝ｔｆ＜ｔｔの場合に使用する。この時のタイムチャートを図２２に示す。ｐ１［ｔ１、ｔ２）とする。Ｈｘ≠０かつＳｍｘ（ｐ１）≠０のときは、期間ｐ１の最初の転送指示ではＨｘセル転送され、それ以降の転送指示では１セルずつ転送されると考える。時刻ｔｆから時刻ｔｔにおいて変化するセルバッファＢｘのセル数を計算する関数ｆ（ ）は、Ｈｘと期間ｐ１の転送指示回数Ｓｍｘ（ｐ１）を引数として、次のように求めることができる。
【０３６３】
【数４】

【０３６４】
（２） 関数ｇ（ ）
関数ｇ（ ）は、ｔｈ＜ｔｆ＜ｔｔの場合に使用する。この時のタイムチャートを図２３に示す。ｐ１＝［ｔ１、ｔ２）とし、ｐ２＝［ｔ３、ｔ１）とする。
【０３６５】
この場合、時刻ｔｈ以降に到着した初めての転送指示が期間ｐ２に管理部３０１から出力されたか否かで場合分けが必要である。期間ｐ２に管理部３０１から転送指示が出力されていないから、期間ｐ１においてＨｘの値を用いることができる。時刻ｔｆから時刻ｔｔにおいて変化するセルバッファＢｘのセル数を計算する関数ｇ（ ）は、Ｈｘと期間ｐ１、ｐ２の転送指示回数Ｓｍｘ（ｐ１）、Ｓｍｘ（ｐ２）を引数として、次のように求めることができる。
【０３６６】
【数５】

【０３６７】
（３） 関数Ｓｃ（ ）
関数Ｓｃ（ ）は、ｔｆ＜ｔｔ＝ｔｈの場合に使用する。この時のタイムチャートを図２４に示す。ｐ１＝［ｔ１、ｔ２）とする。管理部３０１が知り得る最新の蓄積セル数は時刻ｔｆのときの値であるが、この場合はＨＯＬセル数に関しては時刻ｔｆから時刻ｔｔまでの全ての期間における情報が管理部３０１にすでに到着している。
【０３６８】
転送指示がセルバッファＢｘへ到着した時点のＨＯＬセル数がわかれば、転送されるセル数もわかることから、時刻ｔｆから時刻ｔｔにおいて変化するセルバッファのセル数を計算する関数Ｓｃ（ ）は、Ｉｘ（ｔ）、Ｈｘ（ｔ）を用い、期間ｐ１を引数として、次のように求めることができる。
【０３６９】
【数６】

【０３７０】
以上説明してきたようなセル数の修正方法を、例えば、図１に示したようなクラス間の優先制御を行なうセル多重化装置に適用することは容易である。
【０３７１】
さらに、例えば、図６に示したようなＶＣ間公平キューイングを行なうセル多重化装置に、セル数の修正方法を適用することも容易である。
【０３７２】
４．３ 第９の実施形態に係るセルバッファ装置の利点
以上説明したように、上記第９の実施形態によれば、セルバッファとセルバッファを管理する管理部との間に遅延のあるセルバッファ装置は、転送指示を決定する際に転送指示の履歴を用いて、セルバッファから伝送されてきたセル数を、転送指示がセルバッファに作用する時刻のセル数に修正するため、遅延時間を原因とした性能の劣化が少ない。
【０３７３】
５．セルスイッチ（第１０の実施形態）
５．１ 第１０の実施形態（セルスイッチ）
次に、第１０の実施形態として、ここまで説明してきた本発明に係るセル多重化装置、セルバッファ装置を組み合わせたセルスイッチについて説明する。
【０３７４】
図２５は、複数の入力ポート＃ｉ（ｉ＝１〜Ｎ）から入力したセルを一時的に蓄積し、バックプレッシャに応じて出力する複数の入力バッファＩＢと、内部の輻輳状態に応じてバックプレッシャ信号を出力するバックプレッシャ付きセルスイッチ４００と、入力バッファＩＢとの間で情報を転送するカゴ管理部ＫＭとからなる。
【０３７５】
この構成例において扱うセルは、大きくは高優先セル、低優先セルの２つの優先度を持ち、さらに低優先クラスは複数のクラスにわかれている。通常はＣＢＲ、ＶＢＲなどのリアルタイム情報を伝送するセルを高優先セルとし、ＡＢＲ、ＵＢＲなどのノンリアルタイム情報を伝送するセルを低優先セルとする。
【０３７６】
まず、バックプレッシャ付きセルスイッチについて説明する。
【０３７７】
カゴスイッチの特徴は入力バッファＩＢとカゴ管理部ＫＭにある。バックプレッシャ付きセルスイッチ４００は入力したセルをある定められた時間内に出力できればよく、そのアーキテクチャは以下に示すものだけではない。例えば、電子情報通信学会技術報告ＳＳＥ９３−６“バッファ容量拡張可能なＡＴＭスイッチ：ＸＡＴＯＭ”にて示されているＡＴＭスイッチでもよい。
【０３７８】
図２５に示すバックプレッシャ付きセルスイッチ４００を一例として説明する。１段目単位スイッチＳＥ１、２段目単位スイッチＳＥ２、出力バッファＯＢからなり、ＳＥ１とＳＥ２を並列リンクにて２段デルタ網接続し、ＳＥ２の出力したセルをＯＢへ転送して出力ポートへ出力する。ＳＥ１からＯＢの間はｋ倍速で動作する。ｋの値はセルスイッチがノンブロッキングになるように定める。例えばＳＥ１、ＳＥ２が８入力８出力の時、全体で１６入力１６出力とする場合にはｋ＝２とすればよい。
【０３７９】
図２５のバックプレッシャ付きセルスイッチ４００は、高優先セルと低優先セルの２段階の優先度を扱う構成である。
【０３８０】
低優先セルの交換にのみ着目すると基本構成は１９９５年電子情報通信学会総合大会Ｂ−５８９“ＡＴＭ２段スイッチ網のバッファ容量拡張法”にて示されているものとほぼ等しい。低優先セルは、ＳＥ１、ＳＥ２で交換、コピーされる。
【０３８１】
低優先セルがＯＢで輻輳した場合には低優先セル用バックプレッシャ信号を用いてＩＢのその出力ポート行きのセル出力を抑制する。このバックプレッシャ信号により基本的にはＯＢおよびＳＥ２のバッファを溢れさせないようにすることが可能である。しかし、マルチキャストセルの影響のためこれらのバッファが溢れそうになる場合があり、それに備えて低優先セル用オーバーフローバックプレッシャ信号がＯＢからＳＥ２へ出力し、低優先セル非常用バックプレッシャ信号がＳＥ２からＩＢへ出力する。ＩＢが低優先セルを蓄積するのでＳＥ２、ＯＢでは廃棄されない。
【０３８２】
ＯＢは、低優先セル用オーバーフローバックプレッシャ信号をＳＥ２へ出力する代わりに、これを低優先セル非常用バックプレッシャ信号としてＩＢへ出力する構成でもよい。この場合は、ＳＥ２が低優先セル非常用バックプレッシャ信号を出力する必要はない。しかし、先に説明したように、低優先セル非常用バックプレッシャ信号をＳＥ２から出力した方がＳＥ２内でのバッファ共用化効果を有効に活用できるという利点がある。
【０３８３】
高優先セルは、低優先セルと同様、ＳＥ１、ＳＥ２で交換、コピーされる。高優先セルに関してはバックプレッシャ付きセルスイッチからＩＢへのバックプレッシャ信号はない。ＯＢはその高優先セルの輻輳を反映した高優先セル用バックプレッシャ信号によりＳＥ２のセル出力を制御する。ＩＢは高優先セルを蓄積しない。ＳＥ２内に空きバッファが無ければ廃棄されることがある。
【０３８４】
次に、出力バッファについて説明する。
【０３８５】
図２６に、カゴスイッチの出力バッファＯＢの構成例を示す。
【０３８６】
ＳＥ２からＯＢへ転送されたセルは識別部４１０にて優先度を識別され各優先度に対応したキューに入れられる。各キューのセルは選択部４１１により優先度に従って選択され出力ポートへ出力される。ＯＢは、低優先セルのキュー長があるしきい値を越えた場合に低優先セル用バックプレッシャ信号を用いてＩＢの低優先セルの、そのＯＢ行きの出力を止める。高優先セルのキュー長があるしきい値を越えた場合に高優先セル用バックプレッシャ信号を用いてＳＥ２の高優先セルの、そのＯＢ行きの出力を止める。低優先セルのマルチキャストセルの影響により低優先セルのキュー長が伸び続けた場合に備えて低優先セル用オーバーフローバックプレッシャ信号を用いてＳＥ２の低優先セルの、そのＯＢ行きの出力を止める。
【０３８７】
次に、単位スイッチについて説明する。
【０３８８】
図２７に、カゴスイッチに用いる１段目単位スイッチＳＥ１の構成例を示す。ＳＥ１は一般的によく知られているスイッチＬＳＩである。入力リンクより入力したセルに対し、そのセルヘッダを識別部４１５で識別して所定の交換処理を行い出力リンクへ出力する。スイッチ全体がｋ倍速で動作していることから内部のセルバッファの蓄積セル数は多くならない。これについては１９９４年電子情報通信学会秋季大会Ｂ−４３９“並列リンクのあるスイッチ網の検討”にて知られている。
【０３８９】
図２８に、カゴスイッチに用いる２段目単位スイッチＳＥ２の構成例を示す。ＳＥ２は内部のキューが出力リンク毎に優先度毎のキューになっている。各優先度毎のキューの出力は選択部４２１により選択される。高優先セルが存在するときには、低優先セルの有無に関わらずその出力リンクに高優先セルを出力する。ただし、選択部４２１に入力している高優先セル用バックプレッシャ信号が、高優先セルの出力の禁止を指示している場合は高優先セルを出力せず、低優先セルを出力しても良い。低優先セルは低優先セル用オーバーフローバックプレッシャ信号により出力が禁止される場合がある。
【０３９０】
ＳＥ２は、複数の優先度、複数の出力リンク間で物理的なバッファ領域を共有することにより、ＳＥ２内部のバッファを効率的に使用することが可能である。バッファ状態管理部４２２は各キュー毎のキュー長、および優先度毎に全ての出力リンク行きのキュー長を合計した結果などをモニタする。
【０３９１】
例えば、高優先セル用キューは各キュー毎にしきい値を持ち、そのしきい値を越えた場合にそのキューの入力セルを廃棄する。低優先セル用キューは全てのキュー長の合計をモニタし、しきい値を越えた場合は低優先セル非常用バックプレッシャ信号により低優先セルの入力を禁止するようにＩＢに伝える。
【０３９２】
ＳＥ１はＳＥ２と同じ単位スイッチを使用してもかまわない。
【０３９３】
図２５のバックブレッシャ付きセルスイッチ４００は２段の単位スイッチＳＥ１とＳＥ２によりセルを交換するが、内部の経路は各入力ポートと出力ポートのペアにひとつずつしか定めない。そのため各単位スイッチはセルヘッダを見てセルをコピーしつつ交換する際に複雑な経路の選択アルゴリズムは必要ない。出力ポート数が３２ポート程度以下であるなら、セルのヘッダに出力ポートのビットマップ情報を付加することが容易に可能である。ＳＥ１、ＳＥ２はそのビットマップ情報に基づいてセルを交換する。
【０３９４】
次に、入力バッファＩＢについて説明する。
【０３９５】
図２９に、カゴスイッチの入力バッファＩＢの構成例を示す。
【０３９６】
ＩＢに入力した高優先セルは、ユニキャスト、マルチキャストとも優先的にＳＥ１へ出力する。そのため高優先セルのセル遅延揺らぎは非常に小さい。またＩＢに高優先セル用のバッファは存在しない。
【０３９７】
本発明の特徴は低優先セルの処理方法にある。以降、低優先セルについてのみ説明する。
【０３９８】
図２９において、入力バッファＩＢは、主に、入力したユニキャストセルを一時的にそのセルの出力ポート毎に蓄積する複数の出力ポート毎ユニキャストセル管理部４３０と、入力したマルチキャストセルを一時的に蓄積するマルチキャストセル管理部４３１、およびこれらの管理部のセルを選択して入力バッファから出力する出力ポート選択スケジューラ４３２を持つ。
【０３９９】
出力ポート毎ユニキャストセル管理部４３０は、入力したセルを一時的にそのセルのクラス毎に蓄積する複数のクラス毎ユニキャストセル管理部４３３と、そのクラス毎ユニキャストセル管理部４３３から出力したセルを多重化するクラス多重化ＦＩＦＯ４３４を持つ。
【０４００】
マルチキャストセル管理部４３１は、入力したセルを一時的にそのセルのクラス毎に蓄積する複数のクラス毎マルチキャストセル管理部４３５と、そのクラス毎マルチキャストセル管理部４３５から出力したセルを多重化するクラス多重化ＦＩＦＯ４３６を持つ。
【０４０１】
出力ポート毎ユニキャストセル管理部４３０、マルチキャストセル管理部４３１のそれぞれのクラス多重化ＦＩＦＯ４３４、４３６より出力するセルは出力ポート選択スケジューラ４３２により選択され、入力バッファＩＢから出力される。
【０４０２】
出力ポート選択スケジューラ４３２は外部からの低優先セル用バックプレッシャ信号、低優先セル非常用バックプレッシャ信号を考慮してセルを選択する。
【０４０３】
クラス毎ユニキャストセル管理部４３３は、蓄積されているセルのうち、カゴ管理部ＫＭから出力を許可されたセルの集合を管理するカゴと呼ばれるキュー （カゴ４４０）と、それ以外のセルを管理する前カゴと呼ばれるキュー（前カゴ４４１）を持つ。
【０４０４】
前カゴ４４１に入ったセルは単位カゴという単位で管理される。図２９において前カゴ４４１、カゴ４４０内の縦一列が単位カゴを示す。入力したセルは単位カゴ毎にＶＣ（ＣＧ）間で公平に管理される。前カゴ４４１のセルはカゴ管理部ＫＭの指示により、単位カゴを単位としてカゴ４４０に転送される。
【０４０５】
カゴ４４０のセルはカゴ管理部ＫＭの指示により、セルを単位として転送されクラス多重化ＦＩＦＯ４３４で多重化される。
【０４０６】
クラス毎マルチキャストセル管理部４３５の動作は後述する。
【０４０７】
ＩＢの全ての出力ポート、全てのクラスのキューでセルバッファを共有することにより、有限のバッファ量を有効に活用することが可能である。
【０４０８】
ＩＢに到着したセルがＩＢから出力されるためには、セルが到着したことをＩＢからＫＭへ通知し、ＫＭがＩＢからの出力を指示することが必要である。従ってＩＢとＫＭの間の情報伝送に遅延がある場合はその遅延時間だけＩＢからのセルの出力が遅延する。しかし遅延時間の大きさは数セル周期程度と考えられるため、トラヒック特性に及ぼす影響は少ないと考えられる。
【０４０９】
ユニキャストセルを出力ポート毎に優先制御するために、ＩＢには出力ポート毎に、クラス毎ユニキャストセル管理部４３３とクラス多重化ＦＩＦＯ４３４がある。図１のセル多重化装置で説明した優先制御と基本的に同じ方法を使用する。
【０４１０】
図１はセル多重化装置であるが、カゴスイッチはセルスイッチでありＩＢはセルスイッチの入力バッファである。そのためクラス多重化ＦＩＦＯはひとつのＩＢに全ての出力ポートに対応して複数存在し、そのセルは出力ポート選択スケジューラ４３４により選択されＳＥ１へ出力される。
【０４１１】
図１のセル多重化装置のクラス毎セル蓄積部１３は、図２９のＩＢのクラス毎ユニキャストセル管理部４３３に相当し、図１のセル多重化装置のクラス多重化ＦＩＦＯ１４は、図２９のＩＢのクラス多重化ＦＩＦＯ４３４に相当する。
【０４１２】
図１のセル多重化装置のクラス管理部１２は、図２５のＫＭに対応する。クラス毎ユニキャストセル管理部４３３からクラス多重化ＦＩＦＯ４３４へのセルの転送をカゴ管理部ＫＭが指示することにより優先制御を行なうことができる。
【０４１３】
マルチキャストセルの優先制御は後述する。
【０４１４】
ユニキャストセルをクラス毎にＶＣ間公平キューイングするために、クラス毎ユニキャストセル管理部４３３に前カゴ４４１とカゴ４４０がある。図６のセル多重化装置で説明したＶＣ間公平キューイングと基本的に同じ方法を使用する。
【０４１５】
図６はセル多重化装置であり、かつクラスも存在しないが、ＩＢはセルスイッチの入力バッファでありクラスも存在する。前カゴ４４１、カゴ４４０は各ＩＢについて、全ての出力ポート、全てのクラスに対応して存在し、そのセルはクラス多重化ＦＩＦＯ４３４により多重化された後、出力ポート選択スケジューラ４３２により選択されＳＥ１へ出力される。
【０４１６】
図６のセル多重化装置のカゴ２１３は、図２９のＩＢのカゴ４４０に相当し、図６のセル多重化装置の同一の時刻までに出力すべきセル集合２１４が、図２９のＩＢの単位カゴに相当する。図６のセル多重化装置のカゴ管理部１２は、図２５のカゴ管理部ＫＭに相当する。図２９の前カゴ４４１からカゴ４４０への単位カゴの転送をカゴ管理部ＫＭが指示することによりＶＣ間公平キューイングを行なうことができる。
【０４１７】
マルチキャストセルのＶＣ間公平キューイングは後述する。
【０４１８】
ユニキャストセルをＩＢ内でＶＣ間公平キューイングするために、クラス毎ユニキャストセル管理部４３３に前カゴ４４１とカゴ４４０がある。図１０のセルグループＦＩＦＯ２３２ａのポインタチェーンによるデータ構造例で説明した方法と基本的に同じ方法を使用する。
【０４１９】
図１０のセルグループＦＩＦＯ２３２ａが、図２９のＩＢの前カゴ４４１に相当し、図１０の出力待ちセルグループＦＩＦＯ２３２ｂが、図２９のＩＢのカゴ４４０に相当する。また、図１０のセルグループは図２９のＩＢの単位カゴに相当する。
【０４２０】
次に、図３０を参照して、入力バッファＩＢのキューイング処理について説明する。
【０４２１】
セルは、まず前カゴ４４１に蓄積され、その後単位カゴを単位としてカゴ４４０に転送される。カゴ４４０のセルはセルを単位としてカゴ４４０から出力される。それぞれのきっかけについてはカゴ管理部ＫＭが指示を行なう。
【０４２２】
この構成例では、全てのＶＣは、あるコネクショングループ（ＣＧ）に所属する。コネクショングループの概念を持つことにより複数のＶＣにひとつのリソース（帯域やセルバッファ）を共有させることが可能となる。例えば、離れたふたりのユーザ間の通信に対して１本のＶＣ分の課金しか行なわないときに、そのふたりのユーザ間に複数のＶＣを設定する自由度を与えることが可能となる。もしくは、ＶＣ数に応じて公平な帯域の割当を行なう網において、あるふたりのユーザが多数のＶＣを設定して不当に大きな帯域を得ようとすることを防止することが可能となる。
【０４２３】
前カゴ４４１においてセルをどの単位カゴにいれるかを決定するためにＶＣテーブルとＣＧテーブルを使用する。
【０４２４】
ＶＣテーブルを用いて入力したセルのコネクション識別子（例えばＶＣ４）からコネクショングループ識別子（例えばＣＧ５）を知ることができる。ＣＧテーブルを用いてコネクションクループ識別子からＣＧ毎に定められた値を知ることができる。この構成例におけるＣＧ毎の値はＮx 、Ｎc 、Ｐtr、Ｑlen 、Ｃnt１、Ｃnt２、Ｃnt３、ＢＰＩＤt である。
【０４２５】
Ｎx 、Ｎc 、Ｐtr、Ｑlen は、図１０のセルグループＦＩＦＯのポインタチェーンによるデータ構造例で説明した。Ｎx はそのＣＧの重み、Ｎc は作業変数、Ｑlen はそのＣＧの蓄積セル数、ＰtrはそのＣＧのセルが蓄積されている単位カゴの末尾へのポインタである。
【０４２６】
一方、Ｑlen 、Ｃnt１、Ｃnt２、Ｃnt３、ＢＰＩＤt は、図１５および図１６のバックプレッシャ考慮キュー監視部を持つセルバッファ装置で説明した。
【０４２７】
Ｑlen はそのＣＧの蓄積セル数、Ｃnt１は廃棄すべきセル数、ＢＰＩＤt は最後のセル入力時のバックプレッシャ識別子である。よりきめの細かいキュー監視を行なうためＣnt１と同じ機能を持つ変数Ｃnt２、Ｃnt３が存在する。それぞれキュー長監視のしきい値が異なる。Ｃnt２はセルヘッダ内にあるＣＬＰ（Ｃｅｌｌ Ｌｏｓｓ Ｐｒｉｏｒｉｔｙ：セル廃棄優先）ビットが低優先（ＣＬＰ＝１）であるセル用の廃棄すべきセル数、Ｃnt３はこのキュー長監視において輻輳かどうかを判定するために使用する値である。輻輳かどうかの情報は、例えばセルヘッダ内にあるＥＦＣＩをマークするかどうかや、ＲＭセルの輻輳表示ビットをマークするかどうかを決定するために用いる。
【０４２８】
あるクラスでＶＣ間公平キューイングを行なわない設定をすることも可能である。その場合は、そのＶＣが所属するＣＧのＮx を十分大きな値に設定すればよい。
【０４２９】
さて、図２５に示すバックプレッシャ付きセルスイッチは、ＩＢからＯＢまでのセル伝送の遅延時間が大きいことなどの影響により、低優先セル用バックプレッシャ信号が出力可能と出力禁止を繰り返す周期が比較的大きい。従ってＩＢのＣＧ毎のキュー長Ｑlen を観測すると、主に低優先セルバックプレッシャ信号に同期して図１４の様に振動を繰り返す。この様に、バックプレッシャ信号により振動するキュー長の監視には、図１５、図１６で説明したバックプレッシャ考慮キュー長監視アルゴリズムが適している。
【０４３０】
前カゴ４４１のとカゴ４４０に蓄積されているセルのクラス全体の合計セル数についてもバックプレッシャ考慮キュー長監視により入力セルの廃棄やＥＦＣＩのマークなどを行なって、一部のクラスがＩＢのバッファ領域の大半を独占することを防ぐことが可能である。
【０４３１】
図３１に、カゴスイッチに用いる入力バッファＩＢのカゴ管理部ＫＭとのインタフェースの一例を示す。
【０４３２】
ＫＭから各出力ポートのそれぞれに対し、以下に示すような各出力ポート毎の情報が入力される。
【０４３３】
−ＡＢＲ入力セル数
−指示クラス
−前カゴからカゴへ単位カゴの転送指示（図３１の転送指示Ｔ１）
−カゴからクラス多重化ＦＩＦＯへセルの転送指示（図３１の転送指示Ｔ２）ＡＢＲ入力セル数はＡＢＲ処理部４５０へ転送される。ＡＢＲ処理部４５０は、ＡＢＲ入力セル数を知ることによりそのＩＢとペアの出力ポートに流入するトラヒックをモニタすることができる。その情報を用いてＩＢを通過するＲＭセルのペイロードの書き換えなどを行なう。
【０４３４】
カゴ４４０からクラス多重化ＦＩＦＯ４３４へセルの転送をＫＭから指示されると、ＩＢは指示クラスのユニキャストのカゴ４４０からセルをひとつ取りだしクラス多重化ＦＩＦＯ４３４に転送する。また前カゴ４４１からカゴ４４０へ単位カゴの転送指示があると、ＩＢは指示クラスのユニキャストの前カゴ４４１から単位カゴをひとつ取りだしカゴ４４０に転送するとともに、カゴ４４０からセルをひとつ取りだしクラス多重化ＦＩＦＯ４３４に転送する。
【０４３５】
単位カゴの転送指示をそのクラスのセルの転送指示を行なう時のみに限定することにより、転送指示の情報量を減らし、より容易に実装することができる。
【０４３６】
ＩＢ内で前カゴ４４１、カゴ４４０、クラス多重化ＦＩＦＯ４３４のセル数が変化するのは、ＩＢへセルが入力した時、ＫＭが転送指示を行なった時、ＩＢからセルが出力した時である。従って、それに応じてセル数情報をＫＭへ出力する。ひとつのＩＢがＫＭへ出力する情報は、以下のものである。
【０４３７】
各出力ポート毎に、入力したセルについて（ユニキャストの場合はひとつの出力ポートについてのみ出力）、
−入力セルの有無とクラス
各出力ポート毎に、転送の指示クラスについて、
−（転送後の）前カゴセル数（図３１のＣＥ１）
−（転送後の）カゴセル数（図３１のＣＥ２）
−クラス多重化ＦＩＦＯへの転送セル数（図３１のＣＥ３）
各出力ポート毎に、ユニキャストのみの、
−クラス多重化ＦＩＦＯセル数（図３１のＣＥ４）
図３１を用いて説明する。入力したセルの情報はＩＢからＫＭへ入力セルの有無とクラスとして伝送される。また、ユニキャストとマルチキャストの前カゴセル数が加算され、クラス選択部Ｌ５により転送の指示クラスで選択されたものが前カゴセル数として伝送される。さらに、ユニキャストとマルチキャストのカゴセル数が加算され、クラス選択部Ｌ６において指示クラスで選択されたものがカゴセル数となり伝送される。そして転送指示によりカゴからクラス多重化ＦＩＦＯ４３４へ移動したセル数はユニキャストとマルチキャストとが加算され、クラス選択部Ｌ７において指示クラスで選択されて伝送される。クラス多重化ＦＩＦＯセル数はユニキャストについてのみＫＭへ伝送される。マルチキャストのクラス多重化ＦＩＦＯセル数は、クラス毎マルチキャストセル管理部４３５からのセルの出力を制御するためのバックプレッシャ信号として使用する。
【０４３８】
マルチキャストのクラス多重化ＦＩＦＯ４３６は複数の出力バッファＯＢからのバックプレッシャ信号により出力が制御されていることなどから、クラス多重化ＦＩＦＯセル数がゼロでなくともセルスイッチの出力ポートがアンダフローする可能性がある。ユニキャストセルがその影響を受けてアンダフローしないように、この構成例ではユニキャストのクラス多重化ＦＩＦＯセル数とは加算していない。
【０４３９】
ここで、マルチキャストセルの優先制御およびＶＣ間公平キューイングについて説明する。
【０４４０】
マルチキャストＶＣをスループットの視点で考える。一般的に、ある時点のセルスイッチの状態を考えると、その複数の出力ポートには、輻輳している出力ポートもあれば、負荷が低い出力ポートもある。つまり、ＶＣが使用できるスループットは出力ポートによって異なることになる。マルチキャストＶＣは、ひとつの入力ポートから複数の出力ポートへ同じスループットが同時に出力されるから、そのマルチキャストＶＣが得ることのできるスループットは出力先の中で最も輻輳している出力ポートのスループットになるのがよい。従って、ＩＢからマルチキャストセルを出力する場合は、最も輻輳している出力ポートのスループットで出力することが望ましい。
【０４４１】
ある出力ポートのあるクラスに与えられるＶＣ（ＣＧ）あたりのスループットを、ＩＢは前カゴ４４１からカゴ４４０への単位カゴの転送指示の頻度より知ることができる。また、ある出力ポートのあるクラスに与えられるスループットを、ＩＢはカゴ４４０からクラス多重化ＦＩＦＯ４３４へのセルの転送指示の頻度より知ることができる。さらにある出力ポートに与えられるスループットを、ＩＢは低優先セル用バックプレッシャ信号の頻度より知ることができる。これらの転送指示やバックプレッシャ信号は出力ポート毎に与えられる。
【０４４２】
最も輻輳している出力ポートのスループットで出力するためには、マルチキャストセルを、そのセルの出力ポートの全てに関してこれらの信号が指示または許可した時点で転送すればよい。複数の出力ポートへの指示または許可は同時である必要はない。
【０４４３】
ＩＢにおいて、低優先マルチキャストＶＣを管理する場合、本来そのクラス毎かつ出力ポートパターン毎に管理することが望ましいのであるが、一般的にはその組合せの数は大きく、また通信中にその出力ポート数が増減する可能性があるため、その様な実装は現実的ではない。図２５に示すようなカゴスイッチでは全てのマルチキャストコネクションをクラス毎にのみ管理し、出力ポートパターン毎での管理はしない。ある程度のＨＯＬ（Ｈｅａｄ Ｏｆ Ｌｉｎｅ）ブロッキングが発生することになる。
【０４４４】
図３２は、クラス毎マルチキャストセル管理部４３５を説明するための図である。この管理部は、出力ポート表、ＶＣ間公平キュー、単位カゴセル数、カゴセル数、出力許可済みセル数を保持し、管理するものである。
【０４４５】
クラス毎ユニキャストセル管理部４３３が前カゴとカゴでセルを管理していたのに対して、クラス毎マルチキャストセル管理部４３５は前カゴに相当するＶＣ間公平キュー４６０のみによりセルを管理する。ただ本発明のクラス毎マルチキャストセル管理部４３５は、管理の計算上では前カゴ、カゴの概念を用いてユニキャストと同様のセル管理を行なう。
【０４４６】
クラス毎マルチキャストセル管理部４３５は、出力ポート毎に次の情報を入力する。
【０４４７】
・前カゴからカゴへの単位カゴ転送指示
・カゴからクラス多重化ＦＩＦＯへのセル転送指示
また出力ポート毎に次の情報を出力する。
【０４４８】
・前カゴセル数
・カゴセル数
・転送セル数
ＶＣ間公平キュー４６０は単位カゴのＦＩＦＯである。ＶＣ間公平キュー４６０に入力したセルは、各ＶＣ（ＣＧ）についてひとつの単位カゴに予め定められた数までしか入力できない。この構成は図３０で説明したユニキャストの前カゴの構成と同様である。クラス多重化ＦＩＦＯ４３６からバックプレッシャ信号が入力しており、状況によってＶＣ間公平キュー４６０からのセル出力を禁止する。
【０４４９】
出力ポート表は、出力ポート別に、前カゴセル数と先頭単位カゴへのポインタを記憶する。前カゴセル数は単位カゴセル数の合計、先頭単位カゴは計算上の前カゴの先頭の単位カゴへのポインタである。
【０４５０】
単位カゴセル数はＶＣ間公平キュー４６０の単位カゴに対応して出力ポート毎のデータを記憶する。基本的には対応する単位カゴに蓄積しているマルチキャストセルの出力ポート毎のセル数を記憶する。例えば、図３２のＶＣ間公平キュー４６０の先頭の単位カゴには５セル蓄積されている。そのうち、ポート＃１とポート＃Ｎに出力するセルが３セル、ポート＃１とポート＃２に出力するセルが２セルあるので、単位カゴセル数のポート＃１には５、ポート＃２には２、ポート＃Ｎには３が記憶される。
【０４５１】
カゴセル数は計算上のカゴのセル数である。また、出力許可済みセル数は計算上の出力を許可されたセル数である。
【０４５２】
ある出力ポートに対して単位カゴ転送を指示された場合、その出力ポートの先頭単位カゴの単位カゴセル数をカゴセル数に加算し、単位カゴセル数をゼロにする。さらにその出力ポートのカゴセル数から１を減算して出力許可済みセル数に１を加算する。そして出力ポート表の先頭単位カゴのポインタをＶＣ間公平キュー４６０の次の単位カゴへひとつ進める。このときの転送セル数は１セルである。
【０４５３】
先頭単位カゴのポインタを進めることにより、ポインタはＶＣ間公平キュー４６０の先頭の単位カゴから離れていく。この距離に上限を設け、ある距離になったら単位カゴ転送指示を無視してポインタを進めないように制御する。これは、単位カゴの転送が指示された時刻と実際にセルを出力する時刻との差を大きくしないようにする効果がある。
【０４５４】
ある出力ポートに対してＫＭからセル転送が指示された場合、その出力ポートのカゴセル数から１を減算して出力許可済みセル数に１を加算する。このときの転送セル数は１セルである。
【０４５５】
クラス多重化ＦＩＦＯ４３６からのバックプレッシャ信号が出力を許可している時、セルをＶＣ間公平キュー４６０から出力することができる。その際、そのセルの全ての出力ポートについて出力許可済みセル数を１ずつ減算する。出力許可済みセル数がゼロの出力ポートが存在する場合は減算できないので、そのセルはまだ出力できない。
【０４５６】
出力許可済みセル数は単位カゴ転送指示およびセル転送指示により増加する。ある出力ポートの出力許可済みセル数がある値以上になった場合には、その出力ポートについて、クラス毎マルチキャストセル管理部４３５から出力する前カゴセル数とカゴセル数をゼロとし、単位カゴ転送指示とセル転送指示を無視する。これは実際のセルの転送スループット以上の転送指示を無視する効果がある。
【０４５７】
次に、図３３〜図３９を参照して、クラス毎マルチキャストセル管理部の動作について説明する。
【０４５８】
図３２の状態から、出力ポート＃１に対して単位カゴの転送をＫＭから指示された場合の動作を図３３に示す。ポート＃１の先頭単位カゴの単位カゴセル数をカゴセル数に加算し、単位カゴセル数ゼロにする。さらにポート＃１のカゴセル数から１を減算して出力許可済みセル数に１を加算する。ＫＭへの転送セル数は出力ポート＃１に関して１セルである。
【０４５９】
出力ポート表の先頭単位カゴのポインタをＶＣ間公平キュー４６０の次の単位カゴへひとつ進める。
【０４６０】
さらに、出力ポート＃１に対してセルの転送をＫＭから指示された場合の動作を図３４に示す。ポート＃１のカゴセル数から１を減算して出力許可済みセル数に１を加算する。ＫＭへの転送セル数は出力ポート＃１に関して１セルである。
【０４６１】
図３４のＶＣ間公平キュー４６０の先頭のセルの出力ポートは＃１と＃Ｎである。出力許可済みセル数は出力ポート＃１に関してはゼロでない（＝２）が、出力ポート＃Ｎに関してはゼロであるのでまだセルを出力することはできない。
【０４６２】
セルが到着した時の動作を図３５に示す。到着したセルの出力ポートは＃１と＃Ｎである。またこのセルは今までにＶＣ間公平キュー４６０に蓄積していなかったＶＣのセルであるとする。この場合セルはＶＣ間公平キュー４６０の先頭の単位カゴに入力される。
【０４６３】
セルを入力したとき、そのセルの全ての出力ポートの単位カゴセル数を１ずつ加算する。加算する単位カゴは出力ポート毎に決定する。基本的にはセルを入力した単位カゴに１を加えるが、出力ポート表の先頭単位カゴがセルを入力した単位カゴよりも後ろにある場合は出力ポート表の先頭単位カゴが指している単位カゴセル数に１を加える。従って、図３５では出力ポート＃１については先頭単位カゴが指している２番目の単位カゴの単位カゴセル数に１を加算する。出力ポート＃Ｎについてはセルを入力した単位カゴである１番目の単位カゴの単位カゴセル数に１を加算する。
【０４６４】
さらに、またセルが到着した時の動作を図３６に示す。新たに到着したセルの出力ポートは＃１と＃２である。またこのセルは現在ＶＣ間公平キュー４６０にセルが蓄積しているＶＣのセルであるとする。図３６の場合このセルはＶＣ間公平キュー４６０の末尾に新たに単位カゴを設け、その単位カゴに入力した。
【０４６５】
さらに、図３７に出力ポート＃Ｎに対して単位カゴの転送をＫＭから指示された場合の動作を示す。ポート＃Ｎの先頭単位カゴの単位カゴセル数をカゴセル数に加算し、単位カゴセル数ゼロにする。さらにポート＃Ｎのカゴセル数から１を減算して出力許可済みセル数に１を加算する。ＫＭへの転送セル数は出力ポート＃Ｎに関して１である。出力ポート表の先頭単位カゴのポインタをＶＣ間公平キュー４６０の次の単位カゴへひとつ進める。
【０４６６】
ＶＣ間公平キュー４６０の先頭のセルの出力ポートが＃１と＃Ｎであり、その＃１と＃Ｎの出力許可済みセル数がそれぞれ１以上（具体的には２と１）になったため、クラス多重化ＦＩＦＯ４３６が許可すればそのセルを出力できる。
【０４６７】
図３８にセルを出力した場合の状態を示す。出力セルの出力ポートに対応する出力許可済みセル数を１ずつ減算する。
【０４６８】
図３９に、以上のようにして連続して単位カゴ、カゴの転送が指示され、合計６セル出力したときの状態を示す。ＶＣ間公平キュー４６０の先頭の単位カゴはこの時点で空になり、その単位カゴおよび単位カゴセル数は消滅する。必然的に出力ポート表の先頭単位カゴがこの消失した単位カゴを指していることはない。次に、図４０を参照して、出力ポート選択スケジューラ４３２について説明する。
【０４６９】
出力ポート選択スケジューラ４３２に入力する、出力ポート毎のユニキャスト出力待ちセルとマルチキャスト出力待ちセルをセル選択部４７０が選択して出力ポート選択スケジューラ４３２から出力する。セル選択部４７０の選択の候補となるセルは、出力待ちセルのうち許可されたセルである。
【０４７０】
ユニキャストセルは、ユニキャストセル出力許可信号生成部４７１が出力するユニキャストセル出力許可信号により出力が許可される。
【０４７１】
ユニキャストセル出力許可信号生成部４７１には、バックプレッシャ信号と非常用バックプレッシャ信号が入力する。
【０４７２】
バックプレッシャ信号は出力ポート毎である。また非常用バックプレッシャ信号は対応するバックプレッシャ信号が予め定まっている。図２５の場合は、非常用バックプレッシャ信号はＳＥ２から出力しており、そのＳＥ２の出力リンクに接続する出力バッファＯＢからのバックプレッシャ信号に対応している。
【０４７３】
バックプレッシャ信号が出力禁止を示している時、ユニキャストセル出力許可信号はその出力ポートのセルの出力を許可しない。非常用バックプレッシャ信号が出力禁止を示している場合は、その非常用バックプレッシャ信号に対応するバックプレッシャ信号が全て出力禁止を示しているものと見なして出力を許可しない。
【０４７４】
マルチキャストセルは、マルチキャストセル出力許可信号生成部４７２が出力するマルチキャストセル出力許可信号により出力が許可される。
【０４７５】
マルチキャストセル出力許可信号生成部４７２には、ユニキャストセル出力許可信号とマルチキャストセル用クラス多重化ＦＩＦＯ４３６の先頭のセルの出力ポート情報が入力する。
【０４７６】
マルチキャストセル出力許可信号生成部４７２は、マルチキャストセルの出力ポートが全て（同時にでなくてもよい）許可されたかどうかを監視する。どれかの出力ポートが許可されていない場合はマルチキャストセル出力許可信号を出力禁止とする。マルチキャストセルの全ての出力ポートが許可された時、最後に許可された出力ポートのユニキャストセル出力許可信号が出力可能を示している時間はマルチキャストセルの出力を許可する。その時間内にそのマルチキャストセルがセル選択部４７０により選択されなかった場合、およびマルチキャストセルがセル選択部４７０により選択され出力して新しいマルチキャストセルの出力ポート情報が到着した場合は、再び最初から出力ポートが全て許可されたかどうかを監視する。
【０４７７】
セル選択部４７０は、こうして出力が許可された出力待ちセルを公平に選択する。
【０４７８】
上述したように、マルチキャストセルはその出力ポートの全てのバックプレッシャ信号が同時に出力を許可していなくても出力される。すなわち、そのマルチキャストセルの出力時には、そのセルの出力ポートのバックプレッシャ信号のいくつかが出力禁止を示している可能性がある。この様な状況においてもＳＥ２のバッファが溢れないように低優先セル非常用バックプレッシャ信号が有効に作用する。
【０４７９】
上述の構成においては、低優先セル非常用バックプレッシャ信号は出力禁止を示した場合、対応する出力ポート行きのユニキャストセルおよびマルチキャストセルの両方の出力を禁止する。他の構成としては、マルチキャストセル出力許可信号生成部４７２において、ある出力ポートが一度許可されても低優先セル非常用バックプレッシャ信号が出力禁止を指示した時に許可を取り消す処理を行うなどとしてもよい。また、簡単には、低優先非常用バックプレッシャ信号が出力禁止と指示した場合は、全ての低優先マルチキャストセルの出力を禁止する構成でもよい。
【０４８０】
本発明の入力バッファＩＢは、図１５で説明したバックプレッシャ考慮キュー監視を行なう。この監視は、バックプレッシャ信号によりバックプレッシャ識別子を更新し、その値に基づいて動作する。ユニキャストセルの出力ポート毎のバックプレッシャ識別子は出力ポート選択スケジューラ４３２のユニキャストセル出力許可信号により更新し、マルチキャストセルのバックプレッシャ識別子は出力ポート選択スケジューラ４３２のマルチキャストセル出力許可信号により更新する。
【０４８１】
次に、図４１を参照して、図２５に示したカゴスイッチに用いるカゴ管理部ＫＭについて説明する。
【０４８２】
図４１は、カゴ管理部ＫＭの構成例を示したものである。
【０４８３】
ＫＭは出力ポート毎に、
・ＡＢＲ入力セル数合計。
【０４８４】
・クラス毎に、前カゴセル数合計、カゴセル数合計、転送セル数。
【０４８５】
・クラス多重化ＦＩＦＯセル数合計。
【０４８６】
といった情報を保持し、さらに、出力ポート毎に、転送指示履歴管理部４８０、クラス選択スケジューラ４８１を具備している。
【０４８７】
ＡＢＲ入力セル数合計は、ＡＢＲクラスについて各出力ポート行きの全ＩＢの合計入力セル数である。一定時間内で積算し、その周期毎にその出力ポートとペアとなるＩＢへ伝送する。所定の一定時間に達する前にＡＢＲ入力セル数合計があるしきい値以上になった場合は割り込み的にＩＢへその旨を通知する構成でもかまわない。
【０４８８】
前カゴセル数合計は、ＩＢへ入力したセルの有無とクラスの情報より、前カゴに入力したセルの合計を加算する。またＫＭが転送を指示したクラスの前カゴセル数を全てのＩＢについて合計したもので更新する。そのクラスはＫＭの転送指示履歴管理部４８０が記憶している。
【０４８９】
カゴセル数合計は、ＫＭが転送を指示したクラスのカゴセル数を全てのＩＢについて合計したもので更新する。転送を指示したクラスはＫＭの転送指示履歴管理部４８０が記憶している。
【０４９０】
転送セル数は、ＫＭが転送を指示したクラスのクラス多重化ＦＩＦＯへの転送セル数を全てのＩＢについて合計したもので更新する。転送を指示したクラスはＫＭの転送指示履歴管理部４８０が記憶している。
【０４９１】
クラス多重化ＦＩＦＯセル数合計は、クラス多重化ＦＩＦＯセル数を全てのＩＢについて合計したもので更新する。
【０４９２】
クラス選択スケジューラ３８１は、前カゴセル数合計、カゴセル数合計、転送セル数合計、クラス多重化ＦＩＦＯセル数合計などの情報よりＩＢに転送指示を行なう。過去の転送指示の履歴は転送指示履歴管理部４８０が記憶し、またクラス選択スケジューラ４８１はその履歴を利用して上記のセル数情報を修正する。
【０４９３】
図４２、図４３、図４４に、カゴ管理部ＫＭのクラス選択スケジューラ４８１で実行するスケジューリングアルゴリズムの一例を示す。このアルゴリズムは、クラスの最大帯域を制限し最小帯域を保証しつつ優先度による優先制御を行なうものである。
【０４９４】
グローバルな変数として、現在時刻を示す変数ｎｏｗがある。各クラスｉについて、最小帯域１／Ｄi 、出力義務時刻Ｔｄi 、Ｔｄi の上限を与えるパラメタＤｘi 、および最大帯域１／Ｕi 、出力禁止時刻Ｔｕi 、Ｔｕi の下限を与えるパラメタＵｘi を設定する（図４２のステップＳ１００）。
【０４９５】
各クラスｉについて、出力すべき場合は現在時刻ｎｏｗがＴｄi ＜ｎｏｗである時であり、出力が禁止される場合は現在時刻ｎｏｗがｎｏｗ＜Ｔｕi である時である。また優先順位に従って出力すべき場合は現在時刻ｎｏｗがＴｕi ＜ｎｏｗ＜Ｔｄi である時である。Ｔｄi はその上限値を定められており、Ｔｄi ＜ｎｏｗ＋Ｄｘi である。またＴｕi はその下限値を定められており、ｎｏｗ−Ｕｘi ＜Ｔｕi である。ただしＵｘi ＞０、Ｄｘi ＞Ｄi である。
【０４９６】
初期設定は、ｎｏｗをゼロに設定し、各クラスｉに対してＴｄi をＤi −Ｕi とし、Ｔｕi をｎｏｗつまりゼロにする（図４２のステップＳ１０１）。
【０４９７】
このアルゴリズムはセル周期毎に次の処理を行なう。
【０４９８】
まず、クラスがアクティブになった時の処理を行なう。具体的にはセルが無かったクラスｉにセルが到着したとき、Ｔｄi をｎｏｗとＴｄi の大きい方に更新し、Ｔｕi をｎｏｗとＴｕi の大きい方に更新する（図４３のステップＳ１０２）。
【０４９９】
次にセルを転送してもよいかどうかを判定して（図４３のステップＳ１０３）、もしそうであれば転送クラス選択および転送クラス指示を行なう（図４３のステップＳ１０４）。
【０５００】
転送クラス選択は次のような処理である。
【０５０１】
転送すべきセルがある各クラスｉの中で、
１．Ｔｄi ＜ｎｏｗとなっているクラスがあれば、その中で最もｎｏｗ−Ｔｄi の大きいクラスを選択する（同じ値の場合は優先度で判断）。
【０５０２】
２．Ｔｄi ＜ｎｏｗとなっているクラスがなければ、Ｔｕi ＜ｎｏｗ＜Ｔｄi を満足するクラスの中から優先度の最も高いクラスを選択する。
【０５０３】
選択されたクラスをｊとすると、図４４のステップＳ１０５に進み、次のような転送クラス指示の処理を行なう。
【０５０４】
１．クラスｊの転送指示を行なう。
【０５０５】
２．Ｔｕj をｍａｘ（Ｔｕj 、ｎｏｗ−Ｕｘj ）と更新。
【０５０６】
３．Ｔｄj をＴｄj ＋Ｄj と更新。
【０５０７】
４．Ｔｕj をＴｕj ＋Ｕj と更新。
【０５０８】
５．Ｔｄj をｍｉｎ（Ｔｄj 、ｎｏｗ＋Ｄｘj ）と更新。
【０５０９】
最後に、転送セル流量モニタの処理を行なった後（図４４のステップＳ１０６）、ｎｏｗをインクリメントして（図４４のステップＳ１０７）、セル周期毎の処理を終了する。
【０５１０】
図４４のステップＳ１０６の転送セル流量モニタの処理は、クラスｊの転送セル数がｘj の時、クラスｊに関して次の処理を行なう。
【０５１１】
１．Ｔｕj をｍａｘ（Ｔｕj 、ｎｏｗ−Ｕｘj ）と更新。
【０５１２】
２．Ｔｄj をＴｄj ＋（ｘj −１）Ｄj と更新。
【０５１３】
３．Ｔｕj をＴｕj ＋（ｘj −１）Ｕj と更新。
【０５１４】
４．Ｔｄj をｍｉｎ（Ｔｄj 、ｎｏｗ＋Ｄｘj ）と更新。
【０５１５】
図４３のステップＳ１０３のセルを転送指示してもよいかどうかの判定は、クラス多重化ＦＩＦＯセル数合計が、あるしきい値以下かどうかで行なう。あるしきい値とは通常は「１」である。このクラス多重化ＦＩＦＯセル数合計は転送指示履歴管理部４８０の転送指示履歴により修正された値である。
【０５１６】
図４３のステップＳ１０４における、クラスに転送すべきセルがあるかどうかの判定は、前カゴセル数合計またはカゴセル数合計のどちらか一方がゼロでないことを判定して行なう。この前カゴセル数合計とカゴセル数合計は転送指示履歴管理部４８０の転送指示履歴により修正された値である。
【０５１７】
転送指示はカゴ４４０からクラス多重化ＦＩＦＯ４３４へのセルの転送指示 （図３１の転送指示Ｔ２）である。その際に前カゴからカゴへの単位カゴの転送指示を同時に行なうかどうかの判定は、前カゴセル数合計がゼロでなく、かつ、カゴセル数合計があるしきい値以下かどうかを判定して行なう。あるしきい値とは通常は１である。この前カゴセル数合計とカゴセル数合計は転送指示履歴管理部４８０の転送指示履歴により修正された値である。
【０５１８】
本アルゴリズムは、Ｄi を大きな数に設定することにより、最小保証帯域をゼロに近付けることができる。例えば全てのクラスのＤi を大きな数に設定すれば全てのクラスを完全優先で優先制御することができる。
【０５１９】
また、クラスのひとつを、優先度は最も低いが最小保証帯域を持つＩＣ （Ｉｄｌｅ Ｃｅｌｌ）クラスとすることにより、出力ポートの使用率を制御することができる。ＩＢはＩＣクラスの転送指示があった場合にアイドルセルをクラス多重化ＦＩＦＯへ挿入する（このＩＢはひとつだけでよい）。
【０５２０】
アイドルセルは他のセルと同様にセルスイッチの出力ポートに向けて交換され、そこでＵｎａｓｓｉｇｎｅｄ Ｃｅｌｌに置き換えられる。ＫＭは、ＩＣクラスはいつも転送すべきセルがある状態と考えスケジューリングを行なえば良い。
【０５２１】
ところで、図４２〜図４４に示したアルゴリズムでは説明を簡単にするために、変数ｎｏｗ、Ｔｄi 、Ｔｕi といった時刻を示す変数は、表現できる値が上限を持たないとしている。実装時にはこれらの変数は有限のビット長を持つレジスタなどで表現するため長時間経過すると同じ時刻が循環して現われる。アルゴリズムを正常に動作させるためには次のようなことを行なえば良い。これらの周期をＭaxとする。Ｍaxは十分大きい必要がある。
【０５２２】
このとき、ｘ：＝ｆ（ｘ）などの計算は、
ｘ：＝ｆ（ｘ ） ｍｏｄ Ｍax
と置き換える。つまりＭaxでモジュロをとる。また、ｙ＜ｚの比較演算は、
（ｚ＜ｙ−Ｍax／２）ｏｒ（（ｙ＜ｚ）ａｎｄ（ｚ＜ｙ＋Ｍax／２））
に置き換え比較する。
【０５２３】
例えば、ｎｏｗ：＝ｎｏｗ＋１という計算は、
ｎｏｗ：＝（ｎｏｗ＋１） ｍｏｄ Ｍax
と置き換える。Ｔｄi ＜ｎｏｗという比較演算は、
（now ＜Tdi −Max/2) or ((Tdi ＜now) and (now ＜Tdi ＋Max/2)) に置き換え比較すれば良い。
【０５２４】
時刻の変数は周期的に監視し、必要に応じてｎｏｗからＭax／２以上離れ過ぎないように調整を行なうことが必要であるが、Ｍaxを大きくとることによって監視の周期を長くとることができ、実装が容易となる。
【０５２５】
さらに、他のクラス選択スケジューリングとしては次のようなものを有効である。
【０５２６】
すでに説明したように、ＣＧ毎（ＶＣ毎）に設定された重みに従ってＶＣ間公平キューイングを行ったセルバッファ装置は、入力バッファＩＢのＣＧテーブル（図３０）またはＶＣテーブルのＮx に重みを書き込む。
【０５２７】
ここでは、クラス選択スケジューリングを併用することによって、そのクラスに設定されているＶＣ毎の重みを係数倍できることを説明する。
【０５２８】
クラスＡ、クラスＢがあり、クラスＡに設定されているあるＶＣの重みＮxaとし、クラスＢに設定されているあるＶＣの重みをＮxbとする。このとき双方のクラスに出力待ちセルが存在するときにクラス選択スケジューリングにより単位カゴの転送指示回数をクラスＸとクラスＹでＲa 対Ｒb の比になるようにスケジューリングすることにより、それぞれの重みを Ｎxa×Ｒa 、Ｎxb×Ｒb と係数倍することが可能である。３クラス以上の場合も同様である。所望の比になるように、スケジューリングを行うアルゴリズムとして例えば、ＳＣＦＱ（Ｓｅｌｆ−Ｃｌｏｃｋｅｄ Ｆａｉｒ Ｑｕｅｕｅｉｎｇ）などが知られている。
【０５２９】
具体的な例で説明する。例えば、ＶＣ１からＶＣ７の７本のＶＣに重みをそれぞれ１．２４、３．７２、２．１８、９３４、５６２、１３７０、４３６０に設定したいとする。クラスＡにＶＣ１、２を設定し、Ｎx をそれぞれ１．２４、３．７２とする。クラスＢにＶＣ３を設定し、Ｎx を２．１８とする。クラスＣにＶＣ４、５を設定し、Ｎx をそれぞれ９．３４、５．６２とする。クラスＤにＶＣ６、７を設定し、Ｎx をそれぞれ１．３７、４．３６とする。単位カゴの転送指示回数を出力待ちセルが存在するクラス間でクラスＡ：クラスＢ：クラスＣ：クラスＤ＝１：１：１００：１０００の比になるようにクラス選択スケジューリングを行えば、目的の重み１．２４：３．７２：２．１８：９３４：５６２：１３７０：４３６０でセルが出力ポートに多重化される。この方法はＮx の値として大きな数値を設定するとＶＣ間公平キューイングのセル遅延揺らぎが増大してしまうという現象を回避する効果がある。
【０５３０】
図４２〜図４４に示したようなクラス選択スケジューリングのアルゴリズムでは、各クラスの転送セル流量をモニタしていた。これを利用して階層的なクラス選択スケジューリングを行うことが可能である。
【０５３１】
クラスＡ１、Ａ２、Ａ３、…からなるクラス群Ｇa と、別のクラスＢ１、Ｂ２、Ｂ３、…からなるクラス群Ｇb とがあるとき、出力待ちセルが存在するクラス群間で転送セル流量の比をＲa 対Ｒb と設定してクラス選択スケジューリングを行う。クラス群が３以上の場合も同様である。各クラス群内のクラス選択スケジューリングと、クラス群間の選択スケジューリングとは独立である。
【０５３２】
これにより、あるクラス群間の剰余帯域は、そのクラス群内のクラスのみが使用することになり、別のクラス群が使用できることを防止できる。別のクラス群がこの剰余帯域を使用できるのは、あるクラス群の出力待ちセルが一つも存在しない場合だけである。この様な階層的なクラス選択スケジューリングは。例えば、企業毎にクラス群を割り当てるなどの応用が考えられる。
【０５３３】
５．２ 優先制御およびＶＣ間公平キューイングを行うセルスイッチのセル数修正方法
次に、優先制御およびＶＣ間公平キューイングを行うセルスイッチ（カゴスイッチ）（図２５、図２９、図３１）のカゴ管理部ＫＭにおけるセル数の修正方法を図４５を参照して説明する。
【０５３４】
修正の原理は、図１９、図２０などを用いて説明したカゴスイッチの場合も同じ方法でセル数を修正することにより優先制御の性能や出力ポートのスループットの向上などを実現することができる。
【０５３５】
本発明のセル数修正方法の一応用例として、図４５に示すカゴスイッチに適用する。カゴスイッチでは、管理部３０１がクラスｉの前カゴ（Ｂpi）へ転送を指示すると、そのクラスの前カゴのセルがカゴ（Ｂki）へ転送されるとともに、その一部がクラス多重化ＦＩＦＯ（Ｂm ）へ転送される。管理部３０１がクラスｉのカゴからクラス多重化ＦＩＦＯへ転送を指示すると、そのクラスのカゴのセルがクラス多重化ＦＩＦＯへ転送される。
【０５３６】
図４５の様に各セルバッファのセル数情報および遅延時間を定める。
【０５３７】
Ｈpiは転送指示Ｉpiにより前カゴからカゴへ転送されるＨＯＬ数、Ｈpmi は同じく転送指示Ｉpiにより前カゴからクラス多重化ＦＩＦＯへ転送されるＨＯＬセル数である。
【０５３８】
ここで一例として、各遅延時間の値が等しい場合について考える。つまり、ＤＯp ＝ＤＩk ＝ＤＯk ＝ＤＩm ＝Ｄｉpm＝Ｄ、および、ＤＴpm＝ＤＴkmとする。またｐ＝［−Ｄ、０）とする。このとき、クラスｉの前カゴとカゴの修正されたセル数（Ｎ′pi、Ｎ′ki）、およびクラス多重化ＦＩＦＯの修正されたセル数 （Ｎ′m ）は次のように計算できる。
【０５３９】
【数７】

【０５４０】
５．３ 第１０の実施形態に係るセルスイッチの説明の続き
図４６に、カゴスイッチの入力バッファＩＢとカゴ管理部ＫＭとの接続例を示す。
【０５４１】
ここでは、例えば、クラス数を６２クラス、セルスイッチサイズを１６入力１６出力とする。
【０５４２】
クラス番号は、｛０、１、２、…、６０、６１、ＵＣ、ＩＣ｝と６ビットにコーディングする。
【０５４３】
クラスＵＣは非割り当てセル（Ｕｎａｓｓｉｇｎｅｄ Ｃｅｌｌ）、ＩＣはアイドルセル（Ｉｄｌｅ Ｃｅｌｌ）を示し、これらの使い方は以下に記述する。
【０５４４】
前カゴセル数、カゴセル数、クラス多重化ＦＩＦＯセル数は、｛０、１、２、…、１３、１４、１５以上｝と４ビットにコーディングする。
【０５４５】
入力バッファＩＢからカゴ管理部ＫＭへの転送情報を以下に示す。
【０５４６】
（１）入力セル 出力ポート毎に、入力したセルについて（ユニキャストの場合はひとつの出力ポートについてのみ出力する）、
・入力セルの有無とクラス…６ビット
（入力セルがない場合はクラスＵＣを送信する）
（３）転送指示クラス 出力ポート毎に転送の指示クラスについて、
・転送後の前カゴセル数…４ビット
・転送後のカゴセル数…４ビット
・クラス多重化ＦＩＦＯへの転送セル数…２ビット
（最大でユニキャストとマルチキャストの２セルが転送される）
（４）クラス多重化ＦＩＦＯ 出力ポート毎にユニキャストのみの、
・クラス多重化ＦＩＦＯセル数…４ビット
合計すると、ひとつの出力ポートに関する情報は２０ビットである。
【０５４７】
カゴ管理部ＫＭから全ての入力バッファＩＢへ同報する転送情報を以下に示す。
【０５４８】
（２）出力ポート毎に、
・前カゴからカゴへ単位カゴの転送指示（下記のクラスについて）…１ビット
・カゴからクラス多重化ＦＩＦＯへセルの転送指示と、指示クラス…６ビット
（転送指示をしない場合はＵＣクラスを指定。ＩＣクラスが指定された場合はＩＢはアイドルセルを転送（挿入）する。アイドルセルは他のクラスのセルと同様に出力ポートへ交換転送され、セルスイッチからの出力時にＵｎａｓｓｉｇｎｅｄ Ｃｅｌｌに置き換えられるスループット調整用のセルである。）
合計すると、ひとつの出力ポートに関する情報は７ビットである。
【０５４９】
ＫＭは、ＡＢＲトラヒック制御のため出力ポート毎に、対応するＩＢへ次の信号を送信する。
【０５５０】
（５）全ＩＢの入力セルのうち、各出力ポート行きのＡＢＲ入力セル数…５ビット
（１６入力１６出力のセルスイッチの場合）
ひとつの出力ポートに関する情報は５ビットである。
【０５５１】
図４６は、カゴ管理部ＫＭをふたつのＬＳＩにて実現する構成例を示したものである。ふたつのＬＳＩのうち一方は出力ポート＃１から＃８を管理し、もう一方は出力ポート＃９から＃１６を管理する。
【０５５２】
ＩＢからＫＭへの転送情報（前述の（１）（３）（４））は、１出力ポートあたり２０ビットであるから、８ポート分で１６０ビットである。高速差動伝送を２ペア用いてパラレル伝送を行なえば１セル周期に８０ビットの伝送速度でよい。
【０５５３】
ＫＭからＩＢへの同報情報（前述の（２））は、１出力ポートあたり７ビットであるから、８ポート分で５６ビットである。通常の伝送ドライバを用いて、８本のパラレル伝送を行なえば１セル周期に７ビットの伝送速度でよい。
【０５５４】
ＫＭからＩＢへのＡＢＲトラヒック制御のための情報（前述の（５））は、１出力ポートあたり５ビットである。
【０５５５】
セル伝送速度が６２２Ｍｂｐｓであるセルスイッチを考えても、これらの伝送速度は現在の技術において十分実現可能である。
【０５５６】
ＩＢはＫＭへセル数情報をＬＳＢ（最下位桁）から伝送することにより、セル数の加算の回路規模を少なくすることができる。加算回路は全てのＩＢから伝送されてくるセル数情報を（出力ポート毎クラス毎に）下位桁から順に加算することができるためである。より具体的には、加算回路は入力した桁の数字とそれまでに計算した下位桁からの桁上がりの和を計算して、加算結果のその桁の値を得ることができる。加えて次の桁の計算のための桁上がりを保持する。
【０５５７】
ＩＢからＫＭへの信号の中にクラス多重化ＦＩＦＯセル数がある。バックプレッシャ付きセルスイッチが出力ポート毎の蓄積セル数（図２５の出力バッファＯＢのセル数）を出力できる場合には、ＫＭは、クラス多重化ＦＩＦＯセル数の代わりにこの出力ポート毎蓄積セル数を用いても良い。
【０５５８】
これは、図２のクラス間の優先制御を行なうセル多重化装置や、図７のＶＣ間公平キューイングを行なうセル多重化装置と同じ効果を持つ。
【０５５９】
図４７に、ＡＢＲサービスを実現するための情報の経路を示す。
【０５６０】
図４７は、ポート＃１からポート＃Ｎに入力するＡＢＲクラスのセルが、バックプレッシャ付きセルスイッチ４００によりポート＃ｉに交換多重化される部分について特に抜き出して示してある。実際は全ての出力ポートに関して、この図の＃ｉと同じ構成になっている。
【０５６１】
ＡＢＲサービスは、セルスイッチの出力ポートに使用可能な帯域があれば、その帯域をＡＢＲクラスのＶＣで公平に分配して使用するサービスクラスである。トラヒック制御には受信端末から送信端末へ伝送されるＲＭセルを用いる。
【０５６２】
セルスイッチ４００は、出力ポート＃ｉにおいてＡＢＲが使用可能な帯域を知っており、それと現在のＡＢＲの入力トラヒックとの比（または差）を知ることにより、送信端末に対してトラヒック制御を行なうことができる。現在のＡＢＲトラヒックは図４７に示したポート＃ｉ行きの入力セル数の一定周期毎の合計から知ることができる。入力セル数から入力帯域を求め、これが出力ポートにおいてＡＢＲが使用可能な帯域を越えていれば過負荷であるから、ポート＃ｉに入力するＲＭセルにＶＣの帯域を減らす指示を書き込めばよい。逆に、ポート＃ｉ行きの入力セル数から求めた入力帯域が、出力ポートにおいてＡＢＲが使用可能な帯域を下回っていれば、低負荷であるから、ポート＃ｉに入力するＲＭセルにＶＣの帯域を増やす指示を書き込めばよい。入力帯域と出力帯域の比または差を知ることにより、過負荷、低負荷の程度を知ることができ、細やかな制御を行なうことが可能である。
【０５６３】
この処理により輻輳に陥る確率は少なくなるが、さらにＩＢにおいてキュー長を監視して輻輳を検出した場合はＥＦＣＩをマークしたり、ＲＭセルを書き換えたりすることにより、より安全にトラヒックを制御することが可能である。特にマルチキャストの場合は、入力帯域が出力帯域より小さくとも過負荷となる可能性があり、その場合はキュー長監視によるトラヒック制御が重要になる。
【０５６４】
このように、第１０の実施形態に係るカゴスイッチは、ＶＣ間公平キューイングを行なうため、キュー長監視によるトラヒック制御においてもＶＣ間で公平な帯域分配を実現することが可能である。
【０５６５】
【発明の効果】
以上説明したように、本発明のクラス間の優先制御を行なうパケット転送装置（第１、第２の実施形態（請求項１、２、３、４、））によれば、制御部（クラス管理部）が複数の入力バッファ全体の状況を把握して（少なくとも全体の状況を把握していればよいが、個々の入力バッファ毎に把握していても構わない）指示を出すため、各入力バッファのクラス毎の蓄積状況の違いによりクラス間の優先関係が崩れてしまうことが生じず、また、入力ポートの数すなわち入力バッファの数が増えても容易にクラス間の優先制御を実現できる。
【０５６６】
また、複数の入力バッファにまたがってＶＣ（フロー）間公平キューイングをするために、例えば、制御手段が全ての入力バッファの全てのＶＣ（フロー）について、その入力ポート番号とＶＣ番号、パケットの到着状況、出力状況等を把握してパケットの出力順序を制御するのでは、装置構成が複雑になり、スループットの向上が難しい。そこで、本発明のパケット転送装置（第３、第４、第５の実施形態（請求項５、６））によれば、あるフェーズ（その時間的長さは不定）内で出力されるべきパケット集合（カゴ）という概念を導入し、このパケット集合に入れるパケットの選択と、このパケット集合に入っているパケットのみを出力する（その他のパケットは出力が許可されない）という処理を各入力バッファが分担し、パケット集合に新たなパケットを入れるタイミングを指示する処理をカゴ管理部が分担することにより、例えば、入力バッファ方式のセルスイッチにおいて、ＶＣ（フロー）間公平キューイングを容易に実現できる。
【０５６７】
また、本発明のパケット転送装置（第６、第７の実施形態（請求項７、８））によれば、制御手段（バッファポインタ管理部）がパケットが入力されたときに複数の集合への振り分けが行われており、パケットを出力するときには１つの集合に属するポインタを出すだけで済むので、例えば設定すべきＶＣ数が増えても高速にＶＣ（フロー）間公平キューイングのための出力すべきパケットの選択が実現できる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態に係るクラス間の優先制御を行なうセル多重化装置の構成例を示した図。
【図２】本発明の第２の実施形態に係るクラス間の優先制御を行なうセル多重化装置の他の構成例を示した図。
【図３】出力バッファの他の構成例を示した図。
【図４】出力バッファのさらに他の構成例を示した図。
【図５】本発明の第３の実施形態に係るＶＣ毎ＦＩＦＯを備えた出力バッファ型セル多重化装置の構成例を示した図。
【図６】本発明の第４の実施形態に係る：ＶＣ間公平キューイングを行なうセル多重化装置の構成例を示した図。
【図７】本発明の第５の実施形態に係るＶＣ間公平キューイングを行なうセル多重化装置の構成例を示した図。
【図８】本発明の第６の実施形態に係るセルグループＦＩＦＯを用いるセルバッファ装置の構成例を示した図。
【図９】本発明の第７の実施形態に係るセルグループＦＩＦＯを用いるセルバッファ装置の構成例を示した図。
【図１０】第６の実施形態に係るセルグループＦＩＦＯのポインタチェーンによるデータ構造例を説明するための図。
【図１１】第６の実施形態に係るセルグループＦＩＦＯのポインタチェーンによるデータ構造例を説明するための図で、空きセルグループチェーンの構成を示している。
【図１２】第７の実施形態に係るセルグループＦＩＦＯのポインタチェーンによるデータ構造例を説明するための図。
【図１３】第７の実施形態に係るセルグループＦＩＦＯのポインタチェーンによるデータ構造例を説明するための図で、空きセルグループチェーンの構成を示している。
【図１４】パケットグループを用いたフロー間公平キューイングを説明するための図。
【図１５】パケットグループを用いたフロー間公平キューイングを用いたパケットバッファ装置の動作を説明するための図。
【図１６】本発明の第８の実施形態にかかるバックプレッシャ考慮キュー監視を説明する図である。
【図１７】第８の実施形態に係るバックプレッシャ考慮キュー監視部を持つセルバッファ装置の構成例を示した図。
【図１８】第８の実施形態に係るバックプレッシャ考慮キュー監視アルゴリズムを示したフローチャート。
【図１９】本発明の第９の実施形態に係る遅延を考慮したセルバッファ装置の構成例を示した図。
【図２０】遅延を考慮したセル数情報の修正方法の基本原理を説明するための図。
【図２１】セル数修正方法の他の基本原理を説明するための図。
【図２２】図２１のセル数修正方法に用いる基本的な関数ｆ（）を説明するための図。
【図２３】図２１のセル数修正方法に用いる基本的な関数ｇ（）を説明するための図。
【図２４】図２１のセル数修正方法に用いる基本的な関数Ｓｃ（）を説明するための図。
【図２５】本発明の第１０の実施形態に係るカゴスイッチの全体の構成例を示した図。
【図２６】図２５の出力バッファの構成例を示した図。
【図２７】図２５の１段目単位スイッチの構成例を示した図。
【図２８】図２５の２段目単位スイッチの構成例を示した図。
【図２９】図２５の入力バッファの構成例を示した図。
【図３０】入力バッファのキューイング処理を説明するための図。
【図３１】図２５の入力バッファのカゴ管理部とのインタフェースを示した図。
【図３２】図２９のクラス毎マルチキャストセル管理部の動作を説明するための図。
【図３３】図２９のクラス毎マルチキャストセル管理部の動作を説明するための図。
【図３４】図２９のクラス毎マルチキャストセル管理部の動作を説明するための図。
【図３５】図２９のクラス毎マルチキャストセル管理部の動作を説明するための図。
【図３６】図２９のクラス毎マルチキャストセル管理部の動作を説明するための図。
【図３７】図２９のクラス毎マルチキャストセル管理部の動作を説明するための図。
【図３８】図２９のクラス毎マルチキャストセル管理部の動作を説明するための図。
【図３９】図２９のクラス毎マルチキャストセル管理部の動作を説明するための図。
【図４０】図２９の出力ポート選択スケジューラの構成例を示した図。
【図４１】図２５のカゴ管理部の構成例を示した図。
【図４２】図４１のカゴ管理部のクラス選択スケジューラで実行する、最大帯域を制限し最小帯域を保証するスケジューリングアルゴリズムの具体例を示したフローチャート。
【図４３】図４１のカゴ管理部のクラス選択スケジューラで実行する、最大帯域を制限し最小帯域を保証するスケジューリングアルゴリズムの具体例を示したフローチャート。
【図４４】図４１のカゴ管理部のクラス選択スケジューラで実行する、最大帯域を制限し最小帯域を保証するスケジューリングアルゴリズムの具体例を示したフローチャート。
【図４５】セル数情報の修正方法の応用例であるカゴスイッチの動作を説明するための図。
【図４６】図２５の入力バッファとカゴ管理部との接続の具体例を示した図。
【図４７】ＡＢＲサービスのための情報の経路の具体例を示した図。
【図４８】従来のＵＢＲサービスにおける不公平な帯域割り当てについて説明するための図。
【図４９】従来のクラス間の優先制御を行うセル多重化装置の構成を説明するための図。
【図５０】従来の入力バッファを持つセル多重化装置の構成を説明するための図。
【図５１】従来のＶＣテーブルの検索が必要なセルバッファ装置の構成を説明するための図。
【図５２】図５０に示すような従来の入力バッファを持つセル多重化装置における入力バッファのキュー長の変化について説明するための図。
【図５３】従来の優先制御を行うセル多重化装置の構成を説明するための図。
【符号の説明】
１０…入力バッファ、１１…出力バッファ、１２…クラス管理部、２１２、２２２…カゴ管理部、２３０、２４０…バッファポインタ管理部、２８２…キュー監視部、３０２…転送指示履歴、ＫＭ…カゴ管理部、４００…バックプレッシャ付きセルスイッチ。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a cell multiplexing device and a cell buffer device in an ATM communication network, for example.
[0002]
In addition, since a plurality of cell multiplexers are stacked in the cell switch, the configuration of the cell multiplexer of the present invention can be applied to the cell switch as a configuration corresponding to one output port of the cell switch. is there.
[0003]
The cell buffer device of the present invention is applicable not only to cells but also to general buffer devices.
[0004]
Furthermore, the present invention can be applied not only to an ATM communication network but also to a packet switching network.
[0005]
[Prior art]
Currently, research on ATM (Asynchronous Transfer Mode) communication systems is being actively conducted by researchers of communication technologies around the world. In the ATM communication system, information is exchanged by a fixed-length packet called a cell. In the ATM communication system, cell switching by hardware in the switch node enables high-speed cell exchange, and the information transfer capability per unit time can exceed that of an existing communication network.
[0006]
In the ATM communication method, a plurality of connections (Virtual Connection: VC) are logically set in one physical transmission line by identification information called VPI (Virtual Path Identifier) and VCI (Virtual Channel Identifier) in a cell header. Can do. In each switch node in the network, a route is determined in advance for each VC, and the switch node obtains an outgoing route to output a cell from the connection identifiers VPI and VCI of the cell. Since the VPI and VCI are uniquely assigned in the physical transmission path between the switch nodes, the switch node has the ability to rewrite the values of the VPI and VCI of the passing cell.
[0007]
Until now, VCs whose quality has been guaranteed in ATM networks have been centered on CBR (Con-stant Bit Rate) or VBR (Variable Bit Rate) connections. A CBR connection is a VC that transmits traffic that is known in advance with a constant cell transmission rate (also referred to as a cell rate or bandwidth; the number of transmission cells per unit time), and a VBR connection is a cell transmission rate that is not constant. In this VC, the traffic characteristics such as the maximum value (peak rate) and the average value (average rate) are known in advance.
[0008]
Basically, when a plurality of VCs are multiplexed on a single physical transmission line while maintaining sufficient quality, the sum of the peak rates of all VCs should be less than or equal to the bandwidth of the physical transmission line. . This method is called peak rate allocation. When only the CBR connection is assigned the peak rate, sufficiently high utilization efficiency of the physical transmission path can be achieved. In the case of the VBR connection, the use efficiency of the physical transmission path cannot be increased by the peak rate allocation. Therefore, a technique for increasing the utilization efficiency while maintaining the quality by using the statistical multiplexing effect is being studied from the known traffic characteristics.
[0009]
However, when considering ATM communication between computers, the nature of traffic characteristics such as the average rate cannot be predicted in advance, and the burst nature of transmitting a large number of cells instantaneously but not transmitting any cells when not transmitting. There is a nature called. For this reason, it is difficult to increase the network utilization efficiency while guaranteeing quality as in CBR and VBR. In other words, if the quality of data transferred between computers is guaranteed by peak rate allocation or the like, the use efficiency of the network is remarkably reduced. If the statistical multiplexing effect such as VBR is used, the traffic burstiness is increased. If a large number of cells arrive at the output port of the switch at the same time and the buffer amount of the cell switch is not sufficient, cell discard due to buffer overflow occurs. In addition, when cell discard occurs, retransmission occurs in units of packets made up of a plurality of cells, thereby reducing the effective throughput.
[0010]
Therefore, in recent years, a service class called ABR (Available Bit Rate) has been proposed in which flow control is performed between a terminal and a switch node to guarantee cell transfer quality (particularly quality related to cell discard) and to improve network utilization efficiency. Study is progressing. The ABR connection requests that the switch node greets the transmitting terminal to send a cell before the occurrence of the cell congestion when the switch node through which the ABR connection is likely to be congested. Traffic control information to the terminal is mainly performed using cells called RM cells (resource management cells). There is a non-negligible delay time in traffic control from a switch node to a transmission terminal in ABR. Therefore, it is necessary to mount a large-capacity buffer in the cell switch so that the cell is not discarded until the traffic control works effectively.
[0011]
As another service class of CBR, VBR, and ABR, there is a service class called UBR (Unspecified Bit Rate). This class does not require detailed declaration of the traffic characteristics output by the terminal to the network. Instead, the network is a class of so-called Best Effort service that makes no guarantees about its transfer quality.
[0012]
As described above, since the data between computers has a burst property, it is considered that a large capacity cell buffer must be installed in the cell switch in order to satisfy the cell discard rate of the UBR connection. ing.
[0013]
Fortunately, for traffic between computers, there are many cases in which the requirements regarding the transfer delay time and delay fluctuation are not as strict as those of CBR and VBR. Although a cell transmission delay time and delay fluctuation are increased by mounting a buffer with a large capacity in a cell switch, it is considered that there are many applications that can tolerate this.
[0014]
Particularly in the case of ABR and UBR services, it is considered that a means for avoiding network congestion is required. As one of congestion avoiding means, there is a method called EFCI (Explicit Forward Congestion Indication). There is an EFCI bit in the cell header that writes the congestion experience of the cell, and the cell switch in the network marks the EFCI according to the congestion status. The terminal can avoid congestion by using the information.
[0015]
Next, inter-VC fair queuing will be described.
[0016]
First, the fair queuing between VCs required for fault tolerance in the ABR service will be described.
[0017]
The ABR service is established when the transmitting terminal controls cell transmission according to traffic control information from the network. If a certain terminal breaks down (or deliberately) and ignores traffic control information from the network, it may be difficult to escape from network congestion.
[0018]
Such a problem can be solved by performing fair queuing between VCs in a cell multiplexing apparatus or cell switch to realize fair cell multiplexing scheduling between VCs and fair buffer allocation between VCs. By performing fair queuing between VCs, the interaction between VCs can be minimized, and even if there is a VC that ignores traffic control information, only that VC can be congested and the impact on other VCs can be reduced. Because.
[0019]
Also, fair queuing between VCs is required for fairness in UBR service.
[0020]
FIG. 48 shows an example of unfair bandwidth allocation in the UBR service. In this example, there are four terminals A, B, C, and D in the network, and one file server, each of which is a cell switch (or cell multiplexer) X, Y, Z and links 1, 2, 3, 4, 5, 6, 7.
[0021]
Here, assuming that each cell switch multiplexes cells regardless of the number of VCs set as input links, each cell switch treats input ports equally. For example, when the cells from link 2 and link 3 are multiplexed to link 1, cell switch X treats both links equally. Each is given a bandwidth of 0.5.
[0022]
Considering the same, the bandwidth finally given to each terminal is 0.5 for terminal A, and 0.125 for terminals C and D, the smallest. If it is ideal that all terminals have equal access to the file server, this is far from ideal.
[0023]
Furthermore, when the network is congested, the network transmits EFCI information so as to reduce the bandwidth to the terminal. At this time, if there are a terminal that faithfully follows the EFCI information and a terminal that ignores the EFCI information in the network, only the terminal that is faithful to the EFCI suppresses cell transmission. There is also a problem that it will be secured.
[0024]
These problems are due to the cell switch treating each input link equally, ignoring the number of VCs multiplexed on the input link. When the cell switch performs fair queuing between VCs and distributes bandwidth according to the number of VCs, each terminal can access the file server fairly.
[0025]
Next, a cell multiplexing apparatus that performs priority control between classes will be described.
[0026]
FIG. 49 shows a configuration of a conventional cell multiplexing apparatus that performs priority control between classes.
[0027]
FIG. 49 shows a cell multiplexing apparatus that multiplexes cells input from N input ports into one output port.
[0028]
The output buffer stores cells for each class in a cell storage unit for each internal class, and the cell selection unit selects and outputs cells to the output port according to the priority of the class.
[0029]
A back pressure signal is generated by comparing the number of cells stored in each storage unit of the output buffer with a threshold value. The input buffer is also provided with a cell storage unit for each class, and transfers cells to the output buffer in accordance with the class priority from the classes permitted to be output by the back pressure signal.
[0030]
In this configuration, since it is necessary to provide a plurality of cell storage units for each class in the output buffer, there is a drawback that it becomes difficult to realize the output buffer when the number of classes increases. In particular, the input speed of the output buffer must be N times the speed of the input port (N is the number of input ports). If the number of classes and the number of input ports is large, such complex functions cannot be realized. It was difficult.
[0031]
Considering FIG. 49 as a part related to each output port of the cell switch, the same problem exists for a cell switch having a buffer at the input port.
[0032]
Next, the cell multiplexing apparatus will be described.
[0033]
Problems of the cell multiplexing apparatus having an input buffer as shown in FIG. 50 will be described.
[0034]
FIG. 50 shows a cell multiplexing apparatus that multiplexes cells input from N input ports into one output port.
[0035]
The output buffer temporarily accumulates cells from the input port and outputs cells according to the speed of the output port.
[0036]
A back pressure signal is generated by comparing the number of cells stored in the output buffer with a threshold value. The input buffer has one queue corresponding to the output port, and transfers cells to the output buffer only when output is permitted by the back pressure signal.
[0037]
Since such a cell multiplexing apparatus treats each input buffer fairly regardless of the number of set VCs, there is a problem in fault tolerance in the ABR service and fairness in the UBR service.
[0038]
If FIG. 50 is considered as a part related to each output port of the cell switch, the same problem exists also in the cell switch having a buffer at the input port.
[0039]
Next, inter-VC fair queuing will be described.
[0040]
FIG. 51 shows the configuration of a FIFO for each VC, which is a method for realizing fair queuing between VCs.
[0041]
51 notifies the buffer pointer management unit of cell connection identification information input from the input link, obtains a write pointer indicating the cell write position from the buffer pointer management unit, temporarily stores the cell in the cell buffer, This is a cell buffer device that reads a cell from a cell buffer based on a read pointer indicating a read cell from a buffer pointer management unit and outputs the cell to an output link. The buffer pointer management unit manages a buffer pointer indicating the position of the accumulated cell on the cell buffer.
[0042]
The buffer pointer management unit manages the buffer pointer for each VC using the VC table. FIG. 51 shows a management method using a widely known pointer chain.
[0043]
When a cell is input, one buffer pointer is taken out from the head of the empty chain as a write pointer, and is attached to the end of the VC chain corresponding to the input cell. When outputting a cell, the VC storing the cell is selected fairly, and the leading buffer pointer is read out and taken out as a pointer. Round robin is known as a method for selecting a VC fairly at the time of cell output.
[0044]
In order to select a VC by round robin, it is necessary to search on the VC table in order from the next to the previously output VC whether there is a cell stored in the buffer. In the case of a large number of searches, it is necessary to perform almost all the VCs in one cell cycle, but the number of VCs to be set may reach several thousand or more, which is difficult to realize.
Next, queue length monitoring will be described.
[0045]
FIG. 52 shows an example of a change in the queue length of the input buffer in the cell multiplexing apparatus having the input buffer as shown in FIG.
[0046]
The horizontal axis represents time, the vertical axis represents the queue length of the input buffer, and the bottom represents the back pressure signal. When the back pressure signal indicates output prohibition (Tup), the output throughput from the input buffer is zero, so the queue length increases at the buffer input rate (Ri). When the back pressure signal indicates that output is possible, the output throughput from the input buffer is maximum and the normal queue length decreases.
[0047]
In this way, the queue length vibrates in synchronization with the back pressure signal. Conventionally, when a cell arrives at a buffer, if the queue length exceeds a threshold value, the input cell is not accepted but discarded, and if not, it is widely accepted. This method has no problem with a normal buffer, but becomes a problem when the output of the buffer is controlled by the back pressure signal in this way. The maximum value of the queue length is determined by the input rate (Ri) and the time (Tup) when the back pressure signal instructs to inhibit output. In particular, the output inhibition time (Tup) of the back pressure signal is set to other input buffers. This is because it is greatly influenced by input traffic and the like.
[0048]
In the case of a buffer device controlled by a back pressure signal, simply discarding cells by comparing them with the queue length and threshold value makes it difficult to stably discard cells because the cell discards are sensitively affected by external conditions. Met. The same problem exists when judging congestion from the queue length.
[0049]
Next, a cell buffer device that performs priority control will be described.
[0050]
FIG. 53 shows the configuration of a cell buffer device that performs priority control.
[0051]
There is a class 1 cell storage unit that temporarily stores low-priority cells with respect to delay, and a class 2 cell storage unit that temporarily stores high-priority cells. Each output is multiplexed by a class multiplexing FIFO. Is done. The class management unit inputs the class 2 cell storage unit cell number Na and the class multiplexed FIFO cell number Nb, and gives a transfer instruction to one of the classes. Upon receiving the transfer instruction, the class cell storage unit transfers only one cell to the class multiplexing FIFO.
[0052]
In order to improve the priority control performance of the cell buffer device, it is necessary to reduce the number of cells stored in the class multiplexing FIFO. However, in order not to reduce the throughput, the class multiplexing FIFO is not emptied. It is necessary to instruct transfer so that (= no underflow). Furthermore, when either one of the cell storage units is empty, if there is an instruction for transfer to the empty cell storage unit (referred to as an empty instruction), an underflow may occur. Therefore, it is necessary to give a transfer instruction to the cell storage unit in which the storage cell exists.
[0053]
From the above policy, the condition for the class management unit to instruct the transfer to the class 2 cell storage unit is as follows:
(Nb ≤ 1) and (Na > 1)
Given in. The transfer instruction to the class 1 cell storage unit is
(Nb ≤ 1) and (Na == 0)
It is.
[0054]
Here, transmission of cell number information from the cell storage unit for each class or class multiplexing FIFO to the class management unit, transmission of transfer instruction information from the class management unit to the class cell storage unit, and cell storage for each class Consider a case where there is a delay time in cell transfer from the cell to the cell multiplexing FIFO. Conventionally, the following problems existed at this time.
[0055]
Due to these delay times, the class manager cannot accurately determine whether or not the class multiplexing FIFO underflows. Therefore, the number of cells in the class multiplexed FIFO is set as a condition for preventing underflow by comparing with a larger threshold value corresponding to the delay time. As a result, the average queue length of the class multiplexing FIFO is increased and the priority control performance is degraded.
[0056]
In addition, it is impossible to accurately determine that the class 2 cell storage unit is emptied due to delay in transmission of the high priority class 2 cell storage unit information. Therefore, if it is empty but it is not empty, it will give an error, and it will give an empty instruction, or if it is not empty, it will be empty, and the class 1 cell with low priority will take precedence over the class 2 cell with high priority. I was giving instructions to output. As a result, there is a problem that the throughput of the cell buffer device is lowered and the performance of the priority control function is lowered.
[0057]
The problems with the cell buffer device performing priority control in FIG. 53 have been described above. This problem can occur not only in cell buffer devices that perform such priority control, but also in various cell buffer devices.
[0058]
In other words, in the cell buffer device in which the management unit instructs the transfer of cells between a plurality of buffers, the transmission of buffer information to the management unit, the transmission of transfer instruction information from the management unit to the buffer, and the transmission of cells between the buffers are delayed. When time exists, there is a problem that the performance and throughput of the cell buffer device are lowered.
[0059]
[Problems to be solved by the invention]
As described above, the conventional cell multiplexing apparatus has the following first and second problems.
[0060]
First, since it is necessary to provide a plurality of cell storage units for each class in the output buffer, there is a drawback that it becomes difficult to realize the output buffer when the number of classes increases. In particular, the input speed of the output buffer must be N times the speed of the input port (N is the number of input ports). If the number of classes and the number of input ports is large, such complex functions cannot be realized. It was difficult.
[0061]
Next, since each input buffer is treated fairly regardless of the set number of VCs, there is a problem in fault tolerance in the ABR service and fairness in the UBR service.
[0062]
Further, the conventional cell buffer device has the following third and fourth problems.
[0063]
First, in order to select a VC by round robin, it is necessary to sequentially search the VC table for whether or not there is a cell accumulated in the buffer from the next output VC. In the case of a large number of searches, it is necessary to perform almost all the VCs in one cell cycle, but the number of VCs to be set may reach several thousand or more, which is difficult to realize.
[0064]
On the other hand, in recent years, an algorithm as described in “Efficient Fair queuing Defect Round Robin” (pp. 231-242, ACM SIGCOMM '95, August 1995) has been proposed. Since the algorithm called DRR proposed in this document manages VCs that store cells using the concept of active lists, it is not necessary to search the VC table when cells are output. Therefore, even if the number of VCs to be set increases, selection of cells to be output for fair VC queuing can be realized at high speed. However, in this DRR algorithm, since packets are classified and stored for each VC, an amount of packets corresponding to the weight value set for each VC is output at one time, and the burstiness of the output traffic is extremely high. There was a drawback that it would be expensive.
[0065]
Next, in the case of a buffer device controlled by a back pressure signal, the method of determining cell discard simply by comparing the queue length with a threshold value is sensitive to cell discard due to external conditions. Disposal was difficult. The same problem exists when judging congestion from the queue length.
[0066]
Furthermore, the cell buffer device in which the management unit instructs cell transfer between a plurality of buffers has the following fifth problem. That is, if there is a delay time in the transmission of buffer information to the management unit, the transmission of transfer instruction information from the management unit to the buffer, and the transmission of cells between buffers, the performance and throughput of the cell buffer device will be reduced. There was a problem.
[0067]
The present invention has been made in view of the above points, and an object of the present invention is to provide a cell multiplexing apparatus that performs priority control between classes that is easy to realize even when the number of input ports is large. is there.
[0068]
Another object of the present invention is to provide a cell multiplexing apparatus capable of performing per-VC fair queuing for realizing fault tolerance in an ABR service and fairness in a UBR service.
[0069]
Another object of the present invention is to provide a cell multiplexing apparatus that performs inter-VC fair queuing that can be easily realized without depending on the upper limit of the number of settable VCs.
[0070]
Still another object of the present invention is to provide a cell multiplexing apparatus in which the queue length monitoring result is not easily affected by external conditions, and stable queue length monitoring is easy.
[0071]
Another object of the present invention is to transmit buffer information to the management unit, to transmit transfer instruction information from the management unit to the buffer, between buffers when the management unit instructs cell transfer between a plurality of buffers. It is an object of the present invention to provide a cell multiplexing apparatus in which performance and throughput are not lowered as in the prior art even when there is a delay time in cell transmission.
[0072]
[Means for Solving the Problems]
The packet transfer apparatus according to the present invention (claims 1 to 4) includes a plurality of input buffers for temporarily storing input packets, a control means for controlling these input buffers, and a packet output from each input buffer. A packet transfer apparatus comprising at least one output port for transferring
Each of the input buffers is
Accumulation means for each class that temporarily accumulates input packets for each class;
Output means for outputting packets of the class instructed by the control means from the storage means to the output port;
The control means includes
The storage status of all of the plurality of input buffers of the storage means is grasped for each class, a class to which a packet is to be output is determined based on the storage status, and an instruction including designation of the determined class is given to the plurality of input buffers By sending to
Each input buffer is used for the control unit to grasp the status of the entire plurality of input buffers (at least to know the overall status, but may be grasped for each individual input buffer). The priority relationship between classes does not collapse due to the difference in the storage status of each class, and priority control between classes can be easily realized even if the number of input ports, that is, the number of input buffers is increased.
[0073]
The packet transfer apparatus according to the present invention (Claims 5 and 6) includes a plurality of input buffers, control means for controlling the input buffers, and at least one output port for transferring packets output from the input buffers. A packet transfer apparatus comprising:
Each of the input buffers is
Storage means for temporarily storing input packets;
In response to an instruction from the control unit, a selection unit that selects a packet to be output from the storage unit to the output port in the next phase;
Output means for outputting the packet selected by the selection means to the output port;
The control means includes
By grasping the output status of the packet selected by the selection means in the entire plurality of input buffers, and instructing the plurality of input buffers to select a new packet based on the output status,
Introduce the concept of a packet set (cage) to be output within a phase (the time length is indefinite), select packets to be included in this packet set, and output only the packets in this packet set Each input buffer shares the process (output of other packets is not permitted), and the control unit (basket management unit) shares the process of instructing the timing of inserting a new packet into the packet set. In a buffered cell switch, fair queuing between VCs can be easily realized.
[0074]
The packet transfer apparatus according to the present invention (claims 7 and 8) includes a buffer for temporarily storing input packets, a control means for controlling the buffer, and packet transfer for transferring packets output from the buffer. A device,
The control means includes
Management means for managing the packets accumulated in the buffer by dividing them into a plurality of sets;
Distribution means for distributing the packets input to the buffer to any one of the plurality of sets so as to be fair among the flows to which the packets belong;
Instruction means for instructing the buffer to output a packet belonging to one of the plurality of sets managed by the management means;
Thus, when a packet is input by the control means (buffer pointer management unit), distribution to a plurality of sets is performed, and when a packet is output, it is only necessary to output a pointer belonging to one set. Therefore, even when the number of VCs to be set increases, selection of a packet to be output for the fair queuing between VCs can be realized. Further, the operation of the selection means of claim 5 can be realized by the instruction means of the present invention. Furthermore, the present invention can be used as an output buffer when performing fair queuing between VCs in an output buffer type cell switch.
[0077]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0078]
0. Definition of terms
Hereinafter, terms used for describing the embodiments of the present invention will be defined.
[0079]
(1) A packet is a concept including a fixed-length cell, and can be understood as a superordinate concept of a cell. In the following description, a packet is not limited to a variable length or a fixed length. Further, even when the description is limited to the cell, it is merely for the purpose of simplifying the description and is not particularly limited thereto.
[0080]
(2) Difference between packet (cell) multiplexer and packet (cell) buffer device:
Packet buffer device: One or more input ports, one or more output ports, and one or more buffers are provided. Packets input from the input ports are temporarily stored in the buffers as necessary, and then sent to the output ports. Output device. In particular, a packet buffer device that outputs a packet to an output port corresponding to a destination is called a packet switch.
[0081]
Packet multiplexer: A packet multiplexer that has a single packet output port is called a packet multiplexer (multiple packet multiplexers with a common input port when the packet buffer is divided into output ports) Can be seen as a stack of devices). In the following description, the description of the packet multiplexing device can be easily applied to the packet buffer device.
[0082]
(3) Packet transfer device: Includes both a packet buffer device and a packet multiplexing device which is a kind thereof. Also, in the following description, the case where a multiplexing device or a buffer device is described as an example is not particularly limited to this, and can be widely applied as a packet transfer device.
[0083]
1. Inter-class priority control (first embodiment, second embodiment)
First, an embodiment of a cell multiplexing apparatus that performs priority control between classes according to the present invention will be described.
[0084]
1.1 First embodiment
FIG. 1 shows a configuration example of a cell multiplexing apparatus that performs priority control between classes according to the first embodiment.
[0085]
The cell multiplexer of FIG. 1 is provided corresponding to each of the input ports # 1 to #N, and a plurality of input buffers 10 that temporarily store cells input from the input ports # 1 to #N, An output buffer 11 that multiplexes cells output from the input buffer 10 and outputs them to an output port, and a class management unit 12 that manages all the input buffers are provided.
[0086]
The input buffer 10 includes a class cell storage unit 13 (class 1 cell storage unit 13a, class 2 cell storage unit 13b, class 3 cell storage unit 13c) that stores input cells for each class (class 1 to class 3). A class multiplexing FIFO 14 that multiplexes cells output from the cell storage unit 13 and outputs them to the output buffer 11 is provided.
[0087]
The class management unit 12 obtains the number of cell storage units for each class of the cell storage unit 13 and the number of class multiplexed FIFO cells of the class multiplexed FIFO 14, determines a transfer class instruction from a predetermined algorithm, Broadcast to the input buffer 10.
[0088]
The cell storage unit 13 of the class designated by the transfer class instruction broadcast to the input buffer 10 transfers the cell to the class multiplexing FIFO 14, and the class multiplexing FIFO 14 backs up according to the congestion state in the output buffer 11. The cell is output to the output buffer 11 according to the control of the pressure signal.
[0089]
The cell storage unit 13 for each class is usually composed of a FIFO (First In First Out) memory.
[0090]
Although FIG. 1 shows the case of three classes (class 1 to class 3), the first embodiment works effectively regardless of the number of classes.
[0091]
Further, when FIG. 1 is considered to be a part related to each output port of the cell switch, the first embodiment can be applied to the cell switch.
[0092]
The output buffer 11 shown in FIG. 1 is composed of a single-stage FIFO 15. However, the output buffer 11 may take any form as long as it can guarantee that the cells of the class multiplexed FIFO 14 can be output to the output port within a finite time in any situation.
[0093]
For example, the configuration may be such that the cell of the class multiplexed FIFO 14 is arbitrated and output to the output port without having any buffer. Further, for example, the configuration shown in FIG. 3 or FIG.
[0094]
The output buffer 16 shown in FIG. 3 has a plurality of FIFO stages (two stages in FIG. 3), and a back pressure signal is connected to the preceding FIFO.
[0095]
That is, in the output buffer 16 of FIG. 3, input links # 1 to #N provided corresponding to the respective outputs of the input buffer 10 are connected to a plurality of FIFOs 18 on the input side (previous stage). The back pressure signal output from the subsequent FIFO 19 in accordance with the congestion state is connected to each of the plurality of FIFOs 18 in the previous stage, and is connected to each of the FIFOs 18 in the previous stage. A back pressure signal output from each according to the congestion state is connected to each of the plurality of class multiplexing FIFOs 14.
[0096]
The output buffer 17 shown in FIG. 4 has a plurality of FIFOs (two stages in FIG. 4), as in FIG. The difference from FIG. 3 is that the queue length information of a plurality of FIFOs 18 on the input side (or the queue length information of all FIFOs) may be transferred to the back pressure generation unit 20, and the back pressure generation unit 20 A pressure signal is generated and broadcast to all input links.
[0097]
For example, all the queue lengths are summed and compared with a threshold value, and if the threshold value is exceeded, input to the output buffer is prohibited by the back pressure signal. The back pressure generation unit 20 may exist in the class management unit 12.
[0098]
According to the cell multiplexing apparatus that performs priority control between classes according to the first embodiment, it is not necessary to identify a class in an output buffer that requires high throughput, and therefore it can be easily realized. The input buffer needs to manage cells for each class. However, since the throughput required for the input buffer is low, implementation is easy.
[0099]
The configuration of the cell multiplexing apparatus in FIG. 1 will be described in more detail.
[0100]
The number of cell storage units by class input to the class management unit 12 may be the sum of the number of cell storage units by class of all input buffers 10 for each class. Further, the number of class multiplexed FIFO cells may be the sum of all the input buffers 10.
[0101]
The total calculation may be performed inside the class management unit 12 or may be performed outside the class management unit 12.
[0102]
In the cell number information, the class management unit 12 determines a relatively small threshold value and magnitude. Whether the threshold value is a fixed value or a dynamically changing value depends on the algorithm of the class management unit 12. If the threshold value is a fixed value, the comparison result is used instead of the number of cells. You may input into a class management part. Alternatively, if any value greater than a certain value does not affect the processing of the class management unit 12, the value greater than that value may be encoded and input into one code. For example, with 4 bits, the number of cells is (0000) = 0, (0001) = 1, (0010) = 2, (0011) = 3,..., (1101) = 13, (1110) = 14, (1111) = The encoding may be performed in 16 stages of 15 or more. Thereby, there is an advantage that the input information to the class management unit 12 can be compressed and the mounting becomes easy.
[0103]
By handling the total number of cells, the implementation of the class management unit 12 can be simplified. Since the transfer class instruction also broadcasts the same information to all the input buffers, the class management unit does not need to recognize the input buffers individually. Therefore, there is an advantage that even if the number of input ports is increased, the essential difficulty of mounting does not change.
[0104]
The algorithm by which the class manager 12 determines the transfer instruction is, for example, as follows.
[0105]
1. Based on the number of class multiplexed FIFO cells, it is determined whether the class multiplexed FIFO does not underflow, and a transfer instruction is issued so as not to underflow only when it is determined that there is a possibility of underflow. Underflow refers to a state in which the number of class multiplexed FIFO cells becomes zero, and the cells in the cell storage unit for each class that should originally be output cannot be output effectively.
[0106]
2. Based on the number of cells per class, the class in which cells are stored in the input buffer 10 is determined as a transfer instruction candidate.
[0107]
3. When the transfer instruction can be performed, the class having the highest priority among the classes that are candidates for the transfer instruction is obtained, and the transfer of the class is instructed.
[0108]
The class management unit 12 issues a transfer class instruction without directly considering the state of the output buffer and the back pressure signal. Therefore, the cell transfer throughput according to the transfer class instruction may exceed the cell output throughput from the input buffer 10, and the class multiplexing FIFO 14 is prepared to temporarily absorb the difference. By knowing the number of class multiplexed FIFO cells, the class management unit 12 controls the cell transfer throughput according to the transfer class instruction so that it does not exceed the cell output throughput from the input buffer 10 continuously for a long time.
[0109]
The class management unit 12 knows the total number of cells (the number of transfer cells for each class) of the cells actually transferred from the cell storage unit 13 for each class to the class multiplexing FIFO 14 in all the input buffers 10, so that more detailed inter-class Priority control can be performed.
[0110]
In this case, the algorithm by which the class management unit 12 determines the transfer instruction is, for example, as follows.
[0111]
1. Based on the number of cells in the class multiplexed FIFO, it is determined whether or not the class multiplexed FIFO will underflow, and only when it is determined that there is a possibility of underflow, a transfer instruction is given so as not to cause an underflow. Underflow refers to a state in which the number of class multiplexed FIFO cells becomes zero and the cells of the class-by-class cell storage unit 13 that should originally be output cannot be output effectively.
[0112]
2. Based on the number of cells per class, the class in which cells are stored in the input buffer is determined as a transfer instruction candidate.
[0113]
3. A class that obtains a throughput that is equal to or higher than a predetermined throughput for each class, based on the number of transfer cells for each class, lowers the priority for instructing transfer according to the degree. Or it is not a candidate for transfer instruction.
[0114]
4). From the number of transfer cells for each class, a class that obtains only a throughput equal to or lower than the throughput predetermined for each class increases the priority for instructing transfer according to the degree.
[0115]
5. When the transfer instruction can be performed, the class having the highest priority among the classes that are candidates for the transfer instruction is obtained, and the transfer of the class is instructed.
[0116]
1.2 Second Embodiment
Next, a second embodiment will be described.
[0117]
FIG. 2 shows another configuration example of the cell multiplexing apparatus that performs priority control between classes according to the second embodiment.
[0118]
The cell multiplexing apparatus of FIG. 2 is provided corresponding to each of the input ports # 1 to #N, and a plurality of input buffers 100 for temporarily storing cells input from the input ports # 1 to #N; An output buffer 111 that multiplexes cells output from the input buffer 100 and outputs them to an output port, and a class management unit 112 that manages all the input buffers 100 are provided.
[0119]
The input buffer 100 stores the input cells for each class (class 1 to class 3), for each class, cell storage unit 113 (class 1 cell storage unit 113a, class 2 cell storage unit 113b, class 3 cell storage unit 113c). And a class multiplexing FIFO 114 that multiplexes the cells output from the cell storage unit 113 and outputs the multiplexed data to the output buffer 111.
[0120]
The class management unit 112 obtains the number of cells in each cell storage unit 113 and the number of cells in the output buffer of the cell storage unit 113, determines a transfer class instruction from a predetermined algorithm, and broadcasts it to all the input buffers 100. To do.
[0121]
The cell storage unit 113 of the class designated by the transfer class instruction broadcast to the input buffer 100 transfers the cell to the class multiplexing FIFO 114, and the class multiplexing FIFO 114 backs up according to the congestion state in the output buffer 111. The cell is output to the output buffer 111 according to the control of the pressure signal.
[0122]
The cell storage unit 113 for each class is usually composed of a FIFO.
[0123]
FIG. 2 shows the case of three classes (class 1 to class 3), but the second embodiment works effectively regardless of the number of classes.
[0124]
If FIG. 2 is considered as a part regarding each output port of the cell switch, the second embodiment can be applied also to the cell switch.
[0125]
The output buffer 111 of FIG. 2 may take any form as long as it can guarantee that the cell of the class multiplexed FIFO can be output to the output port within a finite time in any situation.
[0126]
For example, the configuration shown in FIG. 4 may be used.
[0127]
In this case, the back pressure generation unit 20 may exist in the class management unit 112. The number Nm of cells in the output buffer is added by the back pressure generation unit 20 and output to the class management unit 112 in FIG.
[0128]
According to the cell multiplexing apparatus that performs priority control between classes according to the second embodiment, since it is not necessary to identify a class in an output buffer that requires high throughput, it can be easily realized. The input buffer 100 needs to manage cells for each class, but is easy to implement because the throughput required for the input buffer 100 is low.
[0129]
The configuration of the cell multiplexing apparatus in FIG. 2 will be described in further detail.
[0130]
The number of cell storage units per class input to the class management unit 112 may be the sum of the number of cell storage cells per class of all the input buffers 100 for each class.
[0131]
The total calculation may be performed inside the class management unit 112 or may be performed outside the class management unit 112.
[0132]
In the cell number information, the class management unit 112 determines a relatively small threshold value and magnitude. Whether the threshold value is a fixed value or a dynamically changing value depends on the algorithm of the class management unit 112. If the threshold value is a fixed value, the comparison result is used instead of the number of cells. You may input into the class management part 112. FIG. Alternatively, if any value above a certain value does not affect the processing of the class management unit 112, the value above that value may be encoded into a single code and input. For example, with 4 bits, the number of cells is (0000) = 0, (0001) = 1, (0010) = 2, (0011) = 3,..., (1101) = 13, (1110) = 14, (1111) = The encoding may be performed in 16 stages of 15 or more. Thereby, there is an advantage that the input information to the class management unit can be compressed, and the mounting becomes easy.
[0133]
By handling the total number of cells, the implementation of the class management unit 112 can be simplified. Since the transfer class instruction also broadcasts the same information to all the input buffers 100, the class management unit 112 does not need to recognize the input buffers 100 individually. Therefore, there is an advantage that even if the number of input ports is increased, the essential difficulty of mounting does not change.
[0134]
For example, the class management unit 112 determines the transfer instruction as follows.
[0135]
1. Based on the number of cells in the output buffer 111, it is determined whether the output buffer 111 does not underflow, and only when it is determined that there is a possibility of underflow, a transfer instruction is given so as not to underflow. Underflow refers to a state in which the number of output buffer cells becomes zero and the cells in the class-by-class cell storage unit 113 that should originally be output cannot be effectively output.
[0136]
2. Based on the number of cells in each class cell storage unit, a class in which cells are stored in the input buffer 100 is determined as a transfer instruction candidate.
[0137]
3. When the transfer instruction can be performed, the class having the highest priority among the classes that are candidates for the transfer instruction is obtained, and the transfer of the class is instructed.
[0138]
The class management unit 112 issues a transfer class instruction by directly considering the state of the output buffer 111. Therefore, if a sufficient buffer amount is prepared for the output buffer 111, the back pressure signal does not suppress the cell output from the input buffer, and the class multiplexing FIFO 114 is basically unnecessary. By knowing the number of cells in the output buffer, the class management unit 112 controls the cell transfer throughput according to the transfer class instruction so as not to exceed the cell output throughput from the output buffer 111 continuously for a long time.
[0139]
Thus, the back pressure signal to the input buffer 100 and the class multiplexing FIFO 114 are basically unnecessary, but they work effectively when the buffer amount of the output buffer 111 is not sufficient. If these are not provided, the buffer amount of the output buffer 111 can be reduced as compared with the case without them.
[0140]
The class management unit 112 knows the number of cells (the number of transferred cells for each class) obtained by totaling the cells actually transferred from the class-by-class cell storage unit 113 to the class multiplexing FIFO 114 in all the input buffers. Priority control can be performed.
[0141]
In this case, the algorithm by which the class management unit 112 determines the transfer instruction is, for example, as follows.
[0142]
1. Based on the number of cells in the output buffer 111, it is determined whether the output buffer 111 does not underflow, and only when it is determined that there is a possibility of underflow, a transfer instruction is given so as not to underflow. Underflow refers to a state in which the number of output buffer cells becomes zero and the cells in the class-by-class cell storage unit 113 that should originally be output cannot be effectively output.
[0143]
2. Based on the number of cells in each class cell storage unit, a class in which cells are stored in the input buffer 100 is determined as a transfer instruction candidate.
[0144]
3. A class that obtains a throughput that is equal to or higher than a predetermined throughput for each class, based on the number of transfer cells for each class, lowers the priority for instructing transfer according to the degree. Or it is not a candidate for transfer instruction.
[0145]
4). From the number of transfer cells for each class, a class that obtains only a throughput equal to or lower than the throughput predetermined for each class increases the priority for instructing transfer according to the degree.
[0146]
5. When the transfer instruction can be performed, the class having the highest priority among the classes that are candidates for the transfer instruction is obtained, and the transfer of the class is instructed.
[0147]
1.3 Advantages of the cell multiplexing apparatus according to the first and second embodiments
As described above, according to the cell multiplexing apparatus that performs priority control between classes of the first and second embodiments, it is not necessary to identify a class in an output buffer that requires high throughput. There is an advantage that it is easy to realize even when the number of input ports is large.
[0148]
2. Fair queuing (third to seventh embodiments)
Next, an embodiment of a cell multiplexing apparatus that performs inter-VC fair queuing according to the present invention will be described.
[0149]
2.1 Third Embodiment (Output Buffer Type Cell Multiplexer)
FIG. 5 shows a configuration example of a cell multiplexing apparatus that performs fair VC queuing according to the third embodiment.
[0150]
The cell multiplexing apparatus of FIG. 5 is called an output buffer type and is provided corresponding to each of the input ports # 1 to #N. The cell input from the input ports # 1 to #N is multiplied by the number of input ports N times. A plurality of speed conversion circuits 200 for speed conversion to the above speed, and an output buffer 201 for temporarily accumulating cells output from the speed conversion circuit 200 and outputting them to an output port.
[0151]
The output buffer 201 selects and outputs a cell output from each of a VC separation unit 201a that separates input cells for each VC, a plurality of FIFOs 201b for each VC provided for each VC, and a plurality of FIFOs 201b for each VC. A cell selection unit 201c that outputs to a port is provided.
[0152]
The per-VC FIFO 201b must have a large capacity in order to obtain a sufficiently good cell discard rate. In addition, due to the non-blocking condition, the input speed of the per-VC FIFO 201b must be N times the input port. When the input port speed is high or the number of input ports is large, a high-speed and large-capacity memory that satisfies such a throughput is not cheap, and a complex queue for each VC while satisfying such a throughput. Management is also difficult.
[0153]
2.2 Fourth Embodiment (Cell Multiplexer Using the Concept of “Kago”)
Next, a fourth embodiment will be described.
[0154]
FIG. 6 shows a configuration example of a cell multiplexing apparatus using a concept called a basket according to the fourth embodiment.
[0155]
The cell multiplexing apparatus shown in FIG. 6 is provided corresponding to each of the input ports # 1 to #N, and includes a plurality of input buffers 210 that temporarily store cells input from the input ports # 1 to #N. And an output buffer 211 that multiplexes the cells output from each input buffer 210 and outputs them to an output port, and controls the cell output of each input buffer 210 by a back pressure signal according to the congestion state in the output buffer 211.
[0156]
This cell multiplexing apparatus includes a basket management unit 212 that manages an output-permitted cell set.
[0157]
Among the cells stored in the input buffer 210, a set of cells permitted to be output (output permitted cell set) is called a basket. A cell to be output from the input buffer 210 is selected from the basket 213.
[0158]
The basket management unit 212 inputs the number of cells included in the basket 213, determines a cell transfer instruction to the basket 213 by a predetermined algorithm, and broadcasts it to all the input buffers 210.
[0159]
The input buffer 210 adds a set 214 of cells to be output by the same time among the cells stored in the input buffer 210 other than the cell determined as the cage 213 according to the cell transfer instruction.
[0160]
If FIG. 6 is considered as a part regarding each output port of the cell switch, the fourth embodiment can be applied also to the cell switch.
[0161]
The output buffer 211 in FIG. 6 may take any form as long as it can guarantee that a car cell can be output to the output port within a finite time in any situation.
[0162]
For example, a configuration may be employed in which the cell of the basket 213 is arbitrated and output to the output port without having any buffer. Further, for example, the configuration shown in FIG. 3 or 4 may be used.
[0163]
In FIG. 4, the back pressure generation unit 20 may exist in the basket management unit 212.
[0164]
According to the cell multiplexing apparatus that performs inter-VC fair queuing according to the fourth embodiment, an output buffer that requires high throughput has a simple configuration and can be easily realized. The input buffer needs to manage cells by a cage, but since the throughput required for the input buffer is low, it is easy to implement.
[0165]
The configuration of the cell multiplexing apparatus in FIG. 6 will be described in further detail.
[0166]
The number of cells in the car that is input to the car management unit 212 may be the sum of the number of cells in the car of all the input buffers 210.
[0167]
The total calculation may be performed inside the basket management unit 212 or may be performed outside the basket management unit 212.
[0168]
The number-of-cells information is determined by the basket management unit 212 as a relatively small threshold value and magnitude. Whether the threshold value is a fixed value or a dynamically changing value depends on the algorithm of the basket management unit 212. If the threshold value is a fixed value, the comparison result is used instead of the number of cells. You may input into the basket management part 212. FIG. Alternatively, if any value above a certain value does not affect the processing of the basket management unit 212, the value above that value may be encoded and input into one code. For example, with 4 bits, the number of cells is (0000) = 0, (0001) = 1, (0010) = 2, (0011) = 3,..., (1101) = 13, (1110) = 14, (1111) = The encoding may be performed in 16 stages of 15 or more. Thereby, there is an advantage that the input information to the basket management unit 212 can be compressed and the mounting becomes easy.
[0169]
By handling the total number of cells, the implementation of the basket management unit 212 can be simplified. Since the cell transfer instruction to the car also broadcasts the same information to all the input buffers 210, the car management unit 212 does not need to recognize the input buffers 210 individually. Therefore, there is an advantage that even if the number of input ports is increased, the essential difficulty of mounting does not change.
[0170]
An example of an algorithm for determining the cell transfer instruction to the basket 213 by the basket management unit 212 is as follows.
[0171]
That is, it is determined whether or not the number of cells in the basket 213 does not underflow based on the number of cells in the basket Nk, and a transfer instruction is issued so as not to underflow only when it is determined that there is a possibility of underflow. The underflow is a state in which the number of cells in the basket Nk becomes zero, and the cells of the input buffer 210 that should originally be output cannot be output effectively.
[0172]
The input buffer 210 adds the cell set 214 to be output by the same time to the car 213 in response to the cell transfer instruction to the car 213. For example, when performing inter-VC fair queuing weighted by the value Nx set for each VC, the cells to be output by the same time are cells not included in the basket 213 in each input buffer 210 for each VC. The oldest Nx cells are collected.
[0173]
Since the transfer instruction is broadcast to all the input buffers 210, cells enter the basket 213 fairly between the VCs through the plurality of input buffers 210. By transferring the cells of the basket 213 to the output buffer 211 in preference to the cells outside the basket 213, it is possible to transfer the cells to the output buffer 211 fairly between the VCs through the plurality of input buffers 210.
[0174]
If the output buffer 211 is configured to be able to output a cell input from the basket 213 within a certain period of time, the cell transferred to the basket 213 fairly between VCs has a delay fluctuation of the time, Output from the output port.
[0175]
FIG. 6 shows, as an example, a state where two, one, and three VCs are queued in the input buffers 210 of the input ports # 1, # 2, and #N, respectively. When all VCs have the same weight, if VC fair queuing is performed, the output from each input buffer 210 needs to be a ratio of 2 to 1: 3. In the cell multiplexing apparatus of this embodiment, the number of cells in the basket 213 is 2: 1 to 3 in each input buffer according to a cell transfer instruction from the basket management unit 212 to the basket 213 that is broadcast to all the input buffers 210. As a result, the output from the output buffer also becomes a ratio of 2 to 1: 3.
[0176]
There are two methods for inputting cells into the basket 213. Here, a case will be described as an example where the oldest Nx cells (values set for each VC) are placed in the basket for each VC when transfer is instructed.
[0177]
One method is a method in which a cell input to the input buffer 210 does not enter the car 213 at first, even if the condition for entering the car 213 is satisfied. A cell is transferred to the car 213 only when cell transfer is instructed by the car management unit 212. As a result, the number of cells in the car is reduced except when the car management unit 212 instructs cell transfer.
[0178]
Another method is a method in which a cell input to the input buffer 210 is inserted into the cage 213 from the beginning when the condition for entering the cage 213 is satisfied. In other words, the VC that has transferred Nx cells to the basket 213 at the time of the transfer instruction cannot enter the cell into the basket 213 until the next transfer instruction is issued, but does not transfer any cells to the basket 213 at the time of the transfer instruction. VCs having less than Nx transfer cells or Nx transfer cells can input 213 into the basket without instructing transfer until Nx. As a result, the number of cells in the car may increase between transfer instructions, but decreases when almost all active VCs have transferred Nx cells. Note that this embodiment works effectively in either method.
[0179]
The determination of the congestion state of the cell multiplexing apparatus of the fourth embodiment may be performed by monitoring information that varies depending on traffic for each VC by a predetermined method. Based on this congestion determination, the traffic control information may be notified to the terminal for each VC.
[0180]
The fluctuating information to be monitored is, for example, the number of stored cells, the relationship between the number of input cells per fixed time and the target value, and the relationship between the time input by a certain number of cells and the target value. A VC having a large number of accumulated cells, a VC having a large number of input cells per fixed time far from the target value, and a short VC having a time of inputting a certain number of cells far from the target value are determined to be a congested VC.
[0181]
The traffic control information can be notified to the terminal by marking the EFCI in the header of the congested VC cell or rewriting the passing RM cell.
[0182]
2.3 Fifth Embodiment (Another Embodiment of Cell Multiplexing Device Using the Concept of “Kago”)
Next, a fifth embodiment will be described.
[0183]
FIG. 7 shows another configuration example of the cell multiplexing apparatus using the concept called the basket according to the fifth embodiment.
[0184]
The cell multiplexing apparatus shown in FIG. 7 is provided corresponding to each of the input ports # 1 to #N, and a plurality of input buffers 220 that temporarily store cells input from the input ports # 1 to #N. And an output buffer 221 that multiplexes the cells output from the input buffer 220 and outputs them to the output port, and controls the cell output of the input buffer 220 by the back pressure signal according to the congestion state in the output buffer 221.
[0185]
This cell multiplexing apparatus includes a basket management unit 222 that manages an output-permitted cell set.
[0186]
Of the cells stored in the input buffer 220, a set of cells permitted to be output (output permitted cell set) is called a basket. A cell to be output from the input buffer is selected from the basket 223.
[0187]
The basket management unit 222 inputs the number of cells in the output buffer, determines a cell transfer instruction to the basket 223 from a predetermined algorithm, and broadcasts it to all the input buffers 220.
[0188]
In response to the cell transfer instruction, the input buffer 220 adds to the car 223 a set of cells 224 to be output by the same time among the cells stored in the input buffer 220 other than the car 223.
[0189]
If FIG. 7 is considered as a part related to each output port of the cell switch, this embodiment can be applied to the cell switch.
[0190]
The output buffer 221 shown in FIG. 7 may take any form as long as it can guarantee that the cells of the basket 223 can be output to the output port within a finite time in any situation.
[0191]
For example, the configuration shown in FIG. 4 may be used. In this case, the back pressure generation unit 20 may exist in the basket management unit 222. The number of cells in the output buffer is added by the back pressure generation unit 20 and output to the basket management unit 222.
[0192]
According to the cell multiplexing apparatus that performs inter-VC fair queuing according to the fifth embodiment, an output buffer that requires high throughput has a simple configuration and can be easily realized. The input buffer needs to manage cells by a cage, but since the throughput required for the input buffer is low, it is easy to implement.
[0193]
The configuration of the cell multiplexing apparatus in FIG. 7 will be described in further detail.
[0194]
For the cell number information, the basket management unit 222 determines a relatively small threshold value and magnitude. Whether the threshold value is a fixed value or a dynamically changing value depends on the algorithm of the basket management unit 222. If the threshold value is a fixed value, the comparison result is used instead of the number of cells. You may input into the basket management part 222. FIG. Alternatively, if any value greater than a certain value does not affect the processing of the basket management unit 222, the value greater than that value may be encoded into a single code and input. For example, with 4 bits, the number of cells is (0000) = 0, (0001) = 1, (0010) = 2, (0011) = 3,..., (1101) = 13, (1110) = 14, (1111) = The encoding may be performed in 16 stages of 15 or more. Accordingly, there is an advantage that the input information to the basket management unit 222 can be compressed and the mounting becomes easy.
[0195]
An example of the algorithm used by the basket management unit 222 to determine a cell transfer instruction to the basket 223 is as follows.
[0196]
That is, it is determined whether or not the number of cells in the output buffer 221 does not underflow based on the number of cells in the output buffer, and a transfer instruction is issued so as not to underflow only when it is determined that there is a possibility of underflow. Underflow refers to a state in which the number of cells in the output buffer becomes zero, and the cells of the input buffer 220 that should originally be output cannot be effectively output.
[0197]
The input buffer 220 adds a set of cells 224 to be output by the same time to the car 223 in response to a cell transfer instruction to the car 223. For example, when performing inter-VC fair queuing weighted by a value Nx set for each VC, a set of cells to be output by the same time is a cell not included in the basket 223 in each input buffer. The oldest Nx cells are collected every time.
[0198]
Since the transfer instruction is broadcast to all the input buffers, cells enter the basket 223 fairly between the VCs through the plurality of input buffers. By transferring the cells of the cage 223 to the output buffer 221 with priority over the cells outside the cage, the cells can be transferred to the output buffer 221 fairly between the VCs through the plurality of input buffers 220. If the output buffer 221 is configured to be able to output a cell input from the car 223 in any time within a certain time, the cell transferred to the car 223 fairly between VCs has a delay fluctuation of that time, Output from the output port.
[0199]
FIG. 7 shows, as an example, a state where two, one, and three VCs are queued in the input buffers 220 of the input ports # 1, # 2, and #N, respectively. When all VCs have the same weight, if the fair VC queuing is performed, the output from each input buffer 220 needs to be a ratio of 2 to 1: 3.
[0200]
In the cell multiplexing apparatus of FIG. 7, the number of cells in the car is a ratio of 2 to 1: 3 in each input buffer according to the cell transfer instruction sent to the car 223 from the car management unit 222 to all the input buffers 220. As a result, the output from the output buffer 221 also has a ratio of 2 to 1: 3.
[0201]
There are two methods for inputting cells into the basket 223. Here, a case will be described as an example where the oldest Nx cells (values set for each VC) are placed in the basket for each VC when transfer is instructed.
[0202]
One method is a method in which a cell input to the input buffer 220 does not enter the cage at first even if the condition for entering the cage 223 is satisfied. A cell is transferred to the car 223 only when cell transfer is instructed by the car management unit 222. As a result, the number of cells in the basket decreases except when the basket management unit 222 instructs cell transfer.
[0203]
As another method, there is a method in which a cell input to the input buffer 220 is inserted into the cage 223 from the beginning when the condition for entering the cage 223 is satisfied. That is, the VC that has transferred Nx cells to the basket 223 at the time of the transfer instruction cannot enter the cell into the basket 223 until the next transfer instruction is issued, but does not transfer any cells to the basket 223 at the time of the transfer instruction. The VC or the VC whose number of transfer cells is less than Nx can input the input cell into the car 223 until there is no transfer instruction until Nx. As a result, the number of cells in the car may increase between transfer instructions, but decreases when almost all active VCs have transferred Nx cells. Note that this embodiment works effectively in either method.
[0204]
The determination of the congestion state of the cell multiplexing apparatus of the fifth embodiment may be performed by monitoring information that varies depending on traffic for each VC by a predetermined method. Then, the cell multiplexing apparatus may notify the traffic control information to the terminal for each VC based on this congestion determination.
[0205]
The fluctuating information to be monitored is, for example, the number of stored cells, the relationship between the number of input cells per fixed time and the target value, and the relationship between the time input by a certain number of cells and the target value. A VC having a large number of accumulated cells, a VC having a large number of input cells per fixed time far from the target value, and a short VC having a time of inputting a certain number of cells far from the target value are determined to be a congested VC.
[0206]
The traffic control information can be notified to the terminal by marking the EFCI in the header of the congested VC cell or rewriting the passing RM cell.
[0207]
2.4 Advantages of cell multiplexing apparatus according to fourth and fifth embodiments
As explained above, according to the cell multiplexing apparatus using the concept of the output permitted cell set (cage) according to the fourth to fifth embodiments, the cells to be included in the output permitted cell set are controlled. In order to adjust the output throughput of each input buffer, fair queuing between VCs can be performed, and fault tolerance in the ABR service and fairness in the UBR service can be realized.
[0208]
2.5 Sixth Embodiment (Cell Buffer Device Using Cell Group FIFO) Next, an embodiment of a cell buffer device that performs fair VC queuing according to the present invention will be described.
[0209]
FIG. 8 shows a configuration example of a cell buffer device using a cell group FIFO according to the sixth embodiment.
[0210]
8 notifies the buffer pointer management unit 230 of the connection identification information of the cell input from the input link, obtains a write pointer indicating the cell write position from the buffer pointer management unit 230, and temporarily stores the cell in the cell buffer 231. This is a cell buffer device that accumulates and reads cells from the cell buffer 231 based on a read pointer indicating a read cell from the buffer pointer management unit 230 and outputs it to an output link.
[0211]
The buffer pointer management unit 230 manages a buffer pointer indicating the position of the accumulated cell on the cell buffer 231.
[0212]
The buffer pointer management unit 230 includes a cell group FIFO 232a for FIFO management of a plurality of cell groups as a set of buffer pointers, an output waiting cell group FIFO 232b, a cell group selection unit 233, and an empty buffer pointer management unit 234.
[0213]
At the time of cell input, the buffer pointer management unit 230 obtains an empty buffer pointer from the empty buffer pointer management unit 234 and uses it as the write pointer, and the cell group selection unit 233 sets the write pointer from the connection identification information to the head of the cell group FIFO 232a. The cell group is instructed so as to enter the number determined in accordance with the predetermined weight for each VC in order from the cell group, and the cell group FIFO 232a inputs the write pointer to the instructed cell group in accordance with the cell group instruction.
[0214]
At the time of cell output, the cell group is output from the head of the cell group FIFO 232a, and a buffer pointer is further output from the cell group as the read pointer, and the read pointer is returned to the empty buffer pointer management unit 234.
[0215]
FIG. 8 shows a configuration in the case where there is a possibility that a plurality of cell groups are output from the cell group FIFO 232a and waiting for output. The cell groups output from the cell group FIFO 232a are input to the output waiting cell group FIFO 232b.
[0216]
The cell group of the output waiting cell group FIFO 232b is a cell group whose output is permitted by some management unit outside the cell buffer 231. For example, it corresponds to the car 231 in FIG.
[0217]
The read pointer is a buffer pointer output from the head cell group of the output waiting cell group FIFO 232b.
[0218]
For example, all VCs have the same weight. The cell of the first cell group of the cell group FIFO 232a is the cell at the head of the queue (except for the cells in the output waiting cell group FIFO 232b) when considering the queue of each VC. The cell in the second cell group from the top of the cell group FIFO 232a is the second cell in the queue of each VC. The same applies to the cells in the third and subsequent cell groups. When these cells are output, the cells are output in order from the first cell group of the cell group FIFO 232a, so that they are output fairly between VCs.
[0219]
When a VC cell that has not arrived at all until this time arrives at this buffer device, it is input to the first cell group of the cell group FIFO 232a, and has priority over the second and subsequent cells of the other VC queues. Is output.
[0220]
As described above, according to the cell buffer device of the sixth embodiment, it is possible to perform fair queuing between VCs while searching for cells as in the conventional example shown in FIG. There is an advantage that no operation is required.
[0221]
As a method for realizing the cell group FIFO 232a of the cell buffer device according to the sixth embodiment, for example, a pointer chain method or a ring buffer method may be considered.
[0222]
2.6 Seventh Embodiment (Another Embodiment of Cell Buffer Device Using Cell Group FIFO)
Next, a seventh embodiment will be described.
[0223]
FIG. 9 shows another configuration example of the cell buffer device using the cell group FIFO according to the seventh embodiment.
[0224]
FIG. 9 notifies the buffer pointer management unit 240 of cell connection identification information input from the input link, obtains a write pointer indicating the cell write position from the buffer pointer management unit 240, and temporarily stores the cell in the cell buffer 241. This is a cell buffer device that accumulates and reads cells from the cell buffer 241 based on a read pointer indicating a read cell from the buffer pointer management unit 240 and outputs it to the output link.
[0225]
The buffer pointer management unit 240 manages a buffer pointer indicating the position of the accumulated cell on the cell buffer 241.
[0226]
The buffer pointer management unit 240 includes a cell group FIFO 242 that performs FIFO management of a cell group that is a set of buffer pointers, a cell group selection unit 243, and an empty buffer pointer management unit 244.
[0227]
At the time of cell input, the buffer pointer management unit 240 obtains an empty buffer pointer from the empty buffer pointer management unit 244 and uses it as the write pointer, and the cell group selection unit 243 sets the write pointer based on the connection identification information to the head of the cell group FIFO 242. The cell group is instructed so as to enter the number determined in accordance with the predetermined weight for each VC in order from the cell group, and the cell group FIFO 242 inputs the write pointer to the instructed cell group according to the cell group instruction.
[0228]
At the time of cell output, a buffer pointer is output from the first cell group of the cell group FIFO 242 to be used as the read pointer, and the read pointer is returned to the empty buffer pointer management unit 244.
[0229]
In FIG. 9, the cell group waiting for output in the cell group FIFO 242 is shown as an output waiting cell group FIFO 242b.
[0230]
The cell group of the output waiting cell group FIFO 242b is a cell group whose output is permitted by some management unit outside the cell buffer 241. For example, it corresponds to the basket of FIG.
[0231]
The read pointer is a buffer pointer output from the head cell group of the output waiting cell group FIFO 242b.
[0232]
For example, all VCs have the same weight. The cell of the head cell group of the cell group FIFO 242 (that is, the cell group in the output waiting cell group FIFO 242b) is the head cell of the queue when considering the queue of each VC. The cell in the second cell group from the top of the cell group FIFO 242 is the second cell in the queue of each VC. The same applies to the cells in the third and subsequent cell groups. When these cells are output, the cells are output in order from the first cell group of the cell group FIFO 242, so that they are output fairly between VCs.
[0233]
When a VC cell that has never arrived at this time arrives at this buffer device, it is input to the first cell group of the cell group FIFO 242, and has priority over the second and subsequent cells in the other VC queues. Is output.
[0234]
As described above, according to the cell buffer device of the seventh embodiment, a search can be performed as in the conventional example shown in FIG. 51 at the time of cell input and output while being able to perform queuing fairly between VCs. There is an advantage that no operation is required.
[0235]
As a method for realizing the cell group FIFO 242 of the cell buffer device according to the seventh embodiment, for example, a pointer chain method or a ring buffer method may be considered.
[0236]
2.7 Data structure used in cell buffer device according to sixth embodiment
Next, the data structure used in the cell buffer device (see FIG. 8) according to the sixth embodiment will be described.
[0237]
10 and 11 show an example of the data structure when the buffer device described in FIG. 8 is realized by the pointer chain method.
[0238]
Broadly divided, as shown in FIG. 10, a VC table 250, a cell group FIFO 232a, an output waiting cell group FIFO 232b, an empty buffer pointer chain 251, and an empty cell group chain 252 as shown in FIG.
[0239]
The cell group FIFO 232a has cell group FIFO management data 253 for managing the cell group FIFO 232a, and the output waiting cell group FIFO 232b has output waiting cell group FIFO management data 254 for managing it.
[0240]
The cell group and empty buffer pointer chain 251 are buffer pointer chains, and the cell group FIFO 232 a and empty cell group chain 252 are chains of cell group management data 255.
[0241]
The output waiting cell group FIFO 232b has a list of pointers (Ptr1, Ptr2, Ptr3,...) Pointing to the cell group in the output waiting cell group FIFO management data 254.
[0242]
The cell group FIFO 232a and the output waiting cell group FIFO 232b may be of a ring buffer system.
[0243]
When a cell is input, it must be determined to which cell group the write pointer extracted from the empty buffer pointer chain 251 is input. Therefore, first, the corresponding area of the VC table 250 is read. In the VC table 250, Nx is the weight of the VC, Nc is the work variable, Qlen is the number of cells stored in the VC, and Ptr is a pointer to the end of the cell group in which the cells of the VC are stored.
[0244]
First, Qlen is checked to see if the VC cell is currently stored in the buffer device. If Qlen is zero, it is put in the first cell group of the cell group FIFO 232a. Even when Qlen is 1 or more, if Ptr indicates a cell group in the output waiting cell group FIFO 232b, the cell group is inserted into the first cell group of the cell group FIFO 232a.
[0245]
In other cases, 1.0 is added to Nc and compared with Nx, and if Nx is larger, it is put in the cell group pointed to by Ptr, otherwise it is put in the cell group next to the cell group pointed to by Ptr. Put in.
[0246]
Here, a procedure for updating Nc when a cell is input will be described. As described above, when a buffer pointer is input to the first cell group of the cell group FIFO 232a for the VC for the first time, Nc: = 1.0. In other cases, Nc is updated to Nc: = Nc + 1.0. As a result, if Nx > If Nc, a buffer pointer is put into the cell group. Conversely, if Nx <Nc, the buffer pointer is inserted into the cell group next to the cell group FIFO 232a, and at the same time, Nc: = Nc−Nx is rewritten (that is, 0 <Nc). < Nx).
[0247]
If it is necessary to put a buffer pointer in the cell group next to the last cell group of the cell group FIFO 232a, the cell group management data 255 is taken out from the head of the empty cell group chain 252 and placed at the end of the cell group FIFO 232a. What is necessary is just to put a buffer pointer in a cell group. In the output waiting cell group FIFO management data 254, pointers Ptr1, Ptr2, Ptr3,... Pointing to the cell groups are shift registers. The cell group indicated by Ptr1 is the head of the FIFO, and the buffer pointer output from this cell group serves as a read pointer. The read pointer is input at the end of the empty buffer pointer chain 251. When the buffer pointer of the cell group indicated by Ptr1 becomes empty, the cell group is input at the end of the empty cell group chain 252. And n > The pointer Ptr (n) is shifted to Ptr (n-1) for all n of 2, and the buffer pointer is output from the cell group indicated by the new Ptr1.
[0248]
As described above, it is necessary to determine whether or not Ptr in the VC table 250 indicates a cell group waiting for output when a cell is input. Therefore, the output waiting cell group FIFO management data 254 needs to be configured so that it can be easily searched.
[0249]
When a new cell group is transferred from the cell group FIFO 232a to the output wait cell group FIFO 232b, the number of cell groups in the output wait cell group FIFO management data 254 is incremented (m), and Ptr (m) becomes the cell group. The cell group output from the FIFO 232a is pointed to.
[0250]
Note that the cell buffer device according to the sixth embodiment can be easily applied to an input buffer using the concept of a cage as shown in FIGS. In this case, the output waiting cell group FIFO 232b corresponds to the basket. The present invention can also be applied to the output buffer shown in FIG.
[0251]
2.8 Data structure used in the cell buffer device according to the seventh embodiment
Next, the data structure used in the cell buffer device (see FIG. 9) according to the seventh embodiment will be described.
[0252]
12 and 13 show an example of the data structure when the buffer device described in FIG. 9 is realized by the pointer chain method.
[0253]
Broadly divided, as shown in FIG. 12, a VC table 260, a cell group FIFO 242, an empty buffer pointer chain 261, and an empty cell group chain 262 as shown in FIG.
[0254]
The cell group FIFO 242 includes an output waiting cell group FIFO 242b, and includes cell group FIFO management data 263 for managing the cell group FIFO 242 and output waiting cell group FIFO management data 264 for managing the output waiting cell group FIFO 242b.
[0255]
The cell group and empty buffer pointer chain 261 are buffer pointer chains, and the cell group FIFO 242 and empty cell group chain 262 are chains of cell group management data 265.
[0256]
The output waiting cell group FIFO 242b is several cell groups at the head of the cell group FIFO 242. That is, in FIG. 12, the cell group FIFO 242 from the cell group pointed to by the head pointer of the cell group FIFO management data 263 to the cell group pointed to by the tail pointer of the output queue cell group FIFO management data 264 is the output queue cell group FIFO 242.
[0257]
The cell group FIFO 242 and the output waiting cell group FIFO 242b may be of a ring buffer system.
[0258]
When a cell is input, it must be determined to which cell group the write pointer extracted from the empty buffer pointer chain 261 is input. Therefore, first, the corresponding area of the VC table 260 is read. In the VC table 260, Nx is the weight of the VC, Nc is a work variable, Qlen is the number of cells stored in the VC, and Ptr is a pointer to the end of the cell group in which the cells of the VC are stored.
[0259]
First, Qlen is checked to see if the VC cell is currently stored in the buffer device. If Qlen is zero, it is put in the first cell group of the cell group FIFO 242.
[0260]
In other cases, 1.0 is added to Nc and compared with Nx, and if Nx is larger, it is put in the cell group pointed to by Ptr, otherwise it is put in the cell group next to the cell group pointed to by Ptr. Put in.
[0261]
Here, a procedure for updating Nc when a cell is input will be described. As described above, when the buffer pointer is input to the first cell group of the cell group FIFO 242 for the VC for the first time, Nc: = 1.0. In other cases, Nc is updated to Nc: = Nc + 1.0. As a result, if Nx > If Nc, a buffer pointer is put into the cell group. Conversely, if Nx <Nc, the buffer pointer is inserted into the cell group next to the cell group FIFO 242, and at the same time, Nc: = Nc-Nx is rewritten (that is, 0 <Nc). < Nx).
[0262]
When a cell is input, if the cell group is not in the cell group FIFO 242, if it is necessary to put a buffer pointer in the cell group next to the last cell group of the cell group FIFO 242, the start of the empty cell group chain 262 The cell group management data 265 is taken out, put at the end of the cell group FIFO 242, and a buffer pointer is put into the cell group.
[0263]
The output waiting cell group FIFO management data 264 has a pointer indicating the end of the output waiting cell group FIFO 242b. The head is the same as the head cell group of the cell group FIFO management data 263.
[0264]
A buffer pointer is output from the head cell group of the output waiting cell group FIFO 242b (the same cell group as the head of the cell group FIFO), and this buffer pointer becomes a read pointer. The read pointer is input at the end of the empty buffer pointer chain 261.
[0265]
When the buffer pointer of the head cell group of the cell group FIFO 242 becomes empty, the cell group management data 265 is output from the cell group FIFO 242 and input to the end of the empty cell group chain 262.
[0266]
When a cell group is newly transferred to the output waiting cell group FIFO 242b, the pointer indicating the end of the output waiting cell group FIFO management data 264 is changed to indicate the next cell group on the cell group FIFO 242.
[0267]
Note that the cell buffer device according to the seventh embodiment can be easily applied to an input buffer using the concept of a cage as shown in FIGS. In this case, the output waiting cell group FIFO 242b corresponds to the basket. The present invention can also be applied to the output buffer shown in FIG.
[0268]
2.9 Advantages of cell buffer device according to sixth and seventh embodiments
As described above, according to the cell buffer device that performs inter-VC fair queuing according to the sixth to seventh embodiments, there is no need to search the VC table, so that the upper limit of the settable number of VCs is reached. It can be easily realized without dependence.
[0269]
2.10 Weighted fair queuing between flows
The above-described cell buffer device that performs fair queuing between VCs has been described by taking as an example the case of handling cells that are fixed-length packets. A packet buffer apparatus capable of simultaneously handling packets of different lengths can output the input packets fairly based on the weights determined for each flow as described below.
[0270]
The flow here is a set of packets identified by a certain standard as shown in the following example.
[0271]
A so-called flow in the IP network (identified by a combination of source address, source report, destination address, destination port), or VCC or VPC in the ATM network.
[0272]
Differences in IP network service classes (guaranted, controlled-load, best-effort, etc.) or ATM network service categories (CBR, VBR, ABR, etc.).
[0273]
・ Protocol differences (TCP / IP, DECnet, SNA, AppleTalk, etc.)
・ Application differences (ftp, telnet, etc.)
・ Different organizations sharing the same bucket buffer device (by company, etc.)
By treating these as different flows in the packet buffer device of the present invention, traffic can be separated from each other.
[0274]
First, general inter-flow weighted fair queuing will be described with reference to FIG. The purpose of this packet buffer device is to output packets stored in the device fairly according to the weight of the flow. The operation is easy to understand when considering a FIFO for each flow as shown in FIG. In the figure, there are three flow queues (FIFOs) of flow 1, flow 2, and flow 3, and packets of various lengths are stored in each queue. The number attached to the packet in the figure is the length of the packet in bytes.
[0275]
Processing when a packet is input to the packet buffer device is to determine a flow to which the input packet belongs and store it in a queue for each flow.
[0276]
On the other hand, it is necessary to output packets fairly between flows, and it is important to output packets in which queue and in which order. One method will be described in accordance with the situation of FIG. In order to simplify the description, the weights of the flows are assumed to be the same here. Here, the unit of fairness is assumed to be 500 bytes.
[0277]
First, a packet of 500 bytes in total including a packet having a length of 300 bytes and a packet having a length of 200 bytes is output from the head of the queue of flow 1. Next, two packets having a length of 250 bytes from the head of the queue of flow 2 are output in succession. Then, one packet having a length of 500 bytes is output from the head of the flow 3 queue. When outputting in this way, one packet of the length of each flow byte is output at this point. If such an output is made, it can be said that at this time, packets of equal 500 bytes are output from each flow, so that they are output fairly. Subsequently, it is sufficient to repeat outputting packets of 500 bytes from each flow in order from flow 1 again. In this way, packets are output fairly between flows.
[0278]
Although the above method is fair in units of 500 bytes, it is not always fair in smaller units. However, it is known that strict fairness requires a very large processing capacity for the packet buffer device, and as a practical problem, it is often judged that the above-mentioned degree of fairness is sufficient.
[0279]
In the above description, the number of flows is three. However, when the packet buffer device handles an enormous number of flows, how to search for a flow in which packets are accumulated in a queue, The issue is whether to output. The present invention solves this problem using the concept of packet groups.
[0280]
In the present invention, the queues of all flows are divided into fixed lengths as in Z, A, B, C, and D in FIG. At this time, attention is paid to that a fair packet output can be realized by outputting a packet in units of each delimiter. In the present invention, packets are grouped and managed for each of these breaks. Each group is called a packet group. A packet group includes a plurality of flow packets. As for the output of the packet, the packet of the packet group Z closest to the output side is output first, and then the packet of the packet group A is output. Further, by outputting the packets of the packet group in order of B, C, and D, the packet buffer device of the present invention can output the packets fairly between the flows.
[0281]
By the way, looking at the flow 3 of the break B in FIG. 14, a 350-byte packet is accumulated after a 400-byte packet. In the figure, the maximum number of packets belonging to the same delimiter is 500 bytes. Therefore, both a 400-byte packet and a 350-byte packet that are not divided in the packet buffer device cannot be delimited and put into B. On the other hand, if a 350-byte packet that has arrived at the packet buffer device later is not included in break B, a gap of 100 bytes will occur in break B. The handling of such a case will be described later.
[0282]
The concept of the packet group of the present invention has been described above.
[0283]
Next, an example of the packet buffer device of the present invention will be described more specifically with reference to FIG.
[0284]
The constituent elements of the present invention include a packet group, a packet group FIFO, a flow table, and an output waiting packet group.
[0285]
The packet group is a group of accumulated packets as described above. In FIG. 15, A, B, C, and D are packet groups. Packets belonging to each packet group are ordered, and the packet group has a FIFO structure.
[0286]
In the present invention, as shown in FIG. 15, a packet group which is a FIFO of a packet is further managed by the FIFO. This FIFO of the packet group is called a packet group FIFO.
[0287]
The flow table stores information for each flow. In the flow table, Nx is a set value of the weight of the flow, Nc is a work variable, an accumulated amount is a total amount of accumulated packets of the flow, and Ptr is a pointer to a packet group to which a packet arriving at the end of the flow belongs. The accumulation amount has the purpose of indicating whether or not the packet buffer device is accumulating packets for the flow. For example, the accumulation amount is accumulated for each flow by adding the input packet length when inputting the packet and subtracting the output packet length when outputting the packet. Holds the total number of bytes in the packet.
[0288]
The output waiting packet group is a packet group output from the packet group FIFO (packet group Z in the figure). When outputting a packet from the packet buffer device, a packet belonging to the output waiting packet group is output.
[0289]
If a packet comes in, you must decide which packet group to put the packet.
[0290]
First, it is checked whether or not the packet of the flow is currently stored in the buffer device. By referring to the accumulated amount of the flow in the flow table from the flow identification information, it can be determined whether it is zero or not. If it is not currently stored, the input packet is put into the first packet group (packet group A in FIG. 15) of the packet group FIFO.
[0291]
Even if the accumulation amount is larger than zero, if Ptr points to the output waiting packet group (packet group Z in FIG. 15), the input packet is also put into the first packet group A of the packet group FIFO.
[0292]
In other cases, it is determined by the input packet length and Nx, Nc, Ptr.
[0293]
Nx of each flow indicates the average amount of packets managed by one packet group for the flow. Nx is set to a value larger than the maximum packet length of the flow.
[0294]
Nc indicates the remaining amount that the flow can enter the packet group indicated by Ptr by calculating Nx-Nc. If Nx−Nc ≧ (input packet length), the input packet is put into the packet group pointed to by Ptr. Conversely, if Nx−Nc <(input packet length), the packet targeted by Ptr on the packet group FIFO Put the input packet in the next packet group of the group.
[0295]
When the packet group is determined, the values of Nc and Ptr are updated. If the first packet of the flow is put in the first packet group of the packet group FIFO, Nc: = (input packet length). In other cases, first, Nc: = Nc + (input packet length), and if Nx <Nc, the result is further rewritten as Nc: = Nc−Nx (that is, 0 <Nc ≦ Nx). Ptr writes a pointer to the packet group containing the input packet.
[0296]
In the present invention, one packet is not managed by two packet groups. Therefore, when the length of the input packet exceeds Nx−Nc, the input packet is put into the next packet group without being put into the packet group pointed to by Ptr. However, in calculating Nc, one packet is divided into two packet groups. That is, Nc: = Nc + (input packet length), and if there is a portion exceeding Nx, that Nc-Nx is set as Nc of the next packet group. By this algorithm, on average, Nx packets belong to one packet group.
[0297]
The packet input operation will be specifically described with reference to FIG. FIG. 15 shows a scene in which a packet having a length of 250 bytes arrives at the packet buffer device in the flow 1. At this time, Ptr of the flow 1 indicates the packet group B. In updating the flow table, Nc is set to Nc: = Nc + (input packet length) = 200 + 250 = 450 according to the above procedure. Since this value is less than or equal to Nx, this input packet is put into the packet group B pointed to by Ptr.
[0298]
If the input packet length of flow 1 is 350 instead of 250, Nc: = 200 + 350 = 550, which exceeds Nx. Therefore, Nc: = Nc-Nx = 550-500 = 50 is updated, and this input packet is put into the packet group C next to the packet group B. Ptr is changed to packet group C.
[0299]
The packet group FIFO is a first-in first-out queue, and the number of queued packet groups can be increased as necessary. For example, assuming that a packet having a packet length of 400 arrives in flow 2 in FIG. 15, an empty packet group (packet group E) is added next to packet group D, and an input packet is put into the packet group E. become.
[0300]
As described above, the processing at the time of packet input may be performed by changing the corresponding part of the flow table, putting the packet into the packet group, and adding an empty packet group to the packet group FIFO if necessary. It is possible to perform processing at the time of input without searching the flow table across a plurality of flows, and the complexity of processing does not change even if the number of flows increases.
[0301]
On the other hand, the processing required when outputting a packet is even simpler. That is, a packet may be output from the output waiting packet group. If necessary, a packet group is output from the packet group FIFO before that. These processes are also possible without searching the flow table across a plurality of flows, and the complexity of the process does not change even if the number of flows increases.
[0302]
As described above, the weight Nx of each flow indicates the average amount of packets per packet group for the flow. Since the packet buffer device of the present invention outputs packets in units of packet groups, the output sleep of each flow is proportional to Nx.
[0303]
According to this packet buffer device, it is possible to realize a weighted and fair packet buffer device that can easily handle variable-length packets without depending on the upper limit of the number of flows that can be set, without requiring processing for searching a flow table. it can.
[0304]
Each packet group of the present invention manages packets in the order of arrival. In other words, the output order of packets belonging to the same packet group is in the order of arrival through all the flows. This property has an effect of reducing packet delay fluctuation.
[0305]
Further, the packet buffer device of the present invention can realize the selection of output cells for fair queuing between VCs at a high speed even when the number of VCs increases as compared with the algorithm called DRR described in the prior art. Even if the value increases, the burstiness of output traffic does not increase. The burstiness does not increase in the present invention because when an input packet is distributed and managed to a plurality of sets (packet groups), the packets are managed independently of the flow (VC) in one set, and This is because when outputting from a set (packet group), it is output regardless of the flow (VC).
[0306]
3. Queue monitoring considering back pressure (eighth embodiment)
Next, a cell buffer device that performs queue monitoring in consideration of back pressure according to an eighth embodiment of the present invention will be described.
[0307]
FIG. 16 shows an example of a change in the queue length in the input buffer as described in the first, second, fourth, and fifth embodiments, for example.
[0308]
The cell buffer device according to the eighth embodiment is a cell buffer device that is controlled in two states of output enabling and output prohibiting by a back pressure signal, and the back pressure signal has changed from output enabling to output prohibiting. From the time until the next change from possible output to prohibited output, only the number of stored cells at the time of the first cell input is monitored.
[0309]
The purpose of monitoring is determination of congestion, determination of discard of input cells to prevent monopolization of the buffer area when a plurality of queues share one buffer area, and the like.
[0310]
FIG. 17 shows a configuration example of a cell buffer device having a queue monitoring unit taking back pressure into consideration. In FIG. 17, the cell buffer device includes a plurality of queues Qi (i = 1 to N), a queue table storage unit 280, a back pressure identifier (BPID) storage unit 281 and a queue monitoring unit 282.
[0311]
Qlen i of the queue table stored in the queue table storage unit 280 is the number of accumulated cells in the queue, Cnti is a congestion determination variable (initial value zero), and BPIDt i is a back pressure identifier (BPID) at the time of the last cell input. .
[0312]
When the cell enters the queue, the input cell information is transferred to the queue monitoring unit 282. BPID is incremented as shown in FIG. 16 when the back pressure signal changes from output enable to output disable. The queue monitoring unit 282 monitors the queue length based on the algorithm shown in FIG.
[0313]
FIG. 18 shows an example of a buffer queue length monitoring algorithm in consideration of back pressure. This shows an example in which the queue length is monitored to determine the presence or absence of congestion.
[0314]
When a cell is input to the queue Qi and cell input processing is started, first, Qlen i is incremented (step S1).
[0315]
Next, it is determined whether or not the queue length should be monitored by comparing BPID and BPIDt i (step S2). That is, monitoring is performed when the queue length that fluctuates due to the back pressure signal becomes shorter.
[0316]
If BPID ≠ BPIDt i, the queue length should be monitored. > It is determined whether or not 1 (step S3). At this time, Cnti > In the case of 1, it is determined that the state is congested until immediately before, and Qlen i is compared with a value (Qth−H) obtained by adding hysteresis to the threshold value Qth for determining whether or not the state is congested (step S4).
[0317]
Meanwhile, Cnti > If not 1, Qlen i> Qth is determined (step S5). When the queue length Qlen i is compared with Qth−H or Qth in step S4 and step S5, these threshold values are exceeded (that is, when Qlen i> Qth−H or Qlen i> Qth. ), Cnti: = Qlen i −Qth + H is performed (step S6, step S7), otherwise Cnti: = 0 is set (step S8, step S9). Further, the process proceeds to step S10.
[0318]
If BPID == BPIDt i in step S2, the queue length should not be monitored, and the process directly proceeds to step S10.
[0319]
In step S10, Cnti > 1 is determined. If so, it is in a congested state, and the process proceeds to step S11, where “1” is subtracted from Cnti (Cnti: = Cnti−1), and the input cell is discarded (step S12). Subtract (Qlen i: = Qlen i −1). Cnti > If it is not 1 (step S10), it is not a congestion state.
[0320]
Finally, the value of BPID is substituted into BPIDt i to update BPIDt i (step S13).
[0321]
As described above, according to the flowchart shown in FIG. 18, the accumulation at the time of the first cell input from when the back pressure signal changes from output possible to output prohibition until the next time when output possible changes to output prohibition. Only the number is monitored.
[0322]
H represents a parameter relating to hysteresis. Hysteresis has the effect of reducing the vibration of determination results such as cell discard and congestion that are performed by monitoring the queue length. 0 < If H <Qth and hysteresis is not required, set to zero.
[0323]
In FIG. 18, the threshold value Qth and the hysteresis parameter H show the case where the same value is used for all the queues, but different values may be set for each queue.
[0324]
Here, a method for determining the threshold value Qth will be described. First, consider a buffer that is not controlled by a backpressure signal. The buffer is input at a constant rate Ri and output at a constant rate R0. When Ri> R0, the buffer amount Qth necessary to prevent discarding for the time tT even if this load (Ri-RO) is applied is obtained by Qth = (Ri-RO) * tT.
[0325]
On the other hand, in the eighth embodiment, as shown in FIG. 16, the input rate is constant at Ri, but the output rate from the input buffer is zero for the Tup time (output inhibition time from the input buffer). , Tdn time (time available for output from the input buffer) is Re. Assuming that changes in Tup and Tdn are small, the buffer amount Qth necessary to prevent discarding for the time tT even when this load is applied is as follows.
[Expression 1]

[0326]
It becomes. Here, the average output rate R′0 from the output port is
[Expression 2]

[0327]
Therefore, Qth = (Ri-R'O) * tT, and the cell buffer device of the eighth embodiment sets the same threshold as that in the case of a simple buffer device without back pressure. By doing so, it is considered that almost the same effect can be obtained.
[0328]
Note that the same algorithm can be applied even when cell discard determination is performed instead of determining the congestion state.
[0329]
As described above, according to the cell buffer device considering the back pressure signal according to the eighth embodiment, the monitoring result of the queue length is hardly affected by the external condition, and the stable monitoring of the queue length is easy. is there.
[0330]
4). Correction of cell number information in consideration of delay (9th embodiment)
Next, an embodiment of a cell buffer device for correcting cell number information according to the present invention will be described.
[0331]
4.1 Ninth Embodiment (Cell Buffer Device Considering Delay)
FIG. 19 shows the configuration of a cell buffer device considering delay according to the ninth embodiment.
[0332]
The cell buffer device shown in FIG. 19 is roughly divided into a cell buffer network 300 in which one or more cell buffers B (Ba, Bb,...) Are connected in a plurality of stages (two stages in FIG. 19), and each cell buffer. The management unit 301 inputs the number of B cells and instructs the cell buffer B to transfer.
[0333]
The management unit 301 stores a transfer instruction history 302 and uses the transfer instruction history 302 when determining a new transfer instruction.
[0334]
The management unit 301 transmits a transfer instruction acting on the cell buffer B from the time when the cell buffer B transmits the number of cells to the management unit 301 until a time when the transfer instruction determined by the management unit acts on the cell buffer B. Is determined from the transfer instruction history 302, and the transfer instruction is determined from the number of transfer instructions and the number of cells.
[0335]
FIG. 20 is a diagram for explaining the principle of correcting the cell number information in the cell buffer device considering delay according to the present invention.
[0336]
Cells input from the input links # 1 and # 2 are temporarily stored in the cell buffers Ba1 and Ba2 in the previous stage, respectively. The cell is transferred to the cell buffer Bb according to the transfer instruction of the management unit 301, and the cell buffer Bb outputs the cell to the output link.
[0337]
Ba2 cell number Na2 and Bb cell number Nb are transmitted to management unit 301, and a transfer instruction is output to Ba1 and Ba2.
[0338]
Now, the cell number information arrives at the management unit 301 from Ba2, determines the transfer instruction from the information, instructs the transfer to Ba2, and sets the delay time until the number of cells of Ba2 changes according to this transfer instruction to D cells. Let it be a period. Further, the cell number information arrives at the management section from Bb, determines the transfer instruction from the information, instructs the transfer to Ba1 and Ba2, and the cell is transferred from Ba1 or Ba2 to Bb by this transfer instruction, and the cell of Bb The delay time until the number changes is also assumed to be the same D cell period for the sake of simplicity.
[0339]
Here, FIG. 20 shows a cell buffer device for performing priority control in which cell buffers Ba1 and Ba2 correspond to the class 1 cell storage unit and class 2 cell storage unit in FIG. 53, and cell buffer Bb corresponds to a cell multiplexing FIFO. Think. The cell transfer policy between the cell buffers Ba1, Ba2, and Bb is the same as that shown in FIG. That is, it is necessary to reduce the number of Bb storage cells, but a transfer instruction is made so as not to empty (= underflow) Bb. Further, the transfer instruction is made so as not to give an empty instruction (the transfer instruction is issued to Ba2 only when a storage cell exists in Ba2).
[0340]
Assume that the cell number information Na2 output from Ba2 at time t2 arrives at the management unit 301, the management unit 301 issues a transfer instruction at time t3, and a cell is output from Ba2 at time t4 according to the transfer instruction. The information that the management unit 301 wants to know is the number of cells of Ba2 at time t4 when the transfer instruction actually acts on Ba2. This time is indicated by a white circle in FIG.
[0341]
Assuming that Ba2 has received a transfer instruction Ma2 times during the period from time t2 to t4 (= D cell period), Ba2 has output Ma2 cells during this period, and the number of cells of Ba2 at time t4 is Na2-Ma2. (When no cell is input to Ba2).
[0342]
Normally, since the transmission delay of the transfer instruction from the management unit 301 to Ba2 is constant, the transfer instruction number Ma2 received by Ba2 is determined by the management unit 301 between t1 and t3 such that t4−t2 = D = t3−t1. It is equal to the number of output transfer instructions. Therefore, by knowing the transfer instruction count Ma2 from the transfer instruction history 302, the number of cells decreased by Ba2 from time t2 to t4 can be accurately obtained.
[0343]
The same applies to Bb, and the amount of increase in the number of Bb cells from time t2 to t4 (the amount of increase due to transfer cells from Ba2) can be accurately obtained.
[0344]
The management unit 301 cannot know the number of cells input to Ba2 from time t2 to t4. In order not to give an empty instruction to Ba2, the number of Ba2 cells may be estimated slightly. Therefore, it is assumed that the cell input from the input link to Ba2 was not from time t2 to t4.
[0345]
Further, the management unit 301 cannot know the cell output from Bb from time t2 to time t4. In order to prevent Bb from underflowing, it is necessary to estimate the number of Bb cells slightly. Therefore, it is assumed that the cell output from Bb is always output from time t2 to time t4 (it is assumed that it is a D cell since it is a D cell period). Furthermore, it is assumed that the input cell from Ba1 is also zero.
[0346]
In summary, if the revised Na2 and Nb are N'a2 and N'b, respectively,
N'a2 = Na2 + 0-Ma2
N'b = Nb + Ma2-D
It is. Therefore, the condition for the management unit 301 to instruct transfer to Ba2 is as follows:
(N'b ≤ Th) and (N'a> 0)
Given in. The transfer instruction to Ba1 is
(N'b ≤ Th) and (N'a ≤ 0)
Perform under the following conditions. Th is normally “1”. By correcting the number of cells as described above, transfer can be instructed while reducing underflow and empty instructions.
[0347]
4.2 Method for correcting the number of cells in a general buffer network
Next, a method for correcting the number of cells in a general buffer network will be described.
[0348]
FIG. 21 is used to explain the basic principle. FIG. 21 shows the cell buffer network 300 and the management unit 301 as described above. The cell buffer network 300 includes a focused cell buffer Bx. The cell buffer Bx may physically be a plurality of buffers. The management unit obtains cell number information from the cell buffer Bx and gives a transfer instruction. First, terms used to describe the present invention are defined.
[0349]
4.2.1. Definition of terms
Unless otherwise specified, the time is a relative time with the current time being zero, and is incremented by 1 every time the cell period elapses. Such a definition of time can be converted into other representation methods and is general. In addition, a period from a certain time t1 to a certain time t2 may be expressed as p, which is expressed as p = [t1, t2). This period p includes time t1, and does not include t2.
[0350]
The number of cells stored in the cell buffer Bx is represented by Nx. Nx is the number of storage cells that have arrived at the management unit 301 at the current time (t = 0).
[0351]
For the cell buffer Bx, the management unit 301 sets the time t (t < The transfer instruction output to 0) is represented by Ix (t). When transfer is instructed, Ix (t) = 1, and when transfer is not instructed, Ix (t) = 0.
[0352]
Time t (t < 0), the number of HOL cells in the cell buffer Bx arriving at the management unit 301 is represented by Hx (t).
[0353]
The number of HOL cells is the number of cells that may be transferred from the cell buffer at a time by one transfer instruction. In particular, the HOL cell number information Hx that has arrived at the management unit 301 at the current time is represented as Hx (0).
[0354]
The management unit 301 of the present invention uses the time t (t < 0), the number of HOL cells Hx (t) of the cell buffer Bx and the transfer instruction Ix (t) output to the cell buffer Bx by itself are stored as history.
[0355]
The number of times the management unit has instructed transfer to the cell buffer Bx during a certain period p is represented as Smx (p). When p = [t1, t2), it is also expressed as Mx [t1, t2). That means
[Equation 3]

[0356]
FIG. 23 is a time chart showing the flow of cell number information from the cell buffer Bx to the management unit 301 and the flow of transfer instructions from the management unit 301 to the cell buffer Bx.
[0357]
As shown in this figure, times tf, tt, and th are determined. It is assumed that the number Nx of accumulated cells in the cell buffer Bx at the time tf and the number of HOL cells Hx in the cell buffer Bx at the time th are the latest information that the management unit 301 can directly know about the cell buffer Bx at the current time. At this time, it is assumed that the management unit 301 wants to predict the number of cells stored in the cell buffer Bx at time tt.
[0358]
Times t1, t3, and t2 are determined for times tf, tt, and th. The time at which the transfer instruction output from the management unit 301 at time t1 reaches the cell buffer Bx is denoted by tf, and the time at which the transfer instruction output by the management unit 301 at time t2 arrives at the cell buffer Bx is denoted by tt. Similarly, let th be the time at which the transfer instruction output by the management unit 301 at time t3 reaches the cell buffer Bx.
[0359]
It is assumed that the times t1, t2, and t3 are past times from the current time. That is, t1 <t2 < 0, t3 < 0.
[0360]
4.2.2. Basic principle
Here, the basic principle of the present invention will be described. The management unit 301 of the present invention predicts a change in the number of stored cells from the transfer instruction history. When it is desired to obtain the number of accumulated cells at time tt for the cell buffer Bx described above, the number of accumulated cells Nx at time tf in the past was transferred according to the transfer instruction during this period using the transfer instruction history. Predict and correct the number of cells. The correction is based on the fact that the number of cells transferred by one transfer instruction is 1 or more. In particular, the number of cells transferred by the first transfer instruction after time th is based on being equal to or greater than the number of HOL cells Hx.
[0361]
4.2.3. Three functions
Based on the above basic principle, three functions f (), g (), and Sc () used for correction are determined. These functions are used to determine how much the cell buffer Bx changes due to transfer of a cell according to a transfer instruction from time tf to time tt. It can be classified into three cases depending on what value th is compared with tf and tt, and different functions are applied.
[0362]
(1) Function f ()
The function f () is used when th = tf <tt. A time chart at this time is shown in FIG. Let p1 [t1, t2). When Hx ≠ 0 and Smx (p1) ≠ 0, it is considered that Hx cell transfer is performed in the first transfer instruction in the period p1, and one cell is transferred in subsequent transfer instructions. The function f () for calculating the number of cells in the cell buffer Bx that changes from time tf to time tt can be obtained as follows using Hx and the number of transfer instructions Smx (p1) in the period p1 as arguments.
[0363]
[Expression 4]

[0364]
(2) Function g ()
The function g () is used when th <tf <tt. A time chart at this time is shown in FIG. p1 = [t1, t2) and p2 = [t3, t1).
[0365]
In this case, it is necessary to distinguish between cases depending on whether or not the first transfer instruction arriving after time th is output from the management unit 301 in the period p2. Since no transfer instruction is output from the management unit 301 in the period p2, the value of Hx can be used in the period p1. The function g () for calculating the number of cells in the cell buffer Bx that changes from the time tf to the time tt is as follows with the transfer instruction counts Smx (p1) and Smx (p2) of Hx and periods p1 and p2 as arguments: Can be sought.
[0366]
[Equation 5]

[0367]
(3) Function Sc ()
The function Sc () is used when tf <tt = th. A time chart at this time is shown in FIG. Let p1 = [t1, t2). The latest number of stored cells that can be known by the management unit 301 is the value at the time tf. In this case, regarding the number of HOL cells, information for all periods from the time tf to the time tt has already arrived at the management unit 301. ing.
[0368]
If the number of HOL cells at the time when the transfer instruction arrives at the cell buffer Bx is known, the number of cells to be transferred can also be known. Therefore, the function Sc () for calculating the number of cells in the cell buffer that changes from time tf to time tt is: Using Ix (t) and Hx (t) and using the period p1 as an argument, it can be obtained as follows.
[0369]
[Formula 6]

[0370]
The method of correcting the number of cells as described above can be easily applied to, for example, a cell multiplexing apparatus that performs priority control between classes as shown in FIG.
[0371]
Further, for example, the cell number correction method can be easily applied to a cell multiplexing apparatus that performs inter-VC fair queuing as shown in FIG.
[0372]
4.3 Advantages of cell buffer device according to ninth embodiment
As described above, according to the ninth embodiment, the cell buffer device having a delay between the cell buffer and the management unit that manages the cell buffer stores the transfer instruction history when determining the transfer instruction. The number of cells transmitted from the cell buffer is corrected to the number of cells at the time when the transfer instruction acts on the cell buffer, so that the performance degradation due to the delay time is small.
[0373]
5. Cell switch (tenth embodiment)
5.1 Tenth Embodiment (Cell Switch)
Next, as a tenth embodiment, a cell switch in which the cell multiplexing device and the cell buffer device according to the present invention described so far are combined will be described.
[0374]
FIG. 25 shows a plurality of input buffers IB that temporarily store cells input from a plurality of input ports #i (i = 1 to N) and output them according to back pressure, and a back that corresponds to an internal congestion state. The cell switch 400 includes a back pressure cell switch 400 that outputs a pressure signal, and a basket management unit KM that transfers information between the input buffer IB.
[0375]
The cells handled in this configuration example generally have two priorities, a high priority cell and a low priority cell, and the low priority class is divided into a plurality of classes. Normally, a cell that transmits real-time information such as CBR and VBR is a high-priority cell, and a cell that transmits non-real-time information such as ABR and UBR is a low-priority cell.
[0376]
First, a cell switch with back pressure will be described.
[0377]
The features of the basket switch are the input buffer IB and the basket management unit KM. The cell switch 400 with back pressure only needs to be able to output an input cell within a predetermined time, and its architecture is not limited to that shown below. For example, the ATM switch shown in the IEICE Technical Report SSE93-6 “ATM Switch with Expandable Buffer Capacity: XATOM” may be used.
[0378]
The back-pressured cell switch 400 shown in FIG. 25 will be described as an example. It consists of a first stage unit switch SE1, a second stage unit switch SE2, and an output buffer OB. SE1 and SE2 are connected in a two-stage delta network via a parallel link, and the cell output from SE2 is transferred to OB and output to the output port. To do. Between SE1 and OB, it operates at k times speed. The value of k is determined so that the cell switch is non-blocking. For example, when SE1 and SE2 are 8 inputs and 8 outputs, k = 2 may be used when 16 inputs and 16 outputs are used as a whole.
[0379]
The cell switch 400 with back pressure in FIG. 25 is configured to handle two levels of priority, a high priority cell and a low priority cell.
[0380]
Focusing only on the replacement of the low-priority cells, the basic configuration is almost the same as that shown in the 1995 IEICE General Conference B-589 “A method for expanding the buffer capacity of an ATM two-stage switch network”. The low priority cell is exchanged and copied in SE1 and SE2.
[0381]
When the low-priority cell is congested by OB, the cell output to the output port of the IB is suppressed using the low-pressure cell back pressure signal. This back pressure signal basically prevents the OB and SE2 buffers from overflowing. However, these buffers may overflow due to the influence of the multicast cell. In preparation for this, an overflow back pressure signal for low priority cells is output from OB to SE2, and an emergency back pressure signal for low priority cells is output from SE2. Output to IB. Since IB accumulates low priority cells, SE2 and OB are not discarded.
[0382]
Instead of outputting the low-priority cell overflow backpressure signal to SE2, the OB may output this to the IB as a low-priority cell emergency backpressure signal. In this case, SE2 does not need to output a low priority cell emergency backpressure signal. However, as described above, the output of the low-priority cell emergency backpressure signal from SE2 has an advantage that the buffer sharing effect in SE2 can be effectively utilized.
[0383]
The high priority cell is exchanged and copied at SE1 and SE2 in the same manner as the low priority cell. For high priority cells, there is no backpressure signal from the cell switch with backpressure to the IB. The OB controls the cell output of SE2 by a high-priority cell back pressure signal reflecting the congestion of the high-priority cell. The IB does not accumulate high priority cells. If there is no empty buffer in SE2, it may be discarded.
[0384]
Next, the output buffer will be described.
[0385]
FIG. 26 shows a configuration example of the output buffer OB of the basket switch.
[0386]
The cells transferred from SE2 to OB are identified in priority by the identification unit 410, and are placed in a queue corresponding to each priority. The cells of each queue are selected according to the priority by the selection unit 411 and output to the output port. When the queue length of the low-priority cell exceeds a certain threshold, the OB stops the output of the IB low-priority cell to the OB using the low-priority cell back pressure signal. When the queue length of the high priority cell exceeds a certain threshold, the output of the high priority cell of SE2 to the OB is stopped using the back pressure signal for the high priority cell. In preparation for the case where the queue length of the low-priority cell continues to increase due to the influence of the multicast cell of the low-priority cell, the output of the SE2 low-priority cell to the OB is stopped using the low-priority cell overflow backpressure signal.
[0387]
Next, the unit switch will be described.
[0388]
FIG. 27 shows a configuration example of the first stage unit switch SE1 used for the basket switch. SE1 is a generally well-known switch LSI. With respect to the cell input from the input link, the identification section 415 identifies the cell header, performs a predetermined exchange process, and outputs it to the output link. Since the entire switch operates at k times speed, the number of cells stored in the internal cell buffer does not increase. This is known in the 1994 IEICE Autumn Conference B-439 “Examination of Switch Networks with Parallel Links”.
[0389]
FIG. 28 shows a configuration example of the second stage unit switch SE2 used for the basket switch. In SE2, the internal queue is a queue for each priority for each output link. The output of the queue for each priority is selected by the selection unit 421. When a high priority cell exists, the high priority cell is output to the output link regardless of the presence or absence of the low priority cell. However, when the high-priority cell backpressure signal input to the selection unit 421 instructs to prohibit the output of the high-priority cell, the high-priority cell may not be output and the low-priority cell may be output. . The output of the low priority cell may be prohibited by the overflow back pressure signal for the low priority cell.
[0390]
SE2 can efficiently use the buffer in SE2 by sharing a physical buffer area among a plurality of priorities and a plurality of output links. The buffer status management unit 422 monitors the queue length for each queue, the result of summing the queue lengths for all output links for each priority, and the like.
[0390]
For example, the high priority cell queue has a threshold value for each queue, and when the threshold value is exceeded, the input cell of the queue is discarded. The low-priority cell queue monitors the total of all queue lengths, and if the threshold value is exceeded, informs the IB to prohibit the input of low-priority cells by a low-priority cell emergency backpressure signal.
[0392]
SE1 may use the same unit switch as SE2.
[0393]
In the cell switch 400 with back pressure in FIG. 25, cells are exchanged by the two-stage unit switches SE1 and SE2, but only one internal path is defined for each pair of input port and output port. Therefore, each unit switch does not need a complicated route selection algorithm when exchanging while copying the cell while looking at the cell header. If the number of output ports is about 32 or less, it is possible to easily add output port bitmap information to the cell header. SE1 and SE2 exchange cells based on the bitmap information.
[0394]
Next, the input buffer IB will be described.
[0395]
FIG. 29 shows a configuration example of the input buffer IB of the cage switch.
[0396]
The high priority cell input to the IB is preferentially output to SE1 for both unicast and multicast. Therefore, the cell delay fluctuation of the high priority cell is very small. There is no buffer for high priority cells in the IB.
[0397]
A feature of the present invention resides in a method for processing low priority cells. Hereinafter, only the low priority cell will be described.
[0398]
In FIG. 29, the input buffer IB mainly includes a plurality of output port unicast cell management units 430 that temporarily store input unicast cells for each output port of the cell, and temporarily inputs input multicast cells. A multicast cell management unit 431 that stores data in the network, and an output port selection scheduler 432 that selects the cells of these management units and outputs them from the input buffer.
[0399]
The unicast cell management unit 430 for each output port outputs the input cells from a plurality of unicast cell management units 433 for each class that temporarily store the input cells for each class of the cells and the unicast cell management unit 433 for each class. It has a class multiplexing FIFO 434 for multiplexing cells.
[0400]
The multicast cell management unit 431 includes a plurality of class-specific multicast cell management units 435 that temporarily store input cells for each class of the cell, and a class that multiplexes cells output from the class-specific multicast cell management unit 435 It has a multiplexed FIFO 436.
[0401]
Cells output from the class multiplexing FIFOs 434 and 436 of the unicast cell management unit 430 and the multicast cell management unit 431 for each output port are selected by the output port selection scheduler 432 and output from the input buffer IB.
[0402]
The output port selection scheduler 432 selects a cell in consideration of an external low pressure cell back pressure signal and a low priority cell emergency back pressure signal.
[0403]
The unicast cell management unit 433 for each class manages a queue (car 440) that manages a set of cells that are permitted to be output from the car management unit KM among the accumulated cells, and other cells. And a queue (front basket 441) called a front basket.
[0404]
The cells that have entered the front basket 441 are managed in units called unit baskets. In FIG. 29, a vertical row in the front car 441 and the car 440 indicates a unit car. The input cell is managed fairly between VCs (CG) for each unit basket. The cell of the front car 441 is transferred to the car 440 in units of unit car according to an instruction from the car management unit KM.
[0405]
The cells of the basket 440 are transferred in units of cells and multiplexed by the class multiplexing FIFO 434 according to an instruction from the basket management unit KM.
[0406]
The operation of the multicast cell management unit 435 for each class will be described later.
[0407]
By sharing the cell buffer among all the output ports of the IB and the queues of all classes, it is possible to effectively use a finite buffer amount.
[0408]
In order for a cell that has arrived at the IB to be output from the IB, it is necessary for the IB to notify the KM that the cell has arrived and to instruct the output from the IB. Therefore, if there is a delay in information transmission between the IB and the KM, the cell output from the IB is delayed by the delay time. However, since the delay time is considered to be about several cell cycles, the influence on the traffic characteristics is considered to be small.
[0409]
In order to preferentially control the unicast cell for each output port, the IB has a unicast cell management unit for each class 433 and a class multiplexing FIFO 434 for each output port. The same method as the priority control described in the cell multiplexing apparatus of FIG. 1 is used.
[0410]
Although FIG. 1 shows a cell multiplexing apparatus, the cage switch is a cell switch and IB is an input buffer of the cell switch. Therefore, a plurality of class multiplexing FIFOs exist in one IB corresponding to all output ports, and the cells are selected by the output port selection scheduler 434 and output to SE1.
[0411]
The cell-by-class cell storage unit 13 of the cell multiplexing device of FIG. 1 corresponds to the IB-by-class unicast cell management unit 433 of FIG. 29, and the class multiplexing FIFO 14 of the cell multiplexing device of FIG. This corresponds to the IB class multiplexing FIFO 434.
[0412]
The class management unit 12 of the cell multiplexing apparatus in FIG. 1 corresponds to the KM in FIG. Priority control can be performed when the basket management unit KM instructs the transfer of cells from the unicast cell management unit 433 for each class to the class multiplexing FIFO 434.
[0413]
Multicast cell priority control will be described later.
[0414]
In order to perform fair queuing between VCs for each class of unicast cells, the unicast cell management unit 433 for each class has a front basket 441 and a basket 440. Basically, the same method as the inter-VC fair queuing described in the cell multiplexing apparatus of FIG. 6 is used.
[0415]
FIG. 6 shows a cell multiplexing apparatus and no class, but IB is an input buffer of a cell switch and also has a class. For each IB, the front basket 441 and the basket 440 exist corresponding to all output ports and all classes, and the cells are multiplexed by the class multiplexing FIFO 434 and then selected by the output port selection scheduler 432 to the SE1. Is output.
[0416]
6 corresponds to the basket 440 of the IB of FIG. 29, and the cell set 214 to be output by the same time of the cell multiplexer of FIG. 6 is the unit of the IB of FIG. It corresponds to a basket. The basket management unit 12 of the cell multiplexing apparatus in FIG. 6 corresponds to the basket management unit KM in FIG. The inter-VC fair queuing can be performed by the basket management unit KM instructing the transfer of the unit basket from the front car 441 to the car 440 in FIG.
[0417]
Inter-VC fair queuing of multicast cells will be described later.
[0418]
There is a front basket 441 and a basket 440 in the unicast cell management unit 433 for each class to perform unicast cell queuing between VCs in the IB. The same method as that described in the data structure example using the pointer chain of the cell group FIFO 232a in FIG. 10 is used.
[0419]
The cell group FIFO 232a in FIG. 10 corresponds to the IB front basket 441 in FIG. 29, and the output waiting cell group FIFO 232b in FIG. 10 corresponds to the IB basket 440 in FIG. The cell group in FIG. 10 corresponds to the unit basket of IB in FIG.
[0420]
Next, the queuing process of the input buffer IB will be described with reference to FIG.
[0421]
The cell is first accumulated in the front car 441 and then transferred to the car 440 in units of unit car. The cell of the cage 440 is output from the cage 440 in units of cells. The basket management unit KM gives instructions for each opportunity.
[0422]
In this configuration example, all VCs belong to a certain connection group (CG). By having the concept of a connection group, a plurality of VCs can share one resource (bandwidth or cell buffer). For example, when only one VC is charged for communication between two distant users, it is possible to give a degree of freedom to set a plurality of VCs between the two users. Alternatively, it is possible to prevent two users from setting a large number of VCs to obtain an unreasonably large band in a network that allocates a fair band according to the number of VCs.
[0423]
The VC table and the CG table are used to determine in which unit car the cell is placed in the front car 441.
[0424]
The connection group identifier (for example, CG5) can be known from the connection identifier (for example, VC4) of the input cell using the VC table. A value determined for each CG can be known from the connection group identifier using the CG table. The values for each CG in this configuration example are Nx, Nc, Ptr, Qlen, Cnt1, Cnt2, Cnt3, and BPIDt.
[0425]
Nx, Nc, Ptr, and Qlen have been described in the data structure example by the pointer chain of the cell group FIFO in FIG. Nx is the weight of the CG, Nc is the work variable, Qlen is the number of cells stored in the CG, and Ptr is a pointer to the end of the unit basket in which the CG cells are stored.
[0426]
On the other hand, Qlen, Cnt1, Cnt2, Cnt3, and BPIDt have been described in the cell buffer device having the back pressure consideration queue monitoring unit shown in FIGS.
[0427]
Qlen is the number of cells stored in the CG, Cnt1 is the number of cells to be discarded, and BPIDt is a back pressure identifier at the time of the last cell input. There are variables Cnt2 and Cnt3 having the same function as Cnt1 in order to perform finer queue monitoring. Each queue length monitoring threshold is different. Cnt2 is the number of cells to be discarded for a cell whose CLP (Cell Loss Priority) bit in the cell header has a low priority (CLP = 1), and Cnt3 is used to determine whether there is congestion in this queue length monitoring. The value to use for. The information on whether or not congestion is used, for example, to determine whether or not to mark EFCI in the cell header and whether to mark the congestion indication bit of the RM cell.
[0428]
It is possible to set not to perform fair queuing between VCs in a certain class. In that case, the Nx of the CG to which the VC belongs may be set to a sufficiently large value.
[0429]
Now, the cell switch with back pressure shown in FIG. 25 has a relatively low cycle for repeating the output prohibition and the output prohibition for the low-priority cell back pressure signal due to the influence of the delay time of cell transmission from IB to OB. large. Accordingly, when the queue length Qlen for each CG of the IB is observed, the oscillation repeats mainly as shown in FIG. 14 in synchronization with the low priority cell back pressure signal. As described above, the back pressure-considered queue length monitoring algorithm described with reference to FIGS. 15 and 16 is suitable for monitoring the queue length that is vibrated by the back pressure signal.
[0430]
Regarding the total number of cells in the entire class of cells stored in the front car 441 and the car 440, the input cell is discarded or the EFCI is marked by monitoring the queue length considering the back pressure, and the buffer of some classes is IB. It is possible to prevent monopolizing most of the territory.
[0431]
FIG. 31 shows an example of an interface with the basket management unit KM of the input buffer IB used for the basket switch.
[0432]
Information for each output port as shown below is input from the KM to each output port.
[0433]
-Number of ABR input cells
-Instruction class
-Transfer instruction of unit basket from previous basket to basket (transfer instruction T1 in FIG. 31)
-Cell transfer instruction from basket to class multiplexing FIFO (transfer instruction T2 in FIG. 31) The number of ABR input cells is transferred to the ABR processing unit 450. The ABR processing unit 450 can monitor the traffic flowing into the output port paired with the IB by knowing the number of ABR input cells. The information is used to rewrite the payload of the RM cell that passes through the IB.
[0434]
When the KM is instructed to transfer a cell from the basket 440 to the class multiplexing FIFO 434, the IB takes out one cell from the unicast basket 440 of the indicated class and transfers it to the class multiplexing FIFO 434. When there is a unit basket transfer instruction from the front car 441 to the car 440, the IB takes out one unit car from the front car 441 of the instruction class unicast and transfers it to the car 440, and takes out one cell from the car 440 and performs class multiplexing. Transfer to the generalized FIFO 434.
[0435]
By limiting the unit basket transfer instruction only to the transfer instruction of the cell of the class, the amount of information of the transfer instruction can be reduced and mounting can be performed more easily.
[0436]
The number of cells in the front basket 441, the basket 440, and the class multiplexing FIFO 434 in the IB changes when a cell is input to the IB, when the KM issues a transfer instruction, or when a cell is output from the IB. Accordingly, cell number information is output to the KM accordingly. Information that one IB outputs to the KM is as follows.
[0437]
For each input port, for input cells (only one output port in case of unicast),
-Presence and class of input cells
For each output port, the transfer instruction class
-Number of previous basket cells (after transfer) (CE1 in FIG. 31)
-Number of kago cells (after transfer) (CE2 in FIG. 31)
-Number of transfer cells to class multiplexing FIFO (CE3 in FIG. 31)
For each output port, only unicast,
Number of class multiplexed FIFO cells (CE4 in FIG. 31)
This will be described with reference to FIG. Input cell information is transmitted from the IB to the KM as the presence and class of the input cell. In addition, the number of previous basket cells of unicast and multicast is added, and the class selected by the class selection unit L5 in the transfer instruction class is transmitted as the number of previous basket cells. Furthermore, the number of unicast and multicast basket cells is added, and the number selected by the instruction class in the class selection unit L6 is transmitted as the number of basket cells. Then, unicast and multicast are added to the number of cells moved from the basket to the class multiplexing FIFO 434 according to the transfer instruction, and the class selection unit L7 selects and transmits the selected class. The number of class multiplexed FIFO cells is transmitted to KM only for unicast. The number of multicast class multiplexed FIFO cells is used as a back pressure signal for controlling the cell output from the multicast cell management unit 435 for each class.
[0438]
Since the output of the multicast class multiplexing FIFO 436 is controlled by back pressure signals from a plurality of output buffers OB, the output port of the cell switch may underflow even if the number of class multiplexed FIFO cells is not zero. There is. In this configuration example, the number of unicast class multiplexed FIFO cells is not added so that the unicast cell does not underflow under the influence.
[0439]
Here, multicast cell priority control and inter-VC fair queuing will be described.
[0440]
Consider a multicast VC from the viewpoint of throughput. In general, considering the state of a cell switch at a certain point in time, the plurality of output ports include a congested output port and an output port with a low load. That is, the throughput that the VC can use varies depending on the output port. Multicast VCs simultaneously output the same throughput from one input port to multiple output ports, so the throughput that the multicast VC can obtain is the throughput of the most congested output port among the output destinations. Is good. Therefore, when outputting a multicast cell from the IB, it is desirable to output at the throughput of the most congested output port.
[0441]
The IB can know the throughput per VC (CG) given to a certain class of a certain output port from the frequency of the unit basket transfer instruction from the previous car 441 to the car 440. Further, the IB can know the throughput given to a certain class of a certain output port from the frequency of the cell transfer instruction from the basket 440 to the class multiplexing FIFO 434. Further, the IB can know the throughput given to a certain output port from the frequency of the low pressure cell back pressure signal. These transfer instructions and back pressure signals are given to each output port.
[0442]
In order to output at the throughput of the most congested output port, the multicast cell may be transferred when these signals indicate or permit all the output ports of the cell. Instructions or permissions to multiple output ports need not be simultaneous.
[0443]
When managing low-priority multicast VCs in IB, it is desirable to manage them for each class and for each output port pattern. In general, however, the number of combinations is large, and the number of output ports during communication is also large. Such an implementation is not realistic. In the cage switch as shown in FIG. 25, all multicast connections are managed only for each class, and are not managed for each output port pattern. A certain amount of HOL (Head Of Line) blocking occurs.
[0444]
FIG. 32 is a diagram for explaining the class-by-class multicast cell management unit 435. This management unit holds and manages the output port table, the VC fair queue, the number of unit basket cells, the number of basket cells, and the number of output permitted cells.
[0445]
Whereas the per-class unicast cell management unit 433 manages cells in the previous car and the car, the per-class multicast cell management unit 435 manages cells only by the inter-VC fair queue 460 corresponding to the previous car. However, the multicast cell management unit 435 for each class according to the present invention performs cell management similar to unicast using the concept of the previous car and the car in the calculation of management.
[0446]
The class-specific multicast cell management unit 435 inputs the following information for each output port.
[0447]
・ Unit basket transfer instruction from previous basket to basket
-Cell transfer instruction from basket to class multiplexing FIFO
The following information is output for each output port.
[0448]
・ Number of previous kago cells
・ Number of Kagocel
・ Number of transfer cells
The inter-VC fair queue 460 is a unit basket FIFO. The number of cells input to the inter-VC fair queue 460 can be input up to a predetermined number in one unit basket for each VC (CG). This configuration is the same as that of the unicast front basket described in FIG. A back pressure signal is input from the class multiplexing FIFO 436, and cell output from the inter-VC fair queue 460 is prohibited depending on the situation.
[0449]
The output port table stores the number of previous basket cells and a pointer to the head unit basket for each output port. The number of previous baskets is the total number of unit baskets, and the head unit basket is a pointer to the head unit basket of the previous basket in calculation.
[0450]
The number of unit basket cells stores data for each output port corresponding to the unit basket of the VC fair queue 460. Basically, the number of cells for each output port of the multicast cell stored in the corresponding unit basket is stored. For example, five cells are stored in the top unit basket of the inter-VC fair queue 460 of FIG. Of these, there are 3 cells to be output to port # 1 and port #N, and 2 cells to be output to port # 1 and port # 2. Therefore, 5 for port # 1 and 5 for port # 2 2, 3 is stored in port #N.
[0451]
The number of basket cells is the calculated number of basket cells. The number of output-permitted cells is the number of cells permitted to be output in calculation.
[0452]
When a unit basket transfer is instructed to a certain output port, the number of unit basket cells of the head unit basket of that output port is added to the number of basket cells, and the number of unit basket cells is made zero. Further, 1 is subtracted from the number of basket cells of the output port, and 1 is added to the number of cells permitted to output. Then, the pointer of the head unit basket in the output port table is advanced by one to the next unit basket in the inter-VC fairness queue 460. The number of transfer cells at this time is one cell.
[0453]
By advancing the pointer of the head unit basket, the pointer moves away from the head unit basket of the inter-VC fairness queue 460. An upper limit is set for this distance, and when the distance is reached, control is performed so that the unit basket transfer instruction is ignored and the pointer cannot be advanced. This has an effect of preventing the difference between the time when the unit basket transfer is instructed and the time when the cell is actually output from being increased.
[0454]
When cell transfer is instructed to a certain output port from the KM, 1 is subtracted from the number of basket cells of that output port, and 1 is added to the number of output-permitted cells. The number of transfer cells at this time is one cell.
[0455]
When the back pressure signal from the class multiplexing FIFO 436 permits output, the cell can be output from the inter-VC fair queue 460. At that time, the number of output-permitted cells is subtracted by 1 for all the output ports of the cell. If there is an output port with the number of output-permitted cells being zero, subtraction cannot be performed, so that cell cannot be output yet.
[0456]
The number of output-permitted cells is increased by unit basket transfer instruction and cell transfer instruction. When the number of output-permitted cells of a certain output port exceeds a certain value, the number of the previous and the number of basket cells output from the multicast cell management unit 435 for each class is set to zero for the output port, and the unit basket transfer instruction and Ignore cell transfer instructions. This has the effect of ignoring transfer instructions exceeding the transfer throughput of the actual cell.
[0457]
Next, with reference to FIGS. 33 to 39, the operation of the multicast cell management unit for each class will be described.
[0458]
FIG. 33 shows the operation when the KM instructs the output port # 1 to transfer the unit basket from the state of FIG. The number of unit basket cells of the head unit basket of port # 1 is added to the number of basket cells to make the number of unit basket cells zero. Further, 1 is subtracted from the number of basket cells of port # 1, and 1 is added to the number of cells whose output is permitted. The number of cells transferred to the KM is 1 cell for the output port # 1.
[0459]
The pointer of the head unit basket in the output port table is advanced by one to the next unit basket of the VC fair queue 460.
[0460]
Furthermore, FIG. 34 shows the operation when the KM instructs the output port # 1 to transfer a cell. 1 is subtracted from the number of basket cells in port # 1, and 1 is added to the number of cells whose output has been permitted. The number of cells transferred to the KM is 1 cell for the output port # 1.
[0461]
The output ports of the first cell of the inter-VC fair queue 460 in FIG. 34 are # 1 and #N. The number of output-permitted cells is not zero (= 2) for the output port # 1, but since the output port #N is zero, no cells can be output yet.
[0462]
The operation when the cell arrives is shown in FIG. The output ports of the arrived cells are # 1 and #N. It is also assumed that this cell is a VC cell that has not been stored in the inter-VC fair queue 460 until now. In this case, the cell is input to the top unit basket of the inter-VC fair queue 460.
[0463]
When a cell is input, the number of unit basket cells of all output ports of the cell is incremented by one. The unit basket to be added is determined for each output port. Basically, 1 is added to the unit basket in which the cell is input, but if the first unit basket in the output port table is behind the unit basket in which the cell is input, the unit basket cell pointed to by the first unit basket in the output port table Add 1 to the number. Accordingly, in FIG. 35, for the output port # 1, 1 is added to the number of unit basket cells of the second unit basket pointed to by the first unit basket. For the output port #N, 1 is added to the number of unit basket cells of the first unit basket that is the unit basket into which cells are input.
[0464]
Furthermore, FIG. 36 shows the operation when a cell arrives. The output ports of newly arrived cells are # 1 and # 2. This cell is a VC cell currently stored in the inter-VC fair queue 460. In the case of FIG. 36, a new unit basket is provided at the end of the inter-VC fair queue 460, and this cell is input to the unit basket.
[0465]
Further, FIG. 37 shows an operation when the KM is instructed to transfer the unit basket to the output port #N. The number of unit basket cells of the head unit basket of port #N is added to the number of basket cells to make the number of unit basket cells zero. Further, 1 is subtracted from the number of cargo cells of port #N, and 1 is added to the number of output-permitted cells. The number of cells transferred to KM is 1 for output port #N. The pointer of the head unit basket in the output port table is advanced by one to the next unit basket of the VC fair queue 460.
[0466]
Since the output ports of the leading cells of the inter-VC fair queue 460 are # 1 and #N, and the number of output-permitted cells of # 1 and #N is 1 or more (specifically 2 and 1), respectively. If the class multiplexing FIFO 436 permits, the cell can be output.
[0467]
FIG. 38 shows a state when cells are output. The number of output permitted cells corresponding to the output port of the output cell is subtracted by one.
[0468]
FIG. 39 shows a state in which unit baskets and basket transfers are instructed continuously as described above, and a total of 6 cells are output. The head unit basket of the inter-VC fair queue 460 becomes empty at this point, and the unit basket and the number of unit basket cells disappear. Inevitably, the head unit basket in the output port table does not point to this lost unit basket. Next, the output port selection scheduler 432 will be described with reference to FIG.
[0469]
The cell selection unit 470 selects a unicast output waiting cell and a multicast output waiting cell for each output port, which are input to the output port selection scheduler 432, and outputs them from the output port selection scheduler 432. Cells that are candidates for selection by the cell selection unit 470 are allowed cells among the output waiting cells.
[0470]
The output of the unicast cell is permitted by the unicast cell output permission signal output from the unicast cell output permission signal generation unit 471.
[0471]
The unicast cell output permission signal generation unit 471 receives the back pressure signal and the emergency back pressure signal.
[0472]
The back pressure signal is for each output port. In addition, the back pressure signal corresponding to the emergency back pressure signal is determined in advance. In the case of FIG. 25, the emergency back pressure signal is output from SE2, and corresponds to the back pressure signal from the output buffer OB connected to the output link of SE2.
[0473]
When the back pressure signal indicates prohibition of output, the unicast cell output permission signal does not permit the output of the cell at the output port. When the emergency back pressure signal indicates that output is prohibited, it is assumed that all back pressure signals corresponding to the emergency back pressure signal indicate that output is prohibited, and output is not permitted.
[0474]
The multicast cell is permitted to be output by the multicast cell output permission signal output from the multicast cell output permission signal generation unit 472.
[0475]
The multicast cell output permission signal generation unit 472 receives the unicast cell output permission signal and the output port information of the first cell of the multicast cell class multiplexing FIFO 436.
[0476]
The multicast cell output permission signal generation unit 472 monitors whether all (not necessarily simultaneously) the output ports of the multicast cell are permitted. If any output port is not permitted, the multicast cell output permission signal is prohibited. When all the output ports of the multicast cell are permitted, the output of the multicast cell is permitted during the time when the unicast cell output permission signal of the last permitted output port indicates that output is possible. If the multicast cell is not selected by the cell selection unit 470 within the time, and if the multicast cell is selected and output by the cell selection unit 470 and the output port information of a new multicast cell arrives, it is output again from the beginning. Monitor whether all ports are allowed.
[0477]
The cell selection unit 470 selects the output waiting cell thus permitted to output in a fair manner.
[0478]
As described above, the multicast cell is output even if all the back pressure signals of the output port do not permit the output at the same time. That is, at the time of output of the multicast cell, some back pressure signals at the output port of the cell may indicate output prohibition. Even in such a situation, the low-priority cell emergency back pressure signal works effectively so that the SE2 buffer does not overflow.
[0479]
In the above configuration, when the output of the low priority cell emergency back pressure signal indicates prohibition, the output of both the unicast cell and the multicast cell for the corresponding output port is prohibited. As another configuration, the multicast cell output permission signal generation unit 472 may perform a process of canceling permission when a low priority cell emergency backpressure signal instructs prohibition of output even if a certain output port is permitted once. . In addition, when the low priority emergency back pressure signal indicates that output is prohibited, the output of all low priority multicast cells may be prohibited.
[0480]
The input buffer IB of the present invention performs back pressure consideration queue monitoring described with reference to FIG. This monitoring is performed based on the value of the back pressure identifier updated by the back pressure signal. The back pressure identifier for each output port of the unicast cell is updated by the unicast cell output permission signal of the output port selection scheduler 432, and the back pressure identifier of the multicast cell is updated by the multicast cell output permission signal of the output port selection scheduler 432.
[0481]
Next, with reference to FIG. 41, the basket management unit KM used for the basket switch shown in FIG. 25 will be described.
[0482]
FIG. 41 shows a configuration example of the basket management unit KM.
[0483]
KM for each output port
-Total number of ABR input cells.
[0484]
-For each class, the total number of previous basket cells, the total number of basket cells, and the number of transferred cells.
[0485]
• Total number of class multiplexed FIFO cells.
[0486]
And a transfer instruction history management unit 480 and a class selection scheduler 481 for each output port.
[0487]
The total number of ABR input cells is the total number of input cells of all IBs for each output port for the ABR class. Integration is performed within a certain period of time, and transmitted to the IB paired with the output port for each cycle. If the total number of ABR input cells exceeds a certain threshold before reaching a predetermined fixed time, a configuration may be used in which the IB is notified interruptively.
[0488]
The total number of previous basket cells is obtained by adding the total number of cells input to the previous basket based on the presence / absence of cells input to the IB and the class information. In addition, the number of previous baskets in the class to which KM has instructed transfer is updated with the sum of all IBs. The class is stored in the transfer instruction history management unit 480 of the KM.
[0489]
The total number of basket cells is updated with the total number of basket cells of all classes for which the KM has instructed transfer. The transfer instruction history management unit 480 of the KM stores the class instructing the transfer.
[0490]
The number of transfer cells is updated by adding the number of transfer cells to the class multiplexed FIFO of the class to which KM has instructed transfer for all IBs. The transfer instruction history management unit 480 of the KM stores the class instructing the transfer.
[0491]
The total number of class multiplexed FIFO cells is updated by adding the number of class multiplexed FIFO cells for all IBs.
[0492]
The class selection scheduler 381 issues a transfer instruction to the IB based on information such as the total number of previous basket cells, the total number of basket cells, the total number of transfer cells, and the total number of class multiplexed FIFO cells. The history of past transfer instructions is stored in the transfer instruction history management unit 480, and the class selection scheduler 481 corrects the cell number information using the history.
[0493]
42, 43, and 44 show an example of a scheduling algorithm executed by the class selection scheduler 481 of the basket management unit KM. This algorithm performs priority control based on priority while limiting the maximum bandwidth of a class and guaranteeing the minimum bandwidth.
[0494]
As a global variable, there is a variable now indicating the current time. For each class i, a parameter Dxi that gives the upper limit of the minimum bandwidth 1 / Di and the output duty time Tdi and Tdi, and a parameter Uxi that gives the lower limit of the maximum bandwidth 1 / Ui and the output inhibition time Tui and Tui are set (FIG. 42). Step S100).
[0495]
For each class i, if it should be output, the current time now is Tdi < This is the time when the output is prohibited, and when the current time now is now <Tui. If output is to be performed according to priority, the current time now is Tui. < This is when now <Tdi. Tdi has an upper limit, and Tdi < now + Dxi. Tui has a lower limit, and now-Uxi. < Tui. However, Uxi > 0, Dxi > Di.
[0496]
In the initial setting, now is set to zero, Tdi is set to Di-Ui for each class i, and Tu is set to now, that is, zero (step S101 in FIG. 42).
[0497]
This algorithm performs the following processing for each cell period.
[0498]
First, the process when the class becomes active is performed. Specifically, when a cell arrives at class i where there is no cell, Tdi is updated to the greater of now and Tdi, and Tu is updated to the greater of now and Tui (step S102 in FIG. 43).
[0499]
Next, it is determined whether or not the cell can be transferred (step S103 in FIG. 43). If so, transfer class selection and transfer class instruction are performed (step S104 in FIG. 43).
[0500]
The transfer class selection is the following process.
[0501]
Within each class i where there are cells to be transferred,
1. Tdi < If there is a class that is now, the class with the largest now-Tdi is selected (if it is the same value, it is determined by the priority).
[0502]
2. Tdi < If there is no class that is now, Tui < The class having the highest priority is selected from the classes satisfying now <Tdi.
[0503]
If the selected class is j, the process proceeds to step S105 in FIG. 44, and the following transfer class instruction process is performed.
[0504]
1. Instruct transfer of class j.
[0505]
2. Update Tuj to max (Tuj, now-Uxj).
[0506]
3. Update Tdj to Tdj + Dj.
[0507]
4). Updated Tuj to Tuj + Uj.
[0508]
5. Tdj is updated to min (Tdj, now + Dxj).
[0509]
Finally, after performing the transfer cell flow rate monitoring process (step S106 in FIG. 44), the value of “now” is incremented (step S107 in FIG. 44), and the process for each cell cycle is completed.
[0510]
The transfer cell flow rate monitor process in step S106 of FIG. 44 performs the following process for class j when the number of transfer cells of class j is xj.
[0511]
1. Update Tuj to max (Tuj, now-Uxj).
[0512]
2. Update Tdj to Tdj + (xj -1) Dj.
[0513]
3. Update Tuj to Tuj + (xj-1) Uj.
[0514]
4). Tdj is updated to min (Tdj, now + Dxj).
[0515]
The determination in step S103 in FIG. 43 as to whether or not to instruct transfer of cells is made based on whether or not the total number of class multiplexed FIFO cells is equal to or less than a certain threshold value. A certain threshold is usually “1”. The total number of class multiplexed FIFO cells is a value corrected by the transfer instruction history of the transfer instruction history management unit 480.
[0516]
In step S104 in FIG. 43, whether or not there is a cell to be transferred to the class is determined by determining that either the total number of previous basket cells or the total number of basket cells is not zero. The total number of previous basket cells and the total number of basket cells are values corrected by the transfer instruction history of the transfer instruction history management unit 480.
[0517]
The transfer instruction is a cell transfer instruction from the basket 440 to the class multiplexing FIFO 434 (transfer instruction T2 in FIG. 31). At this time, whether or not to instruct the transfer of the unit basket from the previous basket to the basket at the same time is determined by determining whether the total number of previous basket cells is not zero and whether the total number of basket cells is equal to or less than a certain threshold. . A certain threshold is usually 1. The total number of previous basket cells and the total number of basket cells are values corrected by the transfer instruction history of the transfer instruction history management unit 480.
[0518]
This algorithm can bring the minimum guaranteed bandwidth closer to zero by setting Di to a large number. For example, if Di of all classes is set to a large number, priority control of all classes can be performed with complete priority.
[0519]
Further, by using one of the classes as an IC (Idle Cell) class having the lowest priority but the minimum guaranteed bandwidth, the usage rate of the output port can be controlled. The IB inserts an idle cell into the class multiplexing FIFO when there is an IC class transfer instruction (only one IB is required).
[0520]
The idle cell is exchanged towards the output port of the cell switch like the other cells, where it is replaced with the Unassigned Cell. The KM may perform scheduling assuming that the IC class always has a cell to be transferred.
[0521]
Incidentally, in the algorithms shown in FIGS. 42 to 44, for the sake of simplicity of explanation, it is assumed that variables that represent time such as variables now, Tdi, and Tui do not have upper limits. At the time of implementation, these variables are expressed by a register having a finite bit length, so that the same time appears cyclically after a long time. In order to operate the algorithm normally, the following may be performed. Let these cycles be Max. Max needs to be large enough.
[0522]
At this time, calculation such as x: = f (x) is
x: = f (x) mod Max
Replace with In other words, take modulo with Max. Y < The comparison operation of z is
(Z < y-Max / 2) or ((y < z) and (z < y + Max / 2))
Replace with and compare.
[0523]
For example, the calculation now: = now + 1 is
now: = (now + 1) mod Max
Replace with Tdi < The comparison operation now is
(Now < Tdi −Max / 2) or ((Tdi < now) and (now < Compare with Tdi + Max / 2)).
[0524]
It is necessary to periodically monitor the time variable and adjust it so that it is not too far from Max / 2 or more as needed. However, by increasing Max, the monitoring cycle can be extended. Easy to implement.
[0525]
Further, as the other class selection scheduling, the following is effective.
[0526]
As already described, the cell buffer device that has performed inter-VC fair queuing according to the weight set for each CG (each VC) writes the weight to the CG table (FIG. 30) of the input buffer IB or Nx of the VC table. .
[0527]
Here, it is explained that the weight for each VC set in the class can be multiplied by a coefficient by using the class selection scheduling together.
[0528]
There are class A and class B, and the weight Nxa of a certain VC set to class A is set to Nxb. At this time, when there are output waiting cells in both classes, the number of unit basket transfer instructions is scheduled to be the ratio of Ra to Rb in class X and class Y by class selection scheduling. It is possible to multiply the coefficient by × Ra and Nxb × Rb. The same applies to three or more classes. For example, SCFQ (Self-Clocked Fair Queuing) is known as an algorithm for performing scheduling so as to obtain a desired ratio.
[0529]
A specific example will be described. For example, assume that weights are set to 1.24, 3.72, 2.18, 934, 562, 1370, and 4360 for seven VCs from VC1 to VC7, respectively. VC1 and 2 are set in class A, and Nx is 1.24 and 3.72, respectively. VC3 is set for class B, and Nx is 2.18. VC4 and 5 are set in class C, and Nx is set to 9.34 and 5.62, respectively. VC6 and 7 are set in class D, and Nx is set to 1.37 and 4.36, respectively. If class selection scheduling is performed so that the number of unit basket transfer instructions is in a ratio of class A: class B: class C: class D = 1: 1: 100: 1000 between classes in which output waiting cells exist, Cells are multiplexed to the output port with weights 1.24: 3.72: 2.18: 934: 562: 1370: 4360. This method has an effect of avoiding the phenomenon that the cell delay fluctuation of the inter-VC fair queuing increases when a large numerical value is set as the value of Nx.
[0530]
In the class selection scheduling algorithm as shown in FIGS. 42 to 44, the transfer cell flow rate of each class is monitored. It is possible to perform hierarchical class selection scheduling using this.
[0531]
When there is a class group Ga consisting of classes A1, A2, A3,... And a class group Gb consisting of other classes B1, B2, B3,. Is set as Ra vs. Rb, and class selection scheduling is performed. The same applies when the class group is 3 or more. Class selection scheduling within each class group and selection scheduling between class groups are independent.
[0532]
As a result, the surplus bandwidth between certain class groups is used only by the classes in the class group, and it can be prevented that another class group can be used. Another class group can use this surplus bandwidth only when there is no output waiting cell of a certain class group. This kind of hierarchical class selection scheduling. For example, an application such as assigning a class group for each company can be considered.
[0533]
5.2 Method of correcting the number of cells in a cell switch that performs priority control and fair queuing between VCs
Next, a method for correcting the number of cells in the cage management unit KM of the cell switch (cage switch) (FIGS. 25, 29, and 31) that performs priority control and fair queuing between VCs will be described with reference to FIG.
[0534]
As for the principle of correction, in the case of the cage switch described with reference to FIGS. 19, 20, etc., it is possible to improve the performance of priority control and the throughput of the output port by correcting the number of cells by the same method.
[0535]
As an application example of the cell number correction method of the present invention, the present invention is applied to the car switch shown in FIG. In the basket switch, when the management unit 301 instructs transfer to the front basket (Bpi) of class i, the cells of the front basket of the class are transferred to the basket (Bki), and a part thereof is a class multiplexed FIFO (Bm ). When the management unit 301 instructs transfer from the class i basket to the class multiplexing FIFO, the cell of the class basket is transferred to the class multiplexing FIFO.
[0536]
As shown in FIG. 45, the cell number information and delay time of each cell buffer are determined.
[0537]
Hpi is the number of HOLs transferred from the previous basket to the basket by the transfer instruction Ipi, and Hpmi is the number of HOL cells transferred from the previous basket to the class multiplexing FIFO by the transfer instruction Ipi.
[0538]
Here, as an example, consider the case where the values of the delay times are equal. That is, DOp = DIk = DOk = DIm = Dipm = D and DTpm = DTkm. Further, p = [− D, 0). At this time, the number of cells before the class i and the modified number of cells (N′pi, N′ki) of the basket and the number of modified cells (N′m) of the class multiplexing FIFO can be calculated as follows.
[0539]
[Expression 7]

[0540]
5.3 Continuation of description of cell switch according to tenth embodiment
FIG. 46 shows a connection example between the input buffer IB of the basket switch and the basket management unit KM.
[0541]
Here, for example, the number of classes is 62 classes, and the cell switch size is 16 inputs and 16 outputs.
[0542]
The class number is coded in {0, 1, 2,..., 60, 61, UC, IC} and 6 bits.
[0543]
Class UC indicates an unassigned cell, IC indicates an idle cell, and usage thereof will be described below.
[0544]
The previous number of basket cells, the number of basket cells, and the number of class multiplexed FIFO cells are coded as {0, 1, 2,..., 13, 14, 15 or more} and 4 bits.
[0545]
The transfer information from the input buffer IB to the basket management unit KM is shown below.
[0546]
(1) Input cell For each output port, for the input cell (in the case of unicast, output only for one output port),
・ Presence / absence of input cell and class: 6 bits
(If there is no input cell, send class UC)
(3) Transfer instruction class For transfer instruction class for each output port,
-Number of previous Kago cells after transfer ... 4 bits
・ Number of Kago cells after transfer: 4 bits
-Number of cells transferred to class multiplexing FIFO: 2 bits
(Up to two unicast and multicast cells are transferred)
(4) Class multiplexing FIFO Only unicast for each output port.
Class multiplexed FIFO cell count: 4 bits
In total, the information about one output port is 20 bits.
[0547]
The transfer information broadcast from the basket management unit KM to all the input buffers IB is shown below.
[0548]
(2) For each output port,
・ Instruction for transferring the unit basket from the previous basket to the basket (for the following classes): 1 bit
-Cell transfer instruction from basket to class multiplexing FIFO, instruction class ... 6 bits
(If no transfer instruction is given, the UC class is specified. If the IC class is specified, the IB transfers (inserts) an idle cell. The idle cell is exchanged and transferred to the output port in the same manner as other classes of cells. (It is a cell for throughput adjustment that is replaced with an Unassigned Cell at the time of output from the switch.)
In total, the information about one output port is 7 bits.
[0549]
The KM transmits the next signal to the corresponding IB for each output port for ABR traffic control.
[0550]
(5) Out of all IB input cells, the number of ABR input cells for each output port: 5 bits
(In the case of 16 input 16 output cell switch)
Information about one output port is 5 bits.
[0551]
FIG. 46 shows a configuration example in which the basket management unit KM is realized by two LSIs. One of the two LSIs manages output ports # 1 to # 8, and the other manages output ports # 9 to # 16.
[0552]
Since the transfer information from the IB to the KM (the above (1), (3) and (4)) is 20 bits per output port, it is 160 bits for 8 ports. If parallel transmission is performed using two pairs of high-speed differential transmission, a transmission rate of 80 bits per cell period is sufficient.
[0553]
Broadcast information from the KM to the IB (the above-mentioned (2)) is 7 bits per output port, so it is 56 bits for 8 ports. If a normal transmission driver is used to perform 8 parallel transmissions, a transmission rate of 7 bits per cell period is sufficient.
[0554]
The information for the ABR traffic control from the KM to the IB (the above (5)) is 5 bits per output port.
[0555]
Even considering a cell switch with a cell transmission rate of 622 Mbps, these transmission rates are sufficiently realizable with current technology.
[0556]
The IB transmits the cell number information to the KM from the LSB (least significant digit), thereby reducing the circuit scale for adding the number of cells. This is because the adder circuit can add information on the number of cells transmitted from all IBs in order from the lower digit (for each class for each output port). More specifically, the addition circuit can calculate the sum of the digits of the input digit and the carry from the lower digits calculated so far, and obtain the value of that digit of the addition result. In addition, it holds the carry for the next digit calculation.
[0557]
Among the signals from IB to KM is the number of class multiplexed FIFO cells. When the cell switch with back pressure can output the number of accumulated cells per output port (number of cells in the output buffer OB in FIG. 25), the KM stores the number of accumulated cells per output port instead of the number of class multiplexed FIFO cells. May be used.
[0558]
This has the same effect as the cell multiplexing apparatus that performs priority control between classes in FIG. 2 and the cell multiplexing apparatus that performs fair VC queuing in FIG.
[0559]
FIG. 47 shows a path of information for realizing the ABR service.
[0560]
FIG. 47 particularly shows a part where the ABR class cell input from port # 1 to port #N is exchange-multiplexed to port #i by the cell switch 400 with back pressure. Actually, all the output ports have the same configuration as #i in this figure.
[0561]
The ABR service is a service class in which, if there is a band that can be used at the output port of the cell switch, the band is distributed and used fairly by the ABR class VC. An RM cell transmitted from the receiving terminal to the transmitting terminal is used for traffic control.
[0562]
The cell switch 400 knows the bandwidth that the ABR can use at the output port #i, and performs traffic control on the transmitting terminal by knowing the ratio (or difference) between the bandwidth and the input traffic of the current ABR. Can do. The current ABR traffic can be known from the sum of the number of input cells destined for port #i for each fixed period shown in FIG. An input band is obtained from the number of input cells, and if this exceeds the usable band of ABR at the output port, it is overloaded. Therefore, an instruction to reduce the VC band may be written in the RM cell input to port #i. Conversely, if the input band obtained from the number of input cells destined for port #i is less than the band where the ABR can be used at the output port, the load is low. An instruction to increase the bandwidth may be written. By knowing the ratio or difference between the input band and the output band, the degree of overload and low load can be known, and fine control can be performed.
[0563]
This process reduces the probability of congestion, but if the congestion is detected by monitoring the queue length in the IB, the traffic can be controlled more safely by marking the EFCI or rewriting the RM cell. Is possible. In particular, in the case of multicast, there is a possibility of overload even if the input bandwidth is smaller than the output bandwidth. In this case, traffic control by monitoring queue length becomes important.
[0564]
As described above, since the cage switch according to the tenth embodiment performs fair queuing between VCs, it is possible to achieve fair bandwidth distribution among VCs even in traffic control based on queue length monitoring.
[0565]
【The invention's effect】
As described above, according to the packet transfer apparatus (first and second embodiments (claims 1, 2, 3, 4)) for performing priority control between classes according to the present invention, the control unit (class management) Each of the input buffers in order to give an instruction by grasping the situation of the plurality of input buffers (which may be grasped at least for each input buffer). The priority relationship between classes does not collapse due to the difference in the storage status of each class, and priority control between classes can be easily realized even if the number of input ports, that is, the number of input buffers is increased.
[0566]
Further, in order to perform fair queuing between VCs (flows) across a plurality of input buffers, for example, the control means for all VCs (flows) of all input buffers, the input port numbers, VC numbers, and packet Controlling the output order of packets by grasping the arrival status, output status, and the like complicates the device configuration and makes it difficult to improve throughput. Therefore, according to the packet transfer apparatus (third, fourth, and fifth embodiments (claims 5 and 6)) of the present invention, packets to be output within a certain phase (the time length is indefinite). Each input buffer shares the process of introducing the concept of a collection (cargo), selecting packets to be included in this packet collection, and outputting only the packets contained in this packet collection (other packets are not allowed to be output) In addition, when the basket management unit shares the process of instructing the timing of inserting a new packet into the packet set, for example, in an input buffer type cell switch, fair queuing between VCs (flows) can be easily realized.
[0567]
Further, according to the packet transfer apparatus of the present invention (sixth and seventh embodiments (claims 7 and 8)), when the control means (buffer pointer management unit) receives a packet, Since distribution is performed and only a pointer belonging to one set needs to be output when packets are output, for example, even if the number of VCs to be set increases, an output for fair queuing between VCs (flows) is performed. The selection of the packet to be realized can be realized.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration example of a cell multiplexing apparatus that performs priority control between classes according to a first embodiment of the present invention;
FIG. 2 is a diagram showing another configuration example of a cell multiplexing apparatus that performs priority control between classes according to the second embodiment of the present invention;
FIG. 3 is a diagram showing another configuration example of the output buffer.
FIG. 4 is a diagram showing still another configuration example of the output buffer.
FIG. 5 is a diagram showing a configuration example of an output buffer type cell multiplexing apparatus including a per-VC FIFO according to a third embodiment of the present invention.
FIG. 6 is a diagram showing a configuration example of a cell multiplexing apparatus that performs inter-VC fair queuing according to the fourth embodiment of the present invention.
FIG. 7 is a diagram showing a configuration example of a cell multiplexing apparatus that performs inter-VC fair queuing according to the fifth embodiment of the present invention;
FIG. 8 is a diagram showing a configuration example of a cell buffer device using a cell group FIFO according to a sixth embodiment of the present invention.
FIG. 9 is a diagram showing a configuration example of a cell buffer device using a cell group FIFO according to a seventh embodiment of the present invention.
FIG. 10 is a diagram for explaining an example of a data structure using a pointer chain of a cell group FIFO according to the sixth embodiment.
FIG. 11 is a diagram for explaining an example of a data structure using a pointer chain of a cell group FIFO according to the sixth embodiment, showing a configuration of an empty cell group chain.
FIG. 12 is a diagram for explaining an example of a data structure using a pointer chain of a cell group FIFO according to the seventh embodiment.
FIG. 13 is a diagram for explaining an example of a data structure using a pointer chain of a cell group FIFO according to the seventh embodiment, and shows a configuration of an empty cell group chain.
FIG. 14 is a diagram for explaining inter-flow fair queuing using a packet group;
FIG. 15 is a diagram for explaining the operation of the packet buffer device using fair queuing between flows using a packet group;
FIG. 16 is a diagram illustrating back pressure consideration queue monitoring according to an eighth embodiment of the present invention.
FIG. 17 is a diagram showing a configuration example of a cell buffer device having a back pressure consideration queue monitoring unit according to an eighth embodiment.
FIG. 18 is a flowchart showing a back pressure consideration queue monitoring algorithm according to the eighth embodiment.
FIG. 19 is a diagram showing a configuration example of a cell buffer device considering delay according to a ninth embodiment of the present invention.
FIG. 20 is a diagram for explaining a basic principle of a cell number information correction method considering delay.
FIG. 21 is a diagram for explaining another basic principle of the cell number correction method;
FIG. 22 is a diagram for explaining a basic function f () used in the cell number correction method of FIG. 21;
FIG. 23 is a diagram for explaining a basic function g () used in the cell number correction method of FIG. 21;
FIG. 24 is a diagram for explaining a basic function Sc () used in the cell number correction method of FIG. 21;
FIG. 25 is a diagram showing an example of the overall configuration of a basket switch according to a tenth embodiment of the present invention.
26 is a diagram showing a configuration example of the output buffer in FIG. 25. FIG.
27 is a diagram showing a configuration example of a first stage unit switch in FIG. 25. FIG.
28 is a diagram showing a configuration example of the second stage unit switch of FIG. 25. FIG.
29 is a diagram showing a configuration example of the input buffer in FIG. 25. FIG.
FIG. 30 is a diagram for explaining queuing processing of an input buffer;
FIG. 31 is a diagram showing an interface with the basket management unit of the input buffer of FIG. 25;
32 is a diagram for explaining the operation of the multicast cell management unit for each class in FIG. 29;
33 is a diagram for explaining the operation of the class-specific multicast cell management unit of FIG. 29;
34 is a diagram for explaining the operation of the class-specific multicast cell management unit of FIG. 29;
FIG. 35 is a diagram for explaining the operation of the class-by-class multicast cell management unit in FIG. 29;
36 is a diagram for explaining the operation of the class-by-class multicast cell management unit in FIG. 29;
FIG. 37 is a diagram for explaining the operation of the class-specific multicast cell management unit of FIG. 29;
38 is a view for explaining the operation of the class-by-class multicast cell management unit in FIG. 29;
FIG. 39 is a diagram for explaining the operation of the class-by-class multicast cell management unit in FIG. 29;
40 is a diagram showing a configuration example of an output port selection scheduler in FIG. 29. FIG.
41 is a diagram showing a configuration example of a basket management unit in FIG. 25. FIG.
42 is a flowchart showing a specific example of a scheduling algorithm for limiting the maximum bandwidth and guaranteeing the minimum bandwidth, which is executed by the class selection scheduler of the basket management unit in FIG. 41. FIG.
43 is a flowchart showing a specific example of a scheduling algorithm for limiting the maximum bandwidth and guaranteeing the minimum bandwidth, which is executed by the class selection scheduler of the basket management unit in FIG. 41. FIG.
44 is a flowchart showing a specific example of a scheduling algorithm for limiting the maximum bandwidth and guaranteeing the minimum bandwidth, which is executed by the class selection scheduler of the basket management unit in FIG. 41. FIG.
FIG. 45 is a diagram for explaining an operation of a basket switch that is an application example of the cell number information correction method;
46 is a diagram showing a specific example of connection between the input buffer and the basket management unit in FIG. 25;
FIG. 47 is a diagram showing a specific example of an information path for an ABR service.
FIG. 48 is a diagram for explaining unfair bandwidth allocation in a conventional UBR service.
FIG. 49 is a diagram for explaining the configuration of a conventional cell multiplexing apparatus that performs priority control between classes.
FIG. 50 is a diagram for explaining the configuration of a conventional cell multiplexing apparatus having an input buffer.
FIG. 51 is a diagram for explaining a configuration of a cell buffer device that needs to search a conventional VC table;
FIG. 52 is a diagram for explaining a change in queue length of the input buffer in the cell multiplexing apparatus having the conventional input buffer as shown in FIG. 50;
FIG. 53 is a diagram for explaining the configuration of a conventional cell multiplexing apparatus that performs priority control.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Input buffer, 11 ... Output buffer, 12 ... Class management part, 212, 222 ... Basket management part, 230, 240 ... Buffer pointer management part, 282 ... Queue monitoring part, 302 ... Transfer instruction history, KM ... Basket management part 400: Cell switch with back pressure.

Claims (8)

A packet transfer apparatus comprising a plurality of input buffers for temporarily storing input packets, control means for controlling the input buffers, and at least one output port for transferring packets output from the input buffers. There,
Each input buffer includes a storage unit for each class that temporarily stores input packets for each class;
Output means for outputting packets of the class instructed by the control means from the storage means to the output port;
The control means includes
The storage status of all of the plurality of input buffers of the storage means is grasped for each class, a class to which a packet is to be output is determined based on the storage status, and an instruction including designation of the determined class is given to the plurality of input buffers A packet transfer apparatus for transmitting to a packet. The output port includes an output buffer for temporarily storing packets output from the input buffer,
2. The packet transfer apparatus according to claim 1, wherein the output means outputs a packet toward the output port in accordance with an accumulation state of the packet in the output buffer. The output means comprises multiplexing means for multiplexing the packets output from the storage means and outputting the multiplexed packets to the output port;
In addition to the accumulation status, the control means grasps the multiplexing status in the entire plurality of input buffers of the multiplexing means, and determines a class to output a packet based on the accumulation status and the multiplexing status. The packet transfer apparatus according to claim 1.   The input buffer selects a packet to be output from the storage means so that packet transfer is fair between virtual connections to which each packet belongs within the same class across a plurality of input buffers. Item 4. The packet transfer apparatus according to Item 1. A packet transfer apparatus comprising a plurality of input buffers for temporarily storing input packets, control means for controlling the input buffers, and at least one output port for transferring packets output from the input buffers. There,
Each of the input buffers is
Storage means for temporarily storing input packets;
In response to an instruction from the control unit, a selection unit that selects a packet to be output from the storage unit to the output port in the next phase;
Output means for outputting the packet selected by the selection means to the output port;
The control means includes
Packet transfer characterized by grasping the output status of the packet selected by the selecting means in the whole of the plurality of input buffers and instructing the plurality of input buffers to select a new packet based on the output status apparatus. The selection means of each input buffer is respectively
6. The packet transfer apparatus according to claim 5, wherein a packet to be output from the storage means is selected so that packet transfer is fair between virtual connections to which each packet belongs. A packet transfer apparatus comprising: a buffer for temporarily storing input packets; a control means for controlling the buffer; and at least one output port for transferring packets output from the buffer.
The control means includes
Management means for managing the packets accumulated in the buffer by dividing them into a plurality of sets;
Distribution means for distributing the packets input to the buffer to any one of the plurality of sets so as to be fair among the flows to which the packets belong;
Instruction means for instructing the buffer to output a packet belonging to one of the plurality of sets managed by the management means to the output port;
A packet transfer apparatus comprising:   The distribution unit is configured to set the plurality of sets of packets input to the buffer based on identification information of a flow to which the packet belongs and at least one of a weight determined for each flow and a length of the input packet. The packet transfer apparatus according to claim 7, wherein the packet transfer apparatus is assigned to any one of the following.

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