JP3628311B2 - Viterbi decoding device, communication system, and viterbi decoding method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is used in the field of digital broadcasting, digital communication, and the like, and particularly relates to a Viterbi decoding device that decodes multilevel modulated data and a wireless communication system using the Viterbi decoding device.
[0002]
[Prior art]
Japanese Patent No. 3230995 discloses a technique of using a general-purpose Viterbi decoding circuit for binary modulation such as QPSK without using a Viterbi decoding circuit for multilevel modulation when Viterbi decoding a multilevel modulation signal. By eliminating the need for a Viterbi decoding circuit for multilevel modulation, the cost of the apparatus is reduced.
[0003]
In the invention disclosed in this publication, all n bits of 1 symbol n bits are Viterbi-decoded. However, in general, in the signal point arrangement of the multilevel modulation signal, the Euclidean distance between the signal points on the upper bit side having the same bit string as the lower bits is made larger than that of the lower bits. That is, if the lower bits are determined, the minimum distance between the upper bits is ensured to some extent. Therefore, the upper bits are less prone to error, and there is little deterioration in characteristics when Viterbi decoding is used and when Viterbi decoding is not used. In addition, if the signal is subjected to the code modulation method in which only m bits of n bits are encoded, it is sufficient to perform Viterbi decoding only of m bits from which a coding gain can be obtained.
[0004]
[Problems to be solved by the invention]
As in Japanese Patent No. 3230995, when all the bits constituting one symbol are decoded by a Viterbi decoding device, the error rate characteristics are good, but the amount of calculation increases and the time required for decoding also increases. Incurs complexity and decoding delay.
[0005]
On the other hand, Japanese Patent No. 3230995 describes that it can be applied to trellis coded modulation in which all n bits are not coded. However, there is no disclosure about a specific configuration of the Viterbi decoding device in that case. It has not been.
[0006]
Further, when decoding a code-modulated signal, G. Unverboeck's "Trellis-coded modulation with redundant signal sets part II: State of the art, 'Significant signal as described in the most common signal, as well as the most common signal in the IEEE Communications Magazin. 1987. Subset decoding is required to calculate the metric with the signal point, in which case the distance between all the signal point candidates and the received signal point must be calculated, and the amount of calculation related to this increases the number of modulation multi-values. To become a huge amount about.
[0007]
The present invention has been made in view of these points, and an object of the present invention is to provide a Viterbi decoding apparatus that has good error rate characteristics and can perform Viterbi decoding with a small amount of calculation.
[0008]
[Means for Solving the Problems]
In order to solve the above-described problems, the present invention encodes m (m is an integer, 0 ≦ m <n) bits of n (n is an integer of 1 or more) bits per symbol. A Viterbi decoding device that performs Viterbi decoding on multilevel modulation data obtained by multilevel modulation of encoded data and (n−m) bit input data excluding the m bits, wherein the multilevel modulation data The lower 2k (k is an integer equal to or greater than 1) bit signal point arrangement is similar to the lower (2k + 1) to lower 4k bit signal point arrangement, and the multilevel corresponding to the lower 2k bits of the encoded data A conversion unit that converts modulation data into first soft decision data, a first Viterbi decoding unit that generates first Viterbi decoding data based on the first soft decision data, and the first Viterbi decoding data To re-encode the first A first re-encoder for generating encoded data, and second soft decision data corresponding to the lower 4k bits from the lower (2k + 1) bits of the encoded data based on the first re-encoded data And a second Viterbi decoding unit that generates second Viterbi decoded data based on the second soft decision data, and a second re-encoding by re-encoding the second Viterbi decoded data. A second re-encoder that generates data; and a determination unit that identifies input data before multi-level modulation based on the first and second re-encoded data and the multi-level modulation data. .
[0009]
In the present invention, only the lower-order bits of the multilevel modulation data are Viterbi-decoded, and the higher-order bits are hard-decided. As a result, the configuration of the apparatus can be simplified, and the Viterbi decoding calculation process can be speeded up.
[0010]
An encoder that encodes m (m is an integer, 0 ≦ m <n) bits of input data of n (n is an integer of 1 or more) bits per symbol to generate encoded data; A multi-level modulator that generates multi-level modulation data by multi-level modulation of (n−m) -bit input data excluding m bits and the encoded data, and a radio transmitter that wirelessly transmits the multi-level modulation data A radio receiver that receives the multilevel modulation data transmitted from the radio transmitter, and a Viterbi decoding device that performs Viterbi decoding on the multilevel modulation data, wherein the Viterbi decoding device includes: The signal point arrangement of the lower 2k (k is an integer of 1 or more) bits of the multilevel modulation data is similar to the signal point arrangement of the lower (2k + 1) bits to the lower 4k bits, and corresponds to the lower 2k bits of the encoded data. The multi-level modulation data Is converted into first soft decision data, a first Viterbi decoding unit that generates first Viterbi decoded data based on the first soft decision data, and the first Viterbi decoded data is A first re-encoder for encoding to generate first re-encoded data, and corresponding to lower 4k bits from lower (2k + 1) bits of the encoded data based on the first re-encoded data A calculator for generating second soft decision data; a second Viterbi decoder for generating second Viterbi decoded data based on the second soft decision data; and re-encoding the second Viterbi decoded data Based on the second re-encoder for generating second re-encoded data and the first and second re-encoded data and the multi-level modulated data, the input data before multi-level modulation is And a determination unit to be identified.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a Viterbi decoding apparatus and a wireless communication system according to the present invention will be specifically described with reference to the drawings.
[0012]
(First embodiment)
FIG. 1 is a schematic block diagram showing an example of a radio communication system according to the present invention. The wireless communication system of FIG. 1 includes an encoding modulator 1, a wireless transmission device 2, a wireless reception device 3, a Viterbi decoding device 4, and a parallel / serial converter 5.
[0013]
The encoding modulator 1 maps input data to a complex plane (IQ plane), and generates a complex baseband signal. The complex baseband signal is wirelessly transmitted from the wireless transmission device 2 and received by the wireless reception device 3. The reception signal received by the wireless reception device 3 is Viterbi decoded by the Viterbi decoding device 4, converted into serial data by the parallel / serial converter 5, and output.
[0014]
FIG. 2 is a block diagram showing an example of the internal configuration of the coding modulator 1 of FIG. 1, and the coding modulator 1 that encodes the lower 2 bits of 64QAM (64 Quadrature Amplitude Modulation) using a convolutional encoder. The internal structure is shown. Note that the encoding method is not limited to that shown in FIG.
[0015]
The encoding modulator 1 in FIG. 2 includes a serial / parallel converter 11 that converts input data into parallel data, an encoder 12 that encodes the least significant bit, and a signal point mapper 13 that generates a complex baseband signal. And have.
[0016]
The serial / parallel converter 11 performs serial / parallel conversion on the input data and outputs parallel data x0 to x4. Of the parallel data x0 to x4, the least significant bit x0 is input to the encoder 12, and the other bits x1 to x4 are input to the signal point mapper 13.
[0017]
The encoder 12 adds 1 redundant bit and outputs 2-bit encoded data y0 and y1. The signal point mapper 13 performs mapping to the I axis and the Q axis based on the output signals y0 to y5 from the encoder 12 and the serial / parallel converter 11, and outputs a complex baseband signal.
[0018]
FIG. 3 is a block diagram showing an example of the internal configuration of the Viterbi decoding device 4 of FIG. The Viterbi decoding device 4 in FIG. 3 includes conversion units 21a and 21b that convert a complex baseband signal into a binary modulation signal, a Viterbi decoding circuit 22 for QPSK, and a re-encoder 23 that re-encodes Viterbi decoded data. And a determination unit 24 that makes a hard decision on the higher-order bits of the complex baseband signal.
[0019]
Of the complex baseband signals, I-phase and Q-phase baseband signals are converted into binary soft decision data by the converters 21a and 21b, respectively.
[0020]
FIG. 4 is a diagram showing the signal point arrangement of the coding modulation apparatus according to the first embodiment, and shows a part of the signal point arrangement of 64QAM. The number described above each signal point indicated by “◯” in FIG. 4 is a bit string of the signal point, and the numbers on the I-phase and Q-phase axes represent the signal reception level.
[0021]
For example, focusing on the least significant bit y0, as the Q-phase reception level increases from 1 to 4, this bit changes in the order of 0 → 1 → 1 → 0. For this reason, if a conversion table is created for each reception level, the conversion units 21a and 21b have values in the range from “0” to “1” according to the reception level in a predetermined procedure. Soft decision data can be output.
[0022]
The data converted by the converters 21a and 21b can be regarded as the same as the data subjected to QPSK modulation. For this reason, the multi-level modulation signal is decoded by the QPSK Viterbi decoding circuit 22 by inputting the I-phase and Q-phase soft decision data to the QPSK Viterbi decoding circuit 22 as the I-phase and Q-phase, respectively. Can do. The decoded data x0 output from the Viterbi decoding circuit 22 corresponds to the least significant bit of the parallel data output from the serial / parallel converter 11, that is, the lower 1 bit of 64QAM.
[0023]
The determination unit 24 performs a hard decision on the higher-order bits of the complex baseband signal based on the decoded data x0 decoded by the Viterbi decoding circuit 22 and the complex baseband signal. Instead of the least significant bit x0, it is generated based on the encoded bits y0 and y1. Therefore, the decoded data x0 decoded by the Viterbi decoding circuit 22 is once encoded by the re-encoder 23 to generate encoded bits y0 and y1, and the encoded bits y0 and y1 are input to the determination unit 24.
[0024]
Based on the higher-order bits y2 to y5 of the complex baseband signal and the encoded bits y0 and y1 from the re-encoder 23, the determination unit 24 outputs the point having the smallest Euclidean distance on the signal point as the received signal point To do. This process is called a hard decision process.
[0025]
Thus, in the first embodiment, only the lower-order bits of the complex baseband signal are converted into soft decision data and Viterbi-decoded by the QPSK Viterbi decoding circuit 22, and the higher-order bits of the complex baseband signal are determined by the decision unit. Since the hard decision is performed at 24, the calculation processing time can be greatly reduced as compared with the case where Viterbi decoding is performed for all bits.
[0026]
In general, when a signal that has been coded and modulated is received, a large computational load is applied to subset decoding for determining a candidate of a received signal point from a reception point. However, since subset decoding is not necessary, conventional coding coding is used. The amount of calculation for subset decoding, which has been a problem, can be greatly reduced. Further, since it is not necessary to use the Viterbi decoding circuit 22 for multilevel modulation, the manufacturing cost of the entire apparatus can be reduced.
[0027]
In the first embodiment described above, the Viterbi decoding circuit 22 for QPSK is used, but a Viterbi decoding circuit 22 for BPSK may be used.
[0028]
(Second Embodiment)
The second embodiment is different from the first embodiment in the signal point arrangement. FIG. 5 is a diagram showing a part of the signal point arrangement of the coding modulation apparatus according to the second embodiment. As shown in the figure, the lower 2 bits are arranged in a natural code. That is, the least significant bit y0 changes from 0 → 1 → 0 → 1 as the Q-phase reception level increases, but is not affected by the change in the I-phase reception level. The adjacent bit y1 changes from 0 → 1 → 0 → 1 as the I-phase reception level increases, but is not affected by the change in the Q-phase reception level.
[0029]
FIG. 6 is a block diagram showing an internal configuration of the Viterbi decoding device 4 in the second embodiment. The Viterbi decoding device 4 of FIG. 6 includes a conversion unit 21, a QPSK Viterbi decoding circuit 22, a re-encoder 23, and a determination unit 24. In FIG. 3, the converters 21a and 21b are provided corresponding to each of the I phase and the Q phase, but in FIG. 6, one converter 21 is shared by the I phase and the Q phase.
[0030]
The reason why the converter 21 can be shared is that, as shown in FIG. 5, the bit pattern changes with respect to the reception level change in both the y0 bit and the y1 bit. For this reason, binary soft decision data for each of the I phase and the Q phase can be output using the same conversion unit 21.
[0031]
FIG. 7 is a diagram for explaining a soft decision technique performed by the QPSK Viterbi decoding circuit 22. The value of the signal point repeats 0 and 1 alternately, and the reception level indicated by the black circle is always a value between 0 and 1.
[0032]
As described above, in the second embodiment, since the change in the bit pattern with respect to the change in the reception level is made common to the y0 bit and the y1 bit, the conversion unit 21 can be shared by the I phase and the Q phase. Therefore, the entire apparatus can be realized at a lower price and smaller than a known apparatus such as Japanese Patent No. 3230995.
[0033]
(Third embodiment)
The third embodiment is described in Imai, Hirakawa et al., “A new multilevel coding method using error-correcting codes,” IEEE Trans. On Info., Vol. IT-23, No. 3, pp. 371-377. The method described in this well-known document such as Imai et al. Requires subset decoding for each level, and the calculation increases as the level to be encoded increases. Although the amount increases significantly, the third embodiment is characterized in that the amount of calculation can be reduced.
[0034]
FIG. 8 is a block diagram showing an example of a multi-level encoding modulator 1 for 64QAM in the third embodiment. 8 includes a serial / parallel converter 11a, two encoders 12a and 12b, and a signal point mapper 13a.
[0035]
The serial / parallel converter 11a converts the input data into parallel data x0 'to x3', the least significant bit x0 'is input to the encoder 12a, and the adjacent bit x1' is input to the encoder 12b. . The encoded data y0 and y1 encoded by the encoder 12a, the encoded data y2 and y3 encoded by the encoder 12b, and the parallel data x2 ′ and x3 ′ are input to the signal point mapper 13a and input to the IQ plane. Mapped above.
[0036]
FIG. 9 is a diagram showing a part of the signal point arrangement of the coding modulation apparatus according to the third embodiment. The lower 2 bits of each signal have a natural code arrangement as in the second embodiment. In the area surrounded by the dotted line in FIG. 9, the lower 3 and 4 bits y2 and y3 are equal in the area, and the bit pattern combination of y2y3 is equal to the bit pattern combination of y1y0. That is, 01, 11, 10, 00. As described above, the signal point arrangement of the lower 1 and 2 bits of the signal and the signal point arrangement of the lower 3 and 4 bits are similar.
[0037]
FIG. 10 is a block diagram showing an example of a Viterbi decoding device 4 that decodes the above-described multilevel encoded modulation signal. The Viterbi decoding device 4 in FIG. 10 includes a conversion unit 21, QPSK Viterbi decoding circuits 22a and 22b, re-encoders 23a and 23b, a calculation unit 25, and a determination unit 24a.
[0038]
Of the complex baseband signal encoded by the encoding modulator 1 in FIG. 8, the I-phase signal and the Q-phase signal corresponding to the input data bit x0 are input to the conversion unit 21 as in the second embodiment. And converted into binary soft decision data. The binary soft decision data is input to the QPSK Viterbi decoding circuit 22a and Viterbi decoded. The Viterbi decoded signal is encoded by the re-encoder 23a to generate encoded data y0 and y1 corresponding to the input data bit x0.
[0039]
The calculation unit 25 generates an I-phase signal and a Q-phase signal corresponding to the input data bit x1 by the following calculation procedure. Suppose that the received signal point is at the position s in FIG. The converter 21 outputs I-phase binary soft decision data d1 and Q-phase binary soft decision data d2 corresponding to the input data bit x1. These data d1 and d2 are equal to the distance between the I phase and the Q phase between the signal D having the lower 2 bits of 0 and the reception signal point s within the dotted line to which the reception signal point belongs. As in the embodiment, soft decision data can be output using a conversion table.
[0040]
Here, it is assumed that the lower 2 bits of the output of the re-encoder 23 are both 1. The signal points whose lower 2 bits are 1 are the four signal points E0, E1, E2, and E3 in FIG. At this time, the binary soft decision data for decoding x1 ′ is equivalent to obtaining the I-phase and Q-phase distances between the reception signal point s and the signal point E0.
[0041]
The signal point E0 is a point where the third bit and the fourth bit are 0 among the signal points whose lower 2 bits are 1. The distance e1 in the I phase and the distance e2 in the Q phase between the reception signal point s and the signal point E0 are expressed by the equations (1) and (2), respectively.
[0042]
e1 = 1-d1 + (α2-α0) (1)
e2 = 1-d2 + (β2-β0) (2)
α and β indicate coordinates of the signal points E0 to E3 relating to the I phase and the Q phase. A value obtained by dividing e1 and e2 by 2 is input to the QPSK Viterbi decoding circuit 22 as binary soft decision data. In other words, the binary soft decision data relating to the signal x1 ′ can be calculated using the binary soft decision data relating to the lower two bits calculated by the conversion unit 21.
[0043]
It should be noted that the calculation formulas represented by the formulas (1) and (2) can be uniquely determined from the signal point arrangement and the received signal level of the lower 2 bits. The upper bit decoding method and the decoding method of uncoded bits are the same as in the second embodiment, and the encoded bits y0 to y3 re-encoded by the re-encoders 23a and 23b and the higher-order bits of the complex baseband signal Based on the above, the determination unit 24a performs a hard determination.
[0044]
As described above, in the third embodiment, when Viterbi decoding a multilevel encoded modulation signal, each lower bit is converted into binary soft decision data and Viterbi decoded, and hard decision is performed on the other bits. Therefore, the calculation amount of subset decoding for calculating soft decision data from the received signal point to the signal point candidate for each level encoder 12a, 12b can be greatly reduced.
[0045]
In the above-described embodiment, the multilevel encoding modulator 1 that encodes only the lower 2 bits of the parallel data corresponding to the input data is used. However, the present invention can be similarly applied to the case of encoding the lower 3 bits or more. is there. For example, among input data of n (n is an integer of 1 or more) bits, m (m is an integer, 0 ≦ m <n) bits encoded data and m bits are excluded (n−m) bits In the case of multi-level modulation data obtained by multi-level modulation of the input data, the low-order (2k + 1) (k is an integer of 1 or more) bits to the low-order 2k-bit signal point arrangement of the multi-level modulation data It should be similar.
[0046]
【The invention's effect】
As described above in detail, according to the present invention, only the lower-order bits of multi-level modulation data are Viterbi-decoded and the upper-order bits are hard-decision. A Viterbi decoding unit can be used, and the manufacturing cost of the entire apparatus can be reduced, and the Viterbi decoding calculation process can be speeded up.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram showing an example of a wireless communication system according to the present invention.
2 is a block diagram showing an example of an internal configuration of the encoding modulator 1 of FIG. 1. FIG.
FIG. 3 is a block diagram showing an example of an internal configuration of the Viterbi decoding device 4 of FIG. 1;
FIG. 4 is a diagram showing a signal point arrangement of the coding modulation apparatus according to the first embodiment.
FIG. 5 is a diagram showing a part of signal point arrangement of a coding modulation apparatus according to a second embodiment.
FIG. 6 is a block diagram showing an internal configuration of a Viterbi decoding device 4 in the second embodiment.
FIG. 7 is a diagram for explaining a soft decision technique performed by the QPSK Viterbi decoding circuit 22;
FIG. 8 is a block diagram showing an example of a 64-QAM multilevel encoding modulator 1 according to a third embodiment.
FIG. 9 is a diagram showing a part of signal point arrangement of a coding modulation apparatus according to a third embodiment.
FIG. 10 is a block diagram illustrating an example of a Viterbi decoding device 4 that decodes the multilevel encoded modulation signal described above.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Code | symbol modulator 2 Wireless transmitter 3 Wireless receiver 4 Viterbi decoder 5 Parallel-serial converter 11, 11a Serial-parallel converter 12, 12a, 12b Encoder 13, 13a Signal point mapper 21, 21a, 21b Conversion Unit 22 QPSK Viterbi Decoding Circuit 23, 23a, 23b Re-encoder 24, 24a, 24b Determination Unit

Claims (9)

Of the input data of n (n is an integer of 1 or more) bits per symbol, m (m is an integer and 0 ≦ m <n) bits are encoded and the m bits are excluded (n− m) A Viterbi decoding device that performs Viterbi decoding on multi-level modulation data obtained by multi-level modulation of bit input data,
The signal point arrangement of lower 2k (k is an integer of 1 or more) bits of the multilevel modulation data is similar to the signal point arrangement of lower (2k + 1) bits to lower 4k bits ,
A conversion unit that converts the multi-level modulation data corresponding to the lower 2k bits of the encoded data into first soft decision data;
A first Viterbi decoding unit that generates first Viterbi decoded data based on the first soft decision data;
A first re-encoder for re-encoding the first Viterbi decoded data to generate first re-encoded data;
A calculation unit that generates second soft decision data corresponding to lower 4k bits from lower (2k + 1) bits of the encoded data based on the first re-encoded data;
A second Viterbi decoding unit that generates second Viterbi decoded data based on the second soft decision data;
A second re-encoder for re-encoding the second Viterbi decoded data to generate second re-encoded data;
A Viterbi decoding device comprising: a determination unit that identifies input data before multi-level modulation based on the first and second re-encoded data and the multi-level modulation data. The multi-level modulation data is a complex baseband signal mapped on a complex plane composed of an I phase and a Q phase,
The Viterbi decoding device according to claim 1, wherein the conversion unit is provided corresponding to each of the I phase and the Q phase. The multi-level modulation data is a complex baseband signal mapped on a complex plane composed of an I phase and a Q phase,
The Viterbi decoding apparatus according to claim 1, wherein the same conversion unit is used in both the I phase and the Q phase. 2. The Viterbi decoding apparatus according to claim 1, wherein the multilevel modulation data is generated such that a bit value is not affected by at least one reception level of an I phase and a Q phase. 5. The Viterbi decoding apparatus according to claim 1, wherein k is 1. An encoder that encodes m (m is an integer and 0 ≦ m <n) bits of n (n is an integer of 1 or more) bits per symbol to generate encoded data;
A multi-level modulator that multi-level modulates (n−m) -bit input data excluding the m bits and the encoded data to generate multi-level modulation data;
A wireless transmitter for wirelessly transmitting the multilevel modulation data;
A radio receiver for receiving the multi-level modulation data transmitted from the radio transmitter;
A Viterbi decoding device that performs Viterbi decoding on the multi-level modulation data,
The Viterbi decoding device
The signal point arrangement of lower 2k (k is an integer of 1 or more) bits of the multilevel modulation data is similar to the signal point arrangement of lower (2k + 1) bits to lower 4k bits,
A converter for converting the multi-level modulation data corresponding to the lower 2k bits of the encoded data to the first soft-decision data,
A first Viterbi decoding unit that generates first Viterbi decoded data based on the first soft decision data;
A first re-encoder for re-encoding the first Viterbi decoded data to generate first re-encoded data;
A calculation unit that generates second soft decision data corresponding to lower 4k bits from lower (2k + 1) bits of the encoded data based on the first re-encoded data;
A second Viterbi decoding unit that generates second Viterbi decoded data based on the second soft decision data;
A second re-encoder for re-encoding the second Viterbi decoded data to generate second re-encoded data;
A wireless communication system comprising: a determination unit that identifies input data before multi-level modulation based on the first and second re-encoded data and the multi-level modulation data . The wireless communication system according to claim 1, wherein k is one. Of the input data of n (n is an integer of 1 or more) bits per symbol, m (m is an integer and 0 ≦ m <n) bits are encoded and the m bits are excluded (n− m) A Viterbi decoding method for performing Viterbi decoding on multi-level modulated data obtained by multi-level modulation of bit input data,
The signal point arrangement of lower 2k (k is an integer of 1 or more) bits of the multilevel modulation data is similar to the signal point arrangement of lower (2k + 1) bits to lower 4k bits ,
Converting the multi-level modulation data corresponding to the lower 2k bits of the encoded data into first soft decision data;
Generating first Viterbi decoded data based on the first soft decision data;
Re-encoding the first Viterbi decoded data to generate first re-encoded data;
Generating second soft decision data corresponding to the lower 4k bits from the lower (2k + 1) bits of the encoded data based on the first re-encoded data;
Generating second Viterbi decoded data based on the second soft decision data;
Re-encoding the second Viterbi decoded data to generate second re-encoded data;
A Viterbi decoding method comprising: identifying input data before multi-level modulation based on the first and second re-encoded data and the multi-level modulation data. 9. The Viterbi decoding method according to claim 8, wherein k is 1.

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