JP3564505B2 - Method for manufacturing semiconductor device - Google Patents

Description

【００２６】
その後、プラズマＣＶＤ法によって、厚さ５００ｎｍのアモルファスシリコン膜を堆積し、これをパターニングして、島状シリコン領域２０３を形成した。さらに、窒素雰囲気に４００℃、３０分放置することによって、水素出しをおこなった。そして、図２（Ａ）に示すようにレーザーアニールをおこなって、結晶化させた。レーザーにはＫｒＦエキシマーレーザー（波長２４８ｎｍ、パルス幅２０ｎｓｅｃ）を用いた。エネルギー密度は２００〜３５０ｍＪ／ｃｍ^２ とした。また、レーザー照射時には基板温度を３００〜５００℃、例えば４５０℃に保った。
【００２７】
その後、図２（Ｂ）に示すように、この島状シリコン領域２０３を覆って、ゲイト絶縁膜として厚さ１０００Åの酸化珪素膜２０４をＴＥＯＳ、酸素、ＴＣＥを原料とする陽光柱方式プラズマＣＶＤ法によって形成した。成膜に先立って、基板の前処理をおこなった。用いた装置は図１に示したものと同じである。前処理の主な条件を以下に示す。

続いて、成膜をおこなった。主な成膜条件は以下の通りである。また、成膜後、アルゴン雰囲気、５５０℃で１時間のアニールをおこなった。

【００２８】
次に、シリコンを２％ドープしたアルミニウム膜を６０００Å堆積し、これをパターニングしてゲイト電極２０５を形成した。そして、図２（Ｃ）に示すように不純物イオン（燐やホウ素）をプラズマドーピング法によって、ゲイト電極２０５をマスクとして自己整合的に導入し、不純物領域２０６、２０７を形成した。不純物が形成されなかった領域はチャネル形成領域２０８となる。ドーピングはゲイト絶縁膜を通しておこなわれるので、燐の場合は８０ｋＶの、また、ホウ素の場合は６５ｋＶの加速電圧が必要であった。また、ドーズ量は１×１０^１５〜４×１０^１５ｃｍ^−２が適当であった。
【００２９】
その後、図２（Ｄ）に示すように、再びレーザーアニール法によって、不純物の活性化をおこなった。レーザーにはＫｒＦエキシマーレーザー（波長２４８ｎｍ、パルス幅２０ｎｓｅｃ）を用いた。エネルギー密度は２００〜３５０ｍＪ／ｃｍ^２ とした。また、レーザー照射時には基板温度を３００〜５００℃に保ってもよい。レーザー照射終了後、０．１〜１気圧の分圧の水素雰囲気、３５０℃で３５分間のアニールをおこなった。
【００３０】
次に、層間絶縁物として厚さ５０００Åの酸化珪素膜２０９を堆積した。酸化珪素膜２０９はＴＥＯＳ、酸素、ＴＣＥを原料とする陽光柱方式プラズマＣＶＤ法によって形成した。用いた装置は図１に示したものと同じである。主な成膜条件は以下の通りである。

【００３１】
そして、層間絶縁物にコンタクトホール２１０、２１１を形成し、アルミニウムによってＴＦＴのソース、ドレインに電極２１２、２１３を形成した。アルミニウムの代わりにチタン、窒化チタンを用いてもよい。以上によってＴＦＴを完成することができた。得られたＴＦＴの歩留りはゲイト絶縁膜のステップカバレージが改善されたことと、ゲイト絶縁膜の信頼性が向上したために歩留りが著しく改善された。
【００３２】
【発明の効果】
本発明によって、得られる酸化珪素膜がゲイト絶縁膜として十分に信頼性に優れていることは以上に述べたとおりである。しかも、信頼性だけでなく、歩留りの向上にも寄与することが明らかになった。また、特に実施例に示したような陽光柱方式のプラズマＣＶＤ装置を用いることによって量産性も改善できる。このように本発明は産業上、有益な発明である。
【図面の簡単な説明】
【図１】実施例に用いられた陽光柱方式ＣＶＤ装置の概念図を示す。
【図２】実施例におけるＴＦＴの作製工程図を示す。
【図３】実施例において得られた絶縁被膜の耐圧特性を示す。
【図４】実施例において得られた絶縁被膜のΔＶ_ＦＢ特性を示す。
【符号の説明】
１０１ ・・・チャンバー
１０２、１０３・・・ＲＦ電源
１０４ ・・・位相シフター
１０５、１０６・・・マッチングボックス
１０７、１０８・・・電極
１０９ ・・・コンテナー
１１０ ・・・基板ホルダー
１１１ ・・・基板
１１２、１１３・・・電極ホルダー
１１４、１１５・・・ヒーター（赤外線ランプ）[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for obtaining a gate insulating film used in a thin film device such as an insulating gate type field effect transistor at a low temperature of 650 ° C. or less, and an insulating film thus obtained.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in a thin film device such as a thin film type insulated gate field effect transistor (TFT), after forming crystalline silicon, the surface is thermally oxidized at a high temperature of 900 to 1100 ° C. to obtain silicon oxide having good characteristics. And using it as a gate insulating film.
[0003]
The features of such a thermal oxide film are summarized in that the interface state density is extremely low and that it can be formed with a uniform thickness on the surface of crystalline silicon. That is, the former provides good on / off characteristics and long-term reliability for bias / temperature, and the latter reduces short circuits between the gate electrode and the semiconductor region (active layer) at the edge of the island-like semiconductor region. As a result, the yield was improved.
[0004]
[Problems to be solved by the invention]
However, when such a thermal oxide film is used, a material that can withstand high temperatures must be selected as a substrate material. In this regard, an inexpensive glass material (non-alkali glass such as Corning 7059) could not be used, and this was disadvantageous in that the cost increased particularly when a large-area substrate was used. In recent years, a technology for forming a TFT on an alkali-free glass substrate is under development. However, in such a technology, a thermal oxide film cannot be used, and a physical method such as a sputtering method, a plasma CVD method, or a reduced pressure CVD method is used. A gate insulating film has been formed by chemical or chemical vapor deposition.
[0005]
However, the characteristics of the silicon oxide film formed by such means were inferior to those of the thermal oxide film. That is, the interface state density is generally large, and there is always a danger that alkali ions such as sodium may enter during film formation. In addition, since step coverage (step coverage) was not so good, short-circuiting between the gate electrode and the active layer at the edge of the island-shaped semiconductor region frequently occurred. For this reason, it has been extremely difficult to obtain a material that satisfies all of the characteristics, reliability, and yield.
[0006]
The present invention has been made to solve at least one of these problems. That is, in the present invention, a method for producing a silicon oxide film having good step coverage is provided. In the present invention, a silicon oxide film having resistance to alkali ions and other undesired impurities and a silicon oxide film having the same are provided. Methods for making are provided.
[0007]
[Means for Solving the Problems]
A first aspect of the present invention is that silicon oxide obtained by a plasma CVD method using a mixed gas containing an organic silane having an ethoxy group, oxygen, and hydrogen chloride or a hydrocarbon containing chlorine as a material gas as a gate insulating film. Is characterized by using a film containing as a main component.
A second aspect of the present invention is a plasma CVD method in which a mixed gas containing an organic silane having an ethoxy group, oxygen, and a fluorine-containing gas (for example, NF ₃ or C ₂ F ₆ ) is used as a gate insulating film. Characterized by using a film containing silicon oxide as a main component obtained by the method described above.
[0008]
Here, examples of the organic silane having an ethoxy group include a chemical formula of Si (OC ₂ H ₅ ) ₄ (tetraethoxysilane, hereinafter referred to as TEOS), Si ₂ O (OC ₂ H ₅ ) ₆ , and Si ₃ O ₂ ( Substances represented by OC ₂ H ₅ ) ₈ , Si ₄ O ₃ (OC ₂ H ₅ ) ₁₀ , and Si ₅ O ₄ (OC ₂ H ₅ ) ₁₂ are preferable. Such an organic silane material takes a long time to migrate on the surface of the substrate and forms a silicon oxide film by decomposition on the surface. Therefore, a coating film having good wraparound to the concave portion and excellent step coverage can be obtained.
[0009]
Further, as the hydrocarbon containing chlorine, a substance represented by a chemical formula of C ₂ HCl ₃ (trichloroethylene), C ₂ H ₃ Cl ₃ (trichloroethane), or CH ₂ Cl ₂ (dichloromethane) is preferable. Such a gas containing chlorine is mainly decomposed in the gas phase and combines with an alkali element such as sodium existing in the film formation atmosphere to separate from the substrate and accelerate the desorption of the alkali element from the silicon oxide film. I do. Some of the chlorine atoms remain in the silicon oxide film, which functions as a barrier against alkali elements that subsequently enter from the outside. As a result, the reliability of the TFT can be improved. The concentration of the hydrocarbon containing chlorine is preferably 0.01 to 1% of the whole. Addition of a concentration of 1% or more adversely affects the characteristics.
[0010]
In the insulating film containing silicon oxide as a main component obtained by the above method, a halogen element (for example, fluorine or chlorine) as an impurity element in secondary ion mass spectrometry is 1 × 10 ^{17 to} 5 × 10 ²⁰ cm. ^-3 , while carbon is also present at a concentration of 5 × 10 ¹⁹ cm ⁻³ or less. In particular, in order to lower the interface state density, it is desired that the concentration of carbon be 1 × 10 ¹⁸ cm ⁻³ or less. In order to reduce the concentration of carbon, the substrate temperature during film formation may be set to 200 ° C. or higher, preferably 300 ° C. or higher.
[0011]
Furthermore, since the insulating film formed in this manner tends to cause a large number of dangling bonds to precipitate in the early stage of its formation, the underlying semiconductor film (preferably one containing silicon as a main component) is preliminarily treated with oxygen. Should be exposed to a plasma atmosphere containing As a result, the interface state density is reduced, the fluctuation of the flat band voltage in the bias / temperature test is reduced, and the reliability is improved. In this case, even more effects can be obtained by mixing a material containing hydrogen chloride or chlorine such as trichloroethylene, trichloroethane, or dichloromethane in addition to oxygen.
[0012]
On the other hand, after forming an insulating film containing silicon oxide as a main component by the above-described method, a heat treatment at 200 to 650 ° C. could also reduce the fluctuation of the flat band voltage. In this case, it is preferable to perform the treatment in an atmosphere having no oxygen such as argon or nitrogen. The fluctuation of the flat band voltage was remarkably reduced particularly by the heat treatment at 450 ° C. or higher, and was saturated at 600 ° C. or higher.
[0013]
A third aspect of the present invention is to cover the non-single-crystal semiconductor region after exposing the island-shaped non-single-crystal semiconductor region containing silicon as a main component to a plasma atmosphere containing oxygen and a hydrocarbon containing hydrogen chloride or chlorine. In addition, a film containing silicon oxide as a main component is formed by a plasma CVD method using an organic silane having an ethoxy group and oxygen as materials.
[0014]
In this case, hydrocarbons containing hydrogen chloride or chlorine are mainly accumulated in the chamber during the plasma treatment, and hydrocarbons containing hydrogen chloride or chlorine are mixed in the first invention during the subsequent film formation of silicon oxide. Has the same effect as The improvement in reliability by the plasma processing is the same as described above. Further, good results were obtained when the concentrations of chlorine and carbon in the obtained silicon oxide film were set to the same values as in the first invention. Further, when a heat treatment is performed at 200 to 650 ° C., preferably 450 to 600 ° C. after the formation of the film containing silicon oxide as a main component, even better results are obtained.
[0015]
The plasma CVD apparatus used in the present invention has a generally used parallel plate type (that is, a structure in which a set of plate electrodes are opposed to each other in a chamber, and a sample substrate is disposed on one or both electrodes). ) Or a positive column type as shown in the embodiment.
[0016]
The latter has two advantages over the former. That is, first, in the former, the amount of the substrate that can be processed at one time is determined by the area of the electrode, whereas in the latter, the amount is determined by the discharge volume. Second, in the former, plasma damage on the substrate surface is large, whereas in the latter, plasma potential is scarce because there is almost no potential gradient, and since uniformity is good, the TFT characteristics and yield are adversely affected. Is less likely to occur.
[0017]
Note that a chamber of a plasma CVD apparatus used for film formation needs to be sufficiently cleaned to reduce alkali elements such as sodium. To clean the chamber, plasma may be generated after introducing chlorine, hydrogen chloride, or a hydrocarbon containing chlorine as described above and oxygen into the chamber. In this case, if the inside of the chamber is heated to 150 ° C. or higher, preferably 300 ° C. or higher, a further effect can be obtained.
[0018]
【Example】
In this embodiment, a method of forming a silicon oxide film as a gate insulating film on a non-single-crystal semiconductor film of island-shaped silicon by a positive column type plasma CVD method, and mainly an electrical It is related to various characteristics. The used plasma CVD apparatus has a vertical section (cross section shown in FIG. 1) and a horizontal section (top view shown in FIG. 1) as shown in FIG. The positive column system is characterized in that a substrate is arranged in a positive column region in plasma discharge to form a coating.
[0019]
Power for generating plasma is supplied from RF power sources 102 and 103. A radio wave represented by 13.56 MHz is generally used as a frequency. The power supplied from the two power supplies is adjusted by the phase shifter 104 and the matching boxes 105 and 106 so that the state of the plasma is optimized. The power supplied from the RF power source is disposed in parallel inside the chamber 101, reaches a pair of electrodes 107 and 108 protected by the electrode covers 112 and 113, and discharge occurs between the electrodes. A substrate is set between the electrodes 107 and 108. The substrate 111 is placed in a container 109 and set on both sides of the sample holder 110 in the container to improve mass productivity. The feature is that the substrate is disposed horizontally between the electrodes. The substrate is heated by an infrared lamp 114 and maintained at a suitable temperature. Although not shown in the drawing, this device is also provided with an exhaust device and a gas supply device.
[0020]
First, the film forming conditions and the characteristics of the obtained film will be described. The substrate temperature was 300 ° C. Further, 300 SCCM of oxygen, 15 SCCM of TEOS, and 2 SCCM of trichlorethylene (hereinafter, referred to as TCE) were introduced into the chamber. The RF power is 75 W and the total pressure is 5 Pa. After the film formation, annealing was performed at 350 ° C. for 35 minutes in a hydrogen atmosphere.
[0021]
FIG. 3 shows the results of a dielectric breakdown test of a 1000-nm-thick silicon oxide film formed on a high-resistance silicon wafer using this apparatus. A 1 mmφ aluminum electrode was formed on the silicon oxide film, and the voltage-current relationship was plotted. FIG. 3C shows a film formed without performing any special treatment on the substrate and having a low withstand voltage. However, after setting the substrate in the chamber, the substrate temperature was set to 300 ° C., oxygen was supplied at 400 SCCM, TCE was flown at 0 to 5 SCCM, and the substrate was exposed to a plasma atmosphere at a total pressure of 5 Pa and an RF power of 150 W for 10 minutes (gas phase reaction in this step). After that, a film was not formed.) Then, when a silicon oxide film was successively deposited, a silicon oxide film having a good withstand voltage was obtained as shown in FIG.
However, when the flow rate of TCE at the time of forming the silicon oxide film was increased to 4 SCCM or more, for example, 5 SCCM, a film having a low withstand voltage was obtained as shown in FIG. From this result, it became clear that there is an optimum value for the concentration of TCE.
[0022]
FIG. 4A shows, as one of the reliability tests, the relationship between the variation (ΔV _FB ) of the flat band voltage (V _FB ) by the bias / temperature application test and the substrate pretreatment. In the bias / temperature test, a voltage of +17 V was applied to the sample at 150 ° C. for 1 hour, then its CV characteristics were measured at room temperature, and further a voltage of −17 V was applied at 150 ° C. for 1 hour, and then at room temperature. The CV characteristics were measured, and the difference between V _FB in the two measurements was evaluated as ΔV _FB .
[0023]
In the sample not subjected to the pretreatment (in FIG. 4A, indicated by (a)), ΔV _FB showed a relatively large value at around 5V. However, it was improved by performing pretreatment. The preprocessing conditions of (b) and (c) of FIG. 4A are shown below.
Sample (b) (c)
Substrate temperature 300 ℃ 300 ℃
TCE / oxygen 0/400 0.5 / 400
RF power 150W 150W
Processing time 10 minutes 10 minutes From FIG. 4, it was confirmed that further improvement was observed by performing the pre-treatment of the substrate using TCE.
[0024]
Similar improvements can be obtained by performing annealing after film formation. Annealing was performed for 1 hour at 300 to 570 ° C. in an argon atmosphere at 1 atm. FIG. 4B shows the relationship between the annealing temperature and ΔV _FB . In particular, a decrease in ΔV _FB is observed at a temperature of 450 ° C. or less, and it can be seen that there is a tendency to approach a constant value as the temperature approaches 600 ° C. From this, it was clarified that annealing after film formation contributed to improvement in reliability.
[0025]
Using the results obtained from the above experiment, a TFT was manufactured. The process is shown in FIG. First, an underlying silicon oxide film 202 having a thickness of 2000 .ANG. Was formed on a substrate (Corning 7059) 201 by a positive column plasma CVD method using TEOS, oxygen, and TCE as raw materials. The equipment used is the same as that shown in FIG. The main conditions are as follows.

[0026]
Thereafter, an amorphous silicon film having a thickness of 500 nm was deposited by a plasma CVD method, and this was patterned to form an island-shaped silicon region 203. Further, hydrogen was discharged by leaving the substrate in a nitrogen atmosphere at 400 ° C. for 30 minutes. Then, as shown in FIG. 2A, laser annealing was performed to crystallize. The laser used was a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec). The energy density was 200 to 350 mJ / cm ² . During laser irradiation, the substrate temperature was kept at 300 to 500C, for example, 450C.
[0027]
Thereafter, as shown in FIG. 2B, a silicon oxide film 204 having a thickness of 1000 Å as a gate insulating film is covered with the island-shaped silicon region 203 by a positive column type plasma CVD method using TEOS, oxygen and TCE as raw materials. Formed by Prior to film formation, pretreatment of the substrate was performed. The equipment used is the same as that shown in FIG. The main conditions for preprocessing are shown below.

Subsequently, a film was formed. The main film forming conditions are as follows. After the film formation, annealing was performed at 550 ° C. for 1 hour in an argon atmosphere.

[0028]
Next, an aluminum film doped with 2% of silicon was deposited at 6000 ° and this was patterned to form a gate electrode 205. Then, as shown in FIG. 2C, impurity ions (phosphorus or boron) were introduced in a self-aligned manner by a plasma doping method using the gate electrode 205 as a mask to form impurity regions 206 and 207. The region where the impurity is not formed becomes the channel formation region 208. Since doping is performed through the gate insulating film, an accelerating voltage of 80 kV for phosphorus and an accelerating voltage of 65 kV for boron are required. Further, the dose amount was appropriately 1 × 10 ¹⁵ to 4 × 10 ¹⁵ cm ⁻² .
[0029]
After that, as shown in FIG. 2D, the impurity was activated again by the laser annealing method. The laser used was a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec). The energy density was 200 to 350 mJ / cm ² . During laser irradiation, the substrate temperature may be kept at 300 to 500 ° C. After the laser irradiation, annealing was performed at 350 ° C. for 35 minutes in a hydrogen atmosphere of a partial pressure of 0.1 to 1 atm.
[0030]
Next, a 5000 nm thick silicon oxide film 209 was deposited as an interlayer insulator. The silicon oxide film 209 was formed by a positive column plasma CVD method using TEOS, oxygen, and TCE as raw materials. The equipment used is the same as that shown in FIG. The main film forming conditions are as follows.

[0031]
Then, contact holes 210 and 211 were formed in the interlayer insulator, and electrodes 212 and 213 were formed in the source and drain of the TFT using aluminum. Titanium or titanium nitride may be used instead of aluminum. Thus, the TFT was completed. The yield of the obtained TFT was remarkably improved because the step coverage of the gate insulating film was improved and the reliability of the gate insulating film was improved.
[0032]
【The invention's effect】
As described above, the silicon oxide film obtained by the present invention has sufficiently high reliability as a gate insulating film. And it became clear that it contributes not only to reliability but also to improvement in yield. In particular, mass productivity can be improved by using a positive column type plasma CVD apparatus as shown in the embodiment. Thus, the present invention is an industrially useful invention.
[Brief description of the drawings]
FIG. 1 shows a conceptual diagram of a positive column CVD apparatus used in Examples.
FIG. 2 shows a manufacturing process of a TFT in an example.
FIG. 3 shows withstand voltage characteristics of an insulating film obtained in an example.
FIG. 4 shows a ΔV _FB characteristic of an insulating film obtained in an example.
[Explanation of symbols]
101: chambers 102, 103: RF power supply 104: phase shifters 105, 106: matching boxes 107, 108: electrodes 109: container 110: substrate holder 111: substrate 112, 113: Electrode holder 114, 115: Heater (infrared lamp)

Claims (11)

Forming a semiconductor region on the substrate,
Forming a gate insulating film having silicon oxide as a main component and a carbon concentration of 5 × 10 ¹⁹ cm ⁻³ or less and a halogen element concentration of 1 × 10 ^{17 to} 5 × 10 ²⁰ cm ⁻³ on the semiconductor region; ,
Forming a gate electrode on the gate insulating film;
Forming an interlayer insulating film containing silicon oxide as a main component on the gate electrode,
The method for manufacturing a semiconductor device, wherein the gate insulating film and the interlayer insulating film are formed using organic silane. Forming a base insulating film on the substrate,
Forming a semiconductor region on the base insulating film,
Forming a gate insulating film having silicon oxide as a main component and a carbon concentration of 5 × 10 ¹⁹ cm ⁻³ or less and a halogen element concentration of 1 × 10 ^{17 to} 5 × 10 ²⁰ cm ⁻³ on the semiconductor region; ,
Forming a gate electrode on the gate insulating film;
Forming an interlayer insulating film containing silicon oxide as a main component on the gate electrode,
The method for manufacturing a semiconductor device, wherein the gate insulating film and the interlayer insulating film are formed using organic silane. Forming a base insulating film containing silicon oxide as a main component on the substrate,
Forming a semiconductor region on the base insulating film,
Forming a gate insulating film having silicon oxide as a main component and a carbon concentration of 5 × 10 ¹⁹ cm ⁻³ or less and a halogen element concentration of 1 × 10 ^{17 to} 5 × 10 ²⁰ cm ⁻³ on the semiconductor region; ,
Forming a gate electrode on the gate insulating film;
Forming an interlayer insulating film containing silicon oxide as a main component on the gate electrode,
The method for manufacturing a semiconductor device, wherein the base insulating film, the gate insulating film, and the interlayer insulating film are formed using organic silane. Forming a base insulating film containing silicon oxide as a main component on the substrate,
Forming a semiconductor region on the base insulating film,
A gate insulating layer containing silicon oxide as a main component and having a carbon concentration of 5 × 10 ¹⁹ cm ⁻³ or less and a halogen element concentration of 1 × 10 ^{17 to} 5 × 10 ²⁰ cm ⁻³ so as to be in close contact with the semiconductor region. Forming a film,
Forming a gate electrode on the gate insulating film;
Forming an interlayer insulating film containing silicon oxide as a main component on the gate electrode,
The method for manufacturing a semiconductor device, wherein the base insulating film, the gate insulating film, and the interlayer insulating film are formed using organic silane. Forming a base insulating film containing silicon oxide as a main component on the substrate,
Forming a semiconductor region on the base insulating film,
A gate insulating layer containing silicon oxide as a main component and having a carbon concentration of 5 × 10 ¹⁹ cm ⁻³ or less and a halogen element concentration of 1 × 10 ^{17 to} 5 × 10 ²⁰ cm ⁻³ so as to be in close contact with the semiconductor region. Forming a film,
Forming a gate electrode on the gate insulating film;
Forming an interlayer insulating film containing silicon oxide as a main component on the gate electrode,
The method for manufacturing a semiconductor device, wherein the base insulating film, the gate insulating film, and the interlayer insulating film are formed by plasma CVD using organosilane. Forming a base insulating film containing silicon oxide as a main component on the substrate,
Forming a semiconductor region on the base insulating film,
Forming a gate insulating film having silicon oxide as a main component and a carbon concentration of 5 × 10 ¹⁹ cm ⁻³ or less and a halogen element concentration of 1 × 10 ^{17 to} 5 × 10 ²⁰ cm ⁻³ on the semiconductor region; ,
Forming a gate electrode on the gate insulating film;
Forming an interlayer insulating film containing silicon oxide as a main component on the gate electrode,
The method for manufacturing a semiconductor device, wherein the base insulating film, the gate insulating film, and the interlayer insulating film are formed in a mixed atmosphere containing an organic silane, oxygen, and a halogen-containing gas. Forming a base insulating film containing silicon oxide as a main component on the substrate,
Forming a semiconductor region on the base insulating film,
Forming a gate insulating film having silicon oxide as a main component and a carbon concentration of 5 × 10 ¹⁹ cm ⁻³ or less and a halogen element concentration of 1 × 10 ^{17 to} 5 × 10 ²⁰ cm ⁻³ on the semiconductor region; ,
Forming a gate electrode on the gate insulating film;
Forming an interlayer insulating film containing silicon oxide as a main component on the gate electrode,
The method for manufacturing a semiconductor device, wherein the base insulating film, the gate insulating film, and the interlayer insulating film are formed in a mixed atmosphere containing a hydrocarbon containing organic silane, oxygen, and chlorine. 8. The method for manufacturing a semiconductor device according to claim 1, wherein the halogen element is chlorine or fluorine. The method for manufacturing a semiconductor device according to claim 1, wherein the substrate is a glass substrate. 8. The method for manufacturing a semiconductor device according to claim 1, wherein the concentrations of the carbon and the halogen element are values detected by a secondary ion mass spectrometry. 9. In any one of claims 1 to 7, wherein the organic _{silane, Si (OC 2 H 5)} 4, Si 2 O (OC 2 H 5) 6, Si 3 O 2 (OC 2 H 5) 8 , Si ₄ O ₃ (OC ₂ H ₅ ) ₁₀ , or Si ₅ O ₄ (OC ₂ H ₅ ) ₁₂ .

Images