JP3535301B2 - Active matrix display device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix display device such as a liquid crystal display device, a plasma display device and an EL display device.

[0002]

2. Description of the Related Art FIG. 2A shows a schematic view of a conventional example of an active matrix display device. A region 104 surrounded by a broken line in the drawing is a display region, and the thin film transistors 101 are arranged in a matrix therein. The source electrode of the thin film transistor 101 has an image (data) signal line 1
A gate (selection) signal line 105 is connected to the gate electrode of the thin film transistor 101. A plurality of gate signal lines 105 and image signal lines 106 are arranged so as to be substantially perpendicular to each other.

Here, paying attention to the drive element, the thin film transistor 101 performs data switching,
The pixel cell 103 is driven. The auxiliary capacitance 102 is a capacitor for reinforcing the capacitance of the pixel cell 103, and is used for holding image data. The thin film transistor 101 is used to switch the image data of the voltage applied to the pixel cell 103.

It is generally known that in a thin film transistor, when a reverse bias is applied to the gate, a leak current (referred to as an OFF current) flows instead of a state in which no current flows (OFF state) between the source and the drain. It was There has been a problem that the potential of the pixel cell fluctuates due to such a leak current.

In the case of an N-channel type thin film transistor, when the gate is negatively biased, a PN junction is formed between the P-type layer induced on the surface of the semiconductor thin film and the N-type layers of the source region and the drain region. However, since many traps exist in the semiconductor thin film, this PN junction is incomplete and a junction leak current easily flows. The OFF current increases as the gate electrode is biased more negatively because the carrier concentration of the P-type layer formed on the surface of the semiconductor thin film increases and the width of the energy barrier of the PN junction narrows.
This is because the electric field is concentrated and the junction leak current is increased.

The OFF current thus generated largely depends on the source / drain voltage. For example, it is known that the OFF current dramatically increases as the voltage applied between the source / drain of the thin film transistor increases. That is, 5 between the source and drain
In the case where the voltage of V is applied and the case where the voltage of 10 V is applied, the OFF current of the latter may be 10 times or 100 times as large as that of the former. Further, such non-linearity also depends on the gate voltage. Generally, when the reverse bias value of the gate electrode is large (a large negative voltage in the N-channel type), the difference between the two is remarkable.

In order to solve this problem, for example, a method of connecting thin film transistors in series (multigate method) has been proposed, as described in JP-B-5-44195 and JP-B-5-44196. . This is intended to reduce the OFF current of each thin film transistor by reducing the voltage applied to the source / drain of each thin film transistor. For example, as shown in FIG. 2B, two thin film transistors 111
When 112 and 112 are connected in series, the voltage applied to the source / drain of each thin film transistor is halved.
If the voltage applied to the source / drain is halved, the OFF current becomes 1/10 or 1/100 from the above discussion. Note that in FIG. 2B, 113 is an auxiliary capacitor,
Reference numeral 114 is a pixel cell, and 115 is a gate signal line.

[0008]

However, when the characteristics required for displaying an image on a liquid crystal display become strict, it becomes difficult to reduce the OFF current as much as necessary even in the above multigate method. That is, even if the number of gate electrodes (number of thin film transistors) is increased to 3, 4, and 5, the voltage applied to the source / drain of each thin film transistor is 1/3, 1/4, 1/5. This is because it decreases only slightly. Further, there is also a problem that the circuit is complicated and the occupied area becomes large.

The present invention has been made in view of the above problems, and the voltage applied to the source / drain of the thin film transistor connected to the pixel electrode is not more than 1/10 of that in the usual case, preferably 1 It is to provide a pixel circuit having a structure that reduces the OFF current by setting the ratio to / 100 or less.

The active matrix display device according to the present invention is characterized by efficiently disposing the thin film transistors for the above purpose. In the embodiments described below, the present invention has five thin film transistors. The thin film transistor achieves the above goals.

[0011]

One of the inventions disclosed in this specification is to provide an image signal line and a gate signal line arranged in a matrix and an area surrounded by the image signal line and the gate signal line. A plurality of thin film transistors, and n thin film transistors of the same conductivity type are connected in series adjacent to the pixel electrode. Alternatively, the drain region is connected to the image signal line,
The drain or source region of the nth thin film transistor of the plurality of thin film transistors is connected to the pixel electrode, and the gate electrodes of the (nm) [n> m] thin film transistors are commonly connected to the gate signal line. Cage,
In the m thin film transistors, the gate potential is fixed to a potential at which the channel formation region has the same conductivity type as the source and drain regions.

In the above structure, n and m are natural numbers except 0. N = 5 to obtain the desired effect
The above is preferable.

FIG. 2C shows a concrete example of the above-mentioned structure. In the structure shown in FIG.
N = 5 thin film transistors indicated by 5 are arranged. In the configuration shown in FIG. 2C, n = 5 and m =
It becomes 2.

Then, n = 1th thin film transistor 1
21 source regions are connected to the image signal line 129. In addition, the n-th (fifth) thin film transistor 123
Of the pixel cell 127 is connected to one electrode (pixel electrode) of the pixel cell 127 and the auxiliary capacitance 126.

The gate electrodes of the (n−m) [n> m] thin film transistors 121, 122, 123 are connected to a common gate signal line 128. On the other hand, the gate electrodes of the m thin film transistors 124 and 125 are connected to the common capacitance line 130, and the capacitance line 130 is kept at an appropriate potential.

The basic idea of the invention disclosed in this specification is that, as shown in FIG.
.About.125 are connected in series, of which the gates of the thin film transistors 121 to 123 are connected to the gate signal line 128, and the gates of the other thin film transistors 124 and 125 are connected to the capacitance line 130. Then, while the potential of the pixel is held, the capacitance line 130 is kept at an appropriate potential to form a capacitance between the channels of the thin film transistors 124 and 125 and the gate electrode.

Then, the thin film transistors 122 and 123
The voltage appearing between the source and drain of the
The OFF current of these thin film transistors can be reduced. Although the auxiliary capacitance 126 is also shown in the figure, this is not always necessary. Rather, since it increases the load at the time of writing, it may be preferable that the ratio of the capacitance of the pixel cell 127 and the capacitance generated in the thin film transistors 124 and 125 is not optimum if it is not optimal.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION A specific operation will be described with reference to FIG. When the selection signal is sent to the gate signal line 128, all the thin film transistors 121 to 123 are turned on. At this time, the thin film transistor 1
It is necessary to apply a signal to the capacitance line 130 so that 24 and 125 are also turned on. As a result, the pixel cell 127 is charged according to the signal of the image signal line 129, but at the same time, the thin film transistors 124 and 125 are also charged.
At the fully charged (equilibrium) stage, the source / drain voltages of the thin film transistors 122 and 123 are substantially equal.

When the selection signal is turned off in this state, all the thin film transistors 121 to 123 are turned off. However, at this stage, the thin film transistors 124 and 125 are
Is still in the ON state. After that, the image signal line 12
Since signals of other pixels are applied to the thin film transistor 9 and the thin film transistor 121 has a finite OFF current, the charges charged in the thin film transistor 124 are discharged, and the voltage drops. However, this speed progresses at the same speed as the voltage drop of the capacitor 102 of the normal active matrix circuit shown in FIG.

On the other hand, regarding the thin film transistor 122, since the voltage between the source and the drain was almost 0 at the beginning, the OFF current was extremely small, but after that,
Since the voltage of the thin film transistor 124 drops, the voltage between the source and the drain gradually increases, and therefore the OF
The F current will also increase. Similarly, the OFF current of the thin film transistor 123 also gradually increases, but needless to say, the speed thereof is smaller than that of the thin film transistor 122. From the above, the pixel cell 12 due to the increase in the OFF current of these thin film transistors
It goes without saying that the voltage drop of 7 is much slower than that in the normal active matrix circuit shown in FIG.

In such a circuit, the gate signal line 12 is formed in the substantially M-shaped semiconductor region 100 as shown in FIG.
The degree of integration can be increased by adopting a circuit arrangement in which 8 and the capacitance line 130 are overlapped. FIG. 1 (B)-
(D) is a possible combination in that case, and the same effect can be obtained regardless of which is used.

In the present invention, since the LDD region and the offset region are formed in the channels of the thin film transistors 121 to 125, these regions become the drain resistance and the source resistance, so that the electric field strength of the drain junction is relaxed and the OFF current is further reduced. Can be reduced.

FIG. 1B shows the most orthodox shape, and the thin film transistor 121 is formed by intersecting the semiconductor region 100 with the gate signal line 128 and the capacitance line 130.
.About.125 are formed at the intersections (3 intersections with the gate signal line, 2 intersections with the capacitance line, 5 in total). In the semiconductor region, there are N-type or P-type regions in the regions separated (sandwiched) by the gate signal line and the capacitance line (four in FIG. 1B) and the regions at both ends of the semiconductor region. Impurities are introduced to serve as the source / drain of the thin film transistor. In particular, a low concentration impurity region, so-called L, is formed in the source / drain of a thin film transistor using a gate signal line as a gate electrode.
By forming DD, the OFF current can be further reduced. Note that the image signal line and the pixel electrode may be formed so as to be connected to either end of the semiconductor region.

As shown in FIG. 1C, the points a and b are connected to the capacitance line 1
It is possible if 30 is not covered. This is because it is sufficient for the thin film transistors 124 and 125 to function only as capacitors. In addition, as shown in FIG. 1D, the semiconductor region 100 is crossed with the gate signal line 138 at four points and with the capacitance line 140 at two points, and the six thin film transistors 131 to 131 connected in series. It is also possible to configure 136. The equivalent circuit diagram in this case is shown in FIG.
2D, which corresponds to the circuit shown in FIG.
7 is a pixel cell, 138 is a gate signal line, and 1
Reference numeral 39 is an image signal line, and 140 is a capacitance line. Figure 2
This corresponds to the thin film transistor 122 of (C) replaced by two thin film transistors 132 and 133 connected in series, and the OFF current can be reduced as compared to the circuit of FIG.

[0025]

【Example】

Example 1 This example is characterized in that an offset gate is formed by anodizing the gate electrode to further reduce the OFF current. A technique for anodizing the gate electrode is disclosed in Japanese Patent Laid-Open No. 5-267667. FIG. 1 shows a top view of the circuit of this embodiment, and FIG. 3 shows a cross-sectional view of the manufacturing process. In FIG. 3, the left side of FIG.
A cross-sectional view taken along the dashed-dotted line XY in (A) is shown, and a cross-sectional view taken along the dashed-dotted line X′-Y ′ in FIG. However, it should be noted that the dashed-dotted lines XY and X′-Y ′ are drawn adjacent to each other in FIG. 3, but are not actually on the same straight line.

First, the substrate 151 (Corning 7059,
100 mm × 100 mm), a silicon oxide film as a base film 152 with a thickness of 1000 to 5000 Å, for example, 3
A film was formed at 000Å. This silicon oxide film is formed by decomposing / depositing TEOS by the plasma CVD method. Alternatively, the film may be formed by a sputtering method.

After that, an amorphous silicon film is formed in a thickness of 300 to 1500 Å by plasma CVD method or LPCVD method.
To the thickness of, for example, 500 Å
Let it stand in an atmosphere of 600 ° C. for 8 to 24 hours for crystallization. At that time, if a small amount of nickel is added to the amorphous silicon film, crystallization is promoted. JP-A-6-24
No. 4104 and the like disclose a technique for promoting crystallization by adding a catalytic metal element such as nickel, thereby lowering / shortening the crystallization temperature / crystallization time. The crystallization process may be performed by combining optical annealing such as laser irradiation, thermal annealing and optical annealing. This step may be performed by optical annealing such as laser irradiation. Also, thermal annealing and optical annealing may be combined.

Then, the crystallized silicon film was etched to form a substantially M-shaped island region 100. Further, a gate insulating film 153 is formed on this. Here, the thickness is 700 to
A silicon oxide film having a thickness of 1500 Å, for example, 1200 Å, was formed. This step may be performed by a sputtering method.
(Fig. 1 (A), Fig. 3 (A))

After that, an aluminum (containing 1 wt% Si or 0.1 to 0.3 wt% Sc) film having a thickness of 1000 Å to 3 μm, for example, 5000 Å, is formed by a sputtering method and is etched. The gate signal line 128 and the capacitance line 130 were formed. All of these become gate electrodes of thin film transistors. (Fig. 1 (B),
(Figure 3 (B))

At this time, as shown in FIG. 8, the aluminum film region 802 remains around the active matrix region 805 on the substrate 806, and the gate signal line 128 and the capacitor line 13 (corresponding to the aluminum wiring 801 in FIG. 8). .)
Are preferably etched so that they are all connected to the aluminum film region 802. However, in this case, the peripheral circuits, that is, the gate driver 803 and the source driver 80
If the aluminum wiring such as the gate electrode of No. 4 is designed so that the aluminum film region 802 is insulated from the aluminum film region 802, the aluminum wiring of the peripheral circuit does not have to be anodized, so that the degree of integration can be improved. .

Then, an electric current is applied to the gate electrode in an electrolytic solution to carry out anodic oxidation to obtain a thickness of 500 to 2500Å, for example,
2000 liters of anodic oxide 154, 155 were formed. The electrolytic solution used was L-tartaric acid in ethylene glycol.
% To pH 7.0 with ammonia.
It is adjusted to 0.2. Immerse the substrate in the solution, connect the + side of the constant current source to the gate electrode on the substrate,
A platinum electrode was connected to the side and a voltage was applied in a constant current state of 20 mA, and oxidation was continued until it reached 150V. Further, oxidation was continued at a constant voltage of 150 V until the current became 0.1 mA or less. As a result, the gate signal line 1
On the 28 and the capacitance line 130, anodic oxides 154 and 155 having a thickness of 2000 Å were obtained. (Fig. 3 (C))

After that, the gate electrode portion (that is, the gate signal line 128, the capacitor line 130 and the anodic oxide 15 around the gate electrode portion) is formed in the island region 100 by ion doping.
4, 155) was used as a mask to implant impurities (phosphorus in this case) to form N-type impurity regions 156 to 159 in a self-aligned manner. Here, phosphine (PH ₃ ) was used as the doping gas. The dose amount in this case is 1 × 10 ^14.
〜5 × 10 ¹⁵ atoms / cm ² , accelerating voltage 60 ~ 90k
V, for example, the dose amount was 1 × 10 ¹⁵ atoms / cm ² , and the acceleration voltage was 80 kV. As a result, the N-type impurity region 15
6-159 were formed. (Fig. 3 (D))

Further, irradiation with a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) is performed to activate the doped high concentration impurity regions 317 to 320 and the low concentration impurity regions 321 to 324. The energy density of the laser was 200 to 400 mJ / cm ² , preferably 250 to 300 mJ / cm ² . This step may be performed by thermal annealing. In particular, it contains a catalytic element (nickel) and can be activated by low-temperature thermal annealing as compared with the usual case (Japanese Patent Laid-Open No. 6-267).
989).

Next, as shown in FIG. 3E, a silicon oxide film having a thickness of 5000 Å was formed as an interlayer insulating film 160 by a plasma CVD method. At this time, the source gas is T
EOS and oxygen were used. Then, the interlayer insulating film 160 and the gate insulating film 153 are etched to form the N-type impurity region 1
At 56, that is, in the source of the thin film transistor 121 in FIG. 2C, a contact hole is formed, an aluminum film is formed by a sputtering method, and the source electrode / wiring 161 is formed by etching. The source electrode / wiring 161 is an extension of the image signal line 129.

As shown in FIG. 3F, a passivation film 162 is formed. Here, NH ₃ / SiH ₄ /
A silicon nitride film having a thickness of 2000 to 8000 Å, for example, 4000 Å is formed by plasma CVD method using H ₂ mixed gas to form a passivation film 162. Then, the passivation film 162 and the interlayer insulating film 160 and the gate insulating film 153 are each etched to form a contact hole in the high-concentration impurity region 159, that is, the drain of the thin film transistor 123 in FIG. 2C. Then, an indium tin oxide (ITO) film was formed by a sputtering method, and this was etched to form a pixel electrode 163. The pixel electrode 163 is the pixel cell 127.
One of the electrodes.

Through the above steps, a switching circuit having N-channel type thin film transistors 121 to 125 was formed. The switching circuit of this embodiment corresponds to the switching circuit shown in FIG. 2C from which the auxiliary capacitance 126 is removed. Note that the thin film transistor 122 is not illustrated in FIG.

In this embodiment, the thin film transistor 12 is used.
Nos. 1-125 have a so-called offset gate structure in which the low-concentration impurity regions are distant from the gate electrode by the thickness of the porous anodic oxides 154 and 155, so that the OFF current can be reduced, so that they are arranged in the pixel matrix. It is suitable as an element.

Example 2 FIG. 4 shows a step of forming a circuit by using the present invention. A publicly known technique or a technique shown in Embodiments 1 and 2 may be used for a specific process, and thus a detailed description thereof will not be given here. Note that FIG.
4C is a cross-sectional view taken along the capacitance line 207 in FIG. 4C, and FIG. 6 is an equivalent circuit diagram of the circuit in FIG. 4C.

First, Examples 1 and 2 (or FIG. 1)
The substantially M-shaped semiconductor regions (active layers) 201 and 202 as described in (A)) were formed. After that, the gate insulating film 240 shown in FIG. 5 was formed, and further the gate signal lines 203 to 205 and the capacitance lines 206 to 208 were formed.
Here, the gate signal lines 203 to 205 and the capacitance line 206 to
The positional relationship between 208 and the active layers 201 and 202 was the same as in the first embodiment. Further, anodic oxide 241 is formed around it as shown in FIG. (Fig. 4 (A))

After doping the active layers 201 and 202, an interlayer insulator 242 shown in FIG. 5 is formed, and further contact holes 210 and 211 are formed at one end of each active layer 201 and 202 to form an image. The signal line 209 was formed. (Fig. 4 (B))

As shown in FIG. 5, the passivation film 24
3 is formed, pixel electrodes 212, 213, and 214 are formed in a region surrounded by the gate signal lines 203 to 205 and the image signal line 209 as illustrated in FIG.
In this way, a switching element composed of a thin film transistor of the active matrix circuit is formed. In FIG. 6, thin film transistors 221 to 225, 226 to 23 connected in series to the pixel electrodes 213 and 214.
0 corresponds to thin film transistors formed on the active layers 201 and 201, respectively.

In this embodiment, as shown in FIG. 4C, the capacitance line 206 is arranged so as not to overlap with the pixel electrode 213 in the row but to overlap with the pixel electrode 212 in the row above.
Therefore, a capacitor 215 corresponding to the auxiliary capacitor 126 in FIG. 2C can be formed between the capacitor line 207 and the pixel electrode 212. The same applies to the other rows.

In this way, the circuit as shown in FIG. 6 is constructed by adopting the arrangement in which the gate signal line is overlapped with the pixel electrode one row above (or below) the row concerned, but the capacitance 215 is the capacitance. It is formed on the line 207, and the capacitor 215 can be added without substantially lowering the aperture ratio, which is effective in improving the degree of integration of the circuit.

In order to increase the capacitance 215, the interlayer insulating material 242 in this overlapping portion may be etched.
By doing so, the distance between the electrodes 207 and 213 can be reduced and the capacitance 215 can be increased. For that purpose, when the surface of the capacitance line 207 is covered with the anodic oxide 241, the anodic oxide 241 can function as a dielectric. Therefore, as shown in FIG. 5, the interlayer insulating film 242 on the surface of the anodic oxide 241 can be entirely removed, which is preferable in that the capacitance 215 is further increased.

Thus, the etching of the portion for the capacitance 215 does not increase the number of steps. That is, the interlayer insulator 241 is etched,
Contact holes 210, 211 or pixel electrode 21
Capacitor line 2 is formed at the same time when the contact hole 3 is formed.
A hole may be formed also on 07. The one shown in FIG. 5 is an example of the latter. Under proper etching conditions,
Since the aluminum anodic oxide 241 and the like are not etched at all (for example, dry etching conditions for etching silicon oxide), the etching can be continued until the opening of the contact hole is completed.

As shown in FIGS. 4D to 4F,
In the semiconductor region 216, the capacitance line 21 is formed in the same manner as in the above embodiment.
7. The gate signal line 218 is arranged, and the semiconductor region 21
The aperture ratio can be further improved by forming the image signal line 219 so as to cover all one side of No. 6. Figure 4
In the state of (F), the thin film transistor 22 shown in FIG.
Part of 1 and 224 and the pixel signal line 219 will overlap.

Further, as shown in FIG. 7A, the island-shaped semiconductor region 701 is bent more and more complicatedly.
As shown in (B), by stacking the gate signal line 702 and the capacitor line 703 on the island-shaped semiconductor region 701, more transistors can be formed. As a result, the OFF current can be further reduced.

[0048]

As described above, by connecting the gates of a plurality of thin film transistors to the gate signal line and the capacitance line as shown in the present invention, the voltage drop of the liquid crystal cell can be suppressed. In general, the deterioration of the thin film transistor depends on the voltage between the source and the drain, but in the present invention, the source / drain of the thin film transistors 122 and 123 of FIG.
The voltage between the drains is kept low during the whole driving process, and these thin film transistors 122, 123,
Since the LDD is formed in 124, deterioration can be prevented by utilizing the present invention.

The present invention is effective in applications in which higher image display is required. That is, in the case of expressing extremely delicate shades of 256 gradations or more, it is necessary to suppress the discharge of the liquid crystal cell to 1% or less during one frame. In the conventional method, neither of FIGS. 2A and 2B is suitable for this purpose.

The present invention is also suitable for an active matrix display device using a thin film transistor of a crystalline silicon semiconductor, which is particularly suitable for the purpose of displaying a matrix having a large number of rows. Generally, in a matrix having a large number of rows, the selection time per row is short, and therefore an amorphous silicon semiconductor thin film transistor is not suitable for use.

However, there is a problem that a thin film transistor using a crystalline silicon semiconductor has a large OFF current. Therefore, the present invention capable of reducing the OFF current can make a great contribution also in this field. Needless to say, the thin film transistor using an amorphous silicon semiconductor is also effective.

In the embodiments, the structure of the thin film transistor has been described mainly about the top gate type.
It goes without saying that the effects of the present invention are invariable even if the structure is a bottom gate type or other structure. The present invention can obtain the maximum effect with the minimum change. Particularly in a top-gate type thin film transistor, the thin semiconductor region (active layer) has a complicated shape, while the gate electrode and the like have an extremely simple shape, so that disconnection of the upper wiring can be prevented. On the contrary, if the gate electrode has a complicated shape, it will be a cause of lowering the aperture ratio. Thus, the present invention is an industrially useful invention.

[Brief description of drawings]

FIG. 1 shows an arrangement example of a semiconductor region, a gate signal line, and a capacitance line of the present invention.

FIG. 2 is a schematic diagram of conventional and present invention active matrix circuits.

FIG. 3 shows a manufacturing process (cross section) of the switching element in the first embodiment.

FIG. 4 shows a manufacturing process (cross section) of a switching element according to a second embodiment.

FIG. 5 shows a cross-sectional view of a switching element according to a second embodiment.

FIG. 6 shows a circuit diagram of a switching element according to a second embodiment.

FIG. 7 shows an arrangement example of a semiconductor region, a gate signal line, and a capacitance line of the second embodiment.

FIG. 8 shows an arrangement example of a gate signal line, a capacitance line, and a peripheral circuit of the embodiment.

[Explanation of symbols]

100 ... Semiconductor regions 121 to 125 ... Thin film transistor 126 ... Auxiliary capacitance 127 ... Pixel cell 128 ... Gate signal line 129 ... Image signal line 130 ... Capacitance lines 131 to 136 ... ... Thin film transistor 137 ... Pixel cell 138 ... Gate signal line 139 ... Image signal line 140 ... Capacitance line 151 ... Substrate 152 ... Underlayer film (silicon oxide) 153 ... Gate insulating film (silicon oxide) 154, 155 ... Anodic oxides 156 to 159 ... N-type impurity region 160 ... Interlayer insulator (silicon oxide) 161. Source electrode / wiring 162 ... Passivation film (silicon nitride) 163 Pixel electrodes (ITO) 201, 202 ... Active layers 203-205 Gate signal line 20 6 to 209 ... Capacitance line 209 ... Image signal lines 210, 211 ... Contact holes 212-214 ... Pixel electrode 215 ... Capacitors 221-230 ... Thin film transistor 240 ... Gate insulating film 241 ... Anodic oxide 242 ... Interlayer insulating film 243 ... Passivation film

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 G02F 1/1368

Claims (7)

(57) [Claims] 1. An image signal line and a gate signal line arranged in a matrix, a pixel electrode arranged in a region surrounded by the image signal line and the gate signal line, and connected in series to the pixel electrode. N of the same conductivity type (n
Is an integer of 5 or more), and a source region or a drain region of the n = 1st thin film transistor of the n thin film transistors is connected to the image signal line, and the n thin film transistors are formed. The source region or the drain region of the n = nth thin film transistor is connected to the pixel electrode, and (n−m) of the n thin film transistors (n> m, m is an integer of 1 or more) An active matrix display device, wherein a gate electrode is connected to the gate signal line, and gate electrodes of m thin film transistors of the n thin film transistors are connected to a common capacitance line. 2. The active matrix display device according to claim 1, wherein each of the n thin film transistors has an LDD region. 3. The active matrix display device according to claim 1, wherein each of the (nm) thin film transistors has an LDD region. 4. The active matrix display device according to claim 1, wherein each of the n thin film transistors has an offset gate structure. 5. The active matrix display device according to claim 1, wherein the n thin film transistors are top gate type thin film transistors. 6. The method according to any one of claims 1 to 5, wherein
(Nm) thin film transistors connected to the gate signal line
A transistor and m thin films connected to the capacitance line.
The number of transistors is m−1 ≦ (n−m) ≦
m + 1 is satisfied, and they are connected in series alternately.
Active matrix display device characterized by
Place 7. The method according to any one of claims 1 to 6, wherein
The active matrix display device is a liquid crystal display device or
Is an EL display device.
Rix display device.