JP3519173B2 - Lateral semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used in power conversion equipment and the like, and more particularly to a lateral semiconductor device in which a switching semiconductor element, a control circuit, a protection circuit and the like can be easily integrated in the same chip.

[0002]

2. Description of the Related Art A power semiconductor device used for power conversion equipment, power control equipment, etc. is required to have a small voltage drop when turned on in order to reduce power loss as much as possible.
Particularly in an application field where a high breakdown voltage is required, a thyristor or an insulated gate bipolar transistor (hereinafter referred to as an IGBT) having a conductivity modulation function is suitable. Figure 8 (a)
FIG. 3 is a cross-sectional view of a basic structure for explaining the configuration and operation of the IGBT. In an actual semiconductor device, a plurality of such structures are used as a unit in a plane and used in parallel. In order to incorporate the IGBT into the output side of the integrated circuit, a lateral structure having a main electrode on one surface of the semiconductor crystal as shown in FIG. 8 is suitable.

In FIG. 8A, the IGBT is a p-type silicon.
N on a part of the surface layer of the p substrate 1 by, for example, diffusion.
N type drift region 2 of high resistivity is formed, and
Diffusion of impurities from the surface in part of the surface layer of the lift region 2
A more p-type p base region 5 is formed, and further its surface layer
The n-type impurity is diffused in a part of the
6 is formed. n drift region 2 and n emitter region
A gate is formed on the surface of the p base region 5 between the region 6 and the region.
Polysilicon connected to the gate terminal G through the oxide film 8
A gate electrode 9 made of a capacitor is provided. In addition, p base
Of the high impurity concentration formed on the surface layer of the region 5⁺Con
The tact region 7 and the n-emitter region 6 have a common second surface.
The emitter electrode 10 connected to the main terminal T2 is in contact
It On the other hand, the right part of the figure prevents punch-through when off.
Or reduce the injection efficiency of minority carriers,
For the purpose of increasing the switching speed of
In the same way, by diffusion of impurities from the surface,⁺buffer
Region 11 is formed, n ⁺Surface of buffer area 11
The first main terminal on the surface of the p collector region 12 formed in the layer.
The collector electrode 13 connected to T1 is in contact.

The operation of this device will be briefly described below. In FIG. 8A, the p base region 5 having a positive polarity with respect to the second main terminal T2 is applied to the gate terminal G with a negative potential applied to the second main terminal T2 and a positive potential applied to the first main terminal T1. When a voltage equal to or higher than a threshold value determined by the surface concentration of the p-type gate oxide film 8 and the thickness of the gate oxide film 8 is applied, an inversion layer is formed on the surface of the p-base region 5, and electrons pass through this inversion layer to produce an n-emitter. It is injected from the region 6 into the n drift region 2. The injected electrons are drawn to the positive potential of the collector and reach the p collector region 12 through the n ⁺ buffer region 11, but this electron current is generated in the p base region 5 and the n drift region 2
And becomes the base current of the pnp transistor constituted by the p collector region 12 and conversely the p collector region 12
A large amount of holes are injected into the n drift region 2 via the n buffer region 11 from. Therefore, the n drift region 2
The electron density inside is increased to satisfy the neutral condition of charge,
The so-called conductivity modulation in which the concentration of both electrons and holes is increased occurs, and the resistance between the collector electrode 13 and the emitter electrode 10 does not have a p collector region and is compared to a normal MOSFET having no conductivity modulation effect. And then drops significantly. On the other hand, when a voltage equal to or lower than the threshold voltage is applied to the gate terminal G, an inversion layer is not generated, so that electron injection does not occur,
Therefore, since holes are not injected, the first main terminal T1-
No current flows between the second main terminals T2, and this IGBT is turned off.

[0005]

As described above, the IGBT is used.
The so-called bipolar element using the conductivity modulation effect such as has an advantage that the on-voltage during conduction can be reduced as compared with the so-called unipolar element that does not use the conductivity modulation effect such as MOSFET. However, at the time of switching, especially at turn-off, excess carriers generated by the conductivity modulation effect reduce the switching speed and increase the switching loss, which causes a problem in application to high frequencies. This problem is particularly serious in the case of a lateral semiconductor device.

The cause will be described below with reference to FIG. The arrow in FIG. 8A indicates a current path. MO
In a unipolar element such as an SFET, the current path is only in the n drift region 2, but in a bipolar element such as an IGBT, excess carriers in the n drift region 2 due to the conductivity modulation effect diffuse into the p substrate 1 as well. A current path is also formed in the substrate 1. The current path formed in the p-substrate 1 contributes to the reduction of the on-voltage of the element, but also causes the increase of switching loss. This is because, as shown in FIG. 8B, as the depletion layer 32 whose end is shown by a dotted line spreads at the time of turn-off, the electrons 33 in the p substrate 1 drop into the depletion layer and flow into the p collector region 12. This current becomes the base current of the above-mentioned pnp transistor, so that holes 34 are continuously injected even after the gate is turned off and the injection of electrons is stopped, and the switching loss increases. In particular, in the deep portion of the p substrate 1, the current path becomes long as shown in FIG. 8 (a), so that it hardly contributes to the decrease of the on-state voltage and causes only the increase of the switching loss.
In the case of a vertical semiconductor device, the conductivity modulation action causes a decrease in switching speed, but the place where the conductivity modulation action occurs is a portion that contributes to the reduction of the on-state voltage. In this case, as described above, there is a portion that hardly contributes to the reduction of the ON voltage and causes the switching speed to decrease. As a means for preventing such an increase in switching loss, the lifetime of carriers in the entire semiconductor is reduced by diffusion of heavy metals, electron beam irradiation, etc., and the recombination speed of electrons and holes is increased to reduce switching loss. Reduction is often done. However, these methods are not preferable because the on-voltage simultaneously increases.

In view of the above problems, the object of the present invention is to reduce the carrier emission from the deep portion of the substrate which does not contribute to the reduction of the on-voltage but deteriorates the switching speed and increases the switching loss. Another object is to provide a lateral semiconductor device with a small switching loss.

[0008]

[Means for Solving the Problems] In order to solve the above problems,
The present invention provides a second conductivity type drift on a first conductivity type semiconductor region.
Doo area, lateral semiconductor element having at least two main electrodes are formed on the surface of the second conductivity type drift region, the second conductivity type drift region mains <br/> flow between their main electrode In a flowing lateral semiconductor device, the first conductive type semiconductor region and the first conductive type first drift region are in contact with each other .
The first conductivity type semiconductor region is in contact with the second conductivity type drift region so that the carrier lifetime on the conductivity type semiconductor region side is shorter than that on the second conductivity type drift region side .
A lifetime killer introduction region having more lifetime killer than the second conductivity type drift region side is formed on the one conductivity type semiconductor region side .

[0009] Then, the thickness of the lifetime killer introduction region, wherein the semiconductor element is a portion where the depletion layer expands in the first conductivity type semiconductor region during the OFF state. Semiconductor elements include diodes, bipolar transistors, thyristors, IGBTs, SITH, MCTs, dual gate IGs.
A MOS in which holes are injected into the second conductivity type drift region through a parasitic diode formed by the BT, the dual gate MCT or the first conductivity type semiconductor region and the second conductivity type drift region.
It shall be applied to any of the FETs.

In the method of manufacturing the lateral semiconductor device as described above, the first conductivity type semiconductor region is irradiated with protons or helium ions. In particular, it is preferable to irradiate protons or helium ions from the surface side on which the electrode is not formed.

[0011]

By the above means, the first conductivity type semiconductor region is formed.
And the second conductivity type drift region are in contact with the first conductivity type half
Lifetime of the conductor region side carrier a second conductivity type Dori
The first conductivity type semiconductor region so that it is shorter than the shift region side.
Region of the first conductivity type where the region contacts the second conductivity type drift region
By providing the semiconductor region side with more lifetime killer than the second conductivity type drift region side , the conductivity modulation action of the second conductivity type drift region is sufficiently performed, but it does not contribute much to the reduction of the on-voltage. First conductivity type semiconductor
It is possible to reduce the conductivity modulation effect in the body region .

Carriers swept out along with the expansion of the depletion layer at turn-off are a problem, and the thickness of the region where the carrier lifetime is short is sufficient if the depletion layer spreads at least in the first conductivity type semiconductor region. Is. The semiconductor element uses the conductivity modulation function as any of a diode, a bipolar transistor, a thyristor, an IGBT, a SITH, an MCT, a dual gate IGBT or a dual gate MCT, and the switching speed is a minority carrier lifetime. Have the greatest impact.

The method for manufacturing the lateral semiconductor device as described above is for irradiating the first conductivity type semiconductor region with protons or helium ions and utilizing the irradiation damage as a lifetime killer, and in particular, it is carried out conventionally. With the electron beam that has been used, the lifetime killer is generated almost all through the semiconductor device, but the lifetime killer can be localized by irradiation with protons or helium ions.

When the irradiation of protons or helium ions is performed from the surface on which the electrode is not formed, the influence of the defect-rich region near the surface can be avoided, and the lifetime killer is localized in the first conductivity type semiconductor region. Is easy.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a lateral IG according to a first embodiment of the present invention.
A sectional view of BT is shown. This embodiment is similar to the IGB shown in FIG.
This is an example applied to T. However IGB in FIG. 8 in this embodiment
Unlike T, the drift region is not a diffusion region formed by diffusion, but an n drift layer 2 (thickness 10 μm) formed by epitaxial growth on a p substrate 1 having a thickness of 300 μm.
In addition, for the purpose of preventing the latch up of the IGBT and improving the withstand voltage characteristic, p ⁺
Although the buried region 3 is formed, there is no essential difference. The p base region 5 is formed in a part of the surface layer of the n drift layer 2, and the n emitter region 6 is formed in a part of the surface layer thereof. On the surface of p base region 5 sandwiched between n drift layer 2 and n emitter region 6, a gate electrode 9 made of polycrystalline silicon and connected to gate terminal G via gate oxide film 8 is provided. Further, a high impurity concentration p ⁺ contact region 7 formed in the surface layer of the p base region 5
The emitter electrode 10 connected to the second main terminal T2 is in common contact with the surface of the n emitter region 6. On the other hand, on the right side of the figure, an n ⁺ buffer region 11 is formed, and the collector electrode 13 connected to the first main terminal T1 is in contact with the surface of the p collector region 12 formed therein. In the present embodiment, the killer introduction region 20 with many lifetime killer is formed immediately below the n drift layer 2 by the proton irradiation and heat treatment from the back surface side of the p substrate 1, and excess carriers penetrate deep into the substrate. To prevent that. The irradiation conditions are, for example, masking with 30 μm Al foil, 6 MeV, 1 × 10 ¹¹ cm ⁻² , and annealing at 300 ° C. In order to control the depth of the killer introduction region, there is a method of changing the acceleration voltage of protons or decelerating with a metal thin film having an appropriate thickness.

In this way, the killer introduction region 20 formed immediately below the n drift layer 2 eliminates the possibility of forming a current path deep in the p substrate 1 when the IGBT is turned on. Therefore, at the time of turning off, carriers are not swept out from a deep current path as in the conventional device, and the turn-off time does not become long. Conventionally, when a pulsed current of about several μs is passed, the longer the pulse width, the longer the fall time thereafter. This was because a current path was formed deeply and a large amount of carriers were accumulated, but even after a current with a long pulse width, such a situation disappeared, and the fall time was shortened to about 1/3. . As a result, switching loss could be significantly reduced.

The thickness of the killer introduction region 20 may be equal to or more than the diffusion length of carriers in consideration of the existence of this region. In this embodiment, the killer introduction region 20 is the n drift layer 2
Although provided near the junction immediately below, if the thickness of the n drift layer 2 is smaller than the drift region length (distance between the cathode region and the anode region), the n drift is reduced in order to reduce the on-voltage. It is also possible to increase the conductivity modulation in a region near the pn junction directly under the layer 2 and provide the killer introduction region 20 to a portion much deeper than the pn junction.

FIG. 2 shows a horizontal type according to the second embodiment of the present invention.
A sectional view of a semiconductor device is shown. This embodiment is similar to FIG.
In this example, the n drift region 2 is formed by diffusion.
Applied to a type of dual-gate IGBT instead of IGBT
It is an example. In the element of this example, n⁺Buffer area
The p collector region 12 is formed on the surface layer 11 of the
The point where the collector electrode 13 is provided on the surface is
The same but different point is that n⁺Buffer area 1
P drain region 14 and n⁺Ko
Contact region 15 is formed, and both are floating contacts.
It is a point electrically connected by the contact 18.
Further, p collector region 12 and p drain region 14
N sandwiched between⁺Gate oxidation on the surface of the buffer region 11
Second gate electrode made of polycrystalline silicon via the film 16
17 is formed and is connected to the G2 terminal. Book
In the device, when the second gate electrode 17 is off,
Operates as a normal IGBT, but on the second gate electrode 17
When a signal is given, n ⁺Flow into contact area 15
The generated electrons become holes by the floating contact 18.
P is converted to p through the inversion layer directly below the second gate electrode 17.
Bypassed to the collector region 12, the p collector area
The injection of holes from the area 12 is stopped, and a normal MOSFET is
Can be operated as. Also in this embodiment, the p substrate
By the proton irradiation and heat treatment from the back side of 1
Killer introduction area 20 with many if-time killers is n-drift
Is formed immediately below the substrate layer 2 and excess carriers in the substrate
It prevents you from going deep. The irradiation condition is the first
Is substantially the same as that of the embodiment.

That is, in the present element, in the ON state, it operates as an IGBT having a low ON voltage, and M
High-speed switching can be performed by switching to the OSFET mode. In the case of this element, when excess carriers penetrate deep into the p substrate, the transition time from the IGBT mode to the MOSFET mode becomes long, and
Losses increase because the mode needs to be shortened. Even in such a case, by forming the killer introduction region 20, the transition time can be shortened and the loss can be reduced without significantly increasing the on-state voltage of the IGBT mode.

FIG. 3 shows a lateral MOS control thyristor (hereinafter referred to as “M”) whose off operation can be controlled by a MOS gate.
It is sectional drawing of the 3rd Example of this invention applied to CT). An n drift layer 2 having an n-type high specific resistance is stacked on the p substrate 1 by, for example, an epitaxial method, and a portion of the surface layer of the n drift layer 2 is diffused from the surface of the n drift layer 2 by p diffusion. A p-type p-type base region 5 is formed, and n is also formed in a part of the surface layer of the p-type base region 5 by impurity diffusion.
Forming an n base region 21 of the mold and
A p cathode region 22 having an impurity concentration higher than that of the p base region 5 is formed in a part of the surface layer of. Then, the cathode electrode 24 connected to the second main terminal T2 is provided in common contact with the p cathode region 22 and the n base region 21. The gate electrode 9 is composed of the n drift layer 2 and the p cathode region 2
The gate oxide film 8 is provided on the surfaces of both the n base region 21 and the p base region 5 sandwiched between the two.
Similarly, in the right part of the figure, due to impurity diffusion from the surface,
The n ⁺ buffer region 11 and the p anode region 23 are formed, and the p anode region 23 is in contact with the anode electrode 25 connected to the first main terminal T1.

To turn on this MCT, the main terminal T1
Gate terminal G with a positive voltage applied to T2
A positive voltage is applied to the gate electrode 9 connected to. Then, an inversion layer is formed on the surface of the p base region 5 immediately below the gate electrode 9, and the n base region 21 is formed through the inversion layer.
Electrons flow from the n-type drift layer 2 to the p-anode region 2
Flow to 3. Since this current corresponds to the base current of a pnp transistor having the p base region 5, the n drift layer 2 and the p anode region 23 as the collector, the base and the emitter, respectively, the pnp transistor is turned on,
Collector current flows from the emitter to the collector. That is, the current flows from the p anode region 23 to the p base region 5, and the main terminals T1 and T2 are electrically connected. The holes of minority carriers are injected from the p anode region 23 to the n drift layer 2,
It is similar to the case of the IGBT in FIG. 8 described above that the ON voltage at the time of conduction can be reduced by the conductivity modulation action by that. In the off operation, a negative voltage is applied to the gate electrode 9. As a result, the inversion layer on the surface of the p base region 5 disappears, and at the same time, an inversion layer is formed on the surface of the n base region 21 immediately below the gate electrode 9, so that the p base region 5 is connected to the cathode via the p cathode region 22. It is short-circuited with the electrode 24, the flow of electrons from the n base region 21 to the n drift layer 2 is stopped, and the MCT is turned off.

In the present embodiment, the killer introduction region 20 with a large lifetime killer is formed immediately below the n drift layer 2 by the proton irradiation and heat treatment from the back surface side of the p substrate 1, and excess carriers are deep inside the substrate. Are prevented from entering. As a result, when the MCT is turned on, no current path is formed deep in the p substrate 1. Therefore, at the time of turning off, carriers are not swept out from a deep current path as in the conventional device, and the turn-off time does not become long.

Further, FIG. 4 shows a dual gate M
It is sectional drawing of the 4th Example of this invention applied to CT. In the element of this example, the structure on the T2 terminal side is the same as that of the MCT of FIG. 3, but on the T1 terminal side, the n ⁺ buffer region 11 is formed.
The n-drain region 27 is further formed inside the p-anode region 23 of the surface layer, and both are connected to the anode electrode 25. Further, a second gate electrode 17 made of polycrystalline silicon is formed on the surface of the p anode region 23 sandwiched between the n ⁺ buffer region 11 and the n drain region 27 with the gate oxide film 16 interposed therebetween.
It is connected to two terminals. In this element, when an off signal is applied to the second gate terminal G2, it operates as the MCT in FIG. 3, but when an on signal is applied to the second gate terminal G2, an inversion layer is formed immediately below the second gate electrode 17. The electrons generated and flowing into the n ⁺ buffer region 11 are n
Since it is bypassed by the drain region 27, the injection of holes from the p anode region 23 is stopped, and a normal MOSFET is formed.
Can be operated as. Also in this embodiment, the killer-introduced region 20 with many lifetime killer is formed immediately below the n drift layer 2 by the proton irradiation and heat treatment from the back surface side of the p-substrate 1, so that excess carriers penetrate deep into the substrate. Is being prevented. The irradiation conditions are almost the same as in the first embodiment.

As a result, in the on state, the low on voltage M
High-speed switching can be performed by operating as CT and switching to the MOSFET mode immediately before turn-off. In the case of this element, the excess carriers are p
If it goes deep into the substrate, the transition time from the MCT mode to the MOSFET mode becomes long and the loss increases. Even in such a case, by forming the killer introduction region 20, M
The transition time can be shortened and the loss can be reduced without significantly increasing the ON voltage in the CT mode.

FIG. 5 is a sectional view of a fifth embodiment of the present invention applied to a lateral electrostatic induction thyristor (hereinafter referred to as SITH). An n-type high resistivity n drift layer 2 is laminated on the p substrate 1 by, for example, an epitaxial method, and the n
A p-type p base region 5 which is close to a part of the surface layer of the drift layer 2 due to impurity diffusion from the surface of the n drift layer 2.
And an n-type n cathode region 26 is formed in a part of the surface layer between the p base regions 5 by impurity diffusion. Then, the cathode electrode 24 connected to the second main terminal T2 is provided in contact with the n cathode region 26. The gate electrode 9 is provided on the p base region 5. In this case, since the electrode is provided in contact with the p base region 5, a metal electrode such as an Al alloy may be used. In the right part of the figure, similarly, the n ⁺ buffer region 11 and the p anode region 23 are formed by impurity diffusion from the surface, and the p anode region 23 is in contact with the anode electrode 25 connected to the first main terminal T1. is doing.

To turn on this SITH, the main terminal T
1 is given a positive voltage with respect to T2, and no signal is given to the gate terminal G. Then, holes are injected from the p anode region 23 into the n drift layer 2, and a conductivity modulation action occurs, so that the on-voltage during conduction can be reduced. In the off operation, a negative voltage is applied to the gate electrode 9. As a result, the depletion layer spreads from the p base region 5, connects with the depletion layer extending from the adjacent p base region 5, closes the current path, and turns off SITH.

In the present embodiment, the killer introduction region 20 with a large lifetime killer is formed immediately below the n drift layer 2 by the proton irradiation and heat treatment from the back surface side of the p substrate 1, and excess carriers are deep inside the substrate. Are prevented from entering. That is, when SITH is turned on, a current path is not formed deep in the p substrate 1. Therefore, at the time of turning off, carriers are not swept out from a deep current path as in the conventional device, and the turn-off time does not become long. Also in this case, the thickness of the killer introduction region 20 may be equal to or more than the diffusion length of carriers in consideration of the existence of this region. In this embodiment, the killer introduction area 20 is n
It is provided in the vicinity of the junction immediately below the drift layer 2, but when the thickness of the n drift layer 2 is smaller than the drift region length (distance between the cathode region and the anode region), it is provided directly below the n drift layer 2. It is also possible to provide the killer introduction region 20 in a deeper portion in order to increase the conductivity modulation in the region near the pn junction and reduce the ON voltage.

The above IGBT, dual gate IGBT,
Although the example applied to the MCT, the dual gate MCT and the SITH has been shown, in addition to this, it can be applied to all lateral bipolar devices such as bipolar transistors and thyristors operating in the bipolar mode to accelerate the switching speed and reduce the loss. It goes without saying that it is effective in reducing the amount. In addition, although an n-channel type element has been described in the present embodiment, it is needless to say that it can be applied to a p-channel type element.

FIG. 6 is a sectional view of a sixth embodiment of the present invention applied to an ordinary diode. In a part of the surface layer of the n drift layer 2 on the p substrate 1, the p type p anode region 23 is formed by impurity diffusion from the surface of the n drift layer 2.
And the n ⁺ cathode region 26 are formed, and the anode electrode 25 and the second main terminal T2 are connected to the first main terminal T1 respectively.
A cathode electrode 24 connected to the.

If a positive voltage is applied to the main terminal T1 with respect to T2, holes are injected from the p anode region 23 into the n drift layer 2 to cause conductivity modulation, and the on-voltage during conduction can be reduced. When the positive voltage is removed, the current stops, but when a reverse bias is further applied, a reverse recovery current flows due to the accumulated carriers. In the present embodiment, the killer introduction region 20 with many lifetime killer is converted into the n drift layer 2 by the proton irradiation and heat treatment from the back surface side of the p substrate 1.
Since it is formed immediately below, it prevents excess carriers from penetrating deep into the substrate. Therefore , when the diode is turned on, a current path is not formed deep in the p substrate 1. Therefore, at the time of off, carriers are not swept out from a deep current path unlike a conventional element, and a large reverse recovery current does not flow. Therefore, the present invention can be applied to the lateral diode in order to achieve both reduction of the on-voltage and reduction of the reverse recovery current.

FIG. 7 is a sectional view of a seventh embodiment of the present invention applied to a MOSFET. n on p board 1
A p-type p base region 5 is formed in a part of the surface layer of the drift layer 2 by impurity diffusion from the surface of the n drift layer 2, and an n source region 28 is formed in a part of the surface layer. Further, the n drain region 29 is formed in a part of the surface layer of the n drift layer 2.
Are provided, and a drain electrode 31 connected to the first main terminal T1 and a source electrode 30 connected to the second main terminal T2 are provided.

If a positive voltage with respect to T2 is applied to the main terminal T1 and a positive voltage above a certain value is applied to the gate terminal G,
An inversion layer is formed in the surface layer of the p base region 5 immediately below the gate electrode 9, and conduction is established between the main terminals T1 and T2 through the inversion layer. In this case, the current is only due to electrons,
The conductivity modulation does not occur, and the current does not reach the p substrate 1. However, there is a parasitic diode between the p substrate 1 and the n drift layer 2, and holes may be injected into the n drift layer 2 through this diode.

In this embodiment, the killer introduction region 20 with a large lifetime killer is formed immediately below the n drift layer 2 by the proton irradiation and heat treatment from the back surface side of the p substrate 1 and is close to the n drift layer 2. Since the carrier lifetime in the p substrate 1 is short, the injection of holes from the p substrate 1 can be suppressed. Thus, the present invention is a MOSF
It can also be applied to ET, and the influence of the parasitic diode can be suppressed.

In the above example, proton irradiation was performed, but the same effect can be obtained by irradiation with helium ions.
Further, in order to improve the switching speed of the device, it is possible to introduce a low level lifetime killer into the drift region, or to combine it with a usual high-speed method such as an anode short type device. Although there have been examples of performing lifetime control with protons or helium ions, they were all applied to a vertical semiconductor device having electrodes on both main surfaces of a semiconductor crystal (eg Akiyama et al .; The Institute of Electrical Engineers of Japan). Electronic Device Study Group Material E
DD-89-40, October 25, 1989).

[0035]

As described above, according to the lateral semiconductor device of the present invention, the carrier lifetime of the first conductivity type semiconductor region below the second conductivity type drift region in which the semiconductor element is formed by proton irradiation or the like is shortened. By doing so, it is possible to reduce excess carriers penetrating deep into the first conductivity type semiconductor region that does not contribute to the reduction of the on-voltage but prolongs the turn-off time. It is possible to achieve both shortening of time, reduction of reverse recovery current, and the like, and a low-loss lateral semiconductor device can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view of an IGBT according to a first embodiment of the present invention.

FIG. 2 is a dual gate IGBT according to a second embodiment of the present invention.
Element cross section of T

FIG. 3 is a sectional view of an MCT of a third embodiment of the present invention.

FIG. 4 is a dual gate MCT according to a fourth embodiment of the present invention.
Element cross section

FIG. 5 is a sectional view of SITH according to a fifth embodiment of the present invention.

FIG. 6 is a sectional view of a diode according to a sixth embodiment of the present invention.

FIG. 7 is a sectional view of a MOSFET according to a seventh embodiment of the present invention.

FIG. 8A is a cross-sectional view of a conventional IGBT and a diagram for explaining a current path therein, and FIG. 8B is a diagram for explaining movement of electrons at turn-off and injection of holes by the movement. Figure

[Explanation of symbols]

1 p substrate 2 n drift layer or n drift region 3 p ⁺ buried region 4 p ⁺ isolation 5 p base region 6 n emitter region 7 p ⁺ contact region 8 gate oxide film 9 gate electrode 10 emitter electrode 11 n ⁺ buffer region 12 p collector region 13 collector electrode 14 p drain region 15 n ⁺ contact region 16 gate oxide film 17 second gate electrode 18 floating contact 20 lifetime killer introduction region 21 n base region 22 p cathode region 23 p anode region 24 cathode electrode 25 anode Electrode 26 n cathode region 27 n drain region 28 n source region 29 n drain region 30 source electrode 31 drain electrode 32 depletion layer 33 electron 34 hole

Front page continuation (51) Int.Cl. ⁷ identification code FI H01L 29/861 H01L 29/91 J C (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/06 H01L 21/331 H01L 29/68 H01L 29/73-29/737 H01L 29/74 H01L 29/78 H01L 29/861

Claims (5)

(57) [Claims] 1. A second-conductivity-type drain on a first-conductivity-type semiconductor region.
A shift area, in at least lateral semiconductor element having two main electrodes are formed, lateral semiconductor device main current flows in the second-conductivity-type drift region between these main electrodes on the surface of the second conductivity type drift region , A first part of a portion where the first conductivity type semiconductor region and the second conductivity type drift region are in contact with each other
The first conductivity type semiconductor region is in contact with the second conductivity type drift region so that the carrier lifetime on the conductivity type semiconductor region side is shorter than that on the second conductivity type drift region side .
A lateral semiconductor device, wherein a lifetime killer introduction region having more lifetime killer than that of the second conductivity type drift region side is formed on the one conductivity type semiconductor region side . 2. The lifetime killer introduction areathickness
A semiconductor region of the first conductivity type when the semiconductor element is off.During ~
so2. A portion where the depletion layer spreads out.
The lateral semiconductor device according to. 3. A semiconductor element is a diode, a bipolar transistor, a thyristor, an IGBT, a SITH, an MCT,
A dual gate IGBT, a dual gate MCT, or a MOSFET in which holes are injected into a second conductivity type drift region through a parasitic diode formed by a first conductivity type semiconductor region and a second conductivity type drift region. Item 3. The lateral semiconductor device according to item 1 or 2. 4. A second conductivity type drain on a first conductivity type semiconductor region.
The shift area of the lateral semiconductor element having at least two main electrodes are formed on the surface of the second conductive type drift region, lateral semiconductor device main current flows in the second-conductivity-type drift region between these main electrodes In the manufacturing method, the lifetime of the carrier on the first conductivity type semiconductor region side of the portion where the first conductivity type semiconductor region and the second conductivity type drift region are in contact is shorter than that on the second conductivity type drift region side. The first conductivity type semiconductor region is in contact with the second conductivity type drift region
And forming by irradiating the protons or helium ions lifetime killers introduction region having more lifetime killer than the second conductivity type drift <br/> region side to the first conductivity type semiconductor region side portions that Method for manufacturing a lateral semiconductor device. 5. Irradiation with protons or helium ions,
The method for manufacturing a lateral semiconductor device according to claim 4, wherein the process is performed from the side where the electrode is not formed.